1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 31 #define PSP_FENCE_BUFFER_SIZE 0x1000 32 #define PSP_CMD_BUFFER_SIZE 0x1000 33 #define PSP_ASD_SHARED_MEM_SIZE 0x4000 34 #define PSP_1_MEG 0x100000 35 #define PSP_TMR_SIZE 0x400000 36 37 struct psp_context; 38 struct psp_xgmi_topology_info; 39 40 enum psp_ring_type 41 { 42 PSP_RING_TYPE__INVALID = 0, 43 /* 44 * These values map to the way the PSP kernel identifies the 45 * rings. 46 */ 47 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 48 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 49 }; 50 51 struct psp_ring 52 { 53 enum psp_ring_type ring_type; 54 struct psp_gfx_rb_frame *ring_mem; 55 uint64_t ring_mem_mc_addr; 56 void *ring_mem_handle; 57 uint32_t ring_size; 58 }; 59 60 struct psp_funcs 61 { 62 int (*init_microcode)(struct psp_context *psp); 63 int (*bootloader_load_sysdrv)(struct psp_context *psp); 64 int (*bootloader_load_sos)(struct psp_context *psp); 65 int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode, 66 struct psp_gfx_cmd_resp *cmd); 67 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); 68 int (*ring_create)(struct psp_context *psp, 69 enum psp_ring_type ring_type); 70 int (*ring_stop)(struct psp_context *psp, 71 enum psp_ring_type ring_type); 72 int (*ring_destroy)(struct psp_context *psp, 73 enum psp_ring_type ring_type); 74 int (*cmd_submit)(struct psp_context *psp, 75 struct amdgpu_firmware_info *ucode, 76 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 77 int index); 78 bool (*compare_sram_data)(struct psp_context *psp, 79 struct amdgpu_firmware_info *ucode, 80 enum AMDGPU_UCODE_ID ucode_type); 81 bool (*smu_reload_quirk)(struct psp_context *psp); 82 int (*mode1_reset)(struct psp_context *psp); 83 uint64_t (*xgmi_get_device_id)(struct psp_context *psp); 84 uint64_t (*xgmi_get_hive_id)(struct psp_context *psp); 85 int (*xgmi_get_topology_info)(struct psp_context *psp, int number_devices, 86 struct psp_xgmi_topology_info *topology); 87 int (*xgmi_set_topology_info)(struct psp_context *psp, int number_devices, 88 struct psp_xgmi_topology_info *topology); 89 }; 90 91 struct psp_context 92 { 93 struct amdgpu_device *adev; 94 struct psp_ring km_ring; 95 struct psp_gfx_cmd_resp *cmd; 96 97 const struct psp_funcs *funcs; 98 99 /* fence buffer */ 100 struct amdgpu_bo *fw_pri_bo; 101 uint64_t fw_pri_mc_addr; 102 void *fw_pri_buf; 103 104 /* sos firmware */ 105 const struct firmware *sos_fw; 106 uint32_t sos_fw_version; 107 uint32_t sos_feature_version; 108 uint32_t sys_bin_size; 109 uint32_t sos_bin_size; 110 uint8_t *sys_start_addr; 111 uint8_t *sos_start_addr; 112 113 /* tmr buffer */ 114 struct amdgpu_bo *tmr_bo; 115 uint64_t tmr_mc_addr; 116 void *tmr_buf; 117 118 /* asd firmware and buffer */ 119 const struct firmware *asd_fw; 120 uint32_t asd_fw_version; 121 uint32_t asd_feature_version; 122 uint32_t asd_ucode_size; 123 uint8_t *asd_start_addr; 124 struct amdgpu_bo *asd_shared_bo; 125 uint64_t asd_shared_mc_addr; 126 void *asd_shared_buf; 127 128 /* fence buffer */ 129 struct amdgpu_bo *fence_buf_bo; 130 uint64_t fence_buf_mc_addr; 131 void *fence_buf; 132 133 /* cmd buffer */ 134 struct amdgpu_bo *cmd_buf_bo; 135 uint64_t cmd_buf_mc_addr; 136 struct psp_gfx_cmd_resp *cmd_buf_mem; 137 }; 138 139 struct amdgpu_psp_funcs { 140 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 141 enum AMDGPU_UCODE_ID); 142 }; 143 144 struct psp_xgmi_topology_info { 145 /* Generated by PSP to identify the GPU instance within xgmi connection */ 146 uint64_t device_id; 147 /* 148 * If all bits set to 0 , driver indicates it wants to retrieve the xgmi 149 * connection vector topology, but not access enable the connections 150 * if some or all bits are set to 1, driver indicates it want to retrieve the 151 * current xgmi topology and access enable the link to GPU[i] associated 152 * with the bit position in the vector. 153 * On return,: bits indicated which xgmi links are present/active depending 154 * on the value passed in. The relative bit offset for the relative GPU index 155 * within the hive is always marked active. 156 */ 157 uint32_t connection_mask; 158 uint32_t reserved; /* must be 0 */ 159 }; 160 161 #define psp_prep_cmd_buf(ucode, type) (psp)->funcs->prep_cmd_buf((ucode), (type)) 162 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type)) 163 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 164 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 165 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 166 #define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \ 167 (psp)->funcs->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index)) 168 #define psp_compare_sram_data(psp, ucode, type) \ 169 (psp)->funcs->compare_sram_data((psp), (ucode), (type)) 170 #define psp_init_microcode(psp) \ 171 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 172 #define psp_bootloader_load_sysdrv(psp) \ 173 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 174 #define psp_bootloader_load_sos(psp) \ 175 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 176 #define psp_smu_reload_quirk(psp) \ 177 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 178 #define psp_mode1_reset(psp) \ 179 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 180 #define psp_xgmi_get_device_id(psp) \ 181 ((psp)->funcs->xgmi_get_device_id ? (psp)->funcs->xgmi_get_device_id((psp)) : 0) 182 #define psp_xgmi_get_hive_id(psp) \ 183 ((psp)->funcs->xgmi_get_hive_id ? (psp)->funcs->xgmi_get_hive_id((psp)) : 0) 184 #define psp_xgmi_get_topology_info(psp, num_device, topology) \ 185 ((psp)->funcs->xgmi_get_topology_info ? \ 186 (psp)->funcs->xgmi_get_topology_info((psp), (num_device), (topology)) : -EINVAL) 187 #define psp_xgmi_set_topology_info(psp, num_device, topology) \ 188 ((psp)->funcs->xgmi_set_topology_info ? \ 189 (psp)->funcs->xgmi_set_topology_info((psp), (num_device), (topology)) : -EINVAL) 190 191 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) 192 193 extern const struct amd_ip_funcs psp_ip_funcs; 194 195 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 196 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 197 uint32_t field_val, uint32_t mask, bool check_changed); 198 199 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 200 201 int psp_gpu_reset(struct amdgpu_device *adev); 202 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 203 204 #endif 205