1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 #include "ta_rap_if.h" 33 #include "ta_secureDisplay_if.h" 34 35 #define PSP_FENCE_BUFFER_SIZE 0x1000 36 #define PSP_CMD_BUFFER_SIZE 0x1000 37 #define PSP_1_MEG 0x100000 38 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) 39 #define PSP_FW_NAME_LEN 0x24 40 41 enum psp_shared_mem_size { 42 PSP_XGMI_SHARED_MEM_SIZE = 0x4000, 43 PSP_RAS_SHARED_MEM_SIZE = 0x4000, 44 PSP_HDCP_SHARED_MEM_SIZE = 0x4000, 45 PSP_DTM_SHARED_MEM_SIZE = 0x4000, 46 PSP_RAP_SHARED_MEM_SIZE = 0x4000, 47 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000, 48 }; 49 50 struct psp_context; 51 struct psp_xgmi_node_info; 52 struct psp_xgmi_topology_info; 53 struct psp_bin_desc; 54 55 enum psp_bootloader_cmd { 56 PSP_BL__LOAD_SYSDRV = 0x10000, 57 PSP_BL__LOAD_SOSDRV = 0x20000, 58 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 59 PSP_BL__LOAD_SOCDRV = 0xB0000, 60 PSP_BL__LOAD_INTFDRV = 0xC0000, 61 PSP_BL__LOAD_DBGDRV = 0xD0000, 62 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 63 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 64 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, 65 }; 66 67 enum psp_ring_type 68 { 69 PSP_RING_TYPE__INVALID = 0, 70 /* 71 * These values map to the way the PSP kernel identifies the 72 * rings. 73 */ 74 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 75 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 76 }; 77 78 struct psp_ring 79 { 80 enum psp_ring_type ring_type; 81 struct psp_gfx_rb_frame *ring_mem; 82 uint64_t ring_mem_mc_addr; 83 void *ring_mem_handle; 84 uint32_t ring_size; 85 uint32_t ring_wptr; 86 }; 87 88 /* More registers may will be supported */ 89 enum psp_reg_prog_id { 90 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 91 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 92 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 93 PSP_REG_LAST 94 }; 95 96 struct psp_funcs 97 { 98 int (*init_microcode)(struct psp_context *psp); 99 int (*bootloader_load_kdb)(struct psp_context *psp); 100 int (*bootloader_load_spl)(struct psp_context *psp); 101 int (*bootloader_load_sysdrv)(struct psp_context *psp); 102 int (*bootloader_load_soc_drv)(struct psp_context *psp); 103 int (*bootloader_load_intf_drv)(struct psp_context *psp); 104 int (*bootloader_load_dbg_drv)(struct psp_context *psp); 105 int (*bootloader_load_sos)(struct psp_context *psp); 106 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); 107 int (*ring_create)(struct psp_context *psp, 108 enum psp_ring_type ring_type); 109 int (*ring_stop)(struct psp_context *psp, 110 enum psp_ring_type ring_type); 111 int (*ring_destroy)(struct psp_context *psp, 112 enum psp_ring_type ring_type); 113 bool (*smu_reload_quirk)(struct psp_context *psp); 114 int (*mode1_reset)(struct psp_context *psp); 115 int (*mem_training)(struct psp_context *psp, uint32_t ops); 116 uint32_t (*ring_get_wptr)(struct psp_context *psp); 117 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); 118 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 119 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); 120 }; 121 122 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 123 struct psp_xgmi_node_info { 124 uint64_t node_id; 125 uint8_t num_hops; 126 uint8_t is_sharing_enabled; 127 enum ta_xgmi_assigned_sdma_engine sdma_engine; 128 uint8_t num_links; 129 }; 130 131 struct psp_xgmi_topology_info { 132 uint32_t num_nodes; 133 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 134 }; 135 136 struct psp_asd_context { 137 bool asd_initialized; 138 uint32_t session_id; 139 }; 140 141 struct ta_mem_context { 142 struct amdgpu_bo *shared_bo; 143 uint64_t shared_mc_addr; 144 void *shared_buf; 145 enum psp_shared_mem_size shared_mem_size; 146 }; 147 148 struct ta_context { 149 bool initialized; 150 uint32_t session_id; 151 struct ta_mem_context mem_context; 152 }; 153 154 struct ta_cp_context { 155 struct ta_context context; 156 struct mutex mutex; 157 }; 158 159 struct psp_xgmi_context { 160 struct ta_context context; 161 struct psp_xgmi_topology_info top_info; 162 bool supports_extended_data; 163 }; 164 165 struct psp_ras_context { 166 struct ta_context context; 167 struct amdgpu_ras *ras; 168 }; 169 170 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 171 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 172 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 173 /*Define the VRAM size that will be encroached by BIST training.*/ 174 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 175 176 enum psp_memory_training_init_flag { 177 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 178 PSP_MEM_TRAIN_SUPPORT = 0x1, 179 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 180 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 181 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 182 }; 183 184 enum psp_memory_training_ops { 185 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 186 PSP_MEM_TRAIN_SAVE = 0x2, 187 PSP_MEM_TRAIN_RESTORE = 0x4, 188 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 189 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 190 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 191 }; 192 193 struct psp_memory_training_context { 194 /*training data size*/ 195 u64 train_data_size; 196 /* 197 * sys_cache 198 * cpu virtual address 199 * system memory buffer that used to store the training data. 200 */ 201 void *sys_cache; 202 203 /*vram offset of the p2c training data*/ 204 u64 p2c_train_data_offset; 205 206 /*vram offset of the c2p training data*/ 207 u64 c2p_train_data_offset; 208 struct amdgpu_bo *c2p_bo; 209 210 enum psp_memory_training_init_flag init; 211 u32 training_cnt; 212 bool enable_mem_training; 213 }; 214 215 /** PSP runtime DB **/ 216 #define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000 217 #define PSP_RUNTIME_DB_OFFSET 0x100000 218 #define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5 219 #define PSP_RUNTIME_DB_VER_1 0x0100 220 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40 221 222 enum psp_runtime_entry_type { 223 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0, 224 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1, 225 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */ 226 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */ 227 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */ 228 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */ 229 }; 230 231 /* PSP runtime DB header */ 232 struct psp_runtime_data_header { 233 /* determine the existence of runtime db */ 234 uint16_t cookie; 235 /* version of runtime db */ 236 uint16_t version; 237 }; 238 239 /* PSP runtime DB entry */ 240 struct psp_runtime_entry { 241 /* type of runtime db entry */ 242 uint32_t entry_type; 243 /* offset of entry in bytes */ 244 uint16_t offset; 245 /* size of entry in bytes */ 246 uint16_t size; 247 }; 248 249 /* PSP runtime DB directory */ 250 struct psp_runtime_data_directory { 251 /* number of valid entries */ 252 uint16_t entry_count; 253 /* db entries*/ 254 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT]; 255 }; 256 257 /* PSP runtime DB boot config feature bitmask */ 258 enum psp_runtime_boot_cfg_feature { 259 BOOT_CFG_FEATURE_GECC = 0x1, 260 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2, 261 }; 262 263 /* PSP runtime DB boot config entry */ 264 struct psp_runtime_boot_cfg_entry { 265 uint32_t boot_cfg_bitmask; 266 uint32_t reserved; 267 }; 268 269 struct psp_bin_desc { 270 uint32_t fw_version; 271 uint32_t feature_version; 272 uint32_t size_bytes; 273 uint8_t *start_addr; 274 }; 275 276 struct psp_context 277 { 278 struct amdgpu_device *adev; 279 struct psp_ring km_ring; 280 struct psp_gfx_cmd_resp *cmd; 281 282 const struct psp_funcs *funcs; 283 284 /* firmware buffer */ 285 struct amdgpu_bo *fw_pri_bo; 286 uint64_t fw_pri_mc_addr; 287 void *fw_pri_buf; 288 289 /* sos firmware */ 290 const struct firmware *sos_fw; 291 struct psp_bin_desc sys; 292 struct psp_bin_desc sos; 293 struct psp_bin_desc toc; 294 struct psp_bin_desc kdb; 295 struct psp_bin_desc spl; 296 struct psp_bin_desc rl; 297 struct psp_bin_desc soc_drv; 298 struct psp_bin_desc intf_drv; 299 struct psp_bin_desc dbg_drv; 300 301 /* tmr buffer */ 302 struct amdgpu_bo *tmr_bo; 303 uint64_t tmr_mc_addr; 304 305 /* asd firmware */ 306 const struct firmware *asd_fw; 307 struct psp_bin_desc asd; 308 309 /* toc firmware */ 310 const struct firmware *toc_fw; 311 312 /* fence buffer */ 313 struct amdgpu_bo *fence_buf_bo; 314 uint64_t fence_buf_mc_addr; 315 void *fence_buf; 316 317 /* cmd buffer */ 318 struct amdgpu_bo *cmd_buf_bo; 319 uint64_t cmd_buf_mc_addr; 320 struct psp_gfx_cmd_resp *cmd_buf_mem; 321 322 /* fence value associated with cmd buffer */ 323 atomic_t fence_value; 324 /* flag to mark whether gfx fw autoload is supported or not */ 325 bool autoload_supported; 326 /* flag to mark whether df cstate management centralized to PMFW */ 327 bool pmfw_centralized_cstate_management; 328 329 /* xgmi ta firmware and buffer */ 330 const struct firmware *ta_fw; 331 uint32_t ta_fw_version; 332 struct psp_bin_desc xgmi; 333 struct psp_bin_desc ras; 334 struct psp_bin_desc hdcp; 335 struct psp_bin_desc dtm; 336 struct psp_bin_desc rap; 337 struct psp_bin_desc securedisplay; 338 339 struct psp_asd_context asd_context; 340 struct psp_xgmi_context xgmi_context; 341 struct psp_ras_context ras_context; 342 struct ta_cp_context hdcp_context; 343 struct ta_cp_context dtm_context; 344 struct ta_cp_context rap_context; 345 struct ta_cp_context securedisplay_context; 346 struct mutex mutex; 347 struct psp_memory_training_context mem_train_ctx; 348 349 uint32_t boot_cfg_bitmask; 350 }; 351 352 struct amdgpu_psp_funcs { 353 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 354 enum AMDGPU_UCODE_ID); 355 }; 356 357 358 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type)) 359 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 360 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 361 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 362 #define psp_init_microcode(psp) \ 363 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 364 #define psp_bootloader_load_kdb(psp) \ 365 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 366 #define psp_bootloader_load_spl(psp) \ 367 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0) 368 #define psp_bootloader_load_sysdrv(psp) \ 369 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 370 #define psp_bootloader_load_soc_drv(psp) \ 371 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0) 372 #define psp_bootloader_load_intf_drv(psp) \ 373 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0) 374 #define psp_bootloader_load_dbg_drv(psp) \ 375 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0) 376 #define psp_bootloader_load_sos(psp) \ 377 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 378 #define psp_smu_reload_quirk(psp) \ 379 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 380 #define psp_mode1_reset(psp) \ 381 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 382 #define psp_mem_training(psp, ops) \ 383 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 384 385 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) 386 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) 387 388 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \ 389 ((psp)->funcs->load_usbc_pd_fw ? \ 390 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL) 391 392 #define psp_read_usbc_pd_fw(psp, fw_ver) \ 393 ((psp)->funcs->read_usbc_pd_fw ? \ 394 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) 395 396 extern const struct amd_ip_funcs psp_ip_funcs; 397 398 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 399 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 400 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 401 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block; 402 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 403 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; 404 405 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 406 uint32_t field_val, uint32_t mask, bool check_changed); 407 408 int psp_gpu_reset(struct amdgpu_device *adev); 409 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 410 uint64_t cmd_gpu_addr, int cmd_size); 411 412 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta); 413 int psp_xgmi_terminate(struct psp_context *psp); 414 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 415 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); 416 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); 417 int psp_xgmi_get_topology_info(struct psp_context *psp, 418 int number_devices, 419 struct psp_xgmi_topology_info *topology, 420 bool get_extended_data); 421 int psp_xgmi_set_topology_info(struct psp_context *psp, 422 int number_devices, 423 struct psp_xgmi_topology_info *topology); 424 425 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 426 int psp_ras_enable_features(struct psp_context *psp, 427 union ta_ras_cmd_input *info, bool enable); 428 int psp_ras_trigger_error(struct psp_context *psp, 429 struct ta_ras_trigger_error_input *info); 430 431 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 432 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 433 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status); 434 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 435 436 int psp_rlc_autoload_start(struct psp_context *psp); 437 438 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 439 uint32_t value); 440 int psp_ring_cmd_submit(struct psp_context *psp, 441 uint64_t cmd_buf_mc_addr, 442 uint64_t fence_mc_addr, 443 int index); 444 int psp_init_asd_microcode(struct psp_context *psp, 445 const char *chip_name); 446 int psp_init_toc_microcode(struct psp_context *psp, 447 const char *chip_name); 448 int psp_init_sos_microcode(struct psp_context *psp, 449 const char *chip_name); 450 int psp_init_ta_microcode(struct psp_context *psp, 451 const char *chip_name); 452 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 453 uint64_t *output_ptr); 454 455 int psp_load_fw_list(struct psp_context *psp, 456 struct amdgpu_firmware_info **ucode_list, int ucode_count); 457 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); 458 459 int is_psp_fw_valid(struct psp_bin_desc bin); 460 #endif 461