1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 33 #define PSP_FENCE_BUFFER_SIZE 0x1000 34 #define PSP_CMD_BUFFER_SIZE 0x1000 35 #define PSP_ASD_SHARED_MEM_SIZE 0x4000 36 #define PSP_XGMI_SHARED_MEM_SIZE 0x4000 37 #define PSP_RAS_SHARED_MEM_SIZE 0x4000 38 #define PSP_1_MEG 0x100000 39 #define PSP_TMR_SIZE 0x400000 40 41 struct psp_context; 42 struct psp_xgmi_node_info; 43 struct psp_xgmi_topology_info; 44 45 enum psp_ring_type 46 { 47 PSP_RING_TYPE__INVALID = 0, 48 /* 49 * These values map to the way the PSP kernel identifies the 50 * rings. 51 */ 52 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 53 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 54 }; 55 56 struct psp_ring 57 { 58 enum psp_ring_type ring_type; 59 struct psp_gfx_rb_frame *ring_mem; 60 uint64_t ring_mem_mc_addr; 61 void *ring_mem_handle; 62 uint32_t ring_size; 63 }; 64 65 /* More registers may will be supported */ 66 enum psp_reg_prog_id { 67 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 68 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 69 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 70 PSP_REG_LAST 71 }; 72 73 struct psp_funcs 74 { 75 int (*init_microcode)(struct psp_context *psp); 76 int (*bootloader_load_sysdrv)(struct psp_context *psp); 77 int (*bootloader_load_sos)(struct psp_context *psp); 78 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); 79 int (*ring_create)(struct psp_context *psp, 80 enum psp_ring_type ring_type); 81 int (*ring_stop)(struct psp_context *psp, 82 enum psp_ring_type ring_type); 83 int (*ring_destroy)(struct psp_context *psp, 84 enum psp_ring_type ring_type); 85 int (*cmd_submit)(struct psp_context *psp, 86 struct amdgpu_firmware_info *ucode, 87 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 88 int index); 89 bool (*compare_sram_data)(struct psp_context *psp, 90 struct amdgpu_firmware_info *ucode, 91 enum AMDGPU_UCODE_ID ucode_type); 92 bool (*smu_reload_quirk)(struct psp_context *psp); 93 int (*mode1_reset)(struct psp_context *psp); 94 int (*xgmi_get_node_id)(struct psp_context *psp, uint64_t *node_id); 95 int (*xgmi_get_hive_id)(struct psp_context *psp, uint64_t *hive_id); 96 int (*xgmi_get_topology_info)(struct psp_context *psp, int number_devices, 97 struct psp_xgmi_topology_info *topology); 98 int (*xgmi_set_topology_info)(struct psp_context *psp, int number_devices, 99 struct psp_xgmi_topology_info *topology); 100 bool (*support_vmr_ring)(struct psp_context *psp); 101 int (*ras_trigger_error)(struct psp_context *psp, 102 struct ta_ras_trigger_error_input *info); 103 int (*ras_cure_posion)(struct psp_context *psp, uint64_t *mode_ptr); 104 }; 105 106 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 107 struct psp_xgmi_node_info { 108 uint64_t node_id; 109 uint8_t num_hops; 110 uint8_t is_sharing_enabled; 111 enum ta_xgmi_assigned_sdma_engine sdma_engine; 112 }; 113 114 struct psp_xgmi_topology_info { 115 uint32_t num_nodes; 116 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 117 }; 118 119 struct psp_xgmi_context { 120 uint8_t initialized; 121 uint32_t session_id; 122 struct amdgpu_bo *xgmi_shared_bo; 123 uint64_t xgmi_shared_mc_addr; 124 void *xgmi_shared_buf; 125 struct psp_xgmi_topology_info top_info; 126 }; 127 128 struct psp_ras_context { 129 /*ras fw*/ 130 bool ras_initialized; 131 uint32_t session_id; 132 struct amdgpu_bo *ras_shared_bo; 133 uint64_t ras_shared_mc_addr; 134 void *ras_shared_buf; 135 struct amdgpu_ras *ras; 136 }; 137 138 struct psp_context 139 { 140 struct amdgpu_device *adev; 141 struct psp_ring km_ring; 142 struct psp_gfx_cmd_resp *cmd; 143 144 const struct psp_funcs *funcs; 145 146 /* firmware buffer */ 147 struct amdgpu_bo *fw_pri_bo; 148 uint64_t fw_pri_mc_addr; 149 void *fw_pri_buf; 150 151 /* sos firmware */ 152 const struct firmware *sos_fw; 153 uint32_t sos_fw_version; 154 uint32_t sos_feature_version; 155 uint32_t sys_bin_size; 156 uint32_t sos_bin_size; 157 uint8_t *sys_start_addr; 158 uint8_t *sos_start_addr; 159 160 /* tmr buffer */ 161 struct amdgpu_bo *tmr_bo; 162 uint64_t tmr_mc_addr; 163 void *tmr_buf; 164 165 /* asd firmware and buffer */ 166 const struct firmware *asd_fw; 167 uint32_t asd_fw_version; 168 uint32_t asd_feature_version; 169 uint32_t asd_ucode_size; 170 uint8_t *asd_start_addr; 171 struct amdgpu_bo *asd_shared_bo; 172 uint64_t asd_shared_mc_addr; 173 void *asd_shared_buf; 174 175 /* fence buffer */ 176 struct amdgpu_bo *fence_buf_bo; 177 uint64_t fence_buf_mc_addr; 178 void *fence_buf; 179 180 /* cmd buffer */ 181 struct amdgpu_bo *cmd_buf_bo; 182 uint64_t cmd_buf_mc_addr; 183 struct psp_gfx_cmd_resp *cmd_buf_mem; 184 185 /* fence value associated with cmd buffer */ 186 atomic_t fence_value; 187 188 /* xgmi ta firmware and buffer */ 189 const struct firmware *ta_fw; 190 uint32_t ta_fw_version; 191 uint32_t ta_xgmi_ucode_version; 192 uint32_t ta_xgmi_ucode_size; 193 uint8_t *ta_xgmi_start_addr; 194 uint32_t ta_ras_ucode_version; 195 uint32_t ta_ras_ucode_size; 196 uint8_t *ta_ras_start_addr; 197 struct psp_xgmi_context xgmi_context; 198 struct psp_ras_context ras; 199 }; 200 201 struct amdgpu_psp_funcs { 202 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 203 enum AMDGPU_UCODE_ID); 204 }; 205 206 207 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type)) 208 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 209 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 210 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 211 #define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \ 212 (psp)->funcs->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index)) 213 #define psp_compare_sram_data(psp, ucode, type) \ 214 (psp)->funcs->compare_sram_data((psp), (ucode), (type)) 215 #define psp_init_microcode(psp) \ 216 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 217 #define psp_bootloader_load_sysdrv(psp) \ 218 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 219 #define psp_bootloader_load_sos(psp) \ 220 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 221 #define psp_smu_reload_quirk(psp) \ 222 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 223 #define psp_support_vmr_ring(psp) \ 224 ((psp)->funcs->support_vmr_ring ? (psp)->funcs->support_vmr_ring((psp)) : false) 225 #define psp_mode1_reset(psp) \ 226 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 227 #define psp_xgmi_get_node_id(psp, node_id) \ 228 ((psp)->funcs->xgmi_get_node_id ? (psp)->funcs->xgmi_get_node_id((psp), (node_id)) : -EINVAL) 229 #define psp_xgmi_get_hive_id(psp, hive_id) \ 230 ((psp)->funcs->xgmi_get_hive_id ? (psp)->funcs->xgmi_get_hive_id((psp), (hive_id)) : -EINVAL) 231 #define psp_xgmi_get_topology_info(psp, num_device, topology) \ 232 ((psp)->funcs->xgmi_get_topology_info ? \ 233 (psp)->funcs->xgmi_get_topology_info((psp), (num_device), (topology)) : -EINVAL) 234 #define psp_xgmi_set_topology_info(psp, num_device, topology) \ 235 ((psp)->funcs->xgmi_set_topology_info ? \ 236 (psp)->funcs->xgmi_set_topology_info((psp), (num_device), (topology)) : -EINVAL) 237 238 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) 239 240 #define psp_ras_trigger_error(psp, info) \ 241 ((psp)->funcs->ras_trigger_error ? \ 242 (psp)->funcs->ras_trigger_error((psp), (info)) : -EINVAL) 243 #define psp_ras_cure_posion(psp, addr) \ 244 ((psp)->funcs->ras_cure_posion ? \ 245 (psp)->funcs->ras_cure_posion(psp, (addr)) : -EINVAL) 246 247 extern const struct amd_ip_funcs psp_ip_funcs; 248 249 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 250 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 251 uint32_t field_val, uint32_t mask, bool check_changed); 252 253 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 254 255 int psp_gpu_reset(struct amdgpu_device *adev); 256 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 257 258 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 259 int psp_ras_enable_features(struct psp_context *psp, 260 union ta_ras_cmd_input *info, bool enable); 261 262 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 263 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 264 uint32_t value); 265 #endif 266