1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Author: Huang Rui
23  *
24  */
25 #ifndef __AMDGPU_PSP_H__
26 #define __AMDGPU_PSP_H__
27 
28 #include "amdgpu.h"
29 #include "psp_gfx_if.h"
30 #include "ta_xgmi_if.h"
31 #include "ta_ras_if.h"
32 #include "ta_rap_if.h"
33 #include "ta_secureDisplay_if.h"
34 
35 #define PSP_FENCE_BUFFER_SIZE	0x1000
36 #define PSP_CMD_BUFFER_SIZE	0x1000
37 #define PSP_1_MEG		0x100000
38 #define PSP_TMR_SIZE(adev)	((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
39 #define PSP_TMR_ALIGNMENT	0x100000
40 #define PSP_FW_NAME_LEN		0x24
41 
42 enum psp_shared_mem_size {
43 	PSP_ASD_SHARED_MEM_SIZE				= 0x0,
44 	PSP_XGMI_SHARED_MEM_SIZE			= 0x4000,
45 	PSP_RAS_SHARED_MEM_SIZE				= 0x4000,
46 	PSP_HDCP_SHARED_MEM_SIZE			= 0x4000,
47 	PSP_DTM_SHARED_MEM_SIZE				= 0x4000,
48 	PSP_RAP_SHARED_MEM_SIZE				= 0x4000,
49 	PSP_SECUREDISPLAY_SHARED_MEM_SIZE	= 0x4000,
50 };
51 
52 enum ta_type_id {
53 	TA_TYPE_XGMI = 1,
54 	TA_TYPE_RAS,
55 	TA_TYPE_HDCP,
56 	TA_TYPE_DTM,
57 	TA_TYPE_RAP,
58 	TA_TYPE_SECUREDISPLAY,
59 
60 	TA_TYPE_MAX_INDEX,
61 };
62 
63 struct psp_context;
64 struct psp_xgmi_node_info;
65 struct psp_xgmi_topology_info;
66 struct psp_bin_desc;
67 
68 enum psp_bootloader_cmd {
69 	PSP_BL__LOAD_SYSDRV		= 0x10000,
70 	PSP_BL__LOAD_SOSDRV		= 0x20000,
71 	PSP_BL__LOAD_KEY_DATABASE	= 0x80000,
72 	PSP_BL__LOAD_SOCDRV             = 0xB0000,
73 	PSP_BL__LOAD_DBGDRV             = 0xC0000,
74 	PSP_BL__LOAD_INTFDRV		= 0xD0000,
75 	PSP_BL__LOAD_RASDRV		    = 0xE0000,
76 	PSP_BL__DRAM_LONG_TRAIN		= 0x100000,
77 	PSP_BL__DRAM_SHORT_TRAIN	= 0x200000,
78 	PSP_BL__LOAD_TOS_SPL_TABLE	= 0x10000000,
79 };
80 
81 enum psp_ring_type
82 {
83 	PSP_RING_TYPE__INVALID = 0,
84 	/*
85 	 * These values map to the way the PSP kernel identifies the
86 	 * rings.
87 	 */
88 	PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
89 	PSP_RING_TYPE__KM = 2  /* Kernel mode ring (formerly called GPCOM) */
90 };
91 
92 struct psp_ring
93 {
94 	enum psp_ring_type		ring_type;
95 	struct psp_gfx_rb_frame		*ring_mem;
96 	uint64_t			ring_mem_mc_addr;
97 	void				*ring_mem_handle;
98 	uint32_t			ring_size;
99 	uint32_t			ring_wptr;
100 };
101 
102 /* More registers may will be supported */
103 enum psp_reg_prog_id {
104 	PSP_REG_IH_RB_CNTL        = 0,  /* register IH_RB_CNTL */
105 	PSP_REG_IH_RB_CNTL_RING1  = 1,  /* register IH_RB_CNTL_RING1 */
106 	PSP_REG_IH_RB_CNTL_RING2  = 2,  /* register IH_RB_CNTL_RING2 */
107 	PSP_REG_LAST
108 };
109 
110 struct psp_funcs
111 {
112 	int (*init_microcode)(struct psp_context *psp);
113 	int (*bootloader_load_kdb)(struct psp_context *psp);
114 	int (*bootloader_load_spl)(struct psp_context *psp);
115 	int (*bootloader_load_sysdrv)(struct psp_context *psp);
116 	int (*bootloader_load_soc_drv)(struct psp_context *psp);
117 	int (*bootloader_load_intf_drv)(struct psp_context *psp);
118 	int (*bootloader_load_dbg_drv)(struct psp_context *psp);
119 	int (*bootloader_load_ras_drv)(struct psp_context *psp);
120 	int (*bootloader_load_sos)(struct psp_context *psp);
121 	int (*ring_create)(struct psp_context *psp,
122 			   enum psp_ring_type ring_type);
123 	int (*ring_stop)(struct psp_context *psp,
124 			    enum psp_ring_type ring_type);
125 	int (*ring_destroy)(struct psp_context *psp,
126 			    enum psp_ring_type ring_type);
127 	bool (*smu_reload_quirk)(struct psp_context *psp);
128 	int (*mode1_reset)(struct psp_context *psp);
129 	int (*mem_training)(struct psp_context *psp, uint32_t ops);
130 	uint32_t (*ring_get_wptr)(struct psp_context *psp);
131 	void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
132 	int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
133 	int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
134 	int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
135 	int (*vbflash_stat)(struct psp_context *psp);
136 };
137 
138 struct ta_funcs {
139 	int (*fn_ta_initialize)(struct psp_context *psp);
140 	int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id);
141 	int (*fn_ta_terminate)(struct psp_context *psp);
142 };
143 
144 #define AMDGPU_XGMI_MAX_CONNECTED_NODES		64
145 struct psp_xgmi_node_info {
146 	uint64_t				node_id;
147 	uint8_t					num_hops;
148 	uint8_t					is_sharing_enabled;
149 	enum ta_xgmi_assigned_sdma_engine	sdma_engine;
150 	uint8_t					num_links;
151 };
152 
153 struct psp_xgmi_topology_info {
154 	uint32_t			num_nodes;
155 	struct psp_xgmi_node_info	nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
156 };
157 
158 struct psp_bin_desc {
159 	uint32_t fw_version;
160 	uint32_t feature_version;
161 	uint32_t size_bytes;
162 	uint8_t *start_addr;
163 };
164 
165 struct ta_mem_context {
166 	struct amdgpu_bo		*shared_bo;
167 	uint64_t		shared_mc_addr;
168 	void			*shared_buf;
169 	enum psp_shared_mem_size	shared_mem_size;
170 };
171 
172 struct ta_context {
173 	bool			initialized;
174 	uint32_t		session_id;
175 	uint32_t		resp_status;
176 	struct ta_mem_context	mem_context;
177 	struct psp_bin_desc		bin_desc;
178 	enum psp_gfx_cmd_id		ta_load_type;
179 	enum ta_type_id		ta_type;
180 };
181 
182 struct ta_cp_context {
183 	struct ta_context		context;
184 	struct mutex			mutex;
185 };
186 
187 struct psp_xgmi_context {
188 	struct ta_context		context;
189 	struct psp_xgmi_topology_info	top_info;
190 	bool				supports_extended_data;
191 };
192 
193 struct psp_ras_context {
194 	struct ta_context		context;
195 	struct amdgpu_ras		*ras;
196 };
197 
198 #define MEM_TRAIN_SYSTEM_SIGNATURE		0x54534942
199 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES	0x1000
200 #define GDDR6_MEM_TRAINING_OFFSET		0x8000
201 /*Define the VRAM size that will be encroached by BIST training.*/
202 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE	0x2000000
203 
204 enum psp_memory_training_init_flag {
205 	PSP_MEM_TRAIN_NOT_SUPPORT	= 0x0,
206 	PSP_MEM_TRAIN_SUPPORT		= 0x1,
207 	PSP_MEM_TRAIN_INIT_FAILED	= 0x2,
208 	PSP_MEM_TRAIN_RESERVE_SUCCESS	= 0x4,
209 	PSP_MEM_TRAIN_INIT_SUCCESS	= 0x8,
210 };
211 
212 enum psp_memory_training_ops {
213 	PSP_MEM_TRAIN_SEND_LONG_MSG	= 0x1,
214 	PSP_MEM_TRAIN_SAVE		= 0x2,
215 	PSP_MEM_TRAIN_RESTORE		= 0x4,
216 	PSP_MEM_TRAIN_SEND_SHORT_MSG	= 0x8,
217 	PSP_MEM_TRAIN_COLD_BOOT		= PSP_MEM_TRAIN_SEND_LONG_MSG,
218 	PSP_MEM_TRAIN_RESUME		= PSP_MEM_TRAIN_SEND_SHORT_MSG,
219 };
220 
221 struct psp_memory_training_context {
222 	/*training data size*/
223 	u64 train_data_size;
224 	/*
225 	 * sys_cache
226 	 * cpu virtual address
227 	 * system memory buffer that used to store the training data.
228 	 */
229 	void *sys_cache;
230 
231 	/*vram offset of the p2c training data*/
232 	u64 p2c_train_data_offset;
233 
234 	/*vram offset of the c2p training data*/
235 	u64 c2p_train_data_offset;
236 	struct amdgpu_bo *c2p_bo;
237 
238 	enum psp_memory_training_init_flag init;
239 	u32 training_cnt;
240 	bool enable_mem_training;
241 };
242 
243 /** PSP runtime DB **/
244 #define PSP_RUNTIME_DB_SIZE_IN_BYTES		0x10000
245 #define PSP_RUNTIME_DB_OFFSET			0x100000
246 #define PSP_RUNTIME_DB_COOKIE_ID		0x0ed5
247 #define PSP_RUNTIME_DB_VER_1			0x0100
248 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT	0x40
249 
250 enum psp_runtime_entry_type {
251 	PSP_RUNTIME_ENTRY_TYPE_INVALID		= 0x0,
252 	PSP_RUNTIME_ENTRY_TYPE_TEST		= 0x1,
253 	PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON	= 0x2,  /* Common mGPU runtime data */
254 	PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL	= 0x3,  /* WAFL runtime data */
255 	PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI	= 0x4,  /* XGMI runtime data */
256 	PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG	= 0x5,  /* Boot Config runtime data */
257 	PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */
258 };
259 
260 /* PSP runtime DB header */
261 struct psp_runtime_data_header {
262 	/* determine the existence of runtime db */
263 	uint16_t cookie;
264 	/* version of runtime db */
265 	uint16_t version;
266 };
267 
268 /* PSP runtime DB entry */
269 struct psp_runtime_entry {
270 	/* type of runtime db entry */
271 	uint32_t entry_type;
272 	/* offset of entry in bytes */
273 	uint16_t offset;
274 	/* size of entry in bytes */
275 	uint16_t size;
276 };
277 
278 /* PSP runtime DB directory */
279 struct psp_runtime_data_directory {
280 	/* number of valid entries */
281 	uint16_t			entry_count;
282 	/* db entries*/
283 	struct psp_runtime_entry	entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT];
284 };
285 
286 /* PSP runtime DB boot config feature bitmask */
287 enum psp_runtime_boot_cfg_feature {
288 	BOOT_CFG_FEATURE_GECC                       = 0x1,
289 	BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING    = 0x2,
290 };
291 
292 /* PSP run time DB SCPM authentication defines */
293 enum psp_runtime_scpm_authentication {
294 	SCPM_DISABLE                     = 0x0,
295 	SCPM_ENABLE                      = 0x1,
296 	SCPM_ENABLE_WITH_SCPM_ERR        = 0x2,
297 };
298 
299 /* PSP runtime DB boot config entry */
300 struct psp_runtime_boot_cfg_entry {
301 	uint32_t boot_cfg_bitmask;
302 	uint32_t reserved;
303 };
304 
305 /* PSP runtime DB SCPM entry */
306 struct psp_runtime_scpm_entry {
307 	enum psp_runtime_scpm_authentication scpm_status;
308 };
309 
310 struct psp_context
311 {
312 	struct amdgpu_device            *adev;
313 	struct psp_ring                 km_ring;
314 	struct psp_gfx_cmd_resp		*cmd;
315 
316 	const struct psp_funcs		*funcs;
317 	const struct ta_funcs		*ta_funcs;
318 
319 	/* firmware buffer */
320 	struct amdgpu_bo		*fw_pri_bo;
321 	uint64_t			fw_pri_mc_addr;
322 	void				*fw_pri_buf;
323 
324 	/* sos firmware */
325 	const struct firmware		*sos_fw;
326 	struct psp_bin_desc		sys;
327 	struct psp_bin_desc		sos;
328 	struct psp_bin_desc		toc;
329 	struct psp_bin_desc		kdb;
330 	struct psp_bin_desc		spl;
331 	struct psp_bin_desc		rl;
332 	struct psp_bin_desc		soc_drv;
333 	struct psp_bin_desc		intf_drv;
334 	struct psp_bin_desc		dbg_drv;
335 	struct psp_bin_desc		ras_drv;
336 
337 	/* tmr buffer */
338 	struct amdgpu_bo		*tmr_bo;
339 	uint64_t			tmr_mc_addr;
340 
341 	/* asd firmware */
342 	const struct firmware	*asd_fw;
343 
344 	/* toc firmware */
345 	const struct firmware		*toc_fw;
346 
347 	/* cap firmware */
348 	const struct firmware		*cap_fw;
349 
350 	/* fence buffer */
351 	struct amdgpu_bo		*fence_buf_bo;
352 	uint64_t			fence_buf_mc_addr;
353 	void				*fence_buf;
354 
355 	/* cmd buffer */
356 	struct amdgpu_bo		*cmd_buf_bo;
357 	uint64_t			cmd_buf_mc_addr;
358 	struct psp_gfx_cmd_resp		*cmd_buf_mem;
359 
360 	/* fence value associated with cmd buffer */
361 	atomic_t			fence_value;
362 	/* flag to mark whether gfx fw autoload is supported or not */
363 	bool				autoload_supported;
364 	/* flag to mark whether df cstate management centralized to PMFW */
365 	bool				pmfw_centralized_cstate_management;
366 
367 	/* xgmi ta firmware and buffer */
368 	const struct firmware		*ta_fw;
369 	uint32_t			ta_fw_version;
370 
371 	uint32_t			cap_fw_version;
372 	uint32_t			cap_feature_version;
373 	uint32_t			cap_ucode_size;
374 
375 	struct ta_context		asd_context;
376 	struct psp_xgmi_context		xgmi_context;
377 	struct psp_ras_context		ras_context;
378 	struct ta_cp_context		hdcp_context;
379 	struct ta_cp_context		dtm_context;
380 	struct ta_cp_context		rap_context;
381 	struct ta_cp_context		securedisplay_context;
382 	struct mutex			mutex;
383 	struct psp_memory_training_context mem_train_ctx;
384 
385 	uint32_t			boot_cfg_bitmask;
386 
387 	char *vbflash_tmp_buf;
388 	size_t vbflash_image_size;
389 	bool vbflash_done;
390 };
391 
392 struct amdgpu_psp_funcs {
393 	bool (*check_fw_loading_status)(struct amdgpu_device *adev,
394 					enum AMDGPU_UCODE_ID);
395 };
396 
397 
398 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
399 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
400 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
401 #define psp_init_microcode(psp) \
402 		((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
403 #define psp_bootloader_load_kdb(psp) \
404 		((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
405 #define psp_bootloader_load_spl(psp) \
406 		((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
407 #define psp_bootloader_load_sysdrv(psp) \
408 		((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
409 #define psp_bootloader_load_soc_drv(psp) \
410 		((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0)
411 #define psp_bootloader_load_intf_drv(psp) \
412 		((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0)
413 #define psp_bootloader_load_dbg_drv(psp) \
414 		((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0)
415 #define psp_bootloader_load_ras_drv(psp) \
416 		((psp)->funcs->bootloader_load_ras_drv ? \
417 		(psp)->funcs->bootloader_load_ras_drv((psp)) : 0)
418 #define psp_bootloader_load_sos(psp) \
419 		((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
420 #define psp_smu_reload_quirk(psp) \
421 		((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
422 #define psp_mode1_reset(psp) \
423 		((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
424 #define psp_mem_training(psp, ops) \
425 	((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
426 
427 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
428 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
429 
430 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \
431 	((psp)->funcs->load_usbc_pd_fw ? \
432 	(psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL)
433 
434 #define psp_read_usbc_pd_fw(psp, fw_ver) \
435 	((psp)->funcs->read_usbc_pd_fw ? \
436 	(psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
437 
438 #define psp_update_spirom(psp, fw_pri_mc_addr) \
439 	((psp)->funcs->update_spirom ? \
440 	(psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL)
441 
442 #define psp_vbflash_status(psp) \
443 	((psp)->funcs->vbflash_stat ? \
444 	(psp)->funcs->vbflash_stat((psp)) : -EINVAL)
445 
446 extern const struct amd_ip_funcs psp_ip_funcs;
447 
448 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
449 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
450 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
451 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block;
452 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
453 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
454 extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
455 
456 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
457 			uint32_t field_val, uint32_t mask, bool check_changed);
458 
459 int psp_gpu_reset(struct amdgpu_device *adev);
460 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
461 			uint64_t cmd_gpu_addr, int cmd_size);
462 
463 int psp_ta_init_shared_buf(struct psp_context *psp,
464 				  struct ta_mem_context *mem_ctx);
465 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx);
466 int psp_ta_unload(struct psp_context *psp, struct ta_context *context);
467 int psp_ta_load(struct psp_context *psp, struct ta_context *context);
468 int psp_ta_invoke(struct psp_context *psp,
469 			uint32_t ta_cmd_id,
470 			struct ta_context *context);
471 
472 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta);
473 int psp_xgmi_terminate(struct psp_context *psp);
474 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
475 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
476 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
477 int psp_xgmi_get_topology_info(struct psp_context *psp,
478 			       int number_devices,
479 			       struct psp_xgmi_topology_info *topology,
480 			       bool get_extended_data);
481 int psp_xgmi_set_topology_info(struct psp_context *psp,
482 			       int number_devices,
483 			       struct psp_xgmi_topology_info *topology);
484 int psp_ras_initialize(struct psp_context *psp);
485 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
486 int psp_ras_enable_features(struct psp_context *psp,
487 		union ta_ras_cmd_input *info, bool enable);
488 int psp_ras_trigger_error(struct psp_context *psp,
489 			  struct ta_ras_trigger_error_input *info);
490 int psp_ras_terminate(struct psp_context *psp);
491 
492 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
493 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
494 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status);
495 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
496 
497 int psp_rlc_autoload_start(struct psp_context *psp);
498 
499 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
500 		uint32_t value);
501 int psp_ring_cmd_submit(struct psp_context *psp,
502 			uint64_t cmd_buf_mc_addr,
503 			uint64_t fence_mc_addr,
504 			int index);
505 int psp_init_asd_microcode(struct psp_context *psp,
506 			   const char *chip_name);
507 int psp_init_toc_microcode(struct psp_context *psp,
508 			   const char *chip_name);
509 int psp_init_sos_microcode(struct psp_context *psp,
510 			   const char *chip_name);
511 int psp_init_ta_microcode(struct psp_context *psp,
512 			  const char *chip_name);
513 int psp_init_cap_microcode(struct psp_context *psp,
514 			  const char *chip_name);
515 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
516 					uint64_t *output_ptr);
517 
518 int psp_load_fw_list(struct psp_context *psp,
519 		     struct amdgpu_firmware_info **ucode_list, int ucode_count);
520 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);
521 
522 int is_psp_fw_valid(struct psp_bin_desc bin);
523 
524 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev);
525 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev);
526 #endif
527