1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 #include "ta_rap_if.h" 33 #include "ta_secureDisplay_if.h" 34 35 #define PSP_FENCE_BUFFER_SIZE 0x1000 36 #define PSP_CMD_BUFFER_SIZE 0x1000 37 #define PSP_1_MEG 0x100000 38 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) 39 #define PSP_FW_NAME_LEN 0x24 40 41 enum psp_shared_mem_size { 42 PSP_ASD_SHARED_MEM_SIZE = 0x0, 43 PSP_XGMI_SHARED_MEM_SIZE = 0x4000, 44 PSP_RAS_SHARED_MEM_SIZE = 0x4000, 45 PSP_HDCP_SHARED_MEM_SIZE = 0x4000, 46 PSP_DTM_SHARED_MEM_SIZE = 0x4000, 47 PSP_RAP_SHARED_MEM_SIZE = 0x4000, 48 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000, 49 }; 50 51 enum ta_type_id { 52 TA_TYPE_XGMI = 1, 53 TA_TYPE_RAS, 54 TA_TYPE_HDCP, 55 TA_TYPE_DTM, 56 TA_TYPE_RAP, 57 TA_TYPE_SECUREDISPLAY, 58 59 TA_TYPE_MAX_INDEX, 60 }; 61 62 struct psp_context; 63 struct psp_xgmi_node_info; 64 struct psp_xgmi_topology_info; 65 struct psp_bin_desc; 66 67 enum psp_bootloader_cmd { 68 PSP_BL__LOAD_SYSDRV = 0x10000, 69 PSP_BL__LOAD_SOSDRV = 0x20000, 70 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 71 PSP_BL__LOAD_SOCDRV = 0xB0000, 72 PSP_BL__LOAD_INTFDRV = 0xC0000, 73 PSP_BL__LOAD_DBGDRV = 0xD0000, 74 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 75 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 76 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, 77 }; 78 79 enum psp_ring_type 80 { 81 PSP_RING_TYPE__INVALID = 0, 82 /* 83 * These values map to the way the PSP kernel identifies the 84 * rings. 85 */ 86 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 87 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 88 }; 89 90 struct psp_ring 91 { 92 enum psp_ring_type ring_type; 93 struct psp_gfx_rb_frame *ring_mem; 94 uint64_t ring_mem_mc_addr; 95 void *ring_mem_handle; 96 uint32_t ring_size; 97 uint32_t ring_wptr; 98 }; 99 100 /* More registers may will be supported */ 101 enum psp_reg_prog_id { 102 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 103 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 104 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 105 PSP_REG_LAST 106 }; 107 108 struct psp_funcs 109 { 110 int (*init_microcode)(struct psp_context *psp); 111 int (*bootloader_load_kdb)(struct psp_context *psp); 112 int (*bootloader_load_spl)(struct psp_context *psp); 113 int (*bootloader_load_sysdrv)(struct psp_context *psp); 114 int (*bootloader_load_soc_drv)(struct psp_context *psp); 115 int (*bootloader_load_intf_drv)(struct psp_context *psp); 116 int (*bootloader_load_dbg_drv)(struct psp_context *psp); 117 int (*bootloader_load_sos)(struct psp_context *psp); 118 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); 119 int (*ring_create)(struct psp_context *psp, 120 enum psp_ring_type ring_type); 121 int (*ring_stop)(struct psp_context *psp, 122 enum psp_ring_type ring_type); 123 int (*ring_destroy)(struct psp_context *psp, 124 enum psp_ring_type ring_type); 125 bool (*smu_reload_quirk)(struct psp_context *psp); 126 int (*mode1_reset)(struct psp_context *psp); 127 int (*mem_training)(struct psp_context *psp, uint32_t ops); 128 uint32_t (*ring_get_wptr)(struct psp_context *psp); 129 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); 130 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 131 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); 132 }; 133 134 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 135 struct psp_xgmi_node_info { 136 uint64_t node_id; 137 uint8_t num_hops; 138 uint8_t is_sharing_enabled; 139 enum ta_xgmi_assigned_sdma_engine sdma_engine; 140 uint8_t num_links; 141 }; 142 143 struct psp_xgmi_topology_info { 144 uint32_t num_nodes; 145 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 146 }; 147 148 struct psp_bin_desc { 149 uint32_t fw_version; 150 uint32_t feature_version; 151 uint32_t size_bytes; 152 uint8_t *start_addr; 153 }; 154 155 struct ta_mem_context { 156 struct amdgpu_bo *shared_bo; 157 uint64_t shared_mc_addr; 158 void *shared_buf; 159 enum psp_shared_mem_size shared_mem_size; 160 }; 161 162 struct ta_context { 163 bool initialized; 164 uint32_t session_id; 165 uint32_t resp_status; 166 struct ta_mem_context mem_context; 167 struct psp_bin_desc bin_desc; 168 enum psp_gfx_cmd_id ta_load_type; 169 enum ta_type_id ta_type; 170 }; 171 172 struct ta_cp_context { 173 struct ta_context context; 174 struct mutex mutex; 175 }; 176 177 struct psp_xgmi_context { 178 struct ta_context context; 179 struct psp_xgmi_topology_info top_info; 180 bool supports_extended_data; 181 }; 182 183 struct psp_ras_context { 184 struct ta_context context; 185 struct amdgpu_ras *ras; 186 }; 187 188 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 189 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 190 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 191 /*Define the VRAM size that will be encroached by BIST training.*/ 192 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 193 194 enum psp_memory_training_init_flag { 195 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 196 PSP_MEM_TRAIN_SUPPORT = 0x1, 197 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 198 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 199 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 200 }; 201 202 enum psp_memory_training_ops { 203 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 204 PSP_MEM_TRAIN_SAVE = 0x2, 205 PSP_MEM_TRAIN_RESTORE = 0x4, 206 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 207 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 208 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 209 }; 210 211 struct psp_memory_training_context { 212 /*training data size*/ 213 u64 train_data_size; 214 /* 215 * sys_cache 216 * cpu virtual address 217 * system memory buffer that used to store the training data. 218 */ 219 void *sys_cache; 220 221 /*vram offset of the p2c training data*/ 222 u64 p2c_train_data_offset; 223 224 /*vram offset of the c2p training data*/ 225 u64 c2p_train_data_offset; 226 struct amdgpu_bo *c2p_bo; 227 228 enum psp_memory_training_init_flag init; 229 u32 training_cnt; 230 bool enable_mem_training; 231 }; 232 233 /** PSP runtime DB **/ 234 #define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000 235 #define PSP_RUNTIME_DB_OFFSET 0x100000 236 #define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5 237 #define PSP_RUNTIME_DB_VER_1 0x0100 238 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40 239 240 enum psp_runtime_entry_type { 241 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0, 242 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1, 243 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */ 244 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */ 245 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */ 246 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */ 247 }; 248 249 /* PSP runtime DB header */ 250 struct psp_runtime_data_header { 251 /* determine the existence of runtime db */ 252 uint16_t cookie; 253 /* version of runtime db */ 254 uint16_t version; 255 }; 256 257 /* PSP runtime DB entry */ 258 struct psp_runtime_entry { 259 /* type of runtime db entry */ 260 uint32_t entry_type; 261 /* offset of entry in bytes */ 262 uint16_t offset; 263 /* size of entry in bytes */ 264 uint16_t size; 265 }; 266 267 /* PSP runtime DB directory */ 268 struct psp_runtime_data_directory { 269 /* number of valid entries */ 270 uint16_t entry_count; 271 /* db entries*/ 272 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT]; 273 }; 274 275 /* PSP runtime DB boot config feature bitmask */ 276 enum psp_runtime_boot_cfg_feature { 277 BOOT_CFG_FEATURE_GECC = 0x1, 278 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2, 279 }; 280 281 /* PSP runtime DB boot config entry */ 282 struct psp_runtime_boot_cfg_entry { 283 uint32_t boot_cfg_bitmask; 284 uint32_t reserved; 285 }; 286 287 struct psp_context 288 { 289 struct amdgpu_device *adev; 290 struct psp_ring km_ring; 291 struct psp_gfx_cmd_resp *cmd; 292 293 const struct psp_funcs *funcs; 294 295 /* firmware buffer */ 296 struct amdgpu_bo *fw_pri_bo; 297 uint64_t fw_pri_mc_addr; 298 void *fw_pri_buf; 299 300 /* sos firmware */ 301 const struct firmware *sos_fw; 302 struct psp_bin_desc sys; 303 struct psp_bin_desc sos; 304 struct psp_bin_desc toc; 305 struct psp_bin_desc kdb; 306 struct psp_bin_desc spl; 307 struct psp_bin_desc rl; 308 struct psp_bin_desc soc_drv; 309 struct psp_bin_desc intf_drv; 310 struct psp_bin_desc dbg_drv; 311 312 /* tmr buffer */ 313 struct amdgpu_bo *tmr_bo; 314 uint64_t tmr_mc_addr; 315 316 /* asd firmware */ 317 const struct firmware *asd_fw; 318 319 /* toc firmware */ 320 const struct firmware *toc_fw; 321 322 /* cap firmware */ 323 const struct firmware *cap_fw; 324 325 /* fence buffer */ 326 struct amdgpu_bo *fence_buf_bo; 327 uint64_t fence_buf_mc_addr; 328 void *fence_buf; 329 330 /* cmd buffer */ 331 struct amdgpu_bo *cmd_buf_bo; 332 uint64_t cmd_buf_mc_addr; 333 struct psp_gfx_cmd_resp *cmd_buf_mem; 334 335 /* fence value associated with cmd buffer */ 336 atomic_t fence_value; 337 /* flag to mark whether gfx fw autoload is supported or not */ 338 bool autoload_supported; 339 /* flag to mark whether df cstate management centralized to PMFW */ 340 bool pmfw_centralized_cstate_management; 341 342 /* xgmi ta firmware and buffer */ 343 const struct firmware *ta_fw; 344 uint32_t ta_fw_version; 345 346 uint32_t cap_fw_version; 347 uint32_t cap_feature_version; 348 uint32_t cap_ucode_size; 349 350 struct ta_context asd_context; 351 struct psp_xgmi_context xgmi_context; 352 struct psp_ras_context ras_context; 353 struct ta_cp_context hdcp_context; 354 struct ta_cp_context dtm_context; 355 struct ta_cp_context rap_context; 356 struct ta_cp_context securedisplay_context; 357 struct mutex mutex; 358 struct psp_memory_training_context mem_train_ctx; 359 360 uint32_t boot_cfg_bitmask; 361 }; 362 363 struct amdgpu_psp_funcs { 364 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 365 enum AMDGPU_UCODE_ID); 366 }; 367 368 369 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type)) 370 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 371 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 372 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 373 #define psp_init_microcode(psp) \ 374 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 375 #define psp_bootloader_load_kdb(psp) \ 376 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 377 #define psp_bootloader_load_spl(psp) \ 378 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0) 379 #define psp_bootloader_load_sysdrv(psp) \ 380 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 381 #define psp_bootloader_load_soc_drv(psp) \ 382 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0) 383 #define psp_bootloader_load_intf_drv(psp) \ 384 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0) 385 #define psp_bootloader_load_dbg_drv(psp) \ 386 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0) 387 #define psp_bootloader_load_sos(psp) \ 388 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 389 #define psp_smu_reload_quirk(psp) \ 390 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 391 #define psp_mode1_reset(psp) \ 392 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 393 #define psp_mem_training(psp, ops) \ 394 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 395 396 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) 397 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) 398 399 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \ 400 ((psp)->funcs->load_usbc_pd_fw ? \ 401 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL) 402 403 #define psp_read_usbc_pd_fw(psp, fw_ver) \ 404 ((psp)->funcs->read_usbc_pd_fw ? \ 405 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) 406 407 extern const struct amd_ip_funcs psp_ip_funcs; 408 409 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 410 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 411 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 412 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block; 413 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 414 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; 415 416 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 417 uint32_t field_val, uint32_t mask, bool check_changed); 418 419 int psp_gpu_reset(struct amdgpu_device *adev); 420 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 421 uint64_t cmd_gpu_addr, int cmd_size); 422 423 int psp_ta_init_shared_buf(struct psp_context *psp, 424 struct ta_mem_context *mem_ctx); 425 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx); 426 int psp_ta_unload(struct psp_context *psp, struct ta_context *context); 427 int psp_ta_load(struct psp_context *psp, struct ta_context *context); 428 int psp_ta_invoke(struct psp_context *psp, 429 uint32_t ta_cmd_id, 430 struct ta_context *context); 431 int psp_ta_invoke_indirect(struct psp_context *psp, 432 uint32_t ta_cmd_id, 433 struct ta_context *context); 434 435 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta); 436 int psp_xgmi_terminate(struct psp_context *psp); 437 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 438 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); 439 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); 440 int psp_xgmi_get_topology_info(struct psp_context *psp, 441 int number_devices, 442 struct psp_xgmi_topology_info *topology, 443 bool get_extended_data); 444 int psp_xgmi_set_topology_info(struct psp_context *psp, 445 int number_devices, 446 struct psp_xgmi_topology_info *topology); 447 448 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 449 int psp_ras_enable_features(struct psp_context *psp, 450 union ta_ras_cmd_input *info, bool enable); 451 int psp_ras_trigger_error(struct psp_context *psp, 452 struct ta_ras_trigger_error_input *info); 453 int psp_ras_terminate(struct psp_context *psp); 454 455 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 456 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 457 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status); 458 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 459 460 int psp_rlc_autoload_start(struct psp_context *psp); 461 462 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 463 uint32_t value); 464 int psp_ring_cmd_submit(struct psp_context *psp, 465 uint64_t cmd_buf_mc_addr, 466 uint64_t fence_mc_addr, 467 int index); 468 int psp_init_asd_microcode(struct psp_context *psp, 469 const char *chip_name); 470 int psp_init_toc_microcode(struct psp_context *psp, 471 const char *chip_name); 472 int psp_init_sos_microcode(struct psp_context *psp, 473 const char *chip_name); 474 int psp_init_ta_microcode(struct psp_context *psp, 475 const char *chip_name); 476 int psp_init_cap_microcode(struct psp_context *psp, 477 const char *chip_name); 478 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 479 uint64_t *output_ptr); 480 481 int psp_load_fw_list(struct psp_context *psp, 482 struct amdgpu_firmware_info **ucode_list, int ucode_count); 483 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); 484 485 int is_psp_fw_valid(struct psp_bin_desc bin); 486 #endif 487