1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Author: Huang Rui
23  *
24  */
25 #ifndef __AMDGPU_PSP_H__
26 #define __AMDGPU_PSP_H__
27 
28 #include "amdgpu.h"
29 #include "psp_gfx_if.h"
30 #include "ta_xgmi_if.h"
31 #include "ta_ras_if.h"
32 #include "ta_rap_if.h"
33 #include "ta_secureDisplay_if.h"
34 
35 #define PSP_FENCE_BUFFER_SIZE	0x1000
36 #define PSP_CMD_BUFFER_SIZE	0x1000
37 #define PSP_1_MEG		0x100000
38 #define PSP_TMR_SIZE(adev)	((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
39 #define PSP_TMR_ALIGNMENT	0x100000
40 #define PSP_FW_NAME_LEN		0x24
41 
42 enum psp_shared_mem_size {
43 	PSP_ASD_SHARED_MEM_SIZE				= 0x0,
44 	PSP_XGMI_SHARED_MEM_SIZE			= 0x4000,
45 	PSP_RAS_SHARED_MEM_SIZE				= 0x4000,
46 	PSP_HDCP_SHARED_MEM_SIZE			= 0x4000,
47 	PSP_DTM_SHARED_MEM_SIZE				= 0x4000,
48 	PSP_RAP_SHARED_MEM_SIZE				= 0x4000,
49 	PSP_SECUREDISPLAY_SHARED_MEM_SIZE	= 0x4000,
50 };
51 
52 enum ta_type_id {
53 	TA_TYPE_XGMI = 1,
54 	TA_TYPE_RAS,
55 	TA_TYPE_HDCP,
56 	TA_TYPE_DTM,
57 	TA_TYPE_RAP,
58 	TA_TYPE_SECUREDISPLAY,
59 
60 	TA_TYPE_MAX_INDEX,
61 };
62 
63 struct psp_context;
64 struct psp_xgmi_node_info;
65 struct psp_xgmi_topology_info;
66 struct psp_bin_desc;
67 
68 enum psp_bootloader_cmd {
69 	PSP_BL__LOAD_SYSDRV		= 0x10000,
70 	PSP_BL__LOAD_SOSDRV		= 0x20000,
71 	PSP_BL__LOAD_KEY_DATABASE	= 0x80000,
72 	PSP_BL__LOAD_SOCDRV             = 0xB0000,
73 	PSP_BL__LOAD_DBGDRV             = 0xC0000,
74 	PSP_BL__LOAD_INTFDRV		= 0xD0000,
75 	PSP_BL__LOAD_RASDRV		    = 0xE0000,
76 	PSP_BL__DRAM_LONG_TRAIN		= 0x100000,
77 	PSP_BL__DRAM_SHORT_TRAIN	= 0x200000,
78 	PSP_BL__LOAD_TOS_SPL_TABLE	= 0x10000000,
79 };
80 
81 enum psp_ring_type
82 {
83 	PSP_RING_TYPE__INVALID = 0,
84 	/*
85 	 * These values map to the way the PSP kernel identifies the
86 	 * rings.
87 	 */
88 	PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
89 	PSP_RING_TYPE__KM = 2  /* Kernel mode ring (formerly called GPCOM) */
90 };
91 
92 struct psp_ring
93 {
94 	enum psp_ring_type		ring_type;
95 	struct psp_gfx_rb_frame		*ring_mem;
96 	uint64_t			ring_mem_mc_addr;
97 	void				*ring_mem_handle;
98 	uint32_t			ring_size;
99 	uint32_t			ring_wptr;
100 };
101 
102 /* More registers may will be supported */
103 enum psp_reg_prog_id {
104 	PSP_REG_IH_RB_CNTL        = 0,  /* register IH_RB_CNTL */
105 	PSP_REG_IH_RB_CNTL_RING1  = 1,  /* register IH_RB_CNTL_RING1 */
106 	PSP_REG_IH_RB_CNTL_RING2  = 2,  /* register IH_RB_CNTL_RING2 */
107 	PSP_REG_LAST
108 };
109 
110 struct psp_funcs
111 {
112 	int (*init_microcode)(struct psp_context *psp);
113 	int (*bootloader_load_kdb)(struct psp_context *psp);
114 	int (*bootloader_load_spl)(struct psp_context *psp);
115 	int (*bootloader_load_sysdrv)(struct psp_context *psp);
116 	int (*bootloader_load_soc_drv)(struct psp_context *psp);
117 	int (*bootloader_load_intf_drv)(struct psp_context *psp);
118 	int (*bootloader_load_dbg_drv)(struct psp_context *psp);
119 	int (*bootloader_load_ras_drv)(struct psp_context *psp);
120 	int (*bootloader_load_sos)(struct psp_context *psp);
121 	int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
122 	int (*ring_create)(struct psp_context *psp,
123 			   enum psp_ring_type ring_type);
124 	int (*ring_stop)(struct psp_context *psp,
125 			    enum psp_ring_type ring_type);
126 	int (*ring_destroy)(struct psp_context *psp,
127 			    enum psp_ring_type ring_type);
128 	bool (*smu_reload_quirk)(struct psp_context *psp);
129 	int (*mode1_reset)(struct psp_context *psp);
130 	int (*mem_training)(struct psp_context *psp, uint32_t ops);
131 	uint32_t (*ring_get_wptr)(struct psp_context *psp);
132 	void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
133 	int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
134 	int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
135 	int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
136 	int (*vbflash_stat)(struct psp_context *psp);
137 };
138 
139 #define AMDGPU_XGMI_MAX_CONNECTED_NODES		64
140 struct psp_xgmi_node_info {
141 	uint64_t				node_id;
142 	uint8_t					num_hops;
143 	uint8_t					is_sharing_enabled;
144 	enum ta_xgmi_assigned_sdma_engine	sdma_engine;
145 	uint8_t					num_links;
146 };
147 
148 struct psp_xgmi_topology_info {
149 	uint32_t			num_nodes;
150 	struct psp_xgmi_node_info	nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
151 };
152 
153 struct psp_bin_desc {
154 	uint32_t fw_version;
155 	uint32_t feature_version;
156 	uint32_t size_bytes;
157 	uint8_t *start_addr;
158 };
159 
160 struct ta_mem_context {
161 	struct amdgpu_bo		*shared_bo;
162 	uint64_t		shared_mc_addr;
163 	void			*shared_buf;
164 	enum psp_shared_mem_size	shared_mem_size;
165 };
166 
167 struct ta_context {
168 	bool			initialized;
169 	uint32_t		session_id;
170 	uint32_t		resp_status;
171 	struct ta_mem_context	mem_context;
172 	struct psp_bin_desc		bin_desc;
173 	enum psp_gfx_cmd_id		ta_load_type;
174 	enum ta_type_id		ta_type;
175 };
176 
177 struct ta_cp_context {
178 	struct ta_context		context;
179 	struct mutex			mutex;
180 };
181 
182 struct psp_xgmi_context {
183 	struct ta_context		context;
184 	struct psp_xgmi_topology_info	top_info;
185 	bool				supports_extended_data;
186 };
187 
188 struct psp_ras_context {
189 	struct ta_context		context;
190 	struct amdgpu_ras		*ras;
191 };
192 
193 #define MEM_TRAIN_SYSTEM_SIGNATURE		0x54534942
194 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES	0x1000
195 #define GDDR6_MEM_TRAINING_OFFSET		0x8000
196 /*Define the VRAM size that will be encroached by BIST training.*/
197 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE	0x2000000
198 
199 enum psp_memory_training_init_flag {
200 	PSP_MEM_TRAIN_NOT_SUPPORT	= 0x0,
201 	PSP_MEM_TRAIN_SUPPORT		= 0x1,
202 	PSP_MEM_TRAIN_INIT_FAILED	= 0x2,
203 	PSP_MEM_TRAIN_RESERVE_SUCCESS	= 0x4,
204 	PSP_MEM_TRAIN_INIT_SUCCESS	= 0x8,
205 };
206 
207 enum psp_memory_training_ops {
208 	PSP_MEM_TRAIN_SEND_LONG_MSG	= 0x1,
209 	PSP_MEM_TRAIN_SAVE		= 0x2,
210 	PSP_MEM_TRAIN_RESTORE		= 0x4,
211 	PSP_MEM_TRAIN_SEND_SHORT_MSG	= 0x8,
212 	PSP_MEM_TRAIN_COLD_BOOT		= PSP_MEM_TRAIN_SEND_LONG_MSG,
213 	PSP_MEM_TRAIN_RESUME		= PSP_MEM_TRAIN_SEND_SHORT_MSG,
214 };
215 
216 struct psp_memory_training_context {
217 	/*training data size*/
218 	u64 train_data_size;
219 	/*
220 	 * sys_cache
221 	 * cpu virtual address
222 	 * system memory buffer that used to store the training data.
223 	 */
224 	void *sys_cache;
225 
226 	/*vram offset of the p2c training data*/
227 	u64 p2c_train_data_offset;
228 
229 	/*vram offset of the c2p training data*/
230 	u64 c2p_train_data_offset;
231 	struct amdgpu_bo *c2p_bo;
232 
233 	enum psp_memory_training_init_flag init;
234 	u32 training_cnt;
235 	bool enable_mem_training;
236 };
237 
238 /** PSP runtime DB **/
239 #define PSP_RUNTIME_DB_SIZE_IN_BYTES		0x10000
240 #define PSP_RUNTIME_DB_OFFSET			0x100000
241 #define PSP_RUNTIME_DB_COOKIE_ID		0x0ed5
242 #define PSP_RUNTIME_DB_VER_1			0x0100
243 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT	0x40
244 
245 enum psp_runtime_entry_type {
246 	PSP_RUNTIME_ENTRY_TYPE_INVALID		= 0x0,
247 	PSP_RUNTIME_ENTRY_TYPE_TEST		= 0x1,
248 	PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON	= 0x2,  /* Common mGPU runtime data */
249 	PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL	= 0x3,  /* WAFL runtime data */
250 	PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI	= 0x4,  /* XGMI runtime data */
251 	PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG	= 0x5,  /* Boot Config runtime data */
252 	PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */
253 };
254 
255 /* PSP runtime DB header */
256 struct psp_runtime_data_header {
257 	/* determine the existence of runtime db */
258 	uint16_t cookie;
259 	/* version of runtime db */
260 	uint16_t version;
261 };
262 
263 /* PSP runtime DB entry */
264 struct psp_runtime_entry {
265 	/* type of runtime db entry */
266 	uint32_t entry_type;
267 	/* offset of entry in bytes */
268 	uint16_t offset;
269 	/* size of entry in bytes */
270 	uint16_t size;
271 };
272 
273 /* PSP runtime DB directory */
274 struct psp_runtime_data_directory {
275 	/* number of valid entries */
276 	uint16_t			entry_count;
277 	/* db entries*/
278 	struct psp_runtime_entry	entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT];
279 };
280 
281 /* PSP runtime DB boot config feature bitmask */
282 enum psp_runtime_boot_cfg_feature {
283 	BOOT_CFG_FEATURE_GECC                       = 0x1,
284 	BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING    = 0x2,
285 };
286 
287 /* PSP run time DB SCPM authentication defines */
288 enum psp_runtime_scpm_authentication {
289 	SCPM_DISABLE                     = 0x0,
290 	SCPM_ENABLE                      = 0x1,
291 	SCPM_ENABLE_WITH_SCPM_ERR        = 0x2,
292 };
293 
294 /* PSP runtime DB boot config entry */
295 struct psp_runtime_boot_cfg_entry {
296 	uint32_t boot_cfg_bitmask;
297 	uint32_t reserved;
298 };
299 
300 /* PSP runtime DB SCPM entry */
301 struct psp_runtime_scpm_entry {
302 	enum psp_runtime_scpm_authentication scpm_status;
303 };
304 
305 struct psp_context
306 {
307 	struct amdgpu_device            *adev;
308 	struct psp_ring                 km_ring;
309 	struct psp_gfx_cmd_resp		*cmd;
310 
311 	const struct psp_funcs		*funcs;
312 
313 	/* firmware buffer */
314 	struct amdgpu_bo		*fw_pri_bo;
315 	uint64_t			fw_pri_mc_addr;
316 	void				*fw_pri_buf;
317 
318 	/* sos firmware */
319 	const struct firmware		*sos_fw;
320 	struct psp_bin_desc		sys;
321 	struct psp_bin_desc		sos;
322 	struct psp_bin_desc		toc;
323 	struct psp_bin_desc		kdb;
324 	struct psp_bin_desc		spl;
325 	struct psp_bin_desc		rl;
326 	struct psp_bin_desc		soc_drv;
327 	struct psp_bin_desc		intf_drv;
328 	struct psp_bin_desc		dbg_drv;
329 	struct psp_bin_desc		ras_drv;
330 
331 	/* tmr buffer */
332 	struct amdgpu_bo		*tmr_bo;
333 	uint64_t			tmr_mc_addr;
334 
335 	/* asd firmware */
336 	const struct firmware	*asd_fw;
337 
338 	/* toc firmware */
339 	const struct firmware		*toc_fw;
340 
341 	/* cap firmware */
342 	const struct firmware		*cap_fw;
343 
344 	/* fence buffer */
345 	struct amdgpu_bo		*fence_buf_bo;
346 	uint64_t			fence_buf_mc_addr;
347 	void				*fence_buf;
348 
349 	/* cmd buffer */
350 	struct amdgpu_bo		*cmd_buf_bo;
351 	uint64_t			cmd_buf_mc_addr;
352 	struct psp_gfx_cmd_resp		*cmd_buf_mem;
353 
354 	/* fence value associated with cmd buffer */
355 	atomic_t			fence_value;
356 	/* flag to mark whether gfx fw autoload is supported or not */
357 	bool				autoload_supported;
358 	/* flag to mark whether df cstate management centralized to PMFW */
359 	bool				pmfw_centralized_cstate_management;
360 
361 	/* xgmi ta firmware and buffer */
362 	const struct firmware		*ta_fw;
363 	uint32_t			ta_fw_version;
364 
365 	uint32_t			cap_fw_version;
366 	uint32_t			cap_feature_version;
367 	uint32_t			cap_ucode_size;
368 
369 	struct ta_context		asd_context;
370 	struct psp_xgmi_context		xgmi_context;
371 	struct psp_ras_context		ras_context;
372 	struct ta_cp_context		hdcp_context;
373 	struct ta_cp_context		dtm_context;
374 	struct ta_cp_context		rap_context;
375 	struct ta_cp_context		securedisplay_context;
376 	struct mutex			mutex;
377 	struct psp_memory_training_context mem_train_ctx;
378 
379 	uint32_t			boot_cfg_bitmask;
380 
381 	char *vbflash_tmp_buf;
382 	size_t vbflash_image_size;
383 	bool vbflash_done;
384 };
385 
386 struct amdgpu_psp_funcs {
387 	bool (*check_fw_loading_status)(struct amdgpu_device *adev,
388 					enum AMDGPU_UCODE_ID);
389 };
390 
391 
392 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
393 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
394 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
395 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
396 #define psp_init_microcode(psp) \
397 		((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
398 #define psp_bootloader_load_kdb(psp) \
399 		((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
400 #define psp_bootloader_load_spl(psp) \
401 		((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
402 #define psp_bootloader_load_sysdrv(psp) \
403 		((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
404 #define psp_bootloader_load_soc_drv(psp) \
405 		((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0)
406 #define psp_bootloader_load_intf_drv(psp) \
407 		((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0)
408 #define psp_bootloader_load_dbg_drv(psp) \
409 		((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0)
410 #define psp_bootloader_load_ras_drv(psp) \
411 		((psp)->funcs->bootloader_load_ras_drv ? \
412 		(psp)->funcs->bootloader_load_ras_drv((psp)) : 0)
413 #define psp_bootloader_load_sos(psp) \
414 		((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
415 #define psp_smu_reload_quirk(psp) \
416 		((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
417 #define psp_mode1_reset(psp) \
418 		((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
419 #define psp_mem_training(psp, ops) \
420 	((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
421 
422 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
423 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
424 
425 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \
426 	((psp)->funcs->load_usbc_pd_fw ? \
427 	(psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL)
428 
429 #define psp_read_usbc_pd_fw(psp, fw_ver) \
430 	((psp)->funcs->read_usbc_pd_fw ? \
431 	(psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
432 
433 #define psp_update_spirom(psp, fw_pri_mc_addr) \
434 	((psp)->funcs->update_spirom ? \
435 	(psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL)
436 
437 #define psp_vbflash_status(psp) \
438 	((psp)->funcs->vbflash_stat ? \
439 	(psp)->funcs->vbflash_stat((psp)) : -EINVAL)
440 
441 extern const struct amd_ip_funcs psp_ip_funcs;
442 
443 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
444 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
445 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
446 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block;
447 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
448 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
449 extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
450 
451 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
452 			uint32_t field_val, uint32_t mask, bool check_changed);
453 
454 int psp_gpu_reset(struct amdgpu_device *adev);
455 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
456 			uint64_t cmd_gpu_addr, int cmd_size);
457 
458 int psp_ta_init_shared_buf(struct psp_context *psp,
459 				  struct ta_mem_context *mem_ctx);
460 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx);
461 int psp_ta_unload(struct psp_context *psp, struct ta_context *context);
462 int psp_ta_load(struct psp_context *psp, struct ta_context *context);
463 int psp_ta_invoke(struct psp_context *psp,
464 			uint32_t ta_cmd_id,
465 			struct ta_context *context);
466 int psp_ta_invoke_indirect(struct psp_context *psp,
467 		  uint32_t ta_cmd_id,
468 		  struct ta_context *context);
469 
470 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta);
471 int psp_xgmi_terminate(struct psp_context *psp);
472 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
473 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
474 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
475 int psp_xgmi_get_topology_info(struct psp_context *psp,
476 			       int number_devices,
477 			       struct psp_xgmi_topology_info *topology,
478 			       bool get_extended_data);
479 int psp_xgmi_set_topology_info(struct psp_context *psp,
480 			       int number_devices,
481 			       struct psp_xgmi_topology_info *topology);
482 
483 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
484 int psp_ras_enable_features(struct psp_context *psp,
485 		union ta_ras_cmd_input *info, bool enable);
486 int psp_ras_trigger_error(struct psp_context *psp,
487 			  struct ta_ras_trigger_error_input *info);
488 int psp_ras_terminate(struct psp_context *psp);
489 
490 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
491 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
492 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status);
493 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
494 
495 int psp_rlc_autoload_start(struct psp_context *psp);
496 
497 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
498 		uint32_t value);
499 int psp_ring_cmd_submit(struct psp_context *psp,
500 			uint64_t cmd_buf_mc_addr,
501 			uint64_t fence_mc_addr,
502 			int index);
503 int psp_init_asd_microcode(struct psp_context *psp,
504 			   const char *chip_name);
505 int psp_init_toc_microcode(struct psp_context *psp,
506 			   const char *chip_name);
507 int psp_init_sos_microcode(struct psp_context *psp,
508 			   const char *chip_name);
509 int psp_init_ta_microcode(struct psp_context *psp,
510 			  const char *chip_name);
511 int psp_init_cap_microcode(struct psp_context *psp,
512 			  const char *chip_name);
513 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
514 					uint64_t *output_ptr);
515 
516 int psp_load_fw_list(struct psp_context *psp,
517 		     struct amdgpu_firmware_info **ucode_list, int ucode_count);
518 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);
519 
520 int is_psp_fw_valid(struct psp_bin_desc bin);
521 
522 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev);
523 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev);
524 #endif
525