1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 32 #define PSP_FENCE_BUFFER_SIZE 0x1000 33 #define PSP_CMD_BUFFER_SIZE 0x1000 34 #define PSP_ASD_SHARED_MEM_SIZE 0x4000 35 #define PSP_XGMI_SHARED_MEM_SIZE 0x4000 36 #define PSP_1_MEG 0x100000 37 #define PSP_TMR_SIZE 0x400000 38 39 struct psp_context; 40 struct psp_xgmi_node_info; 41 struct psp_xgmi_topology_info; 42 43 enum psp_ring_type 44 { 45 PSP_RING_TYPE__INVALID = 0, 46 /* 47 * These values map to the way the PSP kernel identifies the 48 * rings. 49 */ 50 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 51 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 52 }; 53 54 struct psp_ring 55 { 56 enum psp_ring_type ring_type; 57 struct psp_gfx_rb_frame *ring_mem; 58 uint64_t ring_mem_mc_addr; 59 void *ring_mem_handle; 60 uint32_t ring_size; 61 }; 62 63 struct psp_funcs 64 { 65 int (*init_microcode)(struct psp_context *psp); 66 int (*bootloader_load_sysdrv)(struct psp_context *psp); 67 int (*bootloader_load_sos)(struct psp_context *psp); 68 int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode, 69 struct psp_gfx_cmd_resp *cmd); 70 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); 71 int (*ring_create)(struct psp_context *psp, 72 enum psp_ring_type ring_type); 73 int (*ring_stop)(struct psp_context *psp, 74 enum psp_ring_type ring_type); 75 int (*ring_destroy)(struct psp_context *psp, 76 enum psp_ring_type ring_type); 77 int (*cmd_submit)(struct psp_context *psp, 78 struct amdgpu_firmware_info *ucode, 79 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 80 int index); 81 bool (*compare_sram_data)(struct psp_context *psp, 82 struct amdgpu_firmware_info *ucode, 83 enum AMDGPU_UCODE_ID ucode_type); 84 bool (*smu_reload_quirk)(struct psp_context *psp); 85 int (*mode1_reset)(struct psp_context *psp); 86 uint64_t (*xgmi_get_node_id)(struct psp_context *psp); 87 uint64_t (*xgmi_get_hive_id)(struct psp_context *psp); 88 int (*xgmi_get_topology_info)(struct psp_context *psp, int number_devices, 89 struct psp_xgmi_topology_info *topology); 90 int (*xgmi_set_topology_info)(struct psp_context *psp, int number_devices, 91 struct psp_xgmi_topology_info *topology); 92 }; 93 94 struct psp_xgmi_context { 95 uint8_t initialized; 96 uint32_t session_id; 97 struct amdgpu_bo *xgmi_shared_bo; 98 uint64_t xgmi_shared_mc_addr; 99 void *xgmi_shared_buf; 100 }; 101 102 struct psp_context 103 { 104 struct amdgpu_device *adev; 105 struct psp_ring km_ring; 106 struct psp_gfx_cmd_resp *cmd; 107 108 const struct psp_funcs *funcs; 109 110 /* firmware buffer */ 111 struct amdgpu_bo *fw_pri_bo; 112 uint64_t fw_pri_mc_addr; 113 void *fw_pri_buf; 114 115 /* sos firmware */ 116 const struct firmware *sos_fw; 117 uint32_t sos_fw_version; 118 uint32_t sos_feature_version; 119 uint32_t sys_bin_size; 120 uint32_t sos_bin_size; 121 uint8_t *sys_start_addr; 122 uint8_t *sos_start_addr; 123 124 /* tmr buffer */ 125 struct amdgpu_bo *tmr_bo; 126 uint64_t tmr_mc_addr; 127 void *tmr_buf; 128 129 /* asd firmware and buffer */ 130 const struct firmware *asd_fw; 131 uint32_t asd_fw_version; 132 uint32_t asd_feature_version; 133 uint32_t asd_ucode_size; 134 uint8_t *asd_start_addr; 135 struct amdgpu_bo *asd_shared_bo; 136 uint64_t asd_shared_mc_addr; 137 void *asd_shared_buf; 138 139 /* fence buffer */ 140 struct amdgpu_bo *fence_buf_bo; 141 uint64_t fence_buf_mc_addr; 142 void *fence_buf; 143 144 /* cmd buffer */ 145 struct amdgpu_bo *cmd_buf_bo; 146 uint64_t cmd_buf_mc_addr; 147 struct psp_gfx_cmd_resp *cmd_buf_mem; 148 149 /* fence value associated with cmd buffer */ 150 atomic_t fence_value; 151 152 /* xgmi ta firmware and buffer */ 153 const struct firmware *ta_fw; 154 uint32_t ta_xgmi_ucode_version; 155 uint32_t ta_xgmi_ucode_size; 156 uint8_t *ta_xgmi_start_addr; 157 struct psp_xgmi_context xgmi_context; 158 }; 159 160 struct amdgpu_psp_funcs { 161 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 162 enum AMDGPU_UCODE_ID); 163 }; 164 165 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 166 struct psp_xgmi_node_info { 167 uint64_t node_id; 168 uint8_t num_hops; 169 uint8_t is_sharing_enabled; 170 enum ta_xgmi_assigned_sdma_engine sdma_engine; 171 }; 172 173 struct psp_xgmi_topology_info { 174 uint32_t num_nodes; 175 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 176 }; 177 178 #define psp_prep_cmd_buf(ucode, type) (psp)->funcs->prep_cmd_buf((ucode), (type)) 179 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type)) 180 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 181 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 182 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 183 #define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \ 184 (psp)->funcs->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index)) 185 #define psp_compare_sram_data(psp, ucode, type) \ 186 (psp)->funcs->compare_sram_data((psp), (ucode), (type)) 187 #define psp_init_microcode(psp) \ 188 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 189 #define psp_bootloader_load_sysdrv(psp) \ 190 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 191 #define psp_bootloader_load_sos(psp) \ 192 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 193 #define psp_smu_reload_quirk(psp) \ 194 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 195 #define psp_mode1_reset(psp) \ 196 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 197 #define psp_xgmi_get_node_id(psp) \ 198 ((psp)->funcs->xgmi_get_node_id ? (psp)->funcs->xgmi_get_node_id((psp)) : 0) 199 #define psp_xgmi_get_hive_id(psp) \ 200 ((psp)->funcs->xgmi_get_hive_id ? (psp)->funcs->xgmi_get_hive_id((psp)) : 0) 201 #define psp_xgmi_get_topology_info(psp, num_device, topology) \ 202 ((psp)->funcs->xgmi_get_topology_info ? \ 203 (psp)->funcs->xgmi_get_topology_info((psp), (num_device), (topology)) : -EINVAL) 204 #define psp_xgmi_set_topology_info(psp, num_device, topology) \ 205 ((psp)->funcs->xgmi_set_topology_info ? \ 206 (psp)->funcs->xgmi_set_topology_info((psp), (num_device), (topology)) : -EINVAL) 207 208 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) 209 210 extern const struct amd_ip_funcs psp_ip_funcs; 211 212 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 213 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 214 uint32_t field_val, uint32_t mask, bool check_changed); 215 216 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 217 218 int psp_gpu_reset(struct amdgpu_device *adev); 219 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 220 bool psp_support_vmr_ring(struct psp_context *psp); 221 222 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 223 224 #endif 225