1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 33 #define PSP_FENCE_BUFFER_SIZE 0x1000 34 #define PSP_CMD_BUFFER_SIZE 0x1000 35 #define PSP_ASD_SHARED_MEM_SIZE 0x4000 36 #define PSP_XGMI_SHARED_MEM_SIZE 0x4000 37 #define PSP_RAS_SHARED_MEM_SIZE 0x4000 38 #define PSP_1_MEG 0x100000 39 #define PSP_TMR_SIZE 0x400000 40 #define PSP_HDCP_SHARED_MEM_SIZE 0x4000 41 #define PSP_DTM_SHARED_MEM_SIZE 0x4000 42 #define PSP_SHARED_MEM_SIZE 0x4000 43 44 struct psp_context; 45 struct psp_xgmi_node_info; 46 struct psp_xgmi_topology_info; 47 48 enum psp_bootloader_cmd { 49 PSP_BL__LOAD_SYSDRV = 0x10000, 50 PSP_BL__LOAD_SOSDRV = 0x20000, 51 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 52 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 53 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 54 }; 55 56 enum psp_ring_type 57 { 58 PSP_RING_TYPE__INVALID = 0, 59 /* 60 * These values map to the way the PSP kernel identifies the 61 * rings. 62 */ 63 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 64 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 65 }; 66 67 struct psp_ring 68 { 69 enum psp_ring_type ring_type; 70 struct psp_gfx_rb_frame *ring_mem; 71 uint64_t ring_mem_mc_addr; 72 void *ring_mem_handle; 73 uint32_t ring_size; 74 }; 75 76 /* More registers may will be supported */ 77 enum psp_reg_prog_id { 78 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 79 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 80 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 81 PSP_REG_LAST 82 }; 83 84 struct psp_funcs 85 { 86 int (*init_microcode)(struct psp_context *psp); 87 int (*bootloader_load_kdb)(struct psp_context *psp); 88 int (*bootloader_load_sysdrv)(struct psp_context *psp); 89 int (*bootloader_load_sos)(struct psp_context *psp); 90 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); 91 int (*ring_create)(struct psp_context *psp, 92 enum psp_ring_type ring_type); 93 int (*ring_stop)(struct psp_context *psp, 94 enum psp_ring_type ring_type); 95 int (*ring_destroy)(struct psp_context *psp, 96 enum psp_ring_type ring_type); 97 int (*cmd_submit)(struct psp_context *psp, 98 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 99 int index); 100 bool (*compare_sram_data)(struct psp_context *psp, 101 struct amdgpu_firmware_info *ucode, 102 enum AMDGPU_UCODE_ID ucode_type); 103 bool (*smu_reload_quirk)(struct psp_context *psp); 104 int (*mode1_reset)(struct psp_context *psp); 105 int (*xgmi_get_node_id)(struct psp_context *psp, uint64_t *node_id); 106 int (*xgmi_get_hive_id)(struct psp_context *psp, uint64_t *hive_id); 107 int (*xgmi_get_topology_info)(struct psp_context *psp, int number_devices, 108 struct psp_xgmi_topology_info *topology); 109 int (*xgmi_set_topology_info)(struct psp_context *psp, int number_devices, 110 struct psp_xgmi_topology_info *topology); 111 bool (*support_vmr_ring)(struct psp_context *psp); 112 int (*ras_trigger_error)(struct psp_context *psp, 113 struct ta_ras_trigger_error_input *info); 114 int (*ras_cure_posion)(struct psp_context *psp, uint64_t *mode_ptr); 115 int (*rlc_autoload_start)(struct psp_context *psp); 116 int (*mem_training_init)(struct psp_context *psp); 117 void (*mem_training_fini)(struct psp_context *psp); 118 int (*mem_training)(struct psp_context *psp, uint32_t ops); 119 }; 120 121 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 122 struct psp_xgmi_node_info { 123 uint64_t node_id; 124 uint8_t num_hops; 125 uint8_t is_sharing_enabled; 126 enum ta_xgmi_assigned_sdma_engine sdma_engine; 127 }; 128 129 struct psp_xgmi_topology_info { 130 uint32_t num_nodes; 131 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 132 }; 133 134 struct psp_xgmi_context { 135 uint8_t initialized; 136 uint32_t session_id; 137 struct amdgpu_bo *xgmi_shared_bo; 138 uint64_t xgmi_shared_mc_addr; 139 void *xgmi_shared_buf; 140 struct psp_xgmi_topology_info top_info; 141 }; 142 143 struct psp_ras_context { 144 /*ras fw*/ 145 bool ras_initialized; 146 uint32_t session_id; 147 struct amdgpu_bo *ras_shared_bo; 148 uint64_t ras_shared_mc_addr; 149 void *ras_shared_buf; 150 struct amdgpu_ras *ras; 151 }; 152 153 struct psp_hdcp_context { 154 bool hdcp_initialized; 155 uint32_t session_id; 156 struct amdgpu_bo *hdcp_shared_bo; 157 uint64_t hdcp_shared_mc_addr; 158 void *hdcp_shared_buf; 159 }; 160 161 struct psp_dtm_context { 162 bool dtm_initialized; 163 uint32_t session_id; 164 struct amdgpu_bo *dtm_shared_bo; 165 uint64_t dtm_shared_mc_addr; 166 void *dtm_shared_buf; 167 }; 168 169 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 170 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 171 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 172 173 enum psp_memory_training_init_flag { 174 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 175 PSP_MEM_TRAIN_SUPPORT = 0x1, 176 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 177 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 178 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 179 }; 180 181 enum psp_memory_training_ops { 182 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 183 PSP_MEM_TRAIN_SAVE = 0x2, 184 PSP_MEM_TRAIN_RESTORE = 0x4, 185 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 186 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 187 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 188 }; 189 190 struct psp_memory_training_context { 191 /*training data size*/ 192 u64 train_data_size; 193 /* 194 * sys_cache 195 * cpu virtual address 196 * system memory buffer that used to store the training data. 197 */ 198 void *sys_cache; 199 200 /*vram offset of the p2c training data*/ 201 u64 p2c_train_data_offset; 202 struct amdgpu_bo *p2c_bo; 203 204 /*vram offset of the c2p training data*/ 205 u64 c2p_train_data_offset; 206 struct amdgpu_bo *c2p_bo; 207 208 enum psp_memory_training_init_flag init; 209 u32 training_cnt; 210 }; 211 212 struct psp_context 213 { 214 struct amdgpu_device *adev; 215 struct psp_ring km_ring; 216 struct psp_gfx_cmd_resp *cmd; 217 218 const struct psp_funcs *funcs; 219 220 /* firmware buffer */ 221 struct amdgpu_bo *fw_pri_bo; 222 uint64_t fw_pri_mc_addr; 223 void *fw_pri_buf; 224 225 /* sos firmware */ 226 const struct firmware *sos_fw; 227 uint32_t sos_fw_version; 228 uint32_t sos_feature_version; 229 uint32_t sys_bin_size; 230 uint32_t sos_bin_size; 231 uint32_t toc_bin_size; 232 uint32_t kdb_bin_size; 233 uint8_t *sys_start_addr; 234 uint8_t *sos_start_addr; 235 uint8_t *toc_start_addr; 236 uint8_t *kdb_start_addr; 237 238 /* tmr buffer */ 239 struct amdgpu_bo *tmr_bo; 240 uint64_t tmr_mc_addr; 241 242 /* asd firmware and buffer */ 243 const struct firmware *asd_fw; 244 uint32_t asd_fw_version; 245 uint32_t asd_feature_version; 246 uint32_t asd_ucode_size; 247 uint8_t *asd_start_addr; 248 struct amdgpu_bo *asd_shared_bo; 249 uint64_t asd_shared_mc_addr; 250 void *asd_shared_buf; 251 252 /* fence buffer */ 253 struct amdgpu_bo *fence_buf_bo; 254 uint64_t fence_buf_mc_addr; 255 void *fence_buf; 256 257 /* cmd buffer */ 258 struct amdgpu_bo *cmd_buf_bo; 259 uint64_t cmd_buf_mc_addr; 260 struct psp_gfx_cmd_resp *cmd_buf_mem; 261 262 /* fence value associated with cmd buffer */ 263 atomic_t fence_value; 264 /* flag to mark whether gfx fw autoload is supported or not */ 265 bool autoload_supported; 266 267 /* xgmi ta firmware and buffer */ 268 const struct firmware *ta_fw; 269 uint32_t ta_fw_version; 270 uint32_t ta_xgmi_ucode_version; 271 uint32_t ta_xgmi_ucode_size; 272 uint8_t *ta_xgmi_start_addr; 273 uint32_t ta_ras_ucode_version; 274 uint32_t ta_ras_ucode_size; 275 uint8_t *ta_ras_start_addr; 276 277 uint32_t ta_hdcp_ucode_version; 278 uint32_t ta_hdcp_ucode_size; 279 uint8_t *ta_hdcp_start_addr; 280 281 uint32_t ta_dtm_ucode_version; 282 uint32_t ta_dtm_ucode_size; 283 uint8_t *ta_dtm_start_addr; 284 285 struct psp_xgmi_context xgmi_context; 286 struct psp_ras_context ras; 287 struct psp_hdcp_context hdcp_context; 288 struct psp_dtm_context dtm_context; 289 struct mutex mutex; 290 struct psp_memory_training_context mem_train_ctx; 291 }; 292 293 struct amdgpu_psp_funcs { 294 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 295 enum AMDGPU_UCODE_ID); 296 }; 297 298 299 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type)) 300 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 301 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 302 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 303 #define psp_cmd_submit(psp, cmd_mc, fence_mc, index) \ 304 (psp)->funcs->cmd_submit((psp), (cmd_mc), (fence_mc), (index)) 305 #define psp_compare_sram_data(psp, ucode, type) \ 306 (psp)->funcs->compare_sram_data((psp), (ucode), (type)) 307 #define psp_init_microcode(psp) \ 308 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 309 #define psp_bootloader_load_kdb(psp) \ 310 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 311 #define psp_bootloader_load_sysdrv(psp) \ 312 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 313 #define psp_bootloader_load_sos(psp) \ 314 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 315 #define psp_smu_reload_quirk(psp) \ 316 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 317 #define psp_support_vmr_ring(psp) \ 318 ((psp)->funcs->support_vmr_ring ? (psp)->funcs->support_vmr_ring((psp)) : false) 319 #define psp_mode1_reset(psp) \ 320 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 321 #define psp_xgmi_get_node_id(psp, node_id) \ 322 ((psp)->funcs->xgmi_get_node_id ? (psp)->funcs->xgmi_get_node_id((psp), (node_id)) : -EINVAL) 323 #define psp_xgmi_get_hive_id(psp, hive_id) \ 324 ((psp)->funcs->xgmi_get_hive_id ? (psp)->funcs->xgmi_get_hive_id((psp), (hive_id)) : -EINVAL) 325 #define psp_xgmi_get_topology_info(psp, num_device, topology) \ 326 ((psp)->funcs->xgmi_get_topology_info ? \ 327 (psp)->funcs->xgmi_get_topology_info((psp), (num_device), (topology)) : -EINVAL) 328 #define psp_xgmi_set_topology_info(psp, num_device, topology) \ 329 ((psp)->funcs->xgmi_set_topology_info ? \ 330 (psp)->funcs->xgmi_set_topology_info((psp), (num_device), (topology)) : -EINVAL) 331 #define psp_rlc_autoload(psp) \ 332 ((psp)->funcs->rlc_autoload_start ? (psp)->funcs->rlc_autoload_start((psp)) : 0) 333 #define psp_mem_training_init(psp) \ 334 ((psp)->funcs->mem_training_init ? (psp)->funcs->mem_training_init((psp)) : 0) 335 #define psp_mem_training_fini(psp) \ 336 ((psp)->funcs->mem_training_fini ? (psp)->funcs->mem_training_fini((psp)) : 0) 337 #define psp_mem_training(psp, ops) \ 338 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 339 340 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) 341 342 #define psp_ras_trigger_error(psp, info) \ 343 ((psp)->funcs->ras_trigger_error ? \ 344 (psp)->funcs->ras_trigger_error((psp), (info)) : -EINVAL) 345 #define psp_ras_cure_posion(psp, addr) \ 346 ((psp)->funcs->ras_cure_posion ? \ 347 (psp)->funcs->ras_cure_posion(psp, (addr)) : -EINVAL) 348 349 extern const struct amd_ip_funcs psp_ip_funcs; 350 351 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 352 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 353 uint32_t field_val, uint32_t mask, bool check_changed); 354 355 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 356 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 357 358 int psp_gpu_reset(struct amdgpu_device *adev); 359 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 360 uint64_t cmd_gpu_addr, int cmd_size); 361 362 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 363 364 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 365 int psp_ras_enable_features(struct psp_context *psp, 366 union ta_ras_cmd_input *info, bool enable); 367 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 368 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 369 370 int psp_rlc_autoload_start(struct psp_context *psp); 371 372 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 373 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 374 uint32_t value); 375 #endif 376