1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 #include "ta_rap_if.h" 33 #include "ta_secureDisplay_if.h" 34 35 #define PSP_FENCE_BUFFER_SIZE 0x1000 36 #define PSP_CMD_BUFFER_SIZE 0x1000 37 #define PSP_1_MEG 0x100000 38 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) 39 #define PSP_TMR_ALIGNMENT 0x100000 40 #define PSP_FW_NAME_LEN 0x24 41 42 enum psp_shared_mem_size { 43 PSP_ASD_SHARED_MEM_SIZE = 0x0, 44 PSP_XGMI_SHARED_MEM_SIZE = 0x4000, 45 PSP_RAS_SHARED_MEM_SIZE = 0x4000, 46 PSP_HDCP_SHARED_MEM_SIZE = 0x4000, 47 PSP_DTM_SHARED_MEM_SIZE = 0x4000, 48 PSP_RAP_SHARED_MEM_SIZE = 0x4000, 49 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000, 50 }; 51 52 enum ta_type_id { 53 TA_TYPE_XGMI = 1, 54 TA_TYPE_RAS, 55 TA_TYPE_HDCP, 56 TA_TYPE_DTM, 57 TA_TYPE_RAP, 58 TA_TYPE_SECUREDISPLAY, 59 60 TA_TYPE_MAX_INDEX, 61 }; 62 63 struct psp_context; 64 struct psp_xgmi_node_info; 65 struct psp_xgmi_topology_info; 66 struct psp_bin_desc; 67 68 enum psp_bootloader_cmd { 69 PSP_BL__LOAD_SYSDRV = 0x10000, 70 PSP_BL__LOAD_SOSDRV = 0x20000, 71 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 72 PSP_BL__LOAD_SOCDRV = 0xB0000, 73 PSP_BL__LOAD_DBGDRV = 0xC0000, 74 PSP_BL__LOAD_INTFDRV = 0xD0000, 75 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 76 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 77 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, 78 }; 79 80 enum psp_ring_type 81 { 82 PSP_RING_TYPE__INVALID = 0, 83 /* 84 * These values map to the way the PSP kernel identifies the 85 * rings. 86 */ 87 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 88 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 89 }; 90 91 struct psp_ring 92 { 93 enum psp_ring_type ring_type; 94 struct psp_gfx_rb_frame *ring_mem; 95 uint64_t ring_mem_mc_addr; 96 void *ring_mem_handle; 97 uint32_t ring_size; 98 uint32_t ring_wptr; 99 }; 100 101 /* More registers may will be supported */ 102 enum psp_reg_prog_id { 103 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 104 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 105 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 106 PSP_REG_LAST 107 }; 108 109 struct psp_funcs 110 { 111 int (*init_microcode)(struct psp_context *psp); 112 int (*bootloader_load_kdb)(struct psp_context *psp); 113 int (*bootloader_load_spl)(struct psp_context *psp); 114 int (*bootloader_load_sysdrv)(struct psp_context *psp); 115 int (*bootloader_load_soc_drv)(struct psp_context *psp); 116 int (*bootloader_load_intf_drv)(struct psp_context *psp); 117 int (*bootloader_load_dbg_drv)(struct psp_context *psp); 118 int (*bootloader_load_sos)(struct psp_context *psp); 119 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); 120 int (*ring_create)(struct psp_context *psp, 121 enum psp_ring_type ring_type); 122 int (*ring_stop)(struct psp_context *psp, 123 enum psp_ring_type ring_type); 124 int (*ring_destroy)(struct psp_context *psp, 125 enum psp_ring_type ring_type); 126 bool (*smu_reload_quirk)(struct psp_context *psp); 127 int (*mode1_reset)(struct psp_context *psp); 128 int (*mem_training)(struct psp_context *psp, uint32_t ops); 129 uint32_t (*ring_get_wptr)(struct psp_context *psp); 130 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); 131 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 132 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); 133 int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 134 int (*vbflash_stat)(struct psp_context *psp); 135 }; 136 137 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 138 struct psp_xgmi_node_info { 139 uint64_t node_id; 140 uint8_t num_hops; 141 uint8_t is_sharing_enabled; 142 enum ta_xgmi_assigned_sdma_engine sdma_engine; 143 uint8_t num_links; 144 }; 145 146 struct psp_xgmi_topology_info { 147 uint32_t num_nodes; 148 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 149 }; 150 151 struct psp_bin_desc { 152 uint32_t fw_version; 153 uint32_t feature_version; 154 uint32_t size_bytes; 155 uint8_t *start_addr; 156 }; 157 158 struct ta_mem_context { 159 struct amdgpu_bo *shared_bo; 160 uint64_t shared_mc_addr; 161 void *shared_buf; 162 enum psp_shared_mem_size shared_mem_size; 163 }; 164 165 struct ta_context { 166 bool initialized; 167 uint32_t session_id; 168 uint32_t resp_status; 169 struct ta_mem_context mem_context; 170 struct psp_bin_desc bin_desc; 171 enum psp_gfx_cmd_id ta_load_type; 172 enum ta_type_id ta_type; 173 }; 174 175 struct ta_cp_context { 176 struct ta_context context; 177 struct mutex mutex; 178 }; 179 180 struct psp_xgmi_context { 181 struct ta_context context; 182 struct psp_xgmi_topology_info top_info; 183 bool supports_extended_data; 184 }; 185 186 struct psp_ras_context { 187 struct ta_context context; 188 struct amdgpu_ras *ras; 189 }; 190 191 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 192 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 193 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 194 /*Define the VRAM size that will be encroached by BIST training.*/ 195 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 196 197 enum psp_memory_training_init_flag { 198 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 199 PSP_MEM_TRAIN_SUPPORT = 0x1, 200 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 201 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 202 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 203 }; 204 205 enum psp_memory_training_ops { 206 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 207 PSP_MEM_TRAIN_SAVE = 0x2, 208 PSP_MEM_TRAIN_RESTORE = 0x4, 209 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 210 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 211 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 212 }; 213 214 struct psp_memory_training_context { 215 /*training data size*/ 216 u64 train_data_size; 217 /* 218 * sys_cache 219 * cpu virtual address 220 * system memory buffer that used to store the training data. 221 */ 222 void *sys_cache; 223 224 /*vram offset of the p2c training data*/ 225 u64 p2c_train_data_offset; 226 227 /*vram offset of the c2p training data*/ 228 u64 c2p_train_data_offset; 229 struct amdgpu_bo *c2p_bo; 230 231 enum psp_memory_training_init_flag init; 232 u32 training_cnt; 233 bool enable_mem_training; 234 }; 235 236 /** PSP runtime DB **/ 237 #define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000 238 #define PSP_RUNTIME_DB_OFFSET 0x100000 239 #define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5 240 #define PSP_RUNTIME_DB_VER_1 0x0100 241 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40 242 243 enum psp_runtime_entry_type { 244 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0, 245 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1, 246 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */ 247 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */ 248 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */ 249 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */ 250 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */ 251 }; 252 253 /* PSP runtime DB header */ 254 struct psp_runtime_data_header { 255 /* determine the existence of runtime db */ 256 uint16_t cookie; 257 /* version of runtime db */ 258 uint16_t version; 259 }; 260 261 /* PSP runtime DB entry */ 262 struct psp_runtime_entry { 263 /* type of runtime db entry */ 264 uint32_t entry_type; 265 /* offset of entry in bytes */ 266 uint16_t offset; 267 /* size of entry in bytes */ 268 uint16_t size; 269 }; 270 271 /* PSP runtime DB directory */ 272 struct psp_runtime_data_directory { 273 /* number of valid entries */ 274 uint16_t entry_count; 275 /* db entries*/ 276 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT]; 277 }; 278 279 /* PSP runtime DB boot config feature bitmask */ 280 enum psp_runtime_boot_cfg_feature { 281 BOOT_CFG_FEATURE_GECC = 0x1, 282 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2, 283 }; 284 285 /* PSP run time DB SCPM authentication defines */ 286 enum psp_runtime_scpm_authentication { 287 SCPM_DISABLE = 0x0, 288 SCPM_ENABLE = 0x1, 289 SCPM_ENABLE_WITH_SCPM_ERR = 0x2, 290 }; 291 292 /* PSP runtime DB boot config entry */ 293 struct psp_runtime_boot_cfg_entry { 294 uint32_t boot_cfg_bitmask; 295 uint32_t reserved; 296 }; 297 298 /* PSP runtime DB SCPM entry */ 299 struct psp_runtime_scpm_entry { 300 enum psp_runtime_scpm_authentication scpm_status; 301 }; 302 303 struct psp_context 304 { 305 struct amdgpu_device *adev; 306 struct psp_ring km_ring; 307 struct psp_gfx_cmd_resp *cmd; 308 309 const struct psp_funcs *funcs; 310 311 /* firmware buffer */ 312 struct amdgpu_bo *fw_pri_bo; 313 uint64_t fw_pri_mc_addr; 314 void *fw_pri_buf; 315 316 /* sos firmware */ 317 const struct firmware *sos_fw; 318 struct psp_bin_desc sys; 319 struct psp_bin_desc sos; 320 struct psp_bin_desc toc; 321 struct psp_bin_desc kdb; 322 struct psp_bin_desc spl; 323 struct psp_bin_desc rl; 324 struct psp_bin_desc soc_drv; 325 struct psp_bin_desc intf_drv; 326 struct psp_bin_desc dbg_drv; 327 328 /* tmr buffer */ 329 struct amdgpu_bo *tmr_bo; 330 uint64_t tmr_mc_addr; 331 332 /* asd firmware */ 333 const struct firmware *asd_fw; 334 335 /* toc firmware */ 336 const struct firmware *toc_fw; 337 338 /* cap firmware */ 339 const struct firmware *cap_fw; 340 341 /* fence buffer */ 342 struct amdgpu_bo *fence_buf_bo; 343 uint64_t fence_buf_mc_addr; 344 void *fence_buf; 345 346 /* cmd buffer */ 347 struct amdgpu_bo *cmd_buf_bo; 348 uint64_t cmd_buf_mc_addr; 349 struct psp_gfx_cmd_resp *cmd_buf_mem; 350 351 /* fence value associated with cmd buffer */ 352 atomic_t fence_value; 353 /* flag to mark whether gfx fw autoload is supported or not */ 354 bool autoload_supported; 355 /* flag to mark whether df cstate management centralized to PMFW */ 356 bool pmfw_centralized_cstate_management; 357 358 /* xgmi ta firmware and buffer */ 359 const struct firmware *ta_fw; 360 uint32_t ta_fw_version; 361 362 uint32_t cap_fw_version; 363 uint32_t cap_feature_version; 364 uint32_t cap_ucode_size; 365 366 struct ta_context asd_context; 367 struct psp_xgmi_context xgmi_context; 368 struct psp_ras_context ras_context; 369 struct ta_cp_context hdcp_context; 370 struct ta_cp_context dtm_context; 371 struct ta_cp_context rap_context; 372 struct ta_cp_context securedisplay_context; 373 struct mutex mutex; 374 struct psp_memory_training_context mem_train_ctx; 375 376 uint32_t boot_cfg_bitmask; 377 378 char *vbflash_tmp_buf; 379 size_t vbflash_image_size; 380 bool vbflash_done; 381 }; 382 383 struct amdgpu_psp_funcs { 384 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 385 enum AMDGPU_UCODE_ID); 386 }; 387 388 389 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type)) 390 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 391 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 392 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 393 #define psp_init_microcode(psp) \ 394 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 395 #define psp_bootloader_load_kdb(psp) \ 396 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 397 #define psp_bootloader_load_spl(psp) \ 398 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0) 399 #define psp_bootloader_load_sysdrv(psp) \ 400 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 401 #define psp_bootloader_load_soc_drv(psp) \ 402 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0) 403 #define psp_bootloader_load_intf_drv(psp) \ 404 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0) 405 #define psp_bootloader_load_dbg_drv(psp) \ 406 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0) 407 #define psp_bootloader_load_sos(psp) \ 408 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 409 #define psp_smu_reload_quirk(psp) \ 410 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 411 #define psp_mode1_reset(psp) \ 412 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 413 #define psp_mem_training(psp, ops) \ 414 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 415 416 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) 417 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) 418 419 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \ 420 ((psp)->funcs->load_usbc_pd_fw ? \ 421 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL) 422 423 #define psp_read_usbc_pd_fw(psp, fw_ver) \ 424 ((psp)->funcs->read_usbc_pd_fw ? \ 425 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) 426 427 #define psp_update_spirom(psp, fw_pri_mc_addr) \ 428 ((psp)->funcs->update_spirom ? \ 429 (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL) 430 431 #define psp_vbflash_status(psp) \ 432 ((psp)->funcs->vbflash_stat ? \ 433 (psp)->funcs->vbflash_stat((psp)) : -EINVAL) 434 435 extern const struct amd_ip_funcs psp_ip_funcs; 436 437 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 438 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 439 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 440 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block; 441 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 442 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; 443 extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block; 444 445 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 446 uint32_t field_val, uint32_t mask, bool check_changed); 447 448 int psp_gpu_reset(struct amdgpu_device *adev); 449 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 450 uint64_t cmd_gpu_addr, int cmd_size); 451 452 int psp_ta_init_shared_buf(struct psp_context *psp, 453 struct ta_mem_context *mem_ctx); 454 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx); 455 int psp_ta_unload(struct psp_context *psp, struct ta_context *context); 456 int psp_ta_load(struct psp_context *psp, struct ta_context *context); 457 int psp_ta_invoke(struct psp_context *psp, 458 uint32_t ta_cmd_id, 459 struct ta_context *context); 460 int psp_ta_invoke_indirect(struct psp_context *psp, 461 uint32_t ta_cmd_id, 462 struct ta_context *context); 463 464 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta); 465 int psp_xgmi_terminate(struct psp_context *psp); 466 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 467 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); 468 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); 469 int psp_xgmi_get_topology_info(struct psp_context *psp, 470 int number_devices, 471 struct psp_xgmi_topology_info *topology, 472 bool get_extended_data); 473 int psp_xgmi_set_topology_info(struct psp_context *psp, 474 int number_devices, 475 struct psp_xgmi_topology_info *topology); 476 477 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 478 int psp_ras_enable_features(struct psp_context *psp, 479 union ta_ras_cmd_input *info, bool enable); 480 int psp_ras_trigger_error(struct psp_context *psp, 481 struct ta_ras_trigger_error_input *info); 482 int psp_ras_terminate(struct psp_context *psp); 483 484 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 485 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 486 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status); 487 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 488 489 int psp_rlc_autoload_start(struct psp_context *psp); 490 491 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 492 uint32_t value); 493 int psp_ring_cmd_submit(struct psp_context *psp, 494 uint64_t cmd_buf_mc_addr, 495 uint64_t fence_mc_addr, 496 int index); 497 int psp_init_asd_microcode(struct psp_context *psp, 498 const char *chip_name); 499 int psp_init_toc_microcode(struct psp_context *psp, 500 const char *chip_name); 501 int psp_init_sos_microcode(struct psp_context *psp, 502 const char *chip_name); 503 int psp_init_ta_microcode(struct psp_context *psp, 504 const char *chip_name); 505 int psp_init_cap_microcode(struct psp_context *psp, 506 const char *chip_name); 507 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 508 uint64_t *output_ptr); 509 510 int psp_load_fw_list(struct psp_context *psp, 511 struct amdgpu_firmware_info **ucode_list, int ucode_count); 512 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); 513 514 int is_psp_fw_valid(struct psp_bin_desc bin); 515 516 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev); 517 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev); 518 #endif 519