1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 33 #define PSP_FENCE_BUFFER_SIZE 0x1000 34 #define PSP_CMD_BUFFER_SIZE 0x1000 35 #define PSP_XGMI_SHARED_MEM_SIZE 0x4000 36 #define PSP_RAS_SHARED_MEM_SIZE 0x4000 37 #define PSP_1_MEG 0x100000 38 #define PSP_TMR_SIZE 0x400000 39 #define PSP_HDCP_SHARED_MEM_SIZE 0x4000 40 #define PSP_DTM_SHARED_MEM_SIZE 0x4000 41 #define PSP_SHARED_MEM_SIZE 0x4000 42 43 struct psp_context; 44 struct psp_xgmi_node_info; 45 struct psp_xgmi_topology_info; 46 47 enum psp_bootloader_cmd { 48 PSP_BL__LOAD_SYSDRV = 0x10000, 49 PSP_BL__LOAD_SOSDRV = 0x20000, 50 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 51 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 52 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 53 }; 54 55 enum psp_ring_type 56 { 57 PSP_RING_TYPE__INVALID = 0, 58 /* 59 * These values map to the way the PSP kernel identifies the 60 * rings. 61 */ 62 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 63 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 64 }; 65 66 struct psp_ring 67 { 68 enum psp_ring_type ring_type; 69 struct psp_gfx_rb_frame *ring_mem; 70 uint64_t ring_mem_mc_addr; 71 void *ring_mem_handle; 72 uint32_t ring_size; 73 }; 74 75 /* More registers may will be supported */ 76 enum psp_reg_prog_id { 77 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 78 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 79 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 80 PSP_REG_LAST 81 }; 82 83 struct psp_funcs 84 { 85 int (*init_microcode)(struct psp_context *psp); 86 int (*bootloader_load_kdb)(struct psp_context *psp); 87 int (*bootloader_load_sysdrv)(struct psp_context *psp); 88 int (*bootloader_load_sos)(struct psp_context *psp); 89 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); 90 int (*ring_create)(struct psp_context *psp, 91 enum psp_ring_type ring_type); 92 int (*ring_stop)(struct psp_context *psp, 93 enum psp_ring_type ring_type); 94 int (*ring_destroy)(struct psp_context *psp, 95 enum psp_ring_type ring_type); 96 bool (*smu_reload_quirk)(struct psp_context *psp); 97 int (*mode1_reset)(struct psp_context *psp); 98 int (*mem_training)(struct psp_context *psp, uint32_t ops); 99 uint32_t (*ring_get_wptr)(struct psp_context *psp); 100 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); 101 int (*load_usbc_pd_fw)(struct psp_context *psp, dma_addr_t dma_addr); 102 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); 103 }; 104 105 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 106 struct psp_xgmi_node_info { 107 uint64_t node_id; 108 uint8_t num_hops; 109 uint8_t is_sharing_enabled; 110 enum ta_xgmi_assigned_sdma_engine sdma_engine; 111 }; 112 113 struct psp_xgmi_topology_info { 114 uint32_t num_nodes; 115 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 116 }; 117 118 struct psp_asd_context { 119 bool asd_initialized; 120 uint32_t session_id; 121 }; 122 123 struct psp_xgmi_context { 124 uint8_t initialized; 125 uint32_t session_id; 126 struct amdgpu_bo *xgmi_shared_bo; 127 uint64_t xgmi_shared_mc_addr; 128 void *xgmi_shared_buf; 129 struct psp_xgmi_topology_info top_info; 130 }; 131 132 struct psp_ras_context { 133 /*ras fw*/ 134 bool ras_initialized; 135 uint32_t session_id; 136 struct amdgpu_bo *ras_shared_bo; 137 uint64_t ras_shared_mc_addr; 138 void *ras_shared_buf; 139 struct amdgpu_ras *ras; 140 }; 141 142 struct psp_hdcp_context { 143 bool hdcp_initialized; 144 uint32_t session_id; 145 struct amdgpu_bo *hdcp_shared_bo; 146 uint64_t hdcp_shared_mc_addr; 147 void *hdcp_shared_buf; 148 struct mutex mutex; 149 }; 150 151 struct psp_dtm_context { 152 bool dtm_initialized; 153 uint32_t session_id; 154 struct amdgpu_bo *dtm_shared_bo; 155 uint64_t dtm_shared_mc_addr; 156 void *dtm_shared_buf; 157 struct mutex mutex; 158 }; 159 160 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 161 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 162 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 163 /*Define the VRAM size that will be encroached by BIST training.*/ 164 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 165 166 enum psp_memory_training_init_flag { 167 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 168 PSP_MEM_TRAIN_SUPPORT = 0x1, 169 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 170 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 171 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 172 }; 173 174 enum psp_memory_training_ops { 175 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 176 PSP_MEM_TRAIN_SAVE = 0x2, 177 PSP_MEM_TRAIN_RESTORE = 0x4, 178 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 179 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 180 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 181 }; 182 183 struct psp_memory_training_context { 184 /*training data size*/ 185 u64 train_data_size; 186 /* 187 * sys_cache 188 * cpu virtual address 189 * system memory buffer that used to store the training data. 190 */ 191 void *sys_cache; 192 193 /*vram offset of the p2c training data*/ 194 u64 p2c_train_data_offset; 195 196 /*vram offset of the c2p training data*/ 197 u64 c2p_train_data_offset; 198 struct amdgpu_bo *c2p_bo; 199 200 enum psp_memory_training_init_flag init; 201 u32 training_cnt; 202 }; 203 204 struct psp_context 205 { 206 struct amdgpu_device *adev; 207 struct psp_ring km_ring; 208 struct psp_gfx_cmd_resp *cmd; 209 210 const struct psp_funcs *funcs; 211 212 /* firmware buffer */ 213 struct amdgpu_bo *fw_pri_bo; 214 uint64_t fw_pri_mc_addr; 215 void *fw_pri_buf; 216 217 /* sos firmware */ 218 const struct firmware *sos_fw; 219 uint32_t sos_fw_version; 220 uint32_t sos_feature_version; 221 uint32_t sys_bin_size; 222 uint32_t sos_bin_size; 223 uint32_t toc_bin_size; 224 uint32_t kdb_bin_size; 225 uint8_t *sys_start_addr; 226 uint8_t *sos_start_addr; 227 uint8_t *toc_start_addr; 228 uint8_t *kdb_start_addr; 229 230 /* tmr buffer */ 231 struct amdgpu_bo *tmr_bo; 232 uint64_t tmr_mc_addr; 233 234 /* asd firmware */ 235 const struct firmware *asd_fw; 236 uint32_t asd_fw_version; 237 uint32_t asd_feature_version; 238 uint32_t asd_ucode_size; 239 uint8_t *asd_start_addr; 240 241 /* fence buffer */ 242 struct amdgpu_bo *fence_buf_bo; 243 uint64_t fence_buf_mc_addr; 244 void *fence_buf; 245 246 /* cmd buffer */ 247 struct amdgpu_bo *cmd_buf_bo; 248 uint64_t cmd_buf_mc_addr; 249 struct psp_gfx_cmd_resp *cmd_buf_mem; 250 251 /* fence value associated with cmd buffer */ 252 atomic_t fence_value; 253 /* flag to mark whether gfx fw autoload is supported or not */ 254 bool autoload_supported; 255 /* flag to mark whether df cstate management centralized to PMFW */ 256 bool pmfw_centralized_cstate_management; 257 258 /* xgmi ta firmware and buffer */ 259 const struct firmware *ta_fw; 260 uint32_t ta_fw_version; 261 uint32_t ta_xgmi_ucode_version; 262 uint32_t ta_xgmi_ucode_size; 263 uint8_t *ta_xgmi_start_addr; 264 uint32_t ta_ras_ucode_version; 265 uint32_t ta_ras_ucode_size; 266 uint8_t *ta_ras_start_addr; 267 268 uint32_t ta_hdcp_ucode_version; 269 uint32_t ta_hdcp_ucode_size; 270 uint8_t *ta_hdcp_start_addr; 271 272 uint32_t ta_dtm_ucode_version; 273 uint32_t ta_dtm_ucode_size; 274 uint8_t *ta_dtm_start_addr; 275 276 struct psp_asd_context asd_context; 277 struct psp_xgmi_context xgmi_context; 278 struct psp_ras_context ras; 279 struct psp_hdcp_context hdcp_context; 280 struct psp_dtm_context dtm_context; 281 struct mutex mutex; 282 struct psp_memory_training_context mem_train_ctx; 283 }; 284 285 struct amdgpu_psp_funcs { 286 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 287 enum AMDGPU_UCODE_ID); 288 }; 289 290 291 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type)) 292 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 293 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 294 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 295 #define psp_init_microcode(psp) \ 296 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 297 #define psp_bootloader_load_kdb(psp) \ 298 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 299 #define psp_bootloader_load_sysdrv(psp) \ 300 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 301 #define psp_bootloader_load_sos(psp) \ 302 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 303 #define psp_smu_reload_quirk(psp) \ 304 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 305 #define psp_mode1_reset(psp) \ 306 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 307 #define psp_mem_training(psp, ops) \ 308 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 309 310 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) 311 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) 312 313 #define psp_load_usbc_pd_fw(psp, dma_addr) \ 314 ((psp)->funcs->load_usbc_pd_fw ? \ 315 (psp)->funcs->load_usbc_pd_fw((psp), (dma_addr)) : -EINVAL) 316 317 #define psp_read_usbc_pd_fw(psp, fw_ver) \ 318 ((psp)->funcs->read_usbc_pd_fw ? \ 319 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) 320 321 extern const struct amd_ip_funcs psp_ip_funcs; 322 323 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 324 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 325 uint32_t field_val, uint32_t mask, bool check_changed); 326 327 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 328 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 329 330 int psp_gpu_reset(struct amdgpu_device *adev); 331 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 332 uint64_t cmd_gpu_addr, int cmd_size); 333 334 int psp_xgmi_initialize(struct psp_context *psp); 335 int psp_xgmi_terminate(struct psp_context *psp); 336 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 337 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); 338 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); 339 int psp_xgmi_get_topology_info(struct psp_context *psp, 340 int number_devices, 341 struct psp_xgmi_topology_info *topology); 342 int psp_xgmi_set_topology_info(struct psp_context *psp, 343 int number_devices, 344 struct psp_xgmi_topology_info *topology); 345 346 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 347 int psp_ras_enable_features(struct psp_context *psp, 348 union ta_ras_cmd_input *info, bool enable); 349 int psp_ras_trigger_error(struct psp_context *psp, 350 struct ta_ras_trigger_error_input *info); 351 352 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 353 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 354 355 int psp_rlc_autoload_start(struct psp_context *psp); 356 357 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 358 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 359 uint32_t value); 360 int psp_ring_cmd_submit(struct psp_context *psp, 361 uint64_t cmd_buf_mc_addr, 362 uint64_t fence_mc_addr, 363 int index); 364 int psp_init_asd_microcode(struct psp_context *psp, 365 const char *chip_name); 366 int psp_init_sos_microcode(struct psp_context *psp, 367 const char *chip_name); 368 #endif 369