1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 41 #include "amdgpu_ras.h" 42 #include "amdgpu_securedisplay.h" 43 #include "amdgpu_atomfirmware.h" 44 45 static int psp_sysfs_init(struct amdgpu_device *adev); 46 static void psp_sysfs_fini(struct amdgpu_device *adev); 47 48 static int psp_load_smu_fw(struct psp_context *psp); 49 static int psp_rap_terminate(struct psp_context *psp); 50 static int psp_securedisplay_terminate(struct psp_context *psp); 51 52 /* 53 * Due to DF Cstate management centralized to PMFW, the firmware 54 * loading sequence will be updated as below: 55 * - Load KDB 56 * - Load SYS_DRV 57 * - Load tOS 58 * - Load PMFW 59 * - Setup TMR 60 * - Load other non-psp fw 61 * - Load ASD 62 * - Load XGMI/RAS/HDCP/DTM TA if any 63 * 64 * This new sequence is required for 65 * - Arcturus and onwards 66 */ 67 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 68 { 69 struct amdgpu_device *adev = psp->adev; 70 71 if (amdgpu_sriov_vf(adev)) { 72 psp->pmfw_centralized_cstate_management = false; 73 return; 74 } 75 76 switch (adev->ip_versions[MP0_HWIP][0]) { 77 case IP_VERSION(11, 0, 0): 78 case IP_VERSION(11, 0, 4): 79 case IP_VERSION(11, 0, 5): 80 case IP_VERSION(11, 0, 7): 81 case IP_VERSION(11, 0, 9): 82 case IP_VERSION(11, 0, 11): 83 case IP_VERSION(11, 0, 12): 84 case IP_VERSION(11, 0, 13): 85 case IP_VERSION(13, 0, 0): 86 case IP_VERSION(13, 0, 2): 87 psp->pmfw_centralized_cstate_management = true; 88 break; 89 default: 90 psp->pmfw_centralized_cstate_management = false; 91 break; 92 } 93 } 94 95 static int psp_early_init(void *handle) 96 { 97 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 98 struct psp_context *psp = &adev->psp; 99 100 switch (adev->ip_versions[MP0_HWIP][0]) { 101 case IP_VERSION(9, 0, 0): 102 psp_v3_1_set_psp_funcs(psp); 103 psp->autoload_supported = false; 104 break; 105 case IP_VERSION(10, 0, 0): 106 case IP_VERSION(10, 0, 1): 107 psp_v10_0_set_psp_funcs(psp); 108 psp->autoload_supported = false; 109 break; 110 case IP_VERSION(11, 0, 2): 111 case IP_VERSION(11, 0, 4): 112 psp_v11_0_set_psp_funcs(psp); 113 psp->autoload_supported = false; 114 break; 115 case IP_VERSION(11, 0, 0): 116 case IP_VERSION(11, 0, 5): 117 case IP_VERSION(11, 0, 9): 118 case IP_VERSION(11, 0, 7): 119 case IP_VERSION(11, 0, 11): 120 case IP_VERSION(11, 5, 0): 121 case IP_VERSION(11, 0, 12): 122 case IP_VERSION(11, 0, 13): 123 psp_v11_0_set_psp_funcs(psp); 124 psp->autoload_supported = true; 125 break; 126 case IP_VERSION(11, 0, 3): 127 case IP_VERSION(12, 0, 1): 128 psp_v12_0_set_psp_funcs(psp); 129 break; 130 case IP_VERSION(13, 0, 2): 131 psp_v13_0_set_psp_funcs(psp); 132 break; 133 case IP_VERSION(13, 0, 1): 134 case IP_VERSION(13, 0, 3): 135 case IP_VERSION(13, 0, 5): 136 case IP_VERSION(13, 0, 8): 137 psp_v13_0_set_psp_funcs(psp); 138 psp->autoload_supported = true; 139 break; 140 case IP_VERSION(11, 0, 8): 141 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 142 psp_v11_0_8_set_psp_funcs(psp); 143 psp->autoload_supported = false; 144 } 145 break; 146 case IP_VERSION(13, 0, 0): 147 psp_v13_0_set_psp_funcs(psp); 148 psp->autoload_supported = true; 149 break; 150 default: 151 return -EINVAL; 152 } 153 154 psp->adev = adev; 155 156 psp_check_pmfw_centralized_cstate_management(psp); 157 158 return 0; 159 } 160 161 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 162 { 163 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 164 &mem_ctx->shared_buf); 165 } 166 167 static void psp_free_shared_bufs(struct psp_context *psp) 168 { 169 void *tmr_buf; 170 void **pptr; 171 172 /* free TMR memory buffer */ 173 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 174 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 175 176 /* free xgmi shared memory */ 177 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 178 179 /* free ras shared memory */ 180 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 181 182 /* free hdcp shared memory */ 183 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 184 185 /* free dtm shared memory */ 186 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 187 188 /* free rap shared memory */ 189 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 190 191 /* free securedisplay shared memory */ 192 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 193 194 195 } 196 197 static void psp_memory_training_fini(struct psp_context *psp) 198 { 199 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 200 201 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 202 kfree(ctx->sys_cache); 203 ctx->sys_cache = NULL; 204 } 205 206 static int psp_memory_training_init(struct psp_context *psp) 207 { 208 int ret; 209 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 210 211 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 212 DRM_DEBUG("memory training is not supported!\n"); 213 return 0; 214 } 215 216 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 217 if (ctx->sys_cache == NULL) { 218 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 219 ret = -ENOMEM; 220 goto Err_out; 221 } 222 223 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 224 ctx->train_data_size, 225 ctx->p2c_train_data_offset, 226 ctx->c2p_train_data_offset); 227 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 228 return 0; 229 230 Err_out: 231 psp_memory_training_fini(psp); 232 return ret; 233 } 234 235 /* 236 * Helper funciton to query psp runtime database entry 237 * 238 * @adev: amdgpu_device pointer 239 * @entry_type: the type of psp runtime database entry 240 * @db_entry: runtime database entry pointer 241 * 242 * Return false if runtime database doesn't exit or entry is invalid 243 * or true if the specific database entry is found, and copy to @db_entry 244 */ 245 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 246 enum psp_runtime_entry_type entry_type, 247 void *db_entry) 248 { 249 uint64_t db_header_pos, db_dir_pos; 250 struct psp_runtime_data_header db_header = {0}; 251 struct psp_runtime_data_directory db_dir = {0}; 252 bool ret = false; 253 int i; 254 255 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 256 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 257 258 /* read runtime db header from vram */ 259 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 260 sizeof(struct psp_runtime_data_header), false); 261 262 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 263 /* runtime db doesn't exist, exit */ 264 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 265 return false; 266 } 267 268 /* read runtime database entry from vram */ 269 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 270 sizeof(struct psp_runtime_data_directory), false); 271 272 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 273 /* invalid db entry count, exit */ 274 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 275 return false; 276 } 277 278 /* look up for requested entry type */ 279 for (i = 0; i < db_dir.entry_count && !ret; i++) { 280 if (db_dir.entry_list[i].entry_type == entry_type) { 281 switch (entry_type) { 282 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 283 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 284 /* invalid db entry size */ 285 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 286 return false; 287 } 288 /* read runtime database entry */ 289 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 290 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 291 ret = true; 292 break; 293 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 294 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 295 /* invalid db entry size */ 296 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 297 return false; 298 } 299 /* read runtime database entry */ 300 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 301 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 302 ret = true; 303 break; 304 default: 305 ret = false; 306 break; 307 } 308 } 309 } 310 311 return ret; 312 } 313 314 static int psp_init_sriov_microcode(struct psp_context *psp) 315 { 316 struct amdgpu_device *adev = psp->adev; 317 int ret = 0; 318 319 switch (adev->ip_versions[MP0_HWIP][0]) { 320 case IP_VERSION(9, 0, 0): 321 ret = psp_init_cap_microcode(psp, "vega10"); 322 break; 323 case IP_VERSION(11, 0, 9): 324 ret = psp_init_cap_microcode(psp, "navi12"); 325 break; 326 case IP_VERSION(11, 0, 7): 327 ret = psp_init_cap_microcode(psp, "sienna_cichlid"); 328 break; 329 case IP_VERSION(13, 0, 2): 330 ret = psp_init_cap_microcode(psp, "aldebaran"); 331 ret &= psp_init_ta_microcode(psp, "aldebaran"); 332 break; 333 default: 334 BUG(); 335 break; 336 } 337 338 return ret; 339 } 340 341 static int psp_sw_init(void *handle) 342 { 343 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 344 struct psp_context *psp = &adev->psp; 345 int ret; 346 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 347 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 348 struct psp_runtime_scpm_entry scpm_entry; 349 350 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 351 if (!psp->cmd) { 352 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 353 ret = -ENOMEM; 354 } 355 356 if (amdgpu_sriov_vf(adev)) 357 ret = psp_init_sriov_microcode(psp); 358 else 359 ret = psp_init_microcode(psp); 360 if (ret) { 361 DRM_ERROR("Failed to load psp firmware!\n"); 362 return ret; 363 } 364 365 adev->psp.xgmi_context.supports_extended_data = 366 !adev->gmc.xgmi.connected_to_cpu && 367 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 368 369 memset(&scpm_entry, 0, sizeof(scpm_entry)); 370 if ((psp_get_runtime_db_entry(adev, 371 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 372 &scpm_entry)) && 373 (SCPM_DISABLE != scpm_entry.scpm_status)) { 374 adev->scpm_enabled = true; 375 adev->scpm_status = scpm_entry.scpm_status; 376 } else { 377 adev->scpm_enabled = false; 378 adev->scpm_status = SCPM_DISABLE; 379 } 380 381 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 382 383 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 384 if (psp_get_runtime_db_entry(adev, 385 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 386 &boot_cfg_entry)) { 387 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 388 if ((psp->boot_cfg_bitmask) & 389 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 390 /* If psp runtime database exists, then 391 * only enable two stage memory training 392 * when TWO_STAGE_DRAM_TRAINING bit is set 393 * in runtime database */ 394 mem_training_ctx->enable_mem_training = true; 395 } 396 397 } else { 398 /* If psp runtime database doesn't exist or 399 * is invalid, force enable two stage memory 400 * training */ 401 mem_training_ctx->enable_mem_training = true; 402 } 403 404 if (mem_training_ctx->enable_mem_training) { 405 ret = psp_memory_training_init(psp); 406 if (ret) { 407 DRM_ERROR("Failed to initialize memory training!\n"); 408 return ret; 409 } 410 411 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 412 if (ret) { 413 DRM_ERROR("Failed to process memory training!\n"); 414 return ret; 415 } 416 } 417 418 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 419 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 420 ret= psp_sysfs_init(adev); 421 if (ret) { 422 return ret; 423 } 424 } 425 426 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 427 amdgpu_sriov_vf(adev) ? 428 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 429 &psp->fw_pri_bo, 430 &psp->fw_pri_mc_addr, 431 &psp->fw_pri_buf); 432 if (ret) 433 return ret; 434 435 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 436 AMDGPU_GEM_DOMAIN_VRAM, 437 &psp->fence_buf_bo, 438 &psp->fence_buf_mc_addr, 439 &psp->fence_buf); 440 if (ret) 441 goto failed1; 442 443 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 444 AMDGPU_GEM_DOMAIN_VRAM, 445 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 446 (void **)&psp->cmd_buf_mem); 447 if (ret) 448 goto failed2; 449 450 return 0; 451 452 failed2: 453 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 454 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 455 failed1: 456 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 457 &psp->fence_buf_mc_addr, &psp->fence_buf); 458 return ret; 459 } 460 461 static int psp_sw_fini(void *handle) 462 { 463 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 464 struct psp_context *psp = &adev->psp; 465 struct psp_gfx_cmd_resp *cmd = psp->cmd; 466 467 psp_memory_training_fini(psp); 468 if (psp->sos_fw) { 469 release_firmware(psp->sos_fw); 470 psp->sos_fw = NULL; 471 } 472 if (psp->asd_fw) { 473 release_firmware(psp->asd_fw); 474 psp->asd_fw = NULL; 475 } 476 if (psp->ta_fw) { 477 release_firmware(psp->ta_fw); 478 psp->ta_fw = NULL; 479 } 480 if (adev->psp.cap_fw) { 481 release_firmware(psp->cap_fw); 482 psp->cap_fw = NULL; 483 } 484 485 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 486 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 487 psp_sysfs_fini(adev); 488 489 kfree(cmd); 490 cmd = NULL; 491 492 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 493 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 494 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 495 &psp->fence_buf_mc_addr, &psp->fence_buf); 496 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 497 (void **)&psp->cmd_buf_mem); 498 499 return 0; 500 } 501 502 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 503 uint32_t reg_val, uint32_t mask, bool check_changed) 504 { 505 uint32_t val; 506 int i; 507 struct amdgpu_device *adev = psp->adev; 508 509 if (psp->adev->no_hw_access) 510 return 0; 511 512 for (i = 0; i < adev->usec_timeout; i++) { 513 val = RREG32(reg_index); 514 if (check_changed) { 515 if (val != reg_val) 516 return 0; 517 } else { 518 if ((val & mask) == reg_val) 519 return 0; 520 } 521 udelay(1); 522 } 523 524 return -ETIME; 525 } 526 527 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 528 { 529 switch (cmd_id) { 530 case GFX_CMD_ID_LOAD_TA: 531 return "LOAD_TA"; 532 case GFX_CMD_ID_UNLOAD_TA: 533 return "UNLOAD_TA"; 534 case GFX_CMD_ID_INVOKE_CMD: 535 return "INVOKE_CMD"; 536 case GFX_CMD_ID_LOAD_ASD: 537 return "LOAD_ASD"; 538 case GFX_CMD_ID_SETUP_TMR: 539 return "SETUP_TMR"; 540 case GFX_CMD_ID_LOAD_IP_FW: 541 return "LOAD_IP_FW"; 542 case GFX_CMD_ID_DESTROY_TMR: 543 return "DESTROY_TMR"; 544 case GFX_CMD_ID_SAVE_RESTORE: 545 return "SAVE_RESTORE_IP_FW"; 546 case GFX_CMD_ID_SETUP_VMR: 547 return "SETUP_VMR"; 548 case GFX_CMD_ID_DESTROY_VMR: 549 return "DESTROY_VMR"; 550 case GFX_CMD_ID_PROG_REG: 551 return "PROG_REG"; 552 case GFX_CMD_ID_GET_FW_ATTESTATION: 553 return "GET_FW_ATTESTATION"; 554 case GFX_CMD_ID_LOAD_TOC: 555 return "ID_LOAD_TOC"; 556 case GFX_CMD_ID_AUTOLOAD_RLC: 557 return "AUTOLOAD_RLC"; 558 case GFX_CMD_ID_BOOT_CFG: 559 return "BOOT_CFG"; 560 default: 561 return "UNKNOWN CMD"; 562 } 563 } 564 565 static int 566 psp_cmd_submit_buf(struct psp_context *psp, 567 struct amdgpu_firmware_info *ucode, 568 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 569 { 570 int ret; 571 int index, idx; 572 int timeout = 20000; 573 bool ras_intr = false; 574 bool skip_unsupport = false; 575 576 if (psp->adev->no_hw_access) 577 return 0; 578 579 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 580 return 0; 581 582 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 583 584 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 585 586 index = atomic_inc_return(&psp->fence_value); 587 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 588 if (ret) { 589 atomic_dec(&psp->fence_value); 590 goto exit; 591 } 592 593 amdgpu_device_invalidate_hdp(psp->adev, NULL); 594 while (*((unsigned int *)psp->fence_buf) != index) { 595 if (--timeout == 0) 596 break; 597 /* 598 * Shouldn't wait for timeout when err_event_athub occurs, 599 * because gpu reset thread triggered and lock resource should 600 * be released for psp resume sequence. 601 */ 602 ras_intr = amdgpu_ras_intr_triggered(); 603 if (ras_intr) 604 break; 605 usleep_range(10, 100); 606 amdgpu_device_invalidate_hdp(psp->adev, NULL); 607 } 608 609 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 610 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 611 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 612 613 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 614 615 /* In some cases, psp response status is not 0 even there is no 616 * problem while the command is submitted. Some version of PSP FW 617 * doesn't write 0 to that field. 618 * So here we would like to only print a warning instead of an error 619 * during psp initialization to avoid breaking hw_init and it doesn't 620 * return -EINVAL. 621 */ 622 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 623 if (ucode) 624 DRM_WARN("failed to load ucode %s(0x%X) ", 625 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 626 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 627 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 628 psp->cmd_buf_mem->resp.status); 629 /* If we load CAP FW, PSP must return 0 under SRIOV 630 * also return failure in case of timeout 631 */ 632 if ((ucode && (ucode->ucode_id == AMDGPU_UCODE_ID_CAP)) || !timeout) { 633 ret = -EINVAL; 634 goto exit; 635 } 636 } 637 638 if (ucode) { 639 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 640 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 641 } 642 643 exit: 644 drm_dev_exit(idx); 645 return ret; 646 } 647 648 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 649 { 650 struct psp_gfx_cmd_resp *cmd = psp->cmd; 651 652 mutex_lock(&psp->mutex); 653 654 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 655 656 return cmd; 657 } 658 659 static void release_psp_cmd_buf(struct psp_context *psp) 660 { 661 mutex_unlock(&psp->mutex); 662 } 663 664 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 665 struct psp_gfx_cmd_resp *cmd, 666 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 667 { 668 struct amdgpu_device *adev = psp->adev; 669 uint32_t size = amdgpu_bo_size(tmr_bo); 670 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 671 672 if (amdgpu_sriov_vf(psp->adev)) 673 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 674 else 675 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 676 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 677 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 678 cmd->cmd.cmd_setup_tmr.buf_size = size; 679 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 680 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 681 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 682 } 683 684 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 685 uint64_t pri_buf_mc, uint32_t size) 686 { 687 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 688 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 689 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 690 cmd->cmd.cmd_load_toc.toc_size = size; 691 } 692 693 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 694 static int psp_load_toc(struct psp_context *psp, 695 uint32_t *tmr_size) 696 { 697 int ret; 698 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 699 700 /* Copy toc to psp firmware private buffer */ 701 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 702 703 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 704 705 ret = psp_cmd_submit_buf(psp, NULL, cmd, 706 psp->fence_buf_mc_addr); 707 if (!ret) 708 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 709 710 release_psp_cmd_buf(psp); 711 712 return ret; 713 } 714 715 /* Set up Trusted Memory Region */ 716 static int psp_tmr_init(struct psp_context *psp) 717 { 718 int ret; 719 int tmr_size; 720 void *tmr_buf; 721 void **pptr; 722 723 /* 724 * According to HW engineer, they prefer the TMR address be "naturally 725 * aligned" , e.g. the start address be an integer divide of TMR size. 726 * 727 * Note: this memory need be reserved till the driver 728 * uninitializes. 729 */ 730 tmr_size = PSP_TMR_SIZE(psp->adev); 731 732 /* For ASICs support RLC autoload, psp will parse the toc 733 * and calculate the total size of TMR needed */ 734 if (!amdgpu_sriov_vf(psp->adev) && 735 psp->toc.start_addr && 736 psp->toc.size_bytes && 737 psp->fw_pri_buf) { 738 ret = psp_load_toc(psp, &tmr_size); 739 if (ret) { 740 DRM_ERROR("Failed to load toc\n"); 741 return ret; 742 } 743 } 744 745 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 746 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 747 AMDGPU_GEM_DOMAIN_VRAM, 748 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 749 750 return ret; 751 } 752 753 static bool psp_skip_tmr(struct psp_context *psp) 754 { 755 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 756 case IP_VERSION(11, 0, 9): 757 case IP_VERSION(11, 0, 7): 758 case IP_VERSION(13, 0, 2): 759 return true; 760 default: 761 return false; 762 } 763 } 764 765 static int psp_tmr_load(struct psp_context *psp) 766 { 767 int ret; 768 struct psp_gfx_cmd_resp *cmd; 769 770 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 771 * Already set up by host driver. 772 */ 773 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 774 return 0; 775 776 cmd = acquire_psp_cmd_buf(psp); 777 778 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 779 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 780 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 781 782 ret = psp_cmd_submit_buf(psp, NULL, cmd, 783 psp->fence_buf_mc_addr); 784 785 release_psp_cmd_buf(psp); 786 787 return ret; 788 } 789 790 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 791 struct psp_gfx_cmd_resp *cmd) 792 { 793 if (amdgpu_sriov_vf(psp->adev)) 794 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 795 else 796 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 797 } 798 799 static int psp_tmr_unload(struct psp_context *psp) 800 { 801 int ret; 802 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 803 804 psp_prep_tmr_unload_cmd_buf(psp, cmd); 805 DRM_INFO("free PSP TMR buffer\n"); 806 807 ret = psp_cmd_submit_buf(psp, NULL, cmd, 808 psp->fence_buf_mc_addr); 809 810 release_psp_cmd_buf(psp); 811 812 return ret; 813 } 814 815 static int psp_tmr_terminate(struct psp_context *psp) 816 { 817 return psp_tmr_unload(psp); 818 } 819 820 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 821 uint64_t *output_ptr) 822 { 823 int ret; 824 struct psp_gfx_cmd_resp *cmd; 825 826 if (!output_ptr) 827 return -EINVAL; 828 829 if (amdgpu_sriov_vf(psp->adev)) 830 return 0; 831 832 cmd = acquire_psp_cmd_buf(psp); 833 834 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 835 836 ret = psp_cmd_submit_buf(psp, NULL, cmd, 837 psp->fence_buf_mc_addr); 838 839 if (!ret) { 840 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 841 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 842 } 843 844 release_psp_cmd_buf(psp); 845 846 return ret; 847 } 848 849 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 850 { 851 struct psp_context *psp = &adev->psp; 852 struct psp_gfx_cmd_resp *cmd; 853 int ret; 854 855 if (amdgpu_sriov_vf(adev)) 856 return 0; 857 858 cmd = acquire_psp_cmd_buf(psp); 859 860 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 861 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 862 863 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 864 if (!ret) { 865 *boot_cfg = 866 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 867 } 868 869 release_psp_cmd_buf(psp); 870 871 return ret; 872 } 873 874 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 875 { 876 int ret; 877 struct psp_context *psp = &adev->psp; 878 struct psp_gfx_cmd_resp *cmd; 879 880 if (amdgpu_sriov_vf(adev)) 881 return 0; 882 883 cmd = acquire_psp_cmd_buf(psp); 884 885 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 886 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 887 cmd->cmd.boot_cfg.boot_config = boot_cfg; 888 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 889 890 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 891 892 release_psp_cmd_buf(psp); 893 894 return ret; 895 } 896 897 static int psp_rl_load(struct amdgpu_device *adev) 898 { 899 int ret; 900 struct psp_context *psp = &adev->psp; 901 struct psp_gfx_cmd_resp *cmd; 902 903 if (!is_psp_fw_valid(psp->rl)) 904 return 0; 905 906 cmd = acquire_psp_cmd_buf(psp); 907 908 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 909 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 910 911 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 912 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 913 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 914 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 915 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 916 917 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 918 919 release_psp_cmd_buf(psp); 920 921 return ret; 922 } 923 924 static int psp_asd_initialize(struct psp_context *psp) 925 { 926 int ret; 927 928 /* If PSP version doesn't match ASD version, asd loading will be failed. 929 * add workaround to bypass it for sriov now. 930 * TODO: add version check to make it common 931 */ 932 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 933 return 0; 934 935 psp->asd_context.mem_context.shared_mc_addr = 0; 936 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 937 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 938 939 ret = psp_ta_load(psp, &psp->asd_context); 940 if (!ret) 941 psp->asd_context.initialized = true; 942 943 return ret; 944 } 945 946 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 947 uint32_t session_id) 948 { 949 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 950 cmd->cmd.cmd_unload_ta.session_id = session_id; 951 } 952 953 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 954 { 955 int ret; 956 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 957 958 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 959 960 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 961 962 release_psp_cmd_buf(psp); 963 964 return ret; 965 } 966 967 static int psp_asd_terminate(struct psp_context *psp) 968 { 969 int ret; 970 971 if (amdgpu_sriov_vf(psp->adev)) 972 return 0; 973 974 if (!psp->asd_context.initialized) 975 return 0; 976 977 ret = psp_ta_unload(psp, &psp->asd_context); 978 if (!ret) 979 psp->asd_context.initialized = false; 980 981 return ret; 982 } 983 984 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 985 uint32_t id, uint32_t value) 986 { 987 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 988 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 989 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 990 } 991 992 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 993 uint32_t value) 994 { 995 struct psp_gfx_cmd_resp *cmd; 996 int ret = 0; 997 998 if (reg >= PSP_REG_LAST) 999 return -EINVAL; 1000 1001 cmd = acquire_psp_cmd_buf(psp); 1002 1003 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1004 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1005 if (ret) 1006 DRM_ERROR("PSP failed to program reg id %d", reg); 1007 1008 release_psp_cmd_buf(psp); 1009 1010 return ret; 1011 } 1012 1013 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1014 uint64_t ta_bin_mc, 1015 struct ta_context *context) 1016 { 1017 cmd->cmd_id = context->ta_load_type; 1018 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1019 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1020 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1021 1022 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1023 lower_32_bits(context->mem_context.shared_mc_addr); 1024 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1025 upper_32_bits(context->mem_context.shared_mc_addr); 1026 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1027 } 1028 1029 int psp_ta_init_shared_buf(struct psp_context *psp, 1030 struct ta_mem_context *mem_ctx) 1031 { 1032 /* 1033 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1034 * physical) for ta to host memory 1035 */ 1036 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1037 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1038 &mem_ctx->shared_bo, 1039 &mem_ctx->shared_mc_addr, 1040 &mem_ctx->shared_buf); 1041 } 1042 1043 static void psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1044 uint32_t ta_cmd_id, 1045 struct ta_context *context) 1046 { 1047 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1048 cmd->cmd.cmd_invoke_cmd.session_id = context->session_id; 1049 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1050 1051 cmd->cmd.cmd_invoke_cmd.buf.num_desc = 1; 1052 cmd->cmd.cmd_invoke_cmd.buf.total_size = context->mem_context.shared_mem_size; 1053 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_size = context->mem_context.shared_mem_size; 1054 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_lo = 1055 lower_32_bits(context->mem_context.shared_mc_addr); 1056 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_hi = 1057 upper_32_bits(context->mem_context.shared_mc_addr); 1058 } 1059 1060 int psp_ta_invoke_indirect(struct psp_context *psp, 1061 uint32_t ta_cmd_id, 1062 struct ta_context *context) 1063 { 1064 int ret; 1065 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1066 1067 psp_prep_ta_invoke_indirect_cmd_buf(cmd, ta_cmd_id, context); 1068 1069 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1070 psp->fence_buf_mc_addr); 1071 1072 context->resp_status = cmd->resp.status; 1073 1074 release_psp_cmd_buf(psp); 1075 1076 return ret; 1077 } 1078 1079 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1080 uint32_t ta_cmd_id, 1081 uint32_t session_id) 1082 { 1083 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1084 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1085 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1086 } 1087 1088 int psp_ta_invoke(struct psp_context *psp, 1089 uint32_t ta_cmd_id, 1090 struct ta_context *context) 1091 { 1092 int ret; 1093 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1094 1095 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1096 1097 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1098 psp->fence_buf_mc_addr); 1099 1100 context->resp_status = cmd->resp.status; 1101 1102 release_psp_cmd_buf(psp); 1103 1104 return ret; 1105 } 1106 1107 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1108 { 1109 int ret; 1110 struct psp_gfx_cmd_resp *cmd; 1111 1112 cmd = acquire_psp_cmd_buf(psp); 1113 1114 psp_copy_fw(psp, context->bin_desc.start_addr, 1115 context->bin_desc.size_bytes); 1116 1117 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1118 1119 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1120 psp->fence_buf_mc_addr); 1121 1122 context->resp_status = cmd->resp.status; 1123 1124 if (!ret) { 1125 context->session_id = cmd->resp.session_id; 1126 } 1127 1128 release_psp_cmd_buf(psp); 1129 1130 return ret; 1131 } 1132 1133 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1134 { 1135 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1136 } 1137 1138 int psp_xgmi_terminate(struct psp_context *psp) 1139 { 1140 int ret; 1141 struct amdgpu_device *adev = psp->adev; 1142 1143 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1144 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1145 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1146 adev->gmc.xgmi.connected_to_cpu)) 1147 return 0; 1148 1149 if (!psp->xgmi_context.context.initialized) 1150 return 0; 1151 1152 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1153 1154 psp->xgmi_context.context.initialized = false; 1155 1156 return ret; 1157 } 1158 1159 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1160 { 1161 struct ta_xgmi_shared_memory *xgmi_cmd; 1162 int ret; 1163 1164 if (!psp->ta_fw || 1165 !psp->xgmi_context.context.bin_desc.size_bytes || 1166 !psp->xgmi_context.context.bin_desc.start_addr) 1167 return -ENOENT; 1168 1169 if (!load_ta) 1170 goto invoke; 1171 1172 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1173 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1174 1175 if (!psp->xgmi_context.context.initialized) { 1176 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1177 if (ret) 1178 return ret; 1179 } 1180 1181 /* Load XGMI TA */ 1182 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1183 if (!ret) 1184 psp->xgmi_context.context.initialized = true; 1185 else 1186 return ret; 1187 1188 invoke: 1189 /* Initialize XGMI session */ 1190 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1191 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1192 xgmi_cmd->flag_extend_link_record = set_extended_data; 1193 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1194 1195 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1196 1197 return ret; 1198 } 1199 1200 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1201 { 1202 struct ta_xgmi_shared_memory *xgmi_cmd; 1203 int ret; 1204 1205 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1206 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1207 1208 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1209 1210 /* Invoke xgmi ta to get hive id */ 1211 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1212 if (ret) 1213 return ret; 1214 1215 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1216 1217 return 0; 1218 } 1219 1220 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1221 { 1222 struct ta_xgmi_shared_memory *xgmi_cmd; 1223 int ret; 1224 1225 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1226 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1227 1228 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1229 1230 /* Invoke xgmi ta to get the node id */ 1231 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1232 if (ret) 1233 return ret; 1234 1235 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1236 1237 return 0; 1238 } 1239 1240 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1241 { 1242 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1243 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1244 } 1245 1246 /* 1247 * Chips that support extended topology information require the driver to 1248 * reflect topology information in the opposite direction. This is 1249 * because the TA has already exceeded its link record limit and if the 1250 * TA holds bi-directional information, the driver would have to do 1251 * multiple fetches instead of just two. 1252 */ 1253 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1254 struct psp_xgmi_node_info node_info) 1255 { 1256 struct amdgpu_device *mirror_adev; 1257 struct amdgpu_hive_info *hive; 1258 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1259 uint64_t dst_node_id = node_info.node_id; 1260 uint8_t dst_num_hops = node_info.num_hops; 1261 uint8_t dst_num_links = node_info.num_links; 1262 1263 hive = amdgpu_get_xgmi_hive(psp->adev); 1264 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1265 struct psp_xgmi_topology_info *mirror_top_info; 1266 int j; 1267 1268 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1269 continue; 1270 1271 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1272 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1273 if (mirror_top_info->nodes[j].node_id != src_node_id) 1274 continue; 1275 1276 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1277 /* 1278 * prevent 0 num_links value re-reflection since reflection 1279 * criteria is based on num_hops (direct or indirect). 1280 * 1281 */ 1282 if (dst_num_links) 1283 mirror_top_info->nodes[j].num_links = dst_num_links; 1284 1285 break; 1286 } 1287 1288 break; 1289 } 1290 } 1291 1292 int psp_xgmi_get_topology_info(struct psp_context *psp, 1293 int number_devices, 1294 struct psp_xgmi_topology_info *topology, 1295 bool get_extended_data) 1296 { 1297 struct ta_xgmi_shared_memory *xgmi_cmd; 1298 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1299 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1300 int i; 1301 int ret; 1302 1303 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1304 return -EINVAL; 1305 1306 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1307 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1308 xgmi_cmd->flag_extend_link_record = get_extended_data; 1309 1310 /* Fill in the shared memory with topology information as input */ 1311 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1312 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1313 topology_info_input->num_nodes = number_devices; 1314 1315 for (i = 0; i < topology_info_input->num_nodes; i++) { 1316 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1317 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1318 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1319 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1320 } 1321 1322 /* Invoke xgmi ta to get the topology information */ 1323 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1324 if (ret) 1325 return ret; 1326 1327 /* Read the output topology information from the shared memory */ 1328 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1329 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1330 for (i = 0; i < topology->num_nodes; i++) { 1331 /* extended data will either be 0 or equal to non-extended data */ 1332 if (topology_info_output->nodes[i].num_hops) 1333 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1334 1335 /* non-extended data gets everything here so no need to update */ 1336 if (!get_extended_data) { 1337 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1338 topology->nodes[i].is_sharing_enabled = 1339 topology_info_output->nodes[i].is_sharing_enabled; 1340 topology->nodes[i].sdma_engine = 1341 topology_info_output->nodes[i].sdma_engine; 1342 } 1343 1344 } 1345 1346 /* Invoke xgmi ta again to get the link information */ 1347 if (psp_xgmi_peer_link_info_supported(psp)) { 1348 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1349 1350 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1351 1352 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1353 1354 if (ret) 1355 return ret; 1356 1357 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1358 for (i = 0; i < topology->num_nodes; i++) { 1359 /* accumulate num_links on extended data */ 1360 topology->nodes[i].num_links = get_extended_data ? 1361 topology->nodes[i].num_links + 1362 link_info_output->nodes[i].num_links : 1363 link_info_output->nodes[i].num_links; 1364 1365 /* reflect the topology information for bi-directionality */ 1366 if (psp->xgmi_context.supports_extended_data && 1367 get_extended_data && topology->nodes[i].num_hops) 1368 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1369 } 1370 } 1371 1372 return 0; 1373 } 1374 1375 int psp_xgmi_set_topology_info(struct psp_context *psp, 1376 int number_devices, 1377 struct psp_xgmi_topology_info *topology) 1378 { 1379 struct ta_xgmi_shared_memory *xgmi_cmd; 1380 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1381 int i; 1382 1383 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1384 return -EINVAL; 1385 1386 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1387 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1388 1389 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1390 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1391 topology_info_input->num_nodes = number_devices; 1392 1393 for (i = 0; i < topology_info_input->num_nodes; i++) { 1394 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1395 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1396 topology_info_input->nodes[i].is_sharing_enabled = 1; 1397 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1398 } 1399 1400 /* Invoke xgmi ta to set topology information */ 1401 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1402 } 1403 1404 // ras begin 1405 static void psp_ras_ta_check_status(struct psp_context *psp) 1406 { 1407 struct ta_ras_shared_memory *ras_cmd = 1408 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1409 1410 switch (ras_cmd->ras_status) { 1411 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1412 dev_warn(psp->adev->dev, 1413 "RAS WARNING: cmd failed due to unsupported ip\n"); 1414 break; 1415 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1416 dev_warn(psp->adev->dev, 1417 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1418 break; 1419 case TA_RAS_STATUS__SUCCESS: 1420 break; 1421 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1422 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1423 dev_warn(psp->adev->dev, 1424 "RAS WARNING: Inject error to critical region is not allowed\n"); 1425 break; 1426 default: 1427 dev_warn(psp->adev->dev, 1428 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1429 break; 1430 } 1431 } 1432 1433 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1434 { 1435 struct ta_ras_shared_memory *ras_cmd; 1436 int ret; 1437 1438 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1439 1440 /* 1441 * TODO: bypass the loading in sriov for now 1442 */ 1443 if (amdgpu_sriov_vf(psp->adev)) 1444 return 0; 1445 1446 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1447 1448 if (amdgpu_ras_intr_triggered()) 1449 return ret; 1450 1451 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1452 { 1453 DRM_WARN("RAS: Unsupported Interface"); 1454 return -EINVAL; 1455 } 1456 1457 if (!ret) { 1458 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1459 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1460 1461 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1462 } 1463 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1464 dev_warn(psp->adev->dev, 1465 "RAS internal register access blocked\n"); 1466 1467 psp_ras_ta_check_status(psp); 1468 } 1469 1470 return ret; 1471 } 1472 1473 int psp_ras_enable_features(struct psp_context *psp, 1474 union ta_ras_cmd_input *info, bool enable) 1475 { 1476 struct ta_ras_shared_memory *ras_cmd; 1477 int ret; 1478 1479 if (!psp->ras_context.context.initialized) 1480 return -EINVAL; 1481 1482 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1483 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1484 1485 if (enable) 1486 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1487 else 1488 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1489 1490 ras_cmd->ras_in_message = *info; 1491 1492 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1493 if (ret) 1494 return -EINVAL; 1495 1496 return 0; 1497 } 1498 1499 int psp_ras_terminate(struct psp_context *psp) 1500 { 1501 int ret; 1502 1503 /* 1504 * TODO: bypass the terminate in sriov for now 1505 */ 1506 if (amdgpu_sriov_vf(psp->adev)) 1507 return 0; 1508 1509 if (!psp->ras_context.context.initialized) 1510 return 0; 1511 1512 ret = psp_ta_unload(psp, &psp->ras_context.context); 1513 1514 psp->ras_context.context.initialized = false; 1515 1516 return ret; 1517 } 1518 1519 static int psp_ras_initialize(struct psp_context *psp) 1520 { 1521 int ret; 1522 uint32_t boot_cfg = 0xFF; 1523 struct amdgpu_device *adev = psp->adev; 1524 struct ta_ras_shared_memory *ras_cmd; 1525 1526 /* 1527 * TODO: bypass the initialize in sriov for now 1528 */ 1529 if (amdgpu_sriov_vf(adev)) 1530 return 0; 1531 1532 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1533 !adev->psp.ras_context.context.bin_desc.start_addr) { 1534 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1535 return 0; 1536 } 1537 1538 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1539 /* query GECC enablement status from boot config 1540 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1541 */ 1542 ret = psp_boot_config_get(adev, &boot_cfg); 1543 if (ret) 1544 dev_warn(adev->dev, "PSP get boot config failed\n"); 1545 1546 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1547 if (!boot_cfg) { 1548 dev_info(adev->dev, "GECC is disabled\n"); 1549 } else { 1550 /* disable GECC in next boot cycle if ras is 1551 * disabled by module parameter amdgpu_ras_enable 1552 * and/or amdgpu_ras_mask, or boot_config_get call 1553 * is failed 1554 */ 1555 ret = psp_boot_config_set(adev, 0); 1556 if (ret) 1557 dev_warn(adev->dev, "PSP set boot config failed\n"); 1558 else 1559 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1560 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1561 } 1562 } else { 1563 if (1 == boot_cfg) { 1564 dev_info(adev->dev, "GECC is enabled\n"); 1565 } else { 1566 /* enable GECC in next boot cycle if it is disabled 1567 * in boot config, or force enable GECC if failed to 1568 * get boot configuration 1569 */ 1570 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1571 if (ret) 1572 dev_warn(adev->dev, "PSP set boot config failed\n"); 1573 else 1574 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1575 } 1576 } 1577 } 1578 1579 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1580 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1581 1582 if (!psp->ras_context.context.initialized) { 1583 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1584 if (ret) 1585 return ret; 1586 } 1587 1588 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1589 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1590 1591 if (amdgpu_ras_is_poison_mode_supported(adev)) 1592 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1593 if (!adev->gmc.xgmi.connected_to_cpu) 1594 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1595 1596 ret = psp_ta_load(psp, &psp->ras_context.context); 1597 1598 if (!ret && !ras_cmd->ras_status) 1599 psp->ras_context.context.initialized = true; 1600 else { 1601 if (ras_cmd->ras_status) 1602 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1603 amdgpu_ras_fini(psp->adev); 1604 } 1605 1606 return ret; 1607 } 1608 1609 int psp_ras_trigger_error(struct psp_context *psp, 1610 struct ta_ras_trigger_error_input *info) 1611 { 1612 struct ta_ras_shared_memory *ras_cmd; 1613 int ret; 1614 1615 if (!psp->ras_context.context.initialized) 1616 return -EINVAL; 1617 1618 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1619 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1620 1621 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1622 ras_cmd->ras_in_message.trigger_error = *info; 1623 1624 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1625 if (ret) 1626 return -EINVAL; 1627 1628 /* If err_event_athub occurs error inject was successful, however 1629 return status from TA is no long reliable */ 1630 if (amdgpu_ras_intr_triggered()) 1631 return 0; 1632 1633 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1634 return -EACCES; 1635 else if (ras_cmd->ras_status) 1636 return -EINVAL; 1637 1638 return 0; 1639 } 1640 // ras end 1641 1642 // HDCP start 1643 static int psp_hdcp_initialize(struct psp_context *psp) 1644 { 1645 int ret; 1646 1647 /* 1648 * TODO: bypass the initialize in sriov for now 1649 */ 1650 if (amdgpu_sriov_vf(psp->adev)) 1651 return 0; 1652 1653 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1654 !psp->hdcp_context.context.bin_desc.start_addr) { 1655 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1656 return 0; 1657 } 1658 1659 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1660 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1661 1662 if (!psp->hdcp_context.context.initialized) { 1663 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1664 if (ret) 1665 return ret; 1666 } 1667 1668 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1669 if (!ret) { 1670 psp->hdcp_context.context.initialized = true; 1671 mutex_init(&psp->hdcp_context.mutex); 1672 } 1673 1674 return ret; 1675 } 1676 1677 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1678 { 1679 /* 1680 * TODO: bypass the loading in sriov for now 1681 */ 1682 if (amdgpu_sriov_vf(psp->adev)) 1683 return 0; 1684 1685 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1686 } 1687 1688 static int psp_hdcp_terminate(struct psp_context *psp) 1689 { 1690 int ret; 1691 1692 /* 1693 * TODO: bypass the terminate in sriov for now 1694 */ 1695 if (amdgpu_sriov_vf(psp->adev)) 1696 return 0; 1697 1698 if (!psp->hdcp_context.context.initialized) 1699 return 0; 1700 1701 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1702 1703 psp->hdcp_context.context.initialized = false; 1704 1705 return ret; 1706 } 1707 // HDCP end 1708 1709 // DTM start 1710 static int psp_dtm_initialize(struct psp_context *psp) 1711 { 1712 int ret; 1713 1714 /* 1715 * TODO: bypass the initialize in sriov for now 1716 */ 1717 if (amdgpu_sriov_vf(psp->adev)) 1718 return 0; 1719 1720 if (!psp->dtm_context.context.bin_desc.size_bytes || 1721 !psp->dtm_context.context.bin_desc.start_addr) { 1722 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1723 return 0; 1724 } 1725 1726 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1727 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1728 1729 if (!psp->dtm_context.context.initialized) { 1730 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1731 if (ret) 1732 return ret; 1733 } 1734 1735 ret = psp_ta_load(psp, &psp->dtm_context.context); 1736 if (!ret) { 1737 psp->dtm_context.context.initialized = true; 1738 mutex_init(&psp->dtm_context.mutex); 1739 } 1740 1741 return ret; 1742 } 1743 1744 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1745 { 1746 /* 1747 * TODO: bypass the loading in sriov for now 1748 */ 1749 if (amdgpu_sriov_vf(psp->adev)) 1750 return 0; 1751 1752 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1753 } 1754 1755 static int psp_dtm_terminate(struct psp_context *psp) 1756 { 1757 int ret; 1758 1759 /* 1760 * TODO: bypass the terminate in sriov for now 1761 */ 1762 if (amdgpu_sriov_vf(psp->adev)) 1763 return 0; 1764 1765 if (!psp->dtm_context.context.initialized) 1766 return 0; 1767 1768 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1769 1770 psp->dtm_context.context.initialized = false; 1771 1772 return ret; 1773 } 1774 // DTM end 1775 1776 // RAP start 1777 static int psp_rap_initialize(struct psp_context *psp) 1778 { 1779 int ret; 1780 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1781 1782 /* 1783 * TODO: bypass the initialize in sriov for now 1784 */ 1785 if (amdgpu_sriov_vf(psp->adev)) 1786 return 0; 1787 1788 if (!psp->rap_context.context.bin_desc.size_bytes || 1789 !psp->rap_context.context.bin_desc.start_addr) { 1790 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1791 return 0; 1792 } 1793 1794 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1795 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1796 1797 if (!psp->rap_context.context.initialized) { 1798 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1799 if (ret) 1800 return ret; 1801 } 1802 1803 ret = psp_ta_load(psp, &psp->rap_context.context); 1804 if (!ret) { 1805 psp->rap_context.context.initialized = true; 1806 mutex_init(&psp->rap_context.mutex); 1807 } else 1808 return ret; 1809 1810 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1811 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1812 psp_rap_terminate(psp); 1813 /* free rap shared memory */ 1814 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1815 1816 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1817 ret, status); 1818 1819 return ret; 1820 } 1821 1822 return 0; 1823 } 1824 1825 static int psp_rap_terminate(struct psp_context *psp) 1826 { 1827 int ret; 1828 1829 if (!psp->rap_context.context.initialized) 1830 return 0; 1831 1832 ret = psp_ta_unload(psp, &psp->rap_context.context); 1833 1834 psp->rap_context.context.initialized = false; 1835 1836 return ret; 1837 } 1838 1839 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1840 { 1841 struct ta_rap_shared_memory *rap_cmd; 1842 int ret = 0; 1843 1844 if (!psp->rap_context.context.initialized) 1845 return 0; 1846 1847 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1848 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1849 return -EINVAL; 1850 1851 mutex_lock(&psp->rap_context.mutex); 1852 1853 rap_cmd = (struct ta_rap_shared_memory *) 1854 psp->rap_context.context.mem_context.shared_buf; 1855 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1856 1857 rap_cmd->cmd_id = ta_cmd_id; 1858 rap_cmd->validation_method_id = METHOD_A; 1859 1860 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1861 if (ret) 1862 goto out_unlock; 1863 1864 if (status) 1865 *status = rap_cmd->rap_status; 1866 1867 out_unlock: 1868 mutex_unlock(&psp->rap_context.mutex); 1869 1870 return ret; 1871 } 1872 // RAP end 1873 1874 /* securedisplay start */ 1875 static int psp_securedisplay_initialize(struct psp_context *psp) 1876 { 1877 int ret; 1878 struct securedisplay_cmd *securedisplay_cmd; 1879 1880 /* 1881 * TODO: bypass the initialize in sriov for now 1882 */ 1883 if (amdgpu_sriov_vf(psp->adev)) 1884 return 0; 1885 1886 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1887 !psp->securedisplay_context.context.bin_desc.start_addr) { 1888 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1889 return 0; 1890 } 1891 1892 psp->securedisplay_context.context.mem_context.shared_mem_size = 1893 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1894 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1895 1896 if (!psp->securedisplay_context.context.initialized) { 1897 ret = psp_ta_init_shared_buf(psp, 1898 &psp->securedisplay_context.context.mem_context); 1899 if (ret) 1900 return ret; 1901 } 1902 1903 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 1904 if (!ret) { 1905 psp->securedisplay_context.context.initialized = true; 1906 mutex_init(&psp->securedisplay_context.mutex); 1907 } else 1908 return ret; 1909 1910 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1911 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1912 1913 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1914 if (ret) { 1915 psp_securedisplay_terminate(psp); 1916 /* free securedisplay shared memory */ 1917 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1918 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1919 return -EINVAL; 1920 } 1921 1922 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1923 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1924 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1925 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1926 } 1927 1928 return 0; 1929 } 1930 1931 static int psp_securedisplay_terminate(struct psp_context *psp) 1932 { 1933 int ret; 1934 1935 /* 1936 * TODO:bypass the terminate in sriov for now 1937 */ 1938 if (amdgpu_sriov_vf(psp->adev)) 1939 return 0; 1940 1941 if (!psp->securedisplay_context.context.initialized) 1942 return 0; 1943 1944 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 1945 1946 psp->securedisplay_context.context.initialized = false; 1947 1948 return ret; 1949 } 1950 1951 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1952 { 1953 int ret; 1954 1955 if (!psp->securedisplay_context.context.initialized) 1956 return -EINVAL; 1957 1958 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1959 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1960 return -EINVAL; 1961 1962 mutex_lock(&psp->securedisplay_context.mutex); 1963 1964 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1965 1966 mutex_unlock(&psp->securedisplay_context.mutex); 1967 1968 return ret; 1969 } 1970 /* SECUREDISPLAY end */ 1971 1972 static int psp_hw_start(struct psp_context *psp) 1973 { 1974 struct amdgpu_device *adev = psp->adev; 1975 int ret; 1976 1977 if (!amdgpu_sriov_vf(adev)) { 1978 if ((is_psp_fw_valid(psp->kdb)) && 1979 (psp->funcs->bootloader_load_kdb != NULL)) { 1980 ret = psp_bootloader_load_kdb(psp); 1981 if (ret) { 1982 DRM_ERROR("PSP load kdb failed!\n"); 1983 return ret; 1984 } 1985 } 1986 1987 if ((is_psp_fw_valid(psp->spl)) && 1988 (psp->funcs->bootloader_load_spl != NULL)) { 1989 ret = psp_bootloader_load_spl(psp); 1990 if (ret) { 1991 DRM_ERROR("PSP load spl failed!\n"); 1992 return ret; 1993 } 1994 } 1995 1996 if ((is_psp_fw_valid(psp->sys)) && 1997 (psp->funcs->bootloader_load_sysdrv != NULL)) { 1998 ret = psp_bootloader_load_sysdrv(psp); 1999 if (ret) { 2000 DRM_ERROR("PSP load sys drv failed!\n"); 2001 return ret; 2002 } 2003 } 2004 2005 if ((is_psp_fw_valid(psp->soc_drv)) && 2006 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2007 ret = psp_bootloader_load_soc_drv(psp); 2008 if (ret) { 2009 DRM_ERROR("PSP load soc drv failed!\n"); 2010 return ret; 2011 } 2012 } 2013 2014 if ((is_psp_fw_valid(psp->intf_drv)) && 2015 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2016 ret = psp_bootloader_load_intf_drv(psp); 2017 if (ret) { 2018 DRM_ERROR("PSP load intf drv failed!\n"); 2019 return ret; 2020 } 2021 } 2022 2023 if ((is_psp_fw_valid(psp->dbg_drv)) && 2024 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2025 ret = psp_bootloader_load_dbg_drv(psp); 2026 if (ret) { 2027 DRM_ERROR("PSP load dbg drv failed!\n"); 2028 return ret; 2029 } 2030 } 2031 2032 if ((is_psp_fw_valid(psp->sos)) && 2033 (psp->funcs->bootloader_load_sos != NULL)) { 2034 ret = psp_bootloader_load_sos(psp); 2035 if (ret) { 2036 DRM_ERROR("PSP load sos failed!\n"); 2037 return ret; 2038 } 2039 } 2040 } 2041 2042 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2043 if (ret) { 2044 DRM_ERROR("PSP create ring failed!\n"); 2045 return ret; 2046 } 2047 2048 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2049 goto skip_pin_bo; 2050 2051 ret = psp_tmr_init(psp); 2052 if (ret) { 2053 DRM_ERROR("PSP tmr init failed!\n"); 2054 return ret; 2055 } 2056 2057 skip_pin_bo: 2058 /* 2059 * For ASICs with DF Cstate management centralized 2060 * to PMFW, TMR setup should be performed after PMFW 2061 * loaded and before other non-psp firmware loaded. 2062 */ 2063 if (psp->pmfw_centralized_cstate_management) { 2064 ret = psp_load_smu_fw(psp); 2065 if (ret) 2066 return ret; 2067 } 2068 2069 ret = psp_tmr_load(psp); 2070 if (ret) { 2071 DRM_ERROR("PSP load tmr failed!\n"); 2072 return ret; 2073 } 2074 2075 return 0; 2076 } 2077 2078 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2079 enum psp_gfx_fw_type *type) 2080 { 2081 switch (ucode->ucode_id) { 2082 case AMDGPU_UCODE_ID_CAP: 2083 *type = GFX_FW_TYPE_CAP; 2084 break; 2085 case AMDGPU_UCODE_ID_SDMA0: 2086 *type = GFX_FW_TYPE_SDMA0; 2087 break; 2088 case AMDGPU_UCODE_ID_SDMA1: 2089 *type = GFX_FW_TYPE_SDMA1; 2090 break; 2091 case AMDGPU_UCODE_ID_SDMA2: 2092 *type = GFX_FW_TYPE_SDMA2; 2093 break; 2094 case AMDGPU_UCODE_ID_SDMA3: 2095 *type = GFX_FW_TYPE_SDMA3; 2096 break; 2097 case AMDGPU_UCODE_ID_SDMA4: 2098 *type = GFX_FW_TYPE_SDMA4; 2099 break; 2100 case AMDGPU_UCODE_ID_SDMA5: 2101 *type = GFX_FW_TYPE_SDMA5; 2102 break; 2103 case AMDGPU_UCODE_ID_SDMA6: 2104 *type = GFX_FW_TYPE_SDMA6; 2105 break; 2106 case AMDGPU_UCODE_ID_SDMA7: 2107 *type = GFX_FW_TYPE_SDMA7; 2108 break; 2109 case AMDGPU_UCODE_ID_CP_MES: 2110 *type = GFX_FW_TYPE_CP_MES; 2111 break; 2112 case AMDGPU_UCODE_ID_CP_MES_DATA: 2113 *type = GFX_FW_TYPE_MES_STACK; 2114 break; 2115 case AMDGPU_UCODE_ID_CP_MES1: 2116 *type = GFX_FW_TYPE_CP_MES_KIQ; 2117 break; 2118 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2119 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2120 break; 2121 case AMDGPU_UCODE_ID_CP_CE: 2122 *type = GFX_FW_TYPE_CP_CE; 2123 break; 2124 case AMDGPU_UCODE_ID_CP_PFP: 2125 *type = GFX_FW_TYPE_CP_PFP; 2126 break; 2127 case AMDGPU_UCODE_ID_CP_ME: 2128 *type = GFX_FW_TYPE_CP_ME; 2129 break; 2130 case AMDGPU_UCODE_ID_CP_MEC1: 2131 *type = GFX_FW_TYPE_CP_MEC; 2132 break; 2133 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2134 *type = GFX_FW_TYPE_CP_MEC_ME1; 2135 break; 2136 case AMDGPU_UCODE_ID_CP_MEC2: 2137 *type = GFX_FW_TYPE_CP_MEC; 2138 break; 2139 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2140 *type = GFX_FW_TYPE_CP_MEC_ME2; 2141 break; 2142 case AMDGPU_UCODE_ID_RLC_P: 2143 *type = GFX_FW_TYPE_RLC_P; 2144 break; 2145 case AMDGPU_UCODE_ID_RLC_V: 2146 *type = GFX_FW_TYPE_RLC_V; 2147 break; 2148 case AMDGPU_UCODE_ID_RLC_G: 2149 *type = GFX_FW_TYPE_RLC_G; 2150 break; 2151 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2152 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2153 break; 2154 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2155 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2156 break; 2157 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2158 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2159 break; 2160 case AMDGPU_UCODE_ID_RLC_IRAM: 2161 *type = GFX_FW_TYPE_RLC_IRAM; 2162 break; 2163 case AMDGPU_UCODE_ID_RLC_DRAM: 2164 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2165 break; 2166 case AMDGPU_UCODE_ID_SMC: 2167 *type = GFX_FW_TYPE_SMU; 2168 break; 2169 case AMDGPU_UCODE_ID_PPTABLE: 2170 *type = GFX_FW_TYPE_PPTABLE; 2171 break; 2172 case AMDGPU_UCODE_ID_UVD: 2173 *type = GFX_FW_TYPE_UVD; 2174 break; 2175 case AMDGPU_UCODE_ID_UVD1: 2176 *type = GFX_FW_TYPE_UVD1; 2177 break; 2178 case AMDGPU_UCODE_ID_VCE: 2179 *type = GFX_FW_TYPE_VCE; 2180 break; 2181 case AMDGPU_UCODE_ID_VCN: 2182 *type = GFX_FW_TYPE_VCN; 2183 break; 2184 case AMDGPU_UCODE_ID_VCN1: 2185 *type = GFX_FW_TYPE_VCN1; 2186 break; 2187 case AMDGPU_UCODE_ID_DMCU_ERAM: 2188 *type = GFX_FW_TYPE_DMCU_ERAM; 2189 break; 2190 case AMDGPU_UCODE_ID_DMCU_INTV: 2191 *type = GFX_FW_TYPE_DMCU_ISR; 2192 break; 2193 case AMDGPU_UCODE_ID_VCN0_RAM: 2194 *type = GFX_FW_TYPE_VCN0_RAM; 2195 break; 2196 case AMDGPU_UCODE_ID_VCN1_RAM: 2197 *type = GFX_FW_TYPE_VCN1_RAM; 2198 break; 2199 case AMDGPU_UCODE_ID_DMCUB: 2200 *type = GFX_FW_TYPE_DMUB; 2201 break; 2202 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2203 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2204 break; 2205 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2206 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2207 break; 2208 case AMDGPU_UCODE_ID_IMU_I: 2209 *type = GFX_FW_TYPE_IMU_I; 2210 break; 2211 case AMDGPU_UCODE_ID_IMU_D: 2212 *type = GFX_FW_TYPE_IMU_D; 2213 break; 2214 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2215 *type = GFX_FW_TYPE_RS64_PFP; 2216 break; 2217 case AMDGPU_UCODE_ID_CP_RS64_ME: 2218 *type = GFX_FW_TYPE_RS64_ME; 2219 break; 2220 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2221 *type = GFX_FW_TYPE_RS64_MEC; 2222 break; 2223 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2224 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2225 break; 2226 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2227 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2228 break; 2229 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2230 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2231 break; 2232 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2233 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2234 break; 2235 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2236 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2237 break; 2238 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2239 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2240 break; 2241 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2242 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2243 break; 2244 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2245 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2246 break; 2247 case AMDGPU_UCODE_ID_MAXIMUM: 2248 default: 2249 return -EINVAL; 2250 } 2251 2252 return 0; 2253 } 2254 2255 static void psp_print_fw_hdr(struct psp_context *psp, 2256 struct amdgpu_firmware_info *ucode) 2257 { 2258 struct amdgpu_device *adev = psp->adev; 2259 struct common_firmware_header *hdr; 2260 2261 switch (ucode->ucode_id) { 2262 case AMDGPU_UCODE_ID_SDMA0: 2263 case AMDGPU_UCODE_ID_SDMA1: 2264 case AMDGPU_UCODE_ID_SDMA2: 2265 case AMDGPU_UCODE_ID_SDMA3: 2266 case AMDGPU_UCODE_ID_SDMA4: 2267 case AMDGPU_UCODE_ID_SDMA5: 2268 case AMDGPU_UCODE_ID_SDMA6: 2269 case AMDGPU_UCODE_ID_SDMA7: 2270 hdr = (struct common_firmware_header *) 2271 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2272 amdgpu_ucode_print_sdma_hdr(hdr); 2273 break; 2274 case AMDGPU_UCODE_ID_CP_CE: 2275 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2276 amdgpu_ucode_print_gfx_hdr(hdr); 2277 break; 2278 case AMDGPU_UCODE_ID_CP_PFP: 2279 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2280 amdgpu_ucode_print_gfx_hdr(hdr); 2281 break; 2282 case AMDGPU_UCODE_ID_CP_ME: 2283 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2284 amdgpu_ucode_print_gfx_hdr(hdr); 2285 break; 2286 case AMDGPU_UCODE_ID_CP_MEC1: 2287 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2288 amdgpu_ucode_print_gfx_hdr(hdr); 2289 break; 2290 case AMDGPU_UCODE_ID_RLC_G: 2291 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2292 amdgpu_ucode_print_rlc_hdr(hdr); 2293 break; 2294 case AMDGPU_UCODE_ID_SMC: 2295 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2296 amdgpu_ucode_print_smc_hdr(hdr); 2297 break; 2298 default: 2299 break; 2300 } 2301 } 2302 2303 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2304 struct psp_gfx_cmd_resp *cmd) 2305 { 2306 int ret; 2307 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2308 2309 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2310 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2311 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2312 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2313 2314 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2315 if (ret) 2316 DRM_ERROR("Unknown firmware type\n"); 2317 2318 return ret; 2319 } 2320 2321 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2322 struct amdgpu_firmware_info *ucode) 2323 { 2324 int ret = 0; 2325 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2326 2327 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2328 if (!ret) { 2329 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2330 psp->fence_buf_mc_addr); 2331 } 2332 2333 release_psp_cmd_buf(psp); 2334 2335 return ret; 2336 } 2337 2338 static int psp_load_smu_fw(struct psp_context *psp) 2339 { 2340 int ret; 2341 struct amdgpu_device *adev = psp->adev; 2342 struct amdgpu_firmware_info *ucode = 2343 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2344 struct amdgpu_ras *ras = psp->ras_context.ras; 2345 2346 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2347 return 0; 2348 2349 if ((amdgpu_in_reset(adev) && 2350 ras && adev->ras_enabled && 2351 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2352 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2353 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2354 if (ret) { 2355 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2356 } 2357 } 2358 2359 ret = psp_execute_non_psp_fw_load(psp, ucode); 2360 2361 if (ret) 2362 DRM_ERROR("PSP load smu failed!\n"); 2363 2364 return ret; 2365 } 2366 2367 static bool fw_load_skip_check(struct psp_context *psp, 2368 struct amdgpu_firmware_info *ucode) 2369 { 2370 if (!ucode->fw) 2371 return true; 2372 2373 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2374 (psp_smu_reload_quirk(psp) || 2375 psp->autoload_supported || 2376 psp->pmfw_centralized_cstate_management)) 2377 return true; 2378 2379 if (amdgpu_sriov_vf(psp->adev) && 2380 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2381 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2382 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2383 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2384 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2385 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2386 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2387 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2388 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2389 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2390 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2391 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2392 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2393 /*skip ucode loading in SRIOV VF */ 2394 return true; 2395 2396 if (psp->autoload_supported && 2397 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2398 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2399 /* skip mec JT when autoload is enabled */ 2400 return true; 2401 2402 return false; 2403 } 2404 2405 int psp_load_fw_list(struct psp_context *psp, 2406 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2407 { 2408 int ret = 0, i; 2409 struct amdgpu_firmware_info *ucode; 2410 2411 for (i = 0; i < ucode_count; ++i) { 2412 ucode = ucode_list[i]; 2413 psp_print_fw_hdr(psp, ucode); 2414 ret = psp_execute_non_psp_fw_load(psp, ucode); 2415 if (ret) 2416 return ret; 2417 } 2418 return ret; 2419 } 2420 2421 static int psp_load_non_psp_fw(struct psp_context *psp) 2422 { 2423 int i, ret; 2424 struct amdgpu_firmware_info *ucode; 2425 struct amdgpu_device *adev = psp->adev; 2426 2427 if (psp->autoload_supported && 2428 !psp->pmfw_centralized_cstate_management) { 2429 ret = psp_load_smu_fw(psp); 2430 if (ret) 2431 return ret; 2432 } 2433 2434 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2435 ucode = &adev->firmware.ucode[i]; 2436 2437 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2438 !fw_load_skip_check(psp, ucode)) { 2439 ret = psp_load_smu_fw(psp); 2440 if (ret) 2441 return ret; 2442 continue; 2443 } 2444 2445 if (fw_load_skip_check(psp, ucode)) 2446 continue; 2447 2448 if (psp->autoload_supported && 2449 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2450 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2451 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2452 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2453 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2454 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2455 /* PSP only receive one SDMA fw for sienna_cichlid, 2456 * as all four sdma fw are same */ 2457 continue; 2458 2459 psp_print_fw_hdr(psp, ucode); 2460 2461 ret = psp_execute_non_psp_fw_load(psp, ucode); 2462 if (ret) 2463 return ret; 2464 2465 /* Start rlc autoload after psp recieved all the gfx firmware */ 2466 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2467 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2468 ret = psp_rlc_autoload_start(psp); 2469 if (ret) { 2470 DRM_ERROR("Failed to start rlc autoload\n"); 2471 return ret; 2472 } 2473 } 2474 } 2475 2476 return 0; 2477 } 2478 2479 static int psp_load_fw(struct amdgpu_device *adev) 2480 { 2481 int ret; 2482 struct psp_context *psp = &adev->psp; 2483 2484 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2485 /* should not destroy ring, only stop */ 2486 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2487 } else { 2488 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2489 2490 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2491 if (ret) { 2492 DRM_ERROR("PSP ring init failed!\n"); 2493 goto failed; 2494 } 2495 } 2496 2497 ret = psp_hw_start(psp); 2498 if (ret) 2499 goto failed; 2500 2501 ret = psp_load_non_psp_fw(psp); 2502 if (ret) 2503 goto failed1; 2504 2505 ret = psp_asd_initialize(psp); 2506 if (ret) { 2507 DRM_ERROR("PSP load asd failed!\n"); 2508 goto failed1; 2509 } 2510 2511 ret = psp_rl_load(adev); 2512 if (ret) { 2513 DRM_ERROR("PSP load RL failed!\n"); 2514 goto failed1; 2515 } 2516 2517 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2518 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2519 ret = psp_xgmi_initialize(psp, false, true); 2520 /* Warning the XGMI seesion initialize failure 2521 * Instead of stop driver initialization 2522 */ 2523 if (ret) 2524 dev_err(psp->adev->dev, 2525 "XGMI: Failed to initialize XGMI session\n"); 2526 } 2527 } 2528 2529 if (psp->ta_fw) { 2530 ret = psp_ras_initialize(psp); 2531 if (ret) 2532 dev_err(psp->adev->dev, 2533 "RAS: Failed to initialize RAS\n"); 2534 2535 ret = psp_hdcp_initialize(psp); 2536 if (ret) 2537 dev_err(psp->adev->dev, 2538 "HDCP: Failed to initialize HDCP\n"); 2539 2540 ret = psp_dtm_initialize(psp); 2541 if (ret) 2542 dev_err(psp->adev->dev, 2543 "DTM: Failed to initialize DTM\n"); 2544 2545 ret = psp_rap_initialize(psp); 2546 if (ret) 2547 dev_err(psp->adev->dev, 2548 "RAP: Failed to initialize RAP\n"); 2549 2550 ret = psp_securedisplay_initialize(psp); 2551 if (ret) 2552 dev_err(psp->adev->dev, 2553 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2554 } 2555 2556 return 0; 2557 2558 failed1: 2559 psp_free_shared_bufs(psp); 2560 failed: 2561 /* 2562 * all cleanup jobs (xgmi terminate, ras terminate, 2563 * ring destroy, cmd/fence/fw buffers destory, 2564 * psp->cmd destory) are delayed to psp_hw_fini 2565 */ 2566 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2567 return ret; 2568 } 2569 2570 static int psp_hw_init(void *handle) 2571 { 2572 int ret; 2573 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2574 2575 mutex_lock(&adev->firmware.mutex); 2576 /* 2577 * This sequence is just used on hw_init only once, no need on 2578 * resume. 2579 */ 2580 ret = amdgpu_ucode_init_bo(adev); 2581 if (ret) 2582 goto failed; 2583 2584 ret = psp_load_fw(adev); 2585 if (ret) { 2586 DRM_ERROR("PSP firmware loading failed\n"); 2587 goto failed; 2588 } 2589 2590 mutex_unlock(&adev->firmware.mutex); 2591 return 0; 2592 2593 failed: 2594 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2595 mutex_unlock(&adev->firmware.mutex); 2596 return -EINVAL; 2597 } 2598 2599 static int psp_hw_fini(void *handle) 2600 { 2601 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2602 struct psp_context *psp = &adev->psp; 2603 2604 if (psp->ta_fw) { 2605 psp_ras_terminate(psp); 2606 psp_securedisplay_terminate(psp); 2607 psp_rap_terminate(psp); 2608 psp_dtm_terminate(psp); 2609 psp_hdcp_terminate(psp); 2610 } 2611 2612 psp_asd_terminate(psp); 2613 psp_tmr_terminate(psp); 2614 2615 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2616 2617 psp_free_shared_bufs(psp); 2618 2619 return 0; 2620 } 2621 2622 static int psp_suspend(void *handle) 2623 { 2624 int ret = 0; 2625 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2626 struct psp_context *psp = &adev->psp; 2627 2628 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2629 psp->xgmi_context.context.initialized) { 2630 ret = psp_xgmi_terminate(psp); 2631 if (ret) { 2632 DRM_ERROR("Failed to terminate xgmi ta\n"); 2633 goto out; 2634 } 2635 } 2636 2637 if (psp->ta_fw) { 2638 ret = psp_ras_terminate(psp); 2639 if (ret) { 2640 DRM_ERROR("Failed to terminate ras ta\n"); 2641 goto out; 2642 } 2643 ret = psp_hdcp_terminate(psp); 2644 if (ret) { 2645 DRM_ERROR("Failed to terminate hdcp ta\n"); 2646 goto out; 2647 } 2648 ret = psp_dtm_terminate(psp); 2649 if (ret) { 2650 DRM_ERROR("Failed to terminate dtm ta\n"); 2651 goto out; 2652 } 2653 ret = psp_rap_terminate(psp); 2654 if (ret) { 2655 DRM_ERROR("Failed to terminate rap ta\n"); 2656 goto out; 2657 } 2658 ret = psp_securedisplay_terminate(psp); 2659 if (ret) { 2660 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2661 goto out; 2662 } 2663 } 2664 2665 ret = psp_asd_terminate(psp); 2666 if (ret) { 2667 DRM_ERROR("Failed to terminate asd\n"); 2668 goto out; 2669 } 2670 2671 ret = psp_tmr_terminate(psp); 2672 if (ret) { 2673 DRM_ERROR("Failed to terminate tmr\n"); 2674 goto out; 2675 } 2676 2677 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2678 if (ret) { 2679 DRM_ERROR("PSP ring stop failed\n"); 2680 } 2681 2682 out: 2683 psp_free_shared_bufs(psp); 2684 2685 return ret; 2686 } 2687 2688 static int psp_resume(void *handle) 2689 { 2690 int ret; 2691 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2692 struct psp_context *psp = &adev->psp; 2693 2694 DRM_INFO("PSP is resuming...\n"); 2695 2696 if (psp->mem_train_ctx.enable_mem_training) { 2697 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2698 if (ret) { 2699 DRM_ERROR("Failed to process memory training!\n"); 2700 return ret; 2701 } 2702 } 2703 2704 mutex_lock(&adev->firmware.mutex); 2705 2706 ret = psp_hw_start(psp); 2707 if (ret) 2708 goto failed; 2709 2710 ret = psp_load_non_psp_fw(psp); 2711 if (ret) 2712 goto failed; 2713 2714 ret = psp_asd_initialize(psp); 2715 if (ret) { 2716 DRM_ERROR("PSP load asd failed!\n"); 2717 goto failed; 2718 } 2719 2720 ret = psp_rl_load(adev); 2721 if (ret) { 2722 dev_err(adev->dev, "PSP load RL failed!\n"); 2723 goto failed; 2724 } 2725 2726 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2727 ret = psp_xgmi_initialize(psp, false, true); 2728 /* Warning the XGMI seesion initialize failure 2729 * Instead of stop driver initialization 2730 */ 2731 if (ret) 2732 dev_err(psp->adev->dev, 2733 "XGMI: Failed to initialize XGMI session\n"); 2734 } 2735 2736 if (psp->ta_fw) { 2737 ret = psp_ras_initialize(psp); 2738 if (ret) 2739 dev_err(psp->adev->dev, 2740 "RAS: Failed to initialize RAS\n"); 2741 2742 ret = psp_hdcp_initialize(psp); 2743 if (ret) 2744 dev_err(psp->adev->dev, 2745 "HDCP: Failed to initialize HDCP\n"); 2746 2747 ret = psp_dtm_initialize(psp); 2748 if (ret) 2749 dev_err(psp->adev->dev, 2750 "DTM: Failed to initialize DTM\n"); 2751 2752 ret = psp_rap_initialize(psp); 2753 if (ret) 2754 dev_err(psp->adev->dev, 2755 "RAP: Failed to initialize RAP\n"); 2756 2757 ret = psp_securedisplay_initialize(psp); 2758 if (ret) 2759 dev_err(psp->adev->dev, 2760 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2761 } 2762 2763 mutex_unlock(&adev->firmware.mutex); 2764 2765 return 0; 2766 2767 failed: 2768 DRM_ERROR("PSP resume failed\n"); 2769 mutex_unlock(&adev->firmware.mutex); 2770 return ret; 2771 } 2772 2773 int psp_gpu_reset(struct amdgpu_device *adev) 2774 { 2775 int ret; 2776 2777 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2778 return 0; 2779 2780 mutex_lock(&adev->psp.mutex); 2781 ret = psp_mode1_reset(&adev->psp); 2782 mutex_unlock(&adev->psp.mutex); 2783 2784 return ret; 2785 } 2786 2787 int psp_rlc_autoload_start(struct psp_context *psp) 2788 { 2789 int ret; 2790 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2791 2792 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2793 2794 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2795 psp->fence_buf_mc_addr); 2796 2797 release_psp_cmd_buf(psp); 2798 2799 return ret; 2800 } 2801 2802 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2803 uint64_t cmd_gpu_addr, int cmd_size) 2804 { 2805 struct amdgpu_firmware_info ucode = {0}; 2806 2807 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2808 AMDGPU_UCODE_ID_VCN0_RAM; 2809 ucode.mc_addr = cmd_gpu_addr; 2810 ucode.ucode_size = cmd_size; 2811 2812 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2813 } 2814 2815 int psp_ring_cmd_submit(struct psp_context *psp, 2816 uint64_t cmd_buf_mc_addr, 2817 uint64_t fence_mc_addr, 2818 int index) 2819 { 2820 unsigned int psp_write_ptr_reg = 0; 2821 struct psp_gfx_rb_frame *write_frame; 2822 struct psp_ring *ring = &psp->km_ring; 2823 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2824 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2825 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2826 struct amdgpu_device *adev = psp->adev; 2827 uint32_t ring_size_dw = ring->ring_size / 4; 2828 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2829 2830 /* KM (GPCOM) prepare write pointer */ 2831 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2832 2833 /* Update KM RB frame pointer to new frame */ 2834 /* write_frame ptr increments by size of rb_frame in bytes */ 2835 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2836 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2837 write_frame = ring_buffer_start; 2838 else 2839 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2840 /* Check invalid write_frame ptr address */ 2841 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2842 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2843 ring_buffer_start, ring_buffer_end, write_frame); 2844 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2845 return -EINVAL; 2846 } 2847 2848 /* Initialize KM RB frame */ 2849 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2850 2851 /* Update KM RB frame */ 2852 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2853 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2854 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2855 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2856 write_frame->fence_value = index; 2857 amdgpu_device_flush_hdp(adev, NULL); 2858 2859 /* Update the write Pointer in DWORDs */ 2860 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2861 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2862 return 0; 2863 } 2864 2865 int psp_init_asd_microcode(struct psp_context *psp, 2866 const char *chip_name) 2867 { 2868 struct amdgpu_device *adev = psp->adev; 2869 char fw_name[PSP_FW_NAME_LEN]; 2870 const struct psp_firmware_header_v1_0 *asd_hdr; 2871 int err = 0; 2872 2873 if (!chip_name) { 2874 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2875 return -EINVAL; 2876 } 2877 2878 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2879 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2880 if (err) 2881 goto out; 2882 2883 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2884 if (err) 2885 goto out; 2886 2887 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2888 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2889 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2890 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2891 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2892 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2893 return 0; 2894 out: 2895 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2896 release_firmware(adev->psp.asd_fw); 2897 adev->psp.asd_fw = NULL; 2898 return err; 2899 } 2900 2901 int psp_init_toc_microcode(struct psp_context *psp, 2902 const char *chip_name) 2903 { 2904 struct amdgpu_device *adev = psp->adev; 2905 char fw_name[PSP_FW_NAME_LEN]; 2906 const struct psp_firmware_header_v1_0 *toc_hdr; 2907 int err = 0; 2908 2909 if (!chip_name) { 2910 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2911 return -EINVAL; 2912 } 2913 2914 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2915 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2916 if (err) 2917 goto out; 2918 2919 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2920 if (err) 2921 goto out; 2922 2923 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2924 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2925 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2926 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2927 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2928 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2929 return 0; 2930 out: 2931 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2932 release_firmware(adev->psp.toc_fw); 2933 adev->psp.toc_fw = NULL; 2934 return err; 2935 } 2936 2937 static int parse_sos_bin_descriptor(struct psp_context *psp, 2938 const struct psp_fw_bin_desc *desc, 2939 const struct psp_firmware_header_v2_0 *sos_hdr) 2940 { 2941 uint8_t *ucode_start_addr = NULL; 2942 2943 if (!psp || !desc || !sos_hdr) 2944 return -EINVAL; 2945 2946 ucode_start_addr = (uint8_t *)sos_hdr + 2947 le32_to_cpu(desc->offset_bytes) + 2948 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2949 2950 switch (desc->fw_type) { 2951 case PSP_FW_TYPE_PSP_SOS: 2952 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2953 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2954 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2955 psp->sos.start_addr = ucode_start_addr; 2956 break; 2957 case PSP_FW_TYPE_PSP_SYS_DRV: 2958 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2959 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2960 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2961 psp->sys.start_addr = ucode_start_addr; 2962 break; 2963 case PSP_FW_TYPE_PSP_KDB: 2964 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2965 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2966 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2967 psp->kdb.start_addr = ucode_start_addr; 2968 break; 2969 case PSP_FW_TYPE_PSP_TOC: 2970 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2971 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2972 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 2973 psp->toc.start_addr = ucode_start_addr; 2974 break; 2975 case PSP_FW_TYPE_PSP_SPL: 2976 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 2977 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 2978 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 2979 psp->spl.start_addr = ucode_start_addr; 2980 break; 2981 case PSP_FW_TYPE_PSP_RL: 2982 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 2983 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 2984 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 2985 psp->rl.start_addr = ucode_start_addr; 2986 break; 2987 case PSP_FW_TYPE_PSP_SOC_DRV: 2988 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 2989 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 2990 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2991 psp->soc_drv.start_addr = ucode_start_addr; 2992 break; 2993 case PSP_FW_TYPE_PSP_INTF_DRV: 2994 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 2995 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 2996 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2997 psp->intf_drv.start_addr = ucode_start_addr; 2998 break; 2999 case PSP_FW_TYPE_PSP_DBG_DRV: 3000 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3001 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3002 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3003 psp->dbg_drv.start_addr = ucode_start_addr; 3004 break; 3005 default: 3006 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3007 break; 3008 } 3009 3010 return 0; 3011 } 3012 3013 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3014 { 3015 const struct psp_firmware_header_v1_0 *sos_hdr; 3016 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3017 uint8_t *ucode_array_start_addr; 3018 3019 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3020 ucode_array_start_addr = (uint8_t *)sos_hdr + 3021 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3022 3023 if (adev->gmc.xgmi.connected_to_cpu || 3024 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3025 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3026 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3027 3028 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3029 adev->psp.sys.start_addr = ucode_array_start_addr; 3030 3031 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3032 adev->psp.sos.start_addr = ucode_array_start_addr + 3033 le32_to_cpu(sos_hdr->sos.offset_bytes); 3034 } else { 3035 /* Load alternate PSP SOS FW */ 3036 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3037 3038 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3039 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3040 3041 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3042 adev->psp.sys.start_addr = ucode_array_start_addr + 3043 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3044 3045 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3046 adev->psp.sos.start_addr = ucode_array_start_addr + 3047 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3048 } 3049 3050 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3051 dev_warn(adev->dev, "PSP SOS FW not available"); 3052 return -EINVAL; 3053 } 3054 3055 return 0; 3056 } 3057 3058 int psp_init_sos_microcode(struct psp_context *psp, 3059 const char *chip_name) 3060 { 3061 struct amdgpu_device *adev = psp->adev; 3062 char fw_name[PSP_FW_NAME_LEN]; 3063 const struct psp_firmware_header_v1_0 *sos_hdr; 3064 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3065 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3066 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3067 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3068 int err = 0; 3069 uint8_t *ucode_array_start_addr; 3070 int fw_index = 0; 3071 3072 if (!chip_name) { 3073 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3074 return -EINVAL; 3075 } 3076 3077 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3078 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3079 if (err) 3080 goto out; 3081 3082 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3083 if (err) 3084 goto out; 3085 3086 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3087 ucode_array_start_addr = (uint8_t *)sos_hdr + 3088 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3089 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3090 3091 switch (sos_hdr->header.header_version_major) { 3092 case 1: 3093 err = psp_init_sos_base_fw(adev); 3094 if (err) 3095 goto out; 3096 3097 if (sos_hdr->header.header_version_minor == 1) { 3098 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3099 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3100 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3101 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3102 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3103 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3104 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3105 } 3106 if (sos_hdr->header.header_version_minor == 2) { 3107 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3108 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3109 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3110 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3111 } 3112 if (sos_hdr->header.header_version_minor == 3) { 3113 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3114 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3115 adev->psp.toc.start_addr = ucode_array_start_addr + 3116 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3117 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3118 adev->psp.kdb.start_addr = ucode_array_start_addr + 3119 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3120 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3121 adev->psp.spl.start_addr = ucode_array_start_addr + 3122 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3123 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3124 adev->psp.rl.start_addr = ucode_array_start_addr + 3125 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3126 } 3127 break; 3128 case 2: 3129 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3130 3131 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3132 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3133 err = -EINVAL; 3134 goto out; 3135 } 3136 3137 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3138 err = parse_sos_bin_descriptor(psp, 3139 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3140 sos_hdr_v2_0); 3141 if (err) 3142 goto out; 3143 } 3144 break; 3145 default: 3146 dev_err(adev->dev, 3147 "unsupported psp sos firmware\n"); 3148 err = -EINVAL; 3149 goto out; 3150 } 3151 3152 return 0; 3153 out: 3154 dev_err(adev->dev, 3155 "failed to init sos firmware\n"); 3156 release_firmware(adev->psp.sos_fw); 3157 adev->psp.sos_fw = NULL; 3158 3159 return err; 3160 } 3161 3162 static int parse_ta_bin_descriptor(struct psp_context *psp, 3163 const struct psp_fw_bin_desc *desc, 3164 const struct ta_firmware_header_v2_0 *ta_hdr) 3165 { 3166 uint8_t *ucode_start_addr = NULL; 3167 3168 if (!psp || !desc || !ta_hdr) 3169 return -EINVAL; 3170 3171 ucode_start_addr = (uint8_t *)ta_hdr + 3172 le32_to_cpu(desc->offset_bytes) + 3173 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3174 3175 switch (desc->fw_type) { 3176 case TA_FW_TYPE_PSP_ASD: 3177 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3178 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3179 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3180 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3181 break; 3182 case TA_FW_TYPE_PSP_XGMI: 3183 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3184 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3185 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3186 break; 3187 case TA_FW_TYPE_PSP_RAS: 3188 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3189 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3190 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3191 break; 3192 case TA_FW_TYPE_PSP_HDCP: 3193 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3194 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3195 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3196 break; 3197 case TA_FW_TYPE_PSP_DTM: 3198 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3199 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3200 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3201 break; 3202 case TA_FW_TYPE_PSP_RAP: 3203 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3204 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3205 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3206 break; 3207 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3208 psp->securedisplay_context.context.bin_desc.fw_version = 3209 le32_to_cpu(desc->fw_version); 3210 psp->securedisplay_context.context.bin_desc.size_bytes = 3211 le32_to_cpu(desc->size_bytes); 3212 psp->securedisplay_context.context.bin_desc.start_addr = 3213 ucode_start_addr; 3214 break; 3215 default: 3216 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3217 break; 3218 } 3219 3220 return 0; 3221 } 3222 3223 int psp_init_ta_microcode(struct psp_context *psp, 3224 const char *chip_name) 3225 { 3226 struct amdgpu_device *adev = psp->adev; 3227 char fw_name[PSP_FW_NAME_LEN]; 3228 const struct ta_firmware_header_v2_0 *ta_hdr; 3229 int err = 0; 3230 int ta_index = 0; 3231 3232 if (!chip_name) { 3233 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3234 return -EINVAL; 3235 } 3236 3237 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3238 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3239 if (err) 3240 goto out; 3241 3242 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3243 if (err) 3244 goto out; 3245 3246 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3247 3248 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3249 dev_err(adev->dev, "unsupported TA header version\n"); 3250 err = -EINVAL; 3251 goto out; 3252 } 3253 3254 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3255 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3256 err = -EINVAL; 3257 goto out; 3258 } 3259 3260 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3261 err = parse_ta_bin_descriptor(psp, 3262 &ta_hdr->ta_fw_bin[ta_index], 3263 ta_hdr); 3264 if (err) 3265 goto out; 3266 } 3267 3268 return 0; 3269 out: 3270 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3271 release_firmware(adev->psp.ta_fw); 3272 adev->psp.ta_fw = NULL; 3273 return err; 3274 } 3275 3276 int psp_init_cap_microcode(struct psp_context *psp, 3277 const char *chip_name) 3278 { 3279 struct amdgpu_device *adev = psp->adev; 3280 char fw_name[PSP_FW_NAME_LEN]; 3281 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3282 struct amdgpu_firmware_info *info = NULL; 3283 int err = 0; 3284 3285 if (!chip_name) { 3286 dev_err(adev->dev, "invalid chip name for cap microcode\n"); 3287 return -EINVAL; 3288 } 3289 3290 if (!amdgpu_sriov_vf(adev)) { 3291 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3292 return -EINVAL; 3293 } 3294 3295 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3296 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev); 3297 if (err) { 3298 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3299 err = 0; 3300 goto out; 3301 } 3302 3303 err = amdgpu_ucode_validate(adev->psp.cap_fw); 3304 if (err) { 3305 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3306 goto out; 3307 } 3308 3309 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3310 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3311 info->fw = adev->psp.cap_fw; 3312 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3313 adev->psp.cap_fw->data; 3314 adev->firmware.fw_size += ALIGN( 3315 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3316 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3317 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3318 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3319 3320 return 0; 3321 3322 out: 3323 release_firmware(adev->psp.cap_fw); 3324 adev->psp.cap_fw = NULL; 3325 return err; 3326 } 3327 3328 static int psp_set_clockgating_state(void *handle, 3329 enum amd_clockgating_state state) 3330 { 3331 return 0; 3332 } 3333 3334 static int psp_set_powergating_state(void *handle, 3335 enum amd_powergating_state state) 3336 { 3337 return 0; 3338 } 3339 3340 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3341 struct device_attribute *attr, 3342 char *buf) 3343 { 3344 struct drm_device *ddev = dev_get_drvdata(dev); 3345 struct amdgpu_device *adev = drm_to_adev(ddev); 3346 uint32_t fw_ver; 3347 int ret; 3348 3349 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3350 DRM_INFO("PSP block is not ready yet."); 3351 return -EBUSY; 3352 } 3353 3354 mutex_lock(&adev->psp.mutex); 3355 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3356 mutex_unlock(&adev->psp.mutex); 3357 3358 if (ret) { 3359 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3360 return ret; 3361 } 3362 3363 return sysfs_emit(buf, "%x\n", fw_ver); 3364 } 3365 3366 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3367 struct device_attribute *attr, 3368 const char *buf, 3369 size_t count) 3370 { 3371 struct drm_device *ddev = dev_get_drvdata(dev); 3372 struct amdgpu_device *adev = drm_to_adev(ddev); 3373 int ret, idx; 3374 char fw_name[100]; 3375 const struct firmware *usbc_pd_fw; 3376 struct amdgpu_bo *fw_buf_bo = NULL; 3377 uint64_t fw_pri_mc_addr; 3378 void *fw_pri_cpu_addr; 3379 3380 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3381 DRM_INFO("PSP block is not ready yet."); 3382 return -EBUSY; 3383 } 3384 3385 if (!drm_dev_enter(ddev, &idx)) 3386 return -ENODEV; 3387 3388 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3389 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3390 if (ret) 3391 goto fail; 3392 3393 /* LFB address which is aligned to 1MB boundary per PSP request */ 3394 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3395 AMDGPU_GEM_DOMAIN_VRAM, 3396 &fw_buf_bo, 3397 &fw_pri_mc_addr, 3398 &fw_pri_cpu_addr); 3399 if (ret) 3400 goto rel_buf; 3401 3402 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3403 3404 mutex_lock(&adev->psp.mutex); 3405 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3406 mutex_unlock(&adev->psp.mutex); 3407 3408 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3409 3410 rel_buf: 3411 release_firmware(usbc_pd_fw); 3412 fail: 3413 if (ret) { 3414 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3415 count = ret; 3416 } 3417 3418 drm_dev_exit(idx); 3419 return count; 3420 } 3421 3422 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3423 { 3424 int idx; 3425 3426 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3427 return; 3428 3429 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3430 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3431 3432 drm_dev_exit(idx); 3433 } 3434 3435 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3436 psp_usbc_pd_fw_sysfs_read, 3437 psp_usbc_pd_fw_sysfs_write); 3438 3439 int is_psp_fw_valid(struct psp_bin_desc bin) 3440 { 3441 return bin.size_bytes; 3442 } 3443 3444 const struct amd_ip_funcs psp_ip_funcs = { 3445 .name = "psp", 3446 .early_init = psp_early_init, 3447 .late_init = NULL, 3448 .sw_init = psp_sw_init, 3449 .sw_fini = psp_sw_fini, 3450 .hw_init = psp_hw_init, 3451 .hw_fini = psp_hw_fini, 3452 .suspend = psp_suspend, 3453 .resume = psp_resume, 3454 .is_idle = NULL, 3455 .check_soft_reset = NULL, 3456 .wait_for_idle = NULL, 3457 .soft_reset = NULL, 3458 .set_clockgating_state = psp_set_clockgating_state, 3459 .set_powergating_state = psp_set_powergating_state, 3460 }; 3461 3462 static int psp_sysfs_init(struct amdgpu_device *adev) 3463 { 3464 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3465 3466 if (ret) 3467 DRM_ERROR("Failed to create USBC PD FW control file!"); 3468 3469 return ret; 3470 } 3471 3472 static void psp_sysfs_fini(struct amdgpu_device *adev) 3473 { 3474 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3475 } 3476 3477 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3478 { 3479 .type = AMD_IP_BLOCK_TYPE_PSP, 3480 .major = 3, 3481 .minor = 1, 3482 .rev = 0, 3483 .funcs = &psp_ip_funcs, 3484 }; 3485 3486 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3487 { 3488 .type = AMD_IP_BLOCK_TYPE_PSP, 3489 .major = 10, 3490 .minor = 0, 3491 .rev = 0, 3492 .funcs = &psp_ip_funcs, 3493 }; 3494 3495 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3496 { 3497 .type = AMD_IP_BLOCK_TYPE_PSP, 3498 .major = 11, 3499 .minor = 0, 3500 .rev = 0, 3501 .funcs = &psp_ip_funcs, 3502 }; 3503 3504 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3505 .type = AMD_IP_BLOCK_TYPE_PSP, 3506 .major = 11, 3507 .minor = 0, 3508 .rev = 8, 3509 .funcs = &psp_ip_funcs, 3510 }; 3511 3512 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3513 { 3514 .type = AMD_IP_BLOCK_TYPE_PSP, 3515 .major = 12, 3516 .minor = 0, 3517 .rev = 0, 3518 .funcs = &psp_ip_funcs, 3519 }; 3520 3521 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3522 .type = AMD_IP_BLOCK_TYPE_PSP, 3523 .major = 13, 3524 .minor = 0, 3525 .rev = 0, 3526 .funcs = &psp_ip_funcs, 3527 }; 3528