1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/dma-mapping.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v3_1.h" 34 #include "psp_v10_0.h" 35 #include "psp_v11_0.h" 36 #include "psp_v12_0.h" 37 38 #include "amdgpu_ras.h" 39 40 static int psp_sysfs_init(struct amdgpu_device *adev); 41 static void psp_sysfs_fini(struct amdgpu_device *adev); 42 43 static int psp_load_smu_fw(struct psp_context *psp); 44 45 /* 46 * Due to DF Cstate management centralized to PMFW, the firmware 47 * loading sequence will be updated as below: 48 * - Load KDB 49 * - Load SYS_DRV 50 * - Load tOS 51 * - Load PMFW 52 * - Setup TMR 53 * - Load other non-psp fw 54 * - Load ASD 55 * - Load XGMI/RAS/HDCP/DTM TA if any 56 * 57 * This new sequence is required for 58 * - Arcturus 59 * - Navi12 and onwards 60 */ 61 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 62 { 63 struct amdgpu_device *adev = psp->adev; 64 65 psp->pmfw_centralized_cstate_management = false; 66 67 if (amdgpu_sriov_vf(adev)) 68 return; 69 70 if (adev->flags & AMD_IS_APU) 71 return; 72 73 if ((adev->asic_type == CHIP_ARCTURUS) || 74 (adev->asic_type >= CHIP_NAVI12)) 75 psp->pmfw_centralized_cstate_management = true; 76 } 77 78 static int psp_early_init(void *handle) 79 { 80 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 81 struct psp_context *psp = &adev->psp; 82 83 switch (adev->asic_type) { 84 case CHIP_VEGA10: 85 case CHIP_VEGA12: 86 psp_v3_1_set_psp_funcs(psp); 87 psp->autoload_supported = false; 88 break; 89 case CHIP_RAVEN: 90 psp_v10_0_set_psp_funcs(psp); 91 psp->autoload_supported = false; 92 break; 93 case CHIP_VEGA20: 94 case CHIP_ARCTURUS: 95 psp_v11_0_set_psp_funcs(psp); 96 psp->autoload_supported = false; 97 break; 98 case CHIP_NAVI10: 99 case CHIP_NAVI14: 100 case CHIP_NAVI12: 101 case CHIP_SIENNA_CICHLID: 102 case CHIP_NAVY_FLOUNDER: 103 case CHIP_VANGOGH: 104 case CHIP_DIMGREY_CAVEFISH: 105 psp_v11_0_set_psp_funcs(psp); 106 psp->autoload_supported = true; 107 break; 108 case CHIP_RENOIR: 109 psp_v12_0_set_psp_funcs(psp); 110 break; 111 default: 112 return -EINVAL; 113 } 114 115 psp->adev = adev; 116 117 psp_check_pmfw_centralized_cstate_management(psp); 118 119 return 0; 120 } 121 122 static void psp_memory_training_fini(struct psp_context *psp) 123 { 124 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 125 126 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 127 kfree(ctx->sys_cache); 128 ctx->sys_cache = NULL; 129 } 130 131 static int psp_memory_training_init(struct psp_context *psp) 132 { 133 int ret; 134 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 135 136 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 137 DRM_DEBUG("memory training is not supported!\n"); 138 return 0; 139 } 140 141 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 142 if (ctx->sys_cache == NULL) { 143 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 144 ret = -ENOMEM; 145 goto Err_out; 146 } 147 148 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 149 ctx->train_data_size, 150 ctx->p2c_train_data_offset, 151 ctx->c2p_train_data_offset); 152 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 153 return 0; 154 155 Err_out: 156 psp_memory_training_fini(psp); 157 return ret; 158 } 159 160 static int psp_sw_init(void *handle) 161 { 162 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 163 struct psp_context *psp = &adev->psp; 164 int ret; 165 166 if (!amdgpu_sriov_vf(adev)) { 167 ret = psp_init_microcode(psp); 168 if (ret) { 169 DRM_ERROR("Failed to load psp firmware!\n"); 170 return ret; 171 } 172 } 173 174 ret = psp_memory_training_init(psp); 175 if (ret) { 176 DRM_ERROR("Failed to initialize memory training!\n"); 177 return ret; 178 } 179 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 180 if (ret) { 181 DRM_ERROR("Failed to process memory training!\n"); 182 return ret; 183 } 184 185 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 186 ret= psp_sysfs_init(adev); 187 if (ret) { 188 return ret; 189 } 190 } 191 192 return 0; 193 } 194 195 static int psp_sw_fini(void *handle) 196 { 197 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 198 199 psp_memory_training_fini(&adev->psp); 200 if (adev->psp.sos_fw) { 201 release_firmware(adev->psp.sos_fw); 202 adev->psp.sos_fw = NULL; 203 } 204 if (adev->psp.asd_fw) { 205 release_firmware(adev->psp.asd_fw); 206 adev->psp.asd_fw = NULL; 207 } 208 if (adev->psp.ta_fw) { 209 release_firmware(adev->psp.ta_fw); 210 adev->psp.ta_fw = NULL; 211 } 212 213 if (adev->asic_type == CHIP_NAVI10 || 214 adev->asic_type == CHIP_SIENNA_CICHLID) 215 psp_sysfs_fini(adev); 216 217 return 0; 218 } 219 220 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 221 uint32_t reg_val, uint32_t mask, bool check_changed) 222 { 223 uint32_t val; 224 int i; 225 struct amdgpu_device *adev = psp->adev; 226 227 if (psp->adev->in_pci_err_recovery) 228 return 0; 229 230 for (i = 0; i < adev->usec_timeout; i++) { 231 val = RREG32(reg_index); 232 if (check_changed) { 233 if (val != reg_val) 234 return 0; 235 } else { 236 if ((val & mask) == reg_val) 237 return 0; 238 } 239 udelay(1); 240 } 241 242 return -ETIME; 243 } 244 245 static int 246 psp_cmd_submit_buf(struct psp_context *psp, 247 struct amdgpu_firmware_info *ucode, 248 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 249 { 250 int ret; 251 int index; 252 int timeout = 2000; 253 bool ras_intr = false; 254 bool skip_unsupport = false; 255 256 if (psp->adev->in_pci_err_recovery) 257 return 0; 258 259 mutex_lock(&psp->mutex); 260 261 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 262 263 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 264 265 index = atomic_inc_return(&psp->fence_value); 266 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 267 if (ret) { 268 atomic_dec(&psp->fence_value); 269 mutex_unlock(&psp->mutex); 270 return ret; 271 } 272 273 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 274 while (*((unsigned int *)psp->fence_buf) != index) { 275 if (--timeout == 0) 276 break; 277 /* 278 * Shouldn't wait for timeout when err_event_athub occurs, 279 * because gpu reset thread triggered and lock resource should 280 * be released for psp resume sequence. 281 */ 282 ras_intr = amdgpu_ras_intr_triggered(); 283 if (ras_intr) 284 break; 285 msleep(1); 286 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 287 } 288 289 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 290 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 291 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 292 293 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 294 295 /* In some cases, psp response status is not 0 even there is no 296 * problem while the command is submitted. Some version of PSP FW 297 * doesn't write 0 to that field. 298 * So here we would like to only print a warning instead of an error 299 * during psp initialization to avoid breaking hw_init and it doesn't 300 * return -EINVAL. 301 */ 302 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 303 if (ucode) 304 DRM_WARN("failed to load ucode id (%d) ", 305 ucode->ucode_id); 306 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n", 307 psp->cmd_buf_mem->cmd_id, 308 psp->cmd_buf_mem->resp.status); 309 if (!timeout) { 310 mutex_unlock(&psp->mutex); 311 return -EINVAL; 312 } 313 } 314 315 if (ucode) { 316 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 317 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 318 } 319 mutex_unlock(&psp->mutex); 320 321 return ret; 322 } 323 324 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 325 struct psp_gfx_cmd_resp *cmd, 326 uint64_t tmr_mc, uint32_t size) 327 { 328 if (amdgpu_sriov_vf(psp->adev)) 329 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 330 else 331 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 332 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 333 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 334 cmd->cmd.cmd_setup_tmr.buf_size = size; 335 } 336 337 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 338 uint64_t pri_buf_mc, uint32_t size) 339 { 340 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 341 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 342 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 343 cmd->cmd.cmd_load_toc.toc_size = size; 344 } 345 346 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 347 static int psp_load_toc(struct psp_context *psp, 348 uint32_t *tmr_size) 349 { 350 int ret; 351 struct psp_gfx_cmd_resp *cmd; 352 353 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 354 if (!cmd) 355 return -ENOMEM; 356 /* Copy toc to psp firmware private buffer */ 357 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 358 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size); 359 360 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 361 362 ret = psp_cmd_submit_buf(psp, NULL, cmd, 363 psp->fence_buf_mc_addr); 364 if (!ret) 365 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 366 kfree(cmd); 367 return ret; 368 } 369 370 /* Set up Trusted Memory Region */ 371 static int psp_tmr_init(struct psp_context *psp) 372 { 373 int ret; 374 int tmr_size; 375 void *tmr_buf; 376 void **pptr; 377 378 /* 379 * According to HW engineer, they prefer the TMR address be "naturally 380 * aligned" , e.g. the start address be an integer divide of TMR size. 381 * 382 * Note: this memory need be reserved till the driver 383 * uninitializes. 384 */ 385 tmr_size = PSP_TMR_SIZE; 386 387 /* For ASICs support RLC autoload, psp will parse the toc 388 * and calculate the total size of TMR needed */ 389 if (!amdgpu_sriov_vf(psp->adev) && 390 psp->toc_start_addr && 391 psp->toc_bin_size && 392 psp->fw_pri_buf) { 393 ret = psp_load_toc(psp, &tmr_size); 394 if (ret) { 395 DRM_ERROR("Failed to load toc\n"); 396 return ret; 397 } 398 } 399 400 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 401 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE, 402 AMDGPU_GEM_DOMAIN_VRAM, 403 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 404 405 return ret; 406 } 407 408 static int psp_clear_vf_fw(struct psp_context *psp) 409 { 410 int ret; 411 struct psp_gfx_cmd_resp *cmd; 412 413 if (!amdgpu_sriov_vf(psp->adev) || psp->adev->asic_type != CHIP_NAVI12) 414 return 0; 415 416 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 417 if (!cmd) 418 return -ENOMEM; 419 420 cmd->cmd_id = GFX_CMD_ID_CLEAR_VF_FW; 421 422 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 423 kfree(cmd); 424 425 return ret; 426 } 427 428 static bool psp_skip_tmr(struct psp_context *psp) 429 { 430 switch (psp->adev->asic_type) { 431 case CHIP_NAVI12: 432 case CHIP_SIENNA_CICHLID: 433 return true; 434 default: 435 return false; 436 } 437 } 438 439 static int psp_tmr_load(struct psp_context *psp) 440 { 441 int ret; 442 struct psp_gfx_cmd_resp *cmd; 443 444 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 445 * Already set up by host driver. 446 */ 447 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 448 return 0; 449 450 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 451 if (!cmd) 452 return -ENOMEM; 453 454 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, 455 amdgpu_bo_size(psp->tmr_bo)); 456 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 457 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 458 459 ret = psp_cmd_submit_buf(psp, NULL, cmd, 460 psp->fence_buf_mc_addr); 461 462 kfree(cmd); 463 464 return ret; 465 } 466 467 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 468 struct psp_gfx_cmd_resp *cmd) 469 { 470 if (amdgpu_sriov_vf(psp->adev)) 471 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 472 else 473 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 474 } 475 476 static int psp_tmr_unload(struct psp_context *psp) 477 { 478 int ret; 479 struct psp_gfx_cmd_resp *cmd; 480 481 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 482 if (!cmd) 483 return -ENOMEM; 484 485 psp_prep_tmr_unload_cmd_buf(psp, cmd); 486 DRM_INFO("free PSP TMR buffer\n"); 487 488 ret = psp_cmd_submit_buf(psp, NULL, cmd, 489 psp->fence_buf_mc_addr); 490 491 kfree(cmd); 492 493 return ret; 494 } 495 496 static int psp_tmr_terminate(struct psp_context *psp) 497 { 498 int ret; 499 void *tmr_buf; 500 void **pptr; 501 502 ret = psp_tmr_unload(psp); 503 if (ret) 504 return ret; 505 506 /* free TMR memory buffer */ 507 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 508 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 509 510 return 0; 511 } 512 513 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 514 uint64_t *output_ptr) 515 { 516 int ret; 517 struct psp_gfx_cmd_resp *cmd; 518 519 if (!output_ptr) 520 return -EINVAL; 521 522 if (amdgpu_sriov_vf(psp->adev)) 523 return 0; 524 525 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 526 if (!cmd) 527 return -ENOMEM; 528 529 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 530 531 ret = psp_cmd_submit_buf(psp, NULL, cmd, 532 psp->fence_buf_mc_addr); 533 534 if (!ret) { 535 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 536 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 537 } 538 539 kfree(cmd); 540 541 return ret; 542 } 543 544 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 545 uint64_t asd_mc, uint32_t size) 546 { 547 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 548 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 549 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 550 cmd->cmd.cmd_load_ta.app_len = size; 551 552 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 553 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 554 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 555 } 556 557 static int psp_asd_load(struct psp_context *psp) 558 { 559 int ret; 560 struct psp_gfx_cmd_resp *cmd; 561 562 /* If PSP version doesn't match ASD version, asd loading will be failed. 563 * add workaround to bypass it for sriov now. 564 * TODO: add version check to make it common 565 */ 566 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_fw) 567 return 0; 568 569 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 570 if (!cmd) 571 return -ENOMEM; 572 573 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 574 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 575 576 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 577 psp->asd_ucode_size); 578 579 ret = psp_cmd_submit_buf(psp, NULL, cmd, 580 psp->fence_buf_mc_addr); 581 if (!ret) { 582 psp->asd_context.asd_initialized = true; 583 psp->asd_context.session_id = cmd->resp.session_id; 584 } 585 586 kfree(cmd); 587 588 return ret; 589 } 590 591 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 592 uint32_t session_id) 593 { 594 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 595 cmd->cmd.cmd_unload_ta.session_id = session_id; 596 } 597 598 static int psp_asd_unload(struct psp_context *psp) 599 { 600 int ret; 601 struct psp_gfx_cmd_resp *cmd; 602 603 if (amdgpu_sriov_vf(psp->adev)) 604 return 0; 605 606 if (!psp->asd_context.asd_initialized) 607 return 0; 608 609 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 610 if (!cmd) 611 return -ENOMEM; 612 613 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 614 615 ret = psp_cmd_submit_buf(psp, NULL, cmd, 616 psp->fence_buf_mc_addr); 617 if (!ret) 618 psp->asd_context.asd_initialized = false; 619 620 kfree(cmd); 621 622 return ret; 623 } 624 625 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 626 uint32_t id, uint32_t value) 627 { 628 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 629 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 630 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 631 } 632 633 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 634 uint32_t value) 635 { 636 struct psp_gfx_cmd_resp *cmd = NULL; 637 int ret = 0; 638 639 if (reg >= PSP_REG_LAST) 640 return -EINVAL; 641 642 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 643 if (!cmd) 644 return -ENOMEM; 645 646 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 647 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 648 649 kfree(cmd); 650 return ret; 651 } 652 653 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 654 uint64_t ta_bin_mc, 655 uint32_t ta_bin_size, 656 uint64_t ta_shared_mc, 657 uint32_t ta_shared_size) 658 { 659 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 660 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 661 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 662 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 663 664 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 665 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 666 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 667 } 668 669 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 670 { 671 int ret; 672 673 /* 674 * Allocate 16k memory aligned to 4k from Frame Buffer (local 675 * physical) for xgmi ta <-> Driver 676 */ 677 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 678 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 679 &psp->xgmi_context.xgmi_shared_bo, 680 &psp->xgmi_context.xgmi_shared_mc_addr, 681 &psp->xgmi_context.xgmi_shared_buf); 682 683 return ret; 684 } 685 686 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 687 uint32_t ta_cmd_id, 688 uint32_t session_id) 689 { 690 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 691 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 692 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 693 } 694 695 static int psp_ta_invoke(struct psp_context *psp, 696 uint32_t ta_cmd_id, 697 uint32_t session_id) 698 { 699 int ret; 700 struct psp_gfx_cmd_resp *cmd; 701 702 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 703 if (!cmd) 704 return -ENOMEM; 705 706 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 707 708 ret = psp_cmd_submit_buf(psp, NULL, cmd, 709 psp->fence_buf_mc_addr); 710 711 kfree(cmd); 712 713 return ret; 714 } 715 716 static int psp_xgmi_load(struct psp_context *psp) 717 { 718 int ret; 719 struct psp_gfx_cmd_resp *cmd; 720 721 /* 722 * TODO: bypass the loading in sriov for now 723 */ 724 725 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 726 if (!cmd) 727 return -ENOMEM; 728 729 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 730 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 731 732 psp_prep_ta_load_cmd_buf(cmd, 733 psp->fw_pri_mc_addr, 734 psp->ta_xgmi_ucode_size, 735 psp->xgmi_context.xgmi_shared_mc_addr, 736 PSP_XGMI_SHARED_MEM_SIZE); 737 738 ret = psp_cmd_submit_buf(psp, NULL, cmd, 739 psp->fence_buf_mc_addr); 740 741 if (!ret) { 742 psp->xgmi_context.initialized = 1; 743 psp->xgmi_context.session_id = cmd->resp.session_id; 744 } 745 746 kfree(cmd); 747 748 return ret; 749 } 750 751 static int psp_xgmi_unload(struct psp_context *psp) 752 { 753 int ret; 754 struct psp_gfx_cmd_resp *cmd; 755 struct amdgpu_device *adev = psp->adev; 756 757 /* XGMI TA unload currently is not supported on Arcturus */ 758 if (adev->asic_type == CHIP_ARCTURUS) 759 return 0; 760 761 /* 762 * TODO: bypass the unloading in sriov for now 763 */ 764 765 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 766 if (!cmd) 767 return -ENOMEM; 768 769 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 770 771 ret = psp_cmd_submit_buf(psp, NULL, cmd, 772 psp->fence_buf_mc_addr); 773 774 kfree(cmd); 775 776 return ret; 777 } 778 779 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 780 { 781 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 782 } 783 784 int psp_xgmi_terminate(struct psp_context *psp) 785 { 786 int ret; 787 788 if (!psp->xgmi_context.initialized) 789 return 0; 790 791 ret = psp_xgmi_unload(psp); 792 if (ret) 793 return ret; 794 795 psp->xgmi_context.initialized = 0; 796 797 /* free xgmi shared memory */ 798 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 799 &psp->xgmi_context.xgmi_shared_mc_addr, 800 &psp->xgmi_context.xgmi_shared_buf); 801 802 return 0; 803 } 804 805 int psp_xgmi_initialize(struct psp_context *psp) 806 { 807 struct ta_xgmi_shared_memory *xgmi_cmd; 808 int ret; 809 810 if (!psp->adev->psp.ta_fw || 811 !psp->adev->psp.ta_xgmi_ucode_size || 812 !psp->adev->psp.ta_xgmi_start_addr) 813 return -ENOENT; 814 815 if (!psp->xgmi_context.initialized) { 816 ret = psp_xgmi_init_shared_buf(psp); 817 if (ret) 818 return ret; 819 } 820 821 /* Load XGMI TA */ 822 ret = psp_xgmi_load(psp); 823 if (ret) 824 return ret; 825 826 /* Initialize XGMI session */ 827 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 828 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 829 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 830 831 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 832 833 return ret; 834 } 835 836 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 837 { 838 struct ta_xgmi_shared_memory *xgmi_cmd; 839 int ret; 840 841 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 842 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 843 844 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 845 846 /* Invoke xgmi ta to get hive id */ 847 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 848 if (ret) 849 return ret; 850 851 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 852 853 return 0; 854 } 855 856 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 857 { 858 struct ta_xgmi_shared_memory *xgmi_cmd; 859 int ret; 860 861 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 862 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 863 864 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 865 866 /* Invoke xgmi ta to get the node id */ 867 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 868 if (ret) 869 return ret; 870 871 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 872 873 return 0; 874 } 875 876 int psp_xgmi_get_topology_info(struct psp_context *psp, 877 int number_devices, 878 struct psp_xgmi_topology_info *topology) 879 { 880 struct ta_xgmi_shared_memory *xgmi_cmd; 881 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 882 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 883 int i; 884 int ret; 885 886 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 887 return -EINVAL; 888 889 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 890 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 891 892 /* Fill in the shared memory with topology information as input */ 893 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 894 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 895 topology_info_input->num_nodes = number_devices; 896 897 for (i = 0; i < topology_info_input->num_nodes; i++) { 898 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 899 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 900 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 901 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 902 } 903 904 /* Invoke xgmi ta to get the topology information */ 905 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 906 if (ret) 907 return ret; 908 909 /* Read the output topology information from the shared memory */ 910 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 911 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 912 for (i = 0; i < topology->num_nodes; i++) { 913 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 914 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 915 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 916 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 917 } 918 919 return 0; 920 } 921 922 int psp_xgmi_set_topology_info(struct psp_context *psp, 923 int number_devices, 924 struct psp_xgmi_topology_info *topology) 925 { 926 struct ta_xgmi_shared_memory *xgmi_cmd; 927 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 928 int i; 929 930 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 931 return -EINVAL; 932 933 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 934 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 935 936 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 937 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 938 topology_info_input->num_nodes = number_devices; 939 940 for (i = 0; i < topology_info_input->num_nodes; i++) { 941 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 942 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 943 topology_info_input->nodes[i].is_sharing_enabled = 1; 944 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 945 } 946 947 /* Invoke xgmi ta to set topology information */ 948 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 949 } 950 951 // ras begin 952 static int psp_ras_init_shared_buf(struct psp_context *psp) 953 { 954 int ret; 955 956 /* 957 * Allocate 16k memory aligned to 4k from Frame Buffer (local 958 * physical) for ras ta <-> Driver 959 */ 960 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 961 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 962 &psp->ras.ras_shared_bo, 963 &psp->ras.ras_shared_mc_addr, 964 &psp->ras.ras_shared_buf); 965 966 return ret; 967 } 968 969 static int psp_ras_load(struct psp_context *psp) 970 { 971 int ret; 972 struct psp_gfx_cmd_resp *cmd; 973 struct ta_ras_shared_memory *ras_cmd; 974 975 /* 976 * TODO: bypass the loading in sriov for now 977 */ 978 if (amdgpu_sriov_vf(psp->adev)) 979 return 0; 980 981 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 982 if (!cmd) 983 return -ENOMEM; 984 985 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 986 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 987 988 psp_prep_ta_load_cmd_buf(cmd, 989 psp->fw_pri_mc_addr, 990 psp->ta_ras_ucode_size, 991 psp->ras.ras_shared_mc_addr, 992 PSP_RAS_SHARED_MEM_SIZE); 993 994 ret = psp_cmd_submit_buf(psp, NULL, cmd, 995 psp->fence_buf_mc_addr); 996 997 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 998 999 if (!ret) { 1000 psp->ras.session_id = cmd->resp.session_id; 1001 1002 if (!ras_cmd->ras_status) 1003 psp->ras.ras_initialized = true; 1004 else 1005 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1006 } 1007 1008 if (ret || ras_cmd->ras_status) 1009 amdgpu_ras_fini(psp->adev); 1010 1011 kfree(cmd); 1012 1013 return ret; 1014 } 1015 1016 static int psp_ras_unload(struct psp_context *psp) 1017 { 1018 int ret; 1019 struct psp_gfx_cmd_resp *cmd; 1020 1021 /* 1022 * TODO: bypass the unloading in sriov for now 1023 */ 1024 if (amdgpu_sriov_vf(psp->adev)) 1025 return 0; 1026 1027 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1028 if (!cmd) 1029 return -ENOMEM; 1030 1031 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 1032 1033 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1034 psp->fence_buf_mc_addr); 1035 1036 kfree(cmd); 1037 1038 return ret; 1039 } 1040 1041 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1042 { 1043 struct ta_ras_shared_memory *ras_cmd; 1044 int ret; 1045 1046 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1047 1048 /* 1049 * TODO: bypass the loading in sriov for now 1050 */ 1051 if (amdgpu_sriov_vf(psp->adev)) 1052 return 0; 1053 1054 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 1055 1056 if (amdgpu_ras_intr_triggered()) 1057 return ret; 1058 1059 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1060 { 1061 DRM_WARN("RAS: Unsupported Interface"); 1062 return -EINVAL; 1063 } 1064 1065 if (!ret) { 1066 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1067 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1068 1069 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1070 } 1071 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1072 dev_warn(psp->adev->dev, 1073 "RAS internal register access blocked\n"); 1074 } 1075 1076 return ret; 1077 } 1078 1079 int psp_ras_enable_features(struct psp_context *psp, 1080 union ta_ras_cmd_input *info, bool enable) 1081 { 1082 struct ta_ras_shared_memory *ras_cmd; 1083 int ret; 1084 1085 if (!psp->ras.ras_initialized) 1086 return -EINVAL; 1087 1088 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1089 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1090 1091 if (enable) 1092 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1093 else 1094 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1095 1096 ras_cmd->ras_in_message = *info; 1097 1098 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1099 if (ret) 1100 return -EINVAL; 1101 1102 return ras_cmd->ras_status; 1103 } 1104 1105 static int psp_ras_terminate(struct psp_context *psp) 1106 { 1107 int ret; 1108 1109 /* 1110 * TODO: bypass the terminate in sriov for now 1111 */ 1112 if (amdgpu_sriov_vf(psp->adev)) 1113 return 0; 1114 1115 if (!psp->ras.ras_initialized) 1116 return 0; 1117 1118 ret = psp_ras_unload(psp); 1119 if (ret) 1120 return ret; 1121 1122 psp->ras.ras_initialized = false; 1123 1124 /* free ras shared memory */ 1125 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1126 &psp->ras.ras_shared_mc_addr, 1127 &psp->ras.ras_shared_buf); 1128 1129 return 0; 1130 } 1131 1132 static int psp_ras_initialize(struct psp_context *psp) 1133 { 1134 int ret; 1135 1136 /* 1137 * TODO: bypass the initialize in sriov for now 1138 */ 1139 if (amdgpu_sriov_vf(psp->adev)) 1140 return 0; 1141 1142 if (!psp->adev->psp.ta_ras_ucode_size || 1143 !psp->adev->psp.ta_ras_start_addr) { 1144 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n"); 1145 return 0; 1146 } 1147 1148 if (!psp->ras.ras_initialized) { 1149 ret = psp_ras_init_shared_buf(psp); 1150 if (ret) 1151 return ret; 1152 } 1153 1154 ret = psp_ras_load(psp); 1155 if (ret) 1156 return ret; 1157 1158 return 0; 1159 } 1160 1161 int psp_ras_trigger_error(struct psp_context *psp, 1162 struct ta_ras_trigger_error_input *info) 1163 { 1164 struct ta_ras_shared_memory *ras_cmd; 1165 int ret; 1166 1167 if (!psp->ras.ras_initialized) 1168 return -EINVAL; 1169 1170 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1171 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1172 1173 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1174 ras_cmd->ras_in_message.trigger_error = *info; 1175 1176 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1177 if (ret) 1178 return -EINVAL; 1179 1180 /* If err_event_athub occurs error inject was successful, however 1181 return status from TA is no long reliable */ 1182 if (amdgpu_ras_intr_triggered()) 1183 return 0; 1184 1185 return ras_cmd->ras_status; 1186 } 1187 // ras end 1188 1189 // HDCP start 1190 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1191 { 1192 int ret; 1193 1194 /* 1195 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1196 * physical) for hdcp ta <-> Driver 1197 */ 1198 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1199 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1200 &psp->hdcp_context.hdcp_shared_bo, 1201 &psp->hdcp_context.hdcp_shared_mc_addr, 1202 &psp->hdcp_context.hdcp_shared_buf); 1203 1204 return ret; 1205 } 1206 1207 static int psp_hdcp_load(struct psp_context *psp) 1208 { 1209 int ret; 1210 struct psp_gfx_cmd_resp *cmd; 1211 1212 /* 1213 * TODO: bypass the loading in sriov for now 1214 */ 1215 if (amdgpu_sriov_vf(psp->adev)) 1216 return 0; 1217 1218 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1219 if (!cmd) 1220 return -ENOMEM; 1221 1222 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1223 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr, 1224 psp->ta_hdcp_ucode_size); 1225 1226 psp_prep_ta_load_cmd_buf(cmd, 1227 psp->fw_pri_mc_addr, 1228 psp->ta_hdcp_ucode_size, 1229 psp->hdcp_context.hdcp_shared_mc_addr, 1230 PSP_HDCP_SHARED_MEM_SIZE); 1231 1232 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1233 1234 if (!ret) { 1235 psp->hdcp_context.hdcp_initialized = true; 1236 psp->hdcp_context.session_id = cmd->resp.session_id; 1237 mutex_init(&psp->hdcp_context.mutex); 1238 } 1239 1240 kfree(cmd); 1241 1242 return ret; 1243 } 1244 static int psp_hdcp_initialize(struct psp_context *psp) 1245 { 1246 int ret; 1247 1248 /* 1249 * TODO: bypass the initialize in sriov for now 1250 */ 1251 if (amdgpu_sriov_vf(psp->adev)) 1252 return 0; 1253 1254 if (!psp->adev->psp.ta_hdcp_ucode_size || 1255 !psp->adev->psp.ta_hdcp_start_addr) { 1256 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1257 return 0; 1258 } 1259 1260 if (!psp->hdcp_context.hdcp_initialized) { 1261 ret = psp_hdcp_init_shared_buf(psp); 1262 if (ret) 1263 return ret; 1264 } 1265 1266 ret = psp_hdcp_load(psp); 1267 if (ret) 1268 return ret; 1269 1270 return 0; 1271 } 1272 1273 static int psp_hdcp_unload(struct psp_context *psp) 1274 { 1275 int ret; 1276 struct psp_gfx_cmd_resp *cmd; 1277 1278 /* 1279 * TODO: bypass the unloading in sriov for now 1280 */ 1281 if (amdgpu_sriov_vf(psp->adev)) 1282 return 0; 1283 1284 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1285 if (!cmd) 1286 return -ENOMEM; 1287 1288 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1289 1290 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1291 1292 kfree(cmd); 1293 1294 return ret; 1295 } 1296 1297 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1298 { 1299 /* 1300 * TODO: bypass the loading in sriov for now 1301 */ 1302 if (amdgpu_sriov_vf(psp->adev)) 1303 return 0; 1304 1305 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1306 } 1307 1308 static int psp_hdcp_terminate(struct psp_context *psp) 1309 { 1310 int ret; 1311 1312 /* 1313 * TODO: bypass the terminate in sriov for now 1314 */ 1315 if (amdgpu_sriov_vf(psp->adev)) 1316 return 0; 1317 1318 if (!psp->hdcp_context.hdcp_initialized) 1319 return 0; 1320 1321 ret = psp_hdcp_unload(psp); 1322 if (ret) 1323 return ret; 1324 1325 psp->hdcp_context.hdcp_initialized = false; 1326 1327 /* free hdcp shared memory */ 1328 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1329 &psp->hdcp_context.hdcp_shared_mc_addr, 1330 &psp->hdcp_context.hdcp_shared_buf); 1331 1332 return 0; 1333 } 1334 // HDCP end 1335 1336 // DTM start 1337 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1338 { 1339 int ret; 1340 1341 /* 1342 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1343 * physical) for dtm ta <-> Driver 1344 */ 1345 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1346 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1347 &psp->dtm_context.dtm_shared_bo, 1348 &psp->dtm_context.dtm_shared_mc_addr, 1349 &psp->dtm_context.dtm_shared_buf); 1350 1351 return ret; 1352 } 1353 1354 static int psp_dtm_load(struct psp_context *psp) 1355 { 1356 int ret; 1357 struct psp_gfx_cmd_resp *cmd; 1358 1359 /* 1360 * TODO: bypass the loading in sriov for now 1361 */ 1362 if (amdgpu_sriov_vf(psp->adev)) 1363 return 0; 1364 1365 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1366 if (!cmd) 1367 return -ENOMEM; 1368 1369 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1370 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1371 1372 psp_prep_ta_load_cmd_buf(cmd, 1373 psp->fw_pri_mc_addr, 1374 psp->ta_dtm_ucode_size, 1375 psp->dtm_context.dtm_shared_mc_addr, 1376 PSP_DTM_SHARED_MEM_SIZE); 1377 1378 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1379 1380 if (!ret) { 1381 psp->dtm_context.dtm_initialized = true; 1382 psp->dtm_context.session_id = cmd->resp.session_id; 1383 mutex_init(&psp->dtm_context.mutex); 1384 } 1385 1386 kfree(cmd); 1387 1388 return ret; 1389 } 1390 1391 static int psp_dtm_initialize(struct psp_context *psp) 1392 { 1393 int ret; 1394 1395 /* 1396 * TODO: bypass the initialize in sriov for now 1397 */ 1398 if (amdgpu_sriov_vf(psp->adev)) 1399 return 0; 1400 1401 if (!psp->adev->psp.ta_dtm_ucode_size || 1402 !psp->adev->psp.ta_dtm_start_addr) { 1403 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1404 return 0; 1405 } 1406 1407 if (!psp->dtm_context.dtm_initialized) { 1408 ret = psp_dtm_init_shared_buf(psp); 1409 if (ret) 1410 return ret; 1411 } 1412 1413 ret = psp_dtm_load(psp); 1414 if (ret) 1415 return ret; 1416 1417 return 0; 1418 } 1419 1420 static int psp_dtm_unload(struct psp_context *psp) 1421 { 1422 int ret; 1423 struct psp_gfx_cmd_resp *cmd; 1424 1425 /* 1426 * TODO: bypass the unloading in sriov for now 1427 */ 1428 if (amdgpu_sriov_vf(psp->adev)) 1429 return 0; 1430 1431 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1432 if (!cmd) 1433 return -ENOMEM; 1434 1435 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1436 1437 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1438 1439 kfree(cmd); 1440 1441 return ret; 1442 } 1443 1444 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1445 { 1446 /* 1447 * TODO: bypass the loading in sriov for now 1448 */ 1449 if (amdgpu_sriov_vf(psp->adev)) 1450 return 0; 1451 1452 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1453 } 1454 1455 static int psp_dtm_terminate(struct psp_context *psp) 1456 { 1457 int ret; 1458 1459 /* 1460 * TODO: bypass the terminate in sriov for now 1461 */ 1462 if (amdgpu_sriov_vf(psp->adev)) 1463 return 0; 1464 1465 if (!psp->dtm_context.dtm_initialized) 1466 return 0; 1467 1468 ret = psp_dtm_unload(psp); 1469 if (ret) 1470 return ret; 1471 1472 psp->dtm_context.dtm_initialized = false; 1473 1474 /* free hdcp shared memory */ 1475 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1476 &psp->dtm_context.dtm_shared_mc_addr, 1477 &psp->dtm_context.dtm_shared_buf); 1478 1479 return 0; 1480 } 1481 // DTM end 1482 1483 // RAP start 1484 static int psp_rap_init_shared_buf(struct psp_context *psp) 1485 { 1486 int ret; 1487 1488 /* 1489 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1490 * physical) for rap ta <-> Driver 1491 */ 1492 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE, 1493 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1494 &psp->rap_context.rap_shared_bo, 1495 &psp->rap_context.rap_shared_mc_addr, 1496 &psp->rap_context.rap_shared_buf); 1497 1498 return ret; 1499 } 1500 1501 static int psp_rap_load(struct psp_context *psp) 1502 { 1503 int ret; 1504 struct psp_gfx_cmd_resp *cmd; 1505 1506 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1507 if (!cmd) 1508 return -ENOMEM; 1509 1510 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1511 memcpy(psp->fw_pri_buf, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); 1512 1513 psp_prep_ta_load_cmd_buf(cmd, 1514 psp->fw_pri_mc_addr, 1515 psp->ta_rap_ucode_size, 1516 psp->rap_context.rap_shared_mc_addr, 1517 PSP_RAP_SHARED_MEM_SIZE); 1518 1519 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1520 1521 if (!ret) { 1522 psp->rap_context.rap_initialized = true; 1523 psp->rap_context.session_id = cmd->resp.session_id; 1524 mutex_init(&psp->rap_context.mutex); 1525 } 1526 1527 kfree(cmd); 1528 1529 return ret; 1530 } 1531 1532 static int psp_rap_unload(struct psp_context *psp) 1533 { 1534 int ret; 1535 struct psp_gfx_cmd_resp *cmd; 1536 1537 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1538 if (!cmd) 1539 return -ENOMEM; 1540 1541 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id); 1542 1543 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1544 1545 kfree(cmd); 1546 1547 return ret; 1548 } 1549 1550 static int psp_rap_initialize(struct psp_context *psp) 1551 { 1552 int ret; 1553 1554 /* 1555 * TODO: bypass the initialize in sriov for now 1556 */ 1557 if (amdgpu_sriov_vf(psp->adev)) 1558 return 0; 1559 1560 if (!psp->adev->psp.ta_rap_ucode_size || 1561 !psp->adev->psp.ta_rap_start_addr) { 1562 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1563 return 0; 1564 } 1565 1566 if (!psp->rap_context.rap_initialized) { 1567 ret = psp_rap_init_shared_buf(psp); 1568 if (ret) 1569 return ret; 1570 } 1571 1572 ret = psp_rap_load(psp); 1573 if (ret) 1574 return ret; 1575 1576 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE); 1577 if (ret != TA_RAP_STATUS__SUCCESS) { 1578 psp_rap_unload(psp); 1579 1580 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1581 &psp->rap_context.rap_shared_mc_addr, 1582 &psp->rap_context.rap_shared_buf); 1583 1584 psp->rap_context.rap_initialized = false; 1585 1586 dev_warn(psp->adev->dev, "RAP TA initialize fail.\n"); 1587 return -EINVAL; 1588 } 1589 1590 return 0; 1591 } 1592 1593 static int psp_rap_terminate(struct psp_context *psp) 1594 { 1595 int ret; 1596 1597 if (!psp->rap_context.rap_initialized) 1598 return 0; 1599 1600 ret = psp_rap_unload(psp); 1601 1602 psp->rap_context.rap_initialized = false; 1603 1604 /* free rap shared memory */ 1605 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1606 &psp->rap_context.rap_shared_mc_addr, 1607 &psp->rap_context.rap_shared_buf); 1608 1609 return ret; 1610 } 1611 1612 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1613 { 1614 struct ta_rap_shared_memory *rap_cmd; 1615 int ret; 1616 1617 if (!psp->rap_context.rap_initialized) 1618 return -EINVAL; 1619 1620 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1621 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1622 return -EINVAL; 1623 1624 mutex_lock(&psp->rap_context.mutex); 1625 1626 rap_cmd = (struct ta_rap_shared_memory *) 1627 psp->rap_context.rap_shared_buf; 1628 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1629 1630 rap_cmd->cmd_id = ta_cmd_id; 1631 rap_cmd->validation_method_id = METHOD_A; 1632 1633 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id); 1634 if (ret) { 1635 mutex_unlock(&psp->rap_context.mutex); 1636 return ret; 1637 } 1638 1639 mutex_unlock(&psp->rap_context.mutex); 1640 1641 return rap_cmd->rap_status; 1642 } 1643 // RAP end 1644 1645 static int psp_hw_start(struct psp_context *psp) 1646 { 1647 struct amdgpu_device *adev = psp->adev; 1648 int ret; 1649 1650 if (!amdgpu_sriov_vf(adev)) { 1651 if (psp->kdb_bin_size && 1652 (psp->funcs->bootloader_load_kdb != NULL)) { 1653 ret = psp_bootloader_load_kdb(psp); 1654 if (ret) { 1655 DRM_ERROR("PSP load kdb failed!\n"); 1656 return ret; 1657 } 1658 } 1659 1660 if (psp->spl_bin_size) { 1661 ret = psp_bootloader_load_spl(psp); 1662 if (ret) { 1663 DRM_ERROR("PSP load spl failed!\n"); 1664 return ret; 1665 } 1666 } 1667 1668 ret = psp_bootloader_load_sysdrv(psp); 1669 if (ret) { 1670 DRM_ERROR("PSP load sysdrv failed!\n"); 1671 return ret; 1672 } 1673 1674 ret = psp_bootloader_load_sos(psp); 1675 if (ret) { 1676 DRM_ERROR("PSP load sos failed!\n"); 1677 return ret; 1678 } 1679 } 1680 1681 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1682 if (ret) { 1683 DRM_ERROR("PSP create ring failed!\n"); 1684 return ret; 1685 } 1686 1687 ret = psp_clear_vf_fw(psp); 1688 if (ret) { 1689 DRM_ERROR("PSP clear vf fw!\n"); 1690 return ret; 1691 } 1692 1693 ret = psp_tmr_init(psp); 1694 if (ret) { 1695 DRM_ERROR("PSP tmr init failed!\n"); 1696 return ret; 1697 } 1698 1699 /* 1700 * For ASICs with DF Cstate management centralized 1701 * to PMFW, TMR setup should be performed after PMFW 1702 * loaded and before other non-psp firmware loaded. 1703 */ 1704 if (psp->pmfw_centralized_cstate_management) { 1705 ret = psp_load_smu_fw(psp); 1706 if (ret) 1707 return ret; 1708 } 1709 1710 ret = psp_tmr_load(psp); 1711 if (ret) { 1712 DRM_ERROR("PSP load tmr failed!\n"); 1713 return ret; 1714 } 1715 1716 return 0; 1717 } 1718 1719 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 1720 enum psp_gfx_fw_type *type) 1721 { 1722 switch (ucode->ucode_id) { 1723 case AMDGPU_UCODE_ID_SDMA0: 1724 *type = GFX_FW_TYPE_SDMA0; 1725 break; 1726 case AMDGPU_UCODE_ID_SDMA1: 1727 *type = GFX_FW_TYPE_SDMA1; 1728 break; 1729 case AMDGPU_UCODE_ID_SDMA2: 1730 *type = GFX_FW_TYPE_SDMA2; 1731 break; 1732 case AMDGPU_UCODE_ID_SDMA3: 1733 *type = GFX_FW_TYPE_SDMA3; 1734 break; 1735 case AMDGPU_UCODE_ID_SDMA4: 1736 *type = GFX_FW_TYPE_SDMA4; 1737 break; 1738 case AMDGPU_UCODE_ID_SDMA5: 1739 *type = GFX_FW_TYPE_SDMA5; 1740 break; 1741 case AMDGPU_UCODE_ID_SDMA6: 1742 *type = GFX_FW_TYPE_SDMA6; 1743 break; 1744 case AMDGPU_UCODE_ID_SDMA7: 1745 *type = GFX_FW_TYPE_SDMA7; 1746 break; 1747 case AMDGPU_UCODE_ID_CP_MES: 1748 *type = GFX_FW_TYPE_CP_MES; 1749 break; 1750 case AMDGPU_UCODE_ID_CP_MES_DATA: 1751 *type = GFX_FW_TYPE_MES_STACK; 1752 break; 1753 case AMDGPU_UCODE_ID_CP_CE: 1754 *type = GFX_FW_TYPE_CP_CE; 1755 break; 1756 case AMDGPU_UCODE_ID_CP_PFP: 1757 *type = GFX_FW_TYPE_CP_PFP; 1758 break; 1759 case AMDGPU_UCODE_ID_CP_ME: 1760 *type = GFX_FW_TYPE_CP_ME; 1761 break; 1762 case AMDGPU_UCODE_ID_CP_MEC1: 1763 *type = GFX_FW_TYPE_CP_MEC; 1764 break; 1765 case AMDGPU_UCODE_ID_CP_MEC1_JT: 1766 *type = GFX_FW_TYPE_CP_MEC_ME1; 1767 break; 1768 case AMDGPU_UCODE_ID_CP_MEC2: 1769 *type = GFX_FW_TYPE_CP_MEC; 1770 break; 1771 case AMDGPU_UCODE_ID_CP_MEC2_JT: 1772 *type = GFX_FW_TYPE_CP_MEC_ME2; 1773 break; 1774 case AMDGPU_UCODE_ID_RLC_G: 1775 *type = GFX_FW_TYPE_RLC_G; 1776 break; 1777 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 1778 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 1779 break; 1780 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 1781 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 1782 break; 1783 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 1784 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 1785 break; 1786 case AMDGPU_UCODE_ID_RLC_IRAM: 1787 *type = GFX_FW_TYPE_RLC_IRAM; 1788 break; 1789 case AMDGPU_UCODE_ID_RLC_DRAM: 1790 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 1791 break; 1792 case AMDGPU_UCODE_ID_SMC: 1793 *type = GFX_FW_TYPE_SMU; 1794 break; 1795 case AMDGPU_UCODE_ID_UVD: 1796 *type = GFX_FW_TYPE_UVD; 1797 break; 1798 case AMDGPU_UCODE_ID_UVD1: 1799 *type = GFX_FW_TYPE_UVD1; 1800 break; 1801 case AMDGPU_UCODE_ID_VCE: 1802 *type = GFX_FW_TYPE_VCE; 1803 break; 1804 case AMDGPU_UCODE_ID_VCN: 1805 *type = GFX_FW_TYPE_VCN; 1806 break; 1807 case AMDGPU_UCODE_ID_VCN1: 1808 *type = GFX_FW_TYPE_VCN1; 1809 break; 1810 case AMDGPU_UCODE_ID_DMCU_ERAM: 1811 *type = GFX_FW_TYPE_DMCU_ERAM; 1812 break; 1813 case AMDGPU_UCODE_ID_DMCU_INTV: 1814 *type = GFX_FW_TYPE_DMCU_ISR; 1815 break; 1816 case AMDGPU_UCODE_ID_VCN0_RAM: 1817 *type = GFX_FW_TYPE_VCN0_RAM; 1818 break; 1819 case AMDGPU_UCODE_ID_VCN1_RAM: 1820 *type = GFX_FW_TYPE_VCN1_RAM; 1821 break; 1822 case AMDGPU_UCODE_ID_DMCUB: 1823 *type = GFX_FW_TYPE_DMUB; 1824 break; 1825 case AMDGPU_UCODE_ID_MAXIMUM: 1826 default: 1827 return -EINVAL; 1828 } 1829 1830 return 0; 1831 } 1832 1833 static void psp_print_fw_hdr(struct psp_context *psp, 1834 struct amdgpu_firmware_info *ucode) 1835 { 1836 struct amdgpu_device *adev = psp->adev; 1837 struct common_firmware_header *hdr; 1838 1839 switch (ucode->ucode_id) { 1840 case AMDGPU_UCODE_ID_SDMA0: 1841 case AMDGPU_UCODE_ID_SDMA1: 1842 case AMDGPU_UCODE_ID_SDMA2: 1843 case AMDGPU_UCODE_ID_SDMA3: 1844 case AMDGPU_UCODE_ID_SDMA4: 1845 case AMDGPU_UCODE_ID_SDMA5: 1846 case AMDGPU_UCODE_ID_SDMA6: 1847 case AMDGPU_UCODE_ID_SDMA7: 1848 hdr = (struct common_firmware_header *) 1849 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 1850 amdgpu_ucode_print_sdma_hdr(hdr); 1851 break; 1852 case AMDGPU_UCODE_ID_CP_CE: 1853 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 1854 amdgpu_ucode_print_gfx_hdr(hdr); 1855 break; 1856 case AMDGPU_UCODE_ID_CP_PFP: 1857 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 1858 amdgpu_ucode_print_gfx_hdr(hdr); 1859 break; 1860 case AMDGPU_UCODE_ID_CP_ME: 1861 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 1862 amdgpu_ucode_print_gfx_hdr(hdr); 1863 break; 1864 case AMDGPU_UCODE_ID_CP_MEC1: 1865 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 1866 amdgpu_ucode_print_gfx_hdr(hdr); 1867 break; 1868 case AMDGPU_UCODE_ID_RLC_G: 1869 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 1870 amdgpu_ucode_print_rlc_hdr(hdr); 1871 break; 1872 case AMDGPU_UCODE_ID_SMC: 1873 hdr = (struct common_firmware_header *)adev->pm.fw->data; 1874 amdgpu_ucode_print_smc_hdr(hdr); 1875 break; 1876 default: 1877 break; 1878 } 1879 } 1880 1881 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 1882 struct psp_gfx_cmd_resp *cmd) 1883 { 1884 int ret; 1885 uint64_t fw_mem_mc_addr = ucode->mc_addr; 1886 1887 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 1888 1889 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1890 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 1891 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 1892 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 1893 1894 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 1895 if (ret) 1896 DRM_ERROR("Unknown firmware type\n"); 1897 1898 return ret; 1899 } 1900 1901 static int psp_execute_np_fw_load(struct psp_context *psp, 1902 struct amdgpu_firmware_info *ucode) 1903 { 1904 int ret = 0; 1905 1906 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 1907 if (ret) 1908 return ret; 1909 1910 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 1911 psp->fence_buf_mc_addr); 1912 1913 return ret; 1914 } 1915 1916 static int psp_load_smu_fw(struct psp_context *psp) 1917 { 1918 int ret; 1919 struct amdgpu_device *adev = psp->adev; 1920 struct amdgpu_firmware_info *ucode = 1921 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 1922 struct amdgpu_ras *ras = psp->ras.ras; 1923 1924 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 1925 return 0; 1926 1927 1928 if (amdgpu_in_reset(adev) && ras && ras->supported && 1929 adev->asic_type == CHIP_ARCTURUS) { 1930 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 1931 if (ret) { 1932 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 1933 } 1934 } 1935 1936 ret = psp_execute_np_fw_load(psp, ucode); 1937 1938 if (ret) 1939 DRM_ERROR("PSP load smu failed!\n"); 1940 1941 return ret; 1942 } 1943 1944 static bool fw_load_skip_check(struct psp_context *psp, 1945 struct amdgpu_firmware_info *ucode) 1946 { 1947 if (!ucode->fw) 1948 return true; 1949 1950 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 1951 (psp_smu_reload_quirk(psp) || 1952 psp->autoload_supported || 1953 psp->pmfw_centralized_cstate_management)) 1954 return true; 1955 1956 if (amdgpu_sriov_vf(psp->adev) && 1957 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 1958 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 1959 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 1960 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 1961 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 1962 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 1963 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 1964 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 1965 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 1966 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 1967 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 1968 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 1969 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 1970 /*skip ucode loading in SRIOV VF */ 1971 return true; 1972 1973 if (psp->autoload_supported && 1974 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 1975 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 1976 /* skip mec JT when autoload is enabled */ 1977 return true; 1978 1979 return false; 1980 } 1981 1982 static int psp_np_fw_load(struct psp_context *psp) 1983 { 1984 int i, ret; 1985 struct amdgpu_firmware_info *ucode; 1986 struct amdgpu_device *adev = psp->adev; 1987 1988 if (psp->autoload_supported && 1989 !psp->pmfw_centralized_cstate_management) { 1990 ret = psp_load_smu_fw(psp); 1991 if (ret) 1992 return ret; 1993 } 1994 1995 for (i = 0; i < adev->firmware.max_ucodes; i++) { 1996 ucode = &adev->firmware.ucode[i]; 1997 1998 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 1999 !fw_load_skip_check(psp, ucode)) { 2000 ret = psp_load_smu_fw(psp); 2001 if (ret) 2002 return ret; 2003 continue; 2004 } 2005 2006 if (fw_load_skip_check(psp, ucode)) 2007 continue; 2008 2009 if (psp->autoload_supported && 2010 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2011 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2012 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2013 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2014 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2015 /* PSP only receive one SDMA fw for sienna_cichlid, 2016 * as all four sdma fw are same */ 2017 continue; 2018 2019 psp_print_fw_hdr(psp, ucode); 2020 2021 ret = psp_execute_np_fw_load(psp, ucode); 2022 if (ret) 2023 return ret; 2024 2025 /* Start rlc autoload after psp recieved all the gfx firmware */ 2026 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2027 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2028 ret = psp_rlc_autoload_start(psp); 2029 if (ret) { 2030 DRM_ERROR("Failed to start rlc autoload\n"); 2031 return ret; 2032 } 2033 } 2034 } 2035 2036 return 0; 2037 } 2038 2039 static int psp_load_fw(struct amdgpu_device *adev) 2040 { 2041 int ret; 2042 struct psp_context *psp = &adev->psp; 2043 2044 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2045 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2046 goto skip_memalloc; 2047 } 2048 2049 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2050 if (!psp->cmd) 2051 return -ENOMEM; 2052 2053 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2054 AMDGPU_GEM_DOMAIN_GTT, 2055 &psp->fw_pri_bo, 2056 &psp->fw_pri_mc_addr, 2057 &psp->fw_pri_buf); 2058 if (ret) 2059 goto failed; 2060 2061 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2062 AMDGPU_GEM_DOMAIN_VRAM, 2063 &psp->fence_buf_bo, 2064 &psp->fence_buf_mc_addr, 2065 &psp->fence_buf); 2066 if (ret) 2067 goto failed; 2068 2069 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2070 AMDGPU_GEM_DOMAIN_VRAM, 2071 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2072 (void **)&psp->cmd_buf_mem); 2073 if (ret) 2074 goto failed; 2075 2076 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2077 2078 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2079 if (ret) { 2080 DRM_ERROR("PSP ring init failed!\n"); 2081 goto failed; 2082 } 2083 2084 skip_memalloc: 2085 ret = psp_hw_start(psp); 2086 if (ret) 2087 goto failed; 2088 2089 ret = psp_np_fw_load(psp); 2090 if (ret) 2091 goto failed; 2092 2093 ret = psp_asd_load(psp); 2094 if (ret) { 2095 DRM_ERROR("PSP load asd failed!\n"); 2096 return ret; 2097 } 2098 2099 if (psp->adev->psp.ta_fw) { 2100 ret = psp_ras_initialize(psp); 2101 if (ret) 2102 dev_err(psp->adev->dev, 2103 "RAS: Failed to initialize RAS\n"); 2104 2105 ret = psp_hdcp_initialize(psp); 2106 if (ret) 2107 dev_err(psp->adev->dev, 2108 "HDCP: Failed to initialize HDCP\n"); 2109 2110 ret = psp_dtm_initialize(psp); 2111 if (ret) 2112 dev_err(psp->adev->dev, 2113 "DTM: Failed to initialize DTM\n"); 2114 2115 ret = psp_rap_initialize(psp); 2116 if (ret) 2117 dev_err(psp->adev->dev, 2118 "RAP: Failed to initialize RAP\n"); 2119 } 2120 2121 return 0; 2122 2123 failed: 2124 /* 2125 * all cleanup jobs (xgmi terminate, ras terminate, 2126 * ring destroy, cmd/fence/fw buffers destory, 2127 * psp->cmd destory) are delayed to psp_hw_fini 2128 */ 2129 return ret; 2130 } 2131 2132 static int psp_hw_init(void *handle) 2133 { 2134 int ret; 2135 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2136 2137 mutex_lock(&adev->firmware.mutex); 2138 /* 2139 * This sequence is just used on hw_init only once, no need on 2140 * resume. 2141 */ 2142 ret = amdgpu_ucode_init_bo(adev); 2143 if (ret) 2144 goto failed; 2145 2146 ret = psp_load_fw(adev); 2147 if (ret) { 2148 DRM_ERROR("PSP firmware loading failed\n"); 2149 goto failed; 2150 } 2151 2152 mutex_unlock(&adev->firmware.mutex); 2153 return 0; 2154 2155 failed: 2156 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2157 mutex_unlock(&adev->firmware.mutex); 2158 return -EINVAL; 2159 } 2160 2161 static int psp_hw_fini(void *handle) 2162 { 2163 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2164 struct psp_context *psp = &adev->psp; 2165 int ret; 2166 2167 if (psp->adev->psp.ta_fw) { 2168 psp_ras_terminate(psp); 2169 psp_rap_terminate(psp); 2170 psp_dtm_terminate(psp); 2171 psp_hdcp_terminate(psp); 2172 } 2173 2174 psp_asd_unload(psp); 2175 ret = psp_clear_vf_fw(psp); 2176 if (ret) { 2177 DRM_ERROR("PSP clear vf fw!\n"); 2178 return ret; 2179 } 2180 2181 psp_tmr_terminate(psp); 2182 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2183 2184 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2185 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2186 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2187 &psp->fence_buf_mc_addr, &psp->fence_buf); 2188 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2189 (void **)&psp->cmd_buf_mem); 2190 2191 kfree(psp->cmd); 2192 psp->cmd = NULL; 2193 2194 return 0; 2195 } 2196 2197 static int psp_suspend(void *handle) 2198 { 2199 int ret; 2200 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2201 struct psp_context *psp = &adev->psp; 2202 2203 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2204 psp->xgmi_context.initialized == 1) { 2205 ret = psp_xgmi_terminate(psp); 2206 if (ret) { 2207 DRM_ERROR("Failed to terminate xgmi ta\n"); 2208 return ret; 2209 } 2210 } 2211 2212 if (psp->adev->psp.ta_fw) { 2213 ret = psp_ras_terminate(psp); 2214 if (ret) { 2215 DRM_ERROR("Failed to terminate ras ta\n"); 2216 return ret; 2217 } 2218 ret = psp_hdcp_terminate(psp); 2219 if (ret) { 2220 DRM_ERROR("Failed to terminate hdcp ta\n"); 2221 return ret; 2222 } 2223 ret = psp_dtm_terminate(psp); 2224 if (ret) { 2225 DRM_ERROR("Failed to terminate dtm ta\n"); 2226 return ret; 2227 } 2228 ret = psp_rap_terminate(psp); 2229 if (ret) { 2230 DRM_ERROR("Failed to terminate rap ta\n"); 2231 return ret; 2232 } 2233 } 2234 2235 ret = psp_asd_unload(psp); 2236 if (ret) { 2237 DRM_ERROR("Failed to unload asd\n"); 2238 return ret; 2239 } 2240 2241 ret = psp_tmr_terminate(psp); 2242 if (ret) { 2243 DRM_ERROR("Failed to terminate tmr\n"); 2244 return ret; 2245 } 2246 2247 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2248 if (ret) { 2249 DRM_ERROR("PSP ring stop failed\n"); 2250 return ret; 2251 } 2252 2253 return 0; 2254 } 2255 2256 static int psp_resume(void *handle) 2257 { 2258 int ret; 2259 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2260 struct psp_context *psp = &adev->psp; 2261 2262 DRM_INFO("PSP is resuming...\n"); 2263 2264 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2265 if (ret) { 2266 DRM_ERROR("Failed to process memory training!\n"); 2267 return ret; 2268 } 2269 2270 mutex_lock(&adev->firmware.mutex); 2271 2272 ret = psp_hw_start(psp); 2273 if (ret) 2274 goto failed; 2275 2276 ret = psp_np_fw_load(psp); 2277 if (ret) 2278 goto failed; 2279 2280 ret = psp_asd_load(psp); 2281 if (ret) { 2282 DRM_ERROR("PSP load asd failed!\n"); 2283 goto failed; 2284 } 2285 2286 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2287 ret = psp_xgmi_initialize(psp); 2288 /* Warning the XGMI seesion initialize failure 2289 * Instead of stop driver initialization 2290 */ 2291 if (ret) 2292 dev_err(psp->adev->dev, 2293 "XGMI: Failed to initialize XGMI session\n"); 2294 } 2295 2296 if (psp->adev->psp.ta_fw) { 2297 ret = psp_ras_initialize(psp); 2298 if (ret) 2299 dev_err(psp->adev->dev, 2300 "RAS: Failed to initialize RAS\n"); 2301 2302 ret = psp_hdcp_initialize(psp); 2303 if (ret) 2304 dev_err(psp->adev->dev, 2305 "HDCP: Failed to initialize HDCP\n"); 2306 2307 ret = psp_dtm_initialize(psp); 2308 if (ret) 2309 dev_err(psp->adev->dev, 2310 "DTM: Failed to initialize DTM\n"); 2311 2312 ret = psp_rap_initialize(psp); 2313 if (ret) 2314 dev_err(psp->adev->dev, 2315 "RAP: Failed to initialize RAP\n"); 2316 } 2317 2318 mutex_unlock(&adev->firmware.mutex); 2319 2320 return 0; 2321 2322 failed: 2323 DRM_ERROR("PSP resume failed\n"); 2324 mutex_unlock(&adev->firmware.mutex); 2325 return ret; 2326 } 2327 2328 int psp_gpu_reset(struct amdgpu_device *adev) 2329 { 2330 int ret; 2331 2332 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2333 return 0; 2334 2335 mutex_lock(&adev->psp.mutex); 2336 ret = psp_mode1_reset(&adev->psp); 2337 mutex_unlock(&adev->psp.mutex); 2338 2339 return ret; 2340 } 2341 2342 int psp_rlc_autoload_start(struct psp_context *psp) 2343 { 2344 int ret; 2345 struct psp_gfx_cmd_resp *cmd; 2346 2347 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2348 if (!cmd) 2349 return -ENOMEM; 2350 2351 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2352 2353 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2354 psp->fence_buf_mc_addr); 2355 kfree(cmd); 2356 return ret; 2357 } 2358 2359 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2360 uint64_t cmd_gpu_addr, int cmd_size) 2361 { 2362 struct amdgpu_firmware_info ucode = {0}; 2363 2364 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2365 AMDGPU_UCODE_ID_VCN0_RAM; 2366 ucode.mc_addr = cmd_gpu_addr; 2367 ucode.ucode_size = cmd_size; 2368 2369 return psp_execute_np_fw_load(&adev->psp, &ucode); 2370 } 2371 2372 int psp_ring_cmd_submit(struct psp_context *psp, 2373 uint64_t cmd_buf_mc_addr, 2374 uint64_t fence_mc_addr, 2375 int index) 2376 { 2377 unsigned int psp_write_ptr_reg = 0; 2378 struct psp_gfx_rb_frame *write_frame; 2379 struct psp_ring *ring = &psp->km_ring; 2380 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2381 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2382 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2383 struct amdgpu_device *adev = psp->adev; 2384 uint32_t ring_size_dw = ring->ring_size / 4; 2385 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2386 2387 /* KM (GPCOM) prepare write pointer */ 2388 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2389 2390 /* Update KM RB frame pointer to new frame */ 2391 /* write_frame ptr increments by size of rb_frame in bytes */ 2392 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2393 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2394 write_frame = ring_buffer_start; 2395 else 2396 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2397 /* Check invalid write_frame ptr address */ 2398 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2399 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2400 ring_buffer_start, ring_buffer_end, write_frame); 2401 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2402 return -EINVAL; 2403 } 2404 2405 /* Initialize KM RB frame */ 2406 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2407 2408 /* Update KM RB frame */ 2409 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2410 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2411 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2412 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2413 write_frame->fence_value = index; 2414 amdgpu_asic_flush_hdp(adev, NULL); 2415 2416 /* Update the write Pointer in DWORDs */ 2417 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2418 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2419 return 0; 2420 } 2421 2422 int psp_init_asd_microcode(struct psp_context *psp, 2423 const char *chip_name) 2424 { 2425 struct amdgpu_device *adev = psp->adev; 2426 char fw_name[PSP_FW_NAME_LEN]; 2427 const struct psp_firmware_header_v1_0 *asd_hdr; 2428 int err = 0; 2429 2430 if (!chip_name) { 2431 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2432 return -EINVAL; 2433 } 2434 2435 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2436 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2437 if (err) 2438 goto out; 2439 2440 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2441 if (err) 2442 goto out; 2443 2444 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2445 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2446 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 2447 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2448 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2449 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2450 return 0; 2451 out: 2452 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2453 release_firmware(adev->psp.asd_fw); 2454 adev->psp.asd_fw = NULL; 2455 return err; 2456 } 2457 2458 int psp_init_toc_microcode(struct psp_context *psp, 2459 const char *chip_name) 2460 { 2461 struct amdgpu_device *adev = psp->adev; 2462 char fw_name[30]; 2463 const struct psp_firmware_header_v1_0 *toc_hdr; 2464 int err = 0; 2465 2466 if (!chip_name) { 2467 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2468 return -EINVAL; 2469 } 2470 2471 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2472 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2473 if (err) 2474 goto out; 2475 2476 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2477 if (err) 2478 goto out; 2479 2480 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2481 adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2482 adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version); 2483 adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2484 adev->psp.toc_start_addr = (uint8_t *)toc_hdr + 2485 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2486 return 0; 2487 out: 2488 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2489 release_firmware(adev->psp.toc_fw); 2490 adev->psp.toc_fw = NULL; 2491 return err; 2492 } 2493 2494 int psp_init_sos_microcode(struct psp_context *psp, 2495 const char *chip_name) 2496 { 2497 struct amdgpu_device *adev = psp->adev; 2498 char fw_name[PSP_FW_NAME_LEN]; 2499 const struct psp_firmware_header_v1_0 *sos_hdr; 2500 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 2501 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 2502 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2503 int err = 0; 2504 2505 if (!chip_name) { 2506 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 2507 return -EINVAL; 2508 } 2509 2510 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 2511 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 2512 if (err) 2513 goto out; 2514 2515 err = amdgpu_ucode_validate(adev->psp.sos_fw); 2516 if (err) 2517 goto out; 2518 2519 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2520 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 2521 2522 switch (sos_hdr->header.header_version_major) { 2523 case 1: 2524 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 2525 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 2526 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 2527 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 2528 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 2529 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2530 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2531 le32_to_cpu(sos_hdr->sos_offset_bytes); 2532 if (sos_hdr->header.header_version_minor == 1) { 2533 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 2534 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 2535 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2536 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 2537 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); 2538 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2539 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); 2540 } 2541 if (sos_hdr->header.header_version_minor == 2) { 2542 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 2543 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); 2544 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2545 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); 2546 } 2547 if (sos_hdr->header.header_version_minor == 3) { 2548 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 2549 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes); 2550 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2551 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes); 2552 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes); 2553 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2554 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes); 2555 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes); 2556 adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2557 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes); 2558 } 2559 break; 2560 default: 2561 dev_err(adev->dev, 2562 "unsupported psp sos firmware\n"); 2563 err = -EINVAL; 2564 goto out; 2565 } 2566 2567 return 0; 2568 out: 2569 dev_err(adev->dev, 2570 "failed to init sos firmware\n"); 2571 release_firmware(adev->psp.sos_fw); 2572 adev->psp.sos_fw = NULL; 2573 2574 return err; 2575 } 2576 2577 static int parse_ta_bin_descriptor(struct psp_context *psp, 2578 const struct ta_fw_bin_desc *desc, 2579 const struct ta_firmware_header_v2_0 *ta_hdr) 2580 { 2581 uint8_t *ucode_start_addr = NULL; 2582 2583 if (!psp || !desc || !ta_hdr) 2584 return -EINVAL; 2585 2586 ucode_start_addr = (uint8_t *)ta_hdr + 2587 le32_to_cpu(desc->offset_bytes) + 2588 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 2589 2590 switch (desc->fw_type) { 2591 case TA_FW_TYPE_PSP_ASD: 2592 psp->asd_fw_version = le32_to_cpu(desc->fw_version); 2593 psp->asd_feature_version = le32_to_cpu(desc->fw_version); 2594 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 2595 psp->asd_start_addr = ucode_start_addr; 2596 psp->asd_fw = psp->ta_fw; 2597 break; 2598 case TA_FW_TYPE_PSP_XGMI: 2599 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 2600 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 2601 psp->ta_xgmi_start_addr = ucode_start_addr; 2602 break; 2603 case TA_FW_TYPE_PSP_RAS: 2604 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 2605 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 2606 psp->ta_ras_start_addr = ucode_start_addr; 2607 break; 2608 case TA_FW_TYPE_PSP_HDCP: 2609 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 2610 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 2611 psp->ta_hdcp_start_addr = ucode_start_addr; 2612 break; 2613 case TA_FW_TYPE_PSP_DTM: 2614 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 2615 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 2616 psp->ta_dtm_start_addr = ucode_start_addr; 2617 break; 2618 case TA_FW_TYPE_PSP_RAP: 2619 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version); 2620 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes); 2621 psp->ta_rap_start_addr = ucode_start_addr; 2622 break; 2623 default: 2624 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 2625 break; 2626 } 2627 2628 return 0; 2629 } 2630 2631 int psp_init_ta_microcode(struct psp_context *psp, 2632 const char *chip_name) 2633 { 2634 struct amdgpu_device *adev = psp->adev; 2635 char fw_name[PSP_FW_NAME_LEN]; 2636 const struct ta_firmware_header_v2_0 *ta_hdr; 2637 int err = 0; 2638 int ta_index = 0; 2639 2640 if (!chip_name) { 2641 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 2642 return -EINVAL; 2643 } 2644 2645 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 2646 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 2647 if (err) 2648 goto out; 2649 2650 err = amdgpu_ucode_validate(adev->psp.ta_fw); 2651 if (err) 2652 goto out; 2653 2654 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 2655 2656 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 2657 dev_err(adev->dev, "unsupported TA header version\n"); 2658 err = -EINVAL; 2659 goto out; 2660 } 2661 2662 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) { 2663 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 2664 err = -EINVAL; 2665 goto out; 2666 } 2667 2668 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 2669 err = parse_ta_bin_descriptor(psp, 2670 &ta_hdr->ta_fw_bin[ta_index], 2671 ta_hdr); 2672 if (err) 2673 goto out; 2674 } 2675 2676 return 0; 2677 out: 2678 dev_err(adev->dev, "fail to initialize ta microcode\n"); 2679 release_firmware(adev->psp.ta_fw); 2680 adev->psp.ta_fw = NULL; 2681 return err; 2682 } 2683 2684 static int psp_set_clockgating_state(void *handle, 2685 enum amd_clockgating_state state) 2686 { 2687 return 0; 2688 } 2689 2690 static int psp_set_powergating_state(void *handle, 2691 enum amd_powergating_state state) 2692 { 2693 return 0; 2694 } 2695 2696 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 2697 struct device_attribute *attr, 2698 char *buf) 2699 { 2700 struct drm_device *ddev = dev_get_drvdata(dev); 2701 struct amdgpu_device *adev = drm_to_adev(ddev); 2702 uint32_t fw_ver; 2703 int ret; 2704 2705 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2706 DRM_INFO("PSP block is not ready yet."); 2707 return -EBUSY; 2708 } 2709 2710 mutex_lock(&adev->psp.mutex); 2711 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 2712 mutex_unlock(&adev->psp.mutex); 2713 2714 if (ret) { 2715 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 2716 return ret; 2717 } 2718 2719 return snprintf(buf, PAGE_SIZE, "%x\n", fw_ver); 2720 } 2721 2722 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 2723 struct device_attribute *attr, 2724 const char *buf, 2725 size_t count) 2726 { 2727 struct drm_device *ddev = dev_get_drvdata(dev); 2728 struct amdgpu_device *adev = drm_to_adev(ddev); 2729 void *cpu_addr; 2730 dma_addr_t dma_addr; 2731 int ret; 2732 char fw_name[100]; 2733 const struct firmware *usbc_pd_fw; 2734 2735 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2736 DRM_INFO("PSP block is not ready yet."); 2737 return -EBUSY; 2738 } 2739 2740 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 2741 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 2742 if (ret) 2743 goto fail; 2744 2745 /* We need contiguous physical mem to place the FW for psp to access */ 2746 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL); 2747 2748 ret = dma_mapping_error(adev->dev, dma_addr); 2749 if (ret) 2750 goto rel_buf; 2751 2752 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 2753 2754 /* 2755 * x86 specific workaround. 2756 * Without it the buffer is invisible in PSP. 2757 * 2758 * TODO Remove once PSP starts snooping CPU cache 2759 */ 2760 #ifdef CONFIG_X86 2761 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1))); 2762 #endif 2763 2764 mutex_lock(&adev->psp.mutex); 2765 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr); 2766 mutex_unlock(&adev->psp.mutex); 2767 2768 rel_buf: 2769 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr); 2770 release_firmware(usbc_pd_fw); 2771 2772 fail: 2773 if (ret) { 2774 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 2775 return ret; 2776 } 2777 2778 return count; 2779 } 2780 2781 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 2782 psp_usbc_pd_fw_sysfs_read, 2783 psp_usbc_pd_fw_sysfs_write); 2784 2785 2786 2787 const struct amd_ip_funcs psp_ip_funcs = { 2788 .name = "psp", 2789 .early_init = psp_early_init, 2790 .late_init = NULL, 2791 .sw_init = psp_sw_init, 2792 .sw_fini = psp_sw_fini, 2793 .hw_init = psp_hw_init, 2794 .hw_fini = psp_hw_fini, 2795 .suspend = psp_suspend, 2796 .resume = psp_resume, 2797 .is_idle = NULL, 2798 .check_soft_reset = NULL, 2799 .wait_for_idle = NULL, 2800 .soft_reset = NULL, 2801 .set_clockgating_state = psp_set_clockgating_state, 2802 .set_powergating_state = psp_set_powergating_state, 2803 }; 2804 2805 static int psp_sysfs_init(struct amdgpu_device *adev) 2806 { 2807 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 2808 2809 if (ret) 2810 DRM_ERROR("Failed to create USBC PD FW control file!"); 2811 2812 return ret; 2813 } 2814 2815 static void psp_sysfs_fini(struct amdgpu_device *adev) 2816 { 2817 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 2818 } 2819 2820 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 2821 { 2822 .type = AMD_IP_BLOCK_TYPE_PSP, 2823 .major = 3, 2824 .minor = 1, 2825 .rev = 0, 2826 .funcs = &psp_ip_funcs, 2827 }; 2828 2829 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 2830 { 2831 .type = AMD_IP_BLOCK_TYPE_PSP, 2832 .major = 10, 2833 .minor = 0, 2834 .rev = 0, 2835 .funcs = &psp_ip_funcs, 2836 }; 2837 2838 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 2839 { 2840 .type = AMD_IP_BLOCK_TYPE_PSP, 2841 .major = 11, 2842 .minor = 0, 2843 .rev = 0, 2844 .funcs = &psp_ip_funcs, 2845 }; 2846 2847 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 2848 { 2849 .type = AMD_IP_BLOCK_TYPE_PSP, 2850 .major = 12, 2851 .minor = 0, 2852 .rev = 0, 2853 .funcs = &psp_ip_funcs, 2854 }; 2855