1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 42 #include "amdgpu_ras.h" 43 #include "amdgpu_securedisplay.h" 44 #include "amdgpu_atomfirmware.h" 45 46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 47 48 static int psp_sysfs_init(struct amdgpu_device *adev); 49 static void psp_sysfs_fini(struct amdgpu_device *adev); 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 /* 56 * Due to DF Cstate management centralized to PMFW, the firmware 57 * loading sequence will be updated as below: 58 * - Load KDB 59 * - Load SYS_DRV 60 * - Load tOS 61 * - Load PMFW 62 * - Setup TMR 63 * - Load other non-psp fw 64 * - Load ASD 65 * - Load XGMI/RAS/HDCP/DTM TA if any 66 * 67 * This new sequence is required for 68 * - Arcturus and onwards 69 */ 70 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 71 { 72 struct amdgpu_device *adev = psp->adev; 73 74 if (amdgpu_sriov_vf(adev)) { 75 psp->pmfw_centralized_cstate_management = false; 76 return; 77 } 78 79 switch (adev->ip_versions[MP0_HWIP][0]) { 80 case IP_VERSION(11, 0, 0): 81 case IP_VERSION(11, 0, 4): 82 case IP_VERSION(11, 0, 5): 83 case IP_VERSION(11, 0, 7): 84 case IP_VERSION(11, 0, 9): 85 case IP_VERSION(11, 0, 11): 86 case IP_VERSION(11, 0, 12): 87 case IP_VERSION(11, 0, 13): 88 case IP_VERSION(13, 0, 0): 89 case IP_VERSION(13, 0, 2): 90 case IP_VERSION(13, 0, 7): 91 psp->pmfw_centralized_cstate_management = true; 92 break; 93 default: 94 psp->pmfw_centralized_cstate_management = false; 95 break; 96 } 97 } 98 99 static int psp_early_init(void *handle) 100 { 101 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 102 struct psp_context *psp = &adev->psp; 103 104 switch (adev->ip_versions[MP0_HWIP][0]) { 105 case IP_VERSION(9, 0, 0): 106 psp_v3_1_set_psp_funcs(psp); 107 psp->autoload_supported = false; 108 break; 109 case IP_VERSION(10, 0, 0): 110 case IP_VERSION(10, 0, 1): 111 psp_v10_0_set_psp_funcs(psp); 112 psp->autoload_supported = false; 113 break; 114 case IP_VERSION(11, 0, 2): 115 case IP_VERSION(11, 0, 4): 116 psp_v11_0_set_psp_funcs(psp); 117 psp->autoload_supported = false; 118 break; 119 case IP_VERSION(11, 0, 0): 120 case IP_VERSION(11, 0, 5): 121 case IP_VERSION(11, 0, 9): 122 case IP_VERSION(11, 0, 7): 123 case IP_VERSION(11, 0, 11): 124 case IP_VERSION(11, 5, 0): 125 case IP_VERSION(11, 0, 12): 126 case IP_VERSION(11, 0, 13): 127 psp_v11_0_set_psp_funcs(psp); 128 psp->autoload_supported = true; 129 break; 130 case IP_VERSION(11, 0, 3): 131 case IP_VERSION(12, 0, 1): 132 psp_v12_0_set_psp_funcs(psp); 133 break; 134 case IP_VERSION(13, 0, 2): 135 psp_v13_0_set_psp_funcs(psp); 136 break; 137 case IP_VERSION(13, 0, 1): 138 case IP_VERSION(13, 0, 3): 139 case IP_VERSION(13, 0, 5): 140 case IP_VERSION(13, 0, 8): 141 case IP_VERSION(13, 0, 10): 142 psp_v13_0_set_psp_funcs(psp); 143 psp->autoload_supported = true; 144 break; 145 case IP_VERSION(11, 0, 8): 146 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 147 psp_v11_0_8_set_psp_funcs(psp); 148 psp->autoload_supported = false; 149 } 150 break; 151 case IP_VERSION(13, 0, 0): 152 case IP_VERSION(13, 0, 7): 153 psp_v13_0_set_psp_funcs(psp); 154 psp->autoload_supported = true; 155 break; 156 case IP_VERSION(13, 0, 4): 157 psp_v13_0_4_set_psp_funcs(psp); 158 psp->autoload_supported = true; 159 break; 160 default: 161 return -EINVAL; 162 } 163 164 psp->adev = adev; 165 166 psp_check_pmfw_centralized_cstate_management(psp); 167 168 return 0; 169 } 170 171 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 172 { 173 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 174 &mem_ctx->shared_buf); 175 } 176 177 static void psp_free_shared_bufs(struct psp_context *psp) 178 { 179 void *tmr_buf; 180 void **pptr; 181 182 /* free TMR memory buffer */ 183 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 184 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 185 186 /* free xgmi shared memory */ 187 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 188 189 /* free ras shared memory */ 190 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 191 192 /* free hdcp shared memory */ 193 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 194 195 /* free dtm shared memory */ 196 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 197 198 /* free rap shared memory */ 199 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 200 201 /* free securedisplay shared memory */ 202 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 203 204 205 } 206 207 static void psp_memory_training_fini(struct psp_context *psp) 208 { 209 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 210 211 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 212 kfree(ctx->sys_cache); 213 ctx->sys_cache = NULL; 214 } 215 216 static int psp_memory_training_init(struct psp_context *psp) 217 { 218 int ret; 219 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 220 221 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 222 DRM_DEBUG("memory training is not supported!\n"); 223 return 0; 224 } 225 226 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 227 if (ctx->sys_cache == NULL) { 228 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 229 ret = -ENOMEM; 230 goto Err_out; 231 } 232 233 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 234 ctx->train_data_size, 235 ctx->p2c_train_data_offset, 236 ctx->c2p_train_data_offset); 237 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 238 return 0; 239 240 Err_out: 241 psp_memory_training_fini(psp); 242 return ret; 243 } 244 245 /* 246 * Helper funciton to query psp runtime database entry 247 * 248 * @adev: amdgpu_device pointer 249 * @entry_type: the type of psp runtime database entry 250 * @db_entry: runtime database entry pointer 251 * 252 * Return false if runtime database doesn't exit or entry is invalid 253 * or true if the specific database entry is found, and copy to @db_entry 254 */ 255 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 256 enum psp_runtime_entry_type entry_type, 257 void *db_entry) 258 { 259 uint64_t db_header_pos, db_dir_pos; 260 struct psp_runtime_data_header db_header = {0}; 261 struct psp_runtime_data_directory db_dir = {0}; 262 bool ret = false; 263 int i; 264 265 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 266 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 267 268 /* read runtime db header from vram */ 269 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 270 sizeof(struct psp_runtime_data_header), false); 271 272 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 273 /* runtime db doesn't exist, exit */ 274 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 275 return false; 276 } 277 278 /* read runtime database entry from vram */ 279 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 280 sizeof(struct psp_runtime_data_directory), false); 281 282 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 283 /* invalid db entry count, exit */ 284 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 285 return false; 286 } 287 288 /* look up for requested entry type */ 289 for (i = 0; i < db_dir.entry_count && !ret; i++) { 290 if (db_dir.entry_list[i].entry_type == entry_type) { 291 switch (entry_type) { 292 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 293 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 294 /* invalid db entry size */ 295 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 296 return false; 297 } 298 /* read runtime database entry */ 299 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 300 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 301 ret = true; 302 break; 303 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 304 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 305 /* invalid db entry size */ 306 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 307 return false; 308 } 309 /* read runtime database entry */ 310 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 311 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 312 ret = true; 313 break; 314 default: 315 ret = false; 316 break; 317 } 318 } 319 } 320 321 return ret; 322 } 323 324 static int psp_init_sriov_microcode(struct psp_context *psp) 325 { 326 struct amdgpu_device *adev = psp->adev; 327 int ret = 0; 328 329 switch (adev->ip_versions[MP0_HWIP][0]) { 330 case IP_VERSION(9, 0, 0): 331 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 332 ret = psp_init_cap_microcode(psp, "vega10"); 333 break; 334 case IP_VERSION(11, 0, 9): 335 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 336 ret = psp_init_cap_microcode(psp, "navi12"); 337 break; 338 case IP_VERSION(11, 0, 7): 339 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 340 ret = psp_init_cap_microcode(psp, "sienna_cichlid"); 341 break; 342 case IP_VERSION(13, 0, 2): 343 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 344 ret = psp_init_cap_microcode(psp, "aldebaran"); 345 ret &= psp_init_ta_microcode(psp, "aldebaran"); 346 break; 347 case IP_VERSION(13, 0, 0): 348 adev->virt.autoload_ucode_id = 0; 349 break; 350 case IP_VERSION(13, 0, 10): 351 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 352 break; 353 default: 354 BUG(); 355 break; 356 } 357 return ret; 358 } 359 360 static int psp_sw_init(void *handle) 361 { 362 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 363 struct psp_context *psp = &adev->psp; 364 int ret; 365 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 366 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 367 struct psp_runtime_scpm_entry scpm_entry; 368 369 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 370 if (!psp->cmd) { 371 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 372 ret = -ENOMEM; 373 } 374 375 if (amdgpu_sriov_vf(adev)) 376 ret = psp_init_sriov_microcode(psp); 377 else 378 ret = psp_init_microcode(psp); 379 if (ret) { 380 DRM_ERROR("Failed to load psp firmware!\n"); 381 return ret; 382 } 383 384 adev->psp.xgmi_context.supports_extended_data = 385 !adev->gmc.xgmi.connected_to_cpu && 386 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 387 388 memset(&scpm_entry, 0, sizeof(scpm_entry)); 389 if ((psp_get_runtime_db_entry(adev, 390 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 391 &scpm_entry)) && 392 (SCPM_DISABLE != scpm_entry.scpm_status)) { 393 adev->scpm_enabled = true; 394 adev->scpm_status = scpm_entry.scpm_status; 395 } else { 396 adev->scpm_enabled = false; 397 adev->scpm_status = SCPM_DISABLE; 398 } 399 400 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 401 402 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 403 if (psp_get_runtime_db_entry(adev, 404 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 405 &boot_cfg_entry)) { 406 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 407 if ((psp->boot_cfg_bitmask) & 408 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 409 /* If psp runtime database exists, then 410 * only enable two stage memory training 411 * when TWO_STAGE_DRAM_TRAINING bit is set 412 * in runtime database */ 413 mem_training_ctx->enable_mem_training = true; 414 } 415 416 } else { 417 /* If psp runtime database doesn't exist or 418 * is invalid, force enable two stage memory 419 * training */ 420 mem_training_ctx->enable_mem_training = true; 421 } 422 423 if (mem_training_ctx->enable_mem_training) { 424 ret = psp_memory_training_init(psp); 425 if (ret) { 426 DRM_ERROR("Failed to initialize memory training!\n"); 427 return ret; 428 } 429 430 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 431 if (ret) { 432 DRM_ERROR("Failed to process memory training!\n"); 433 return ret; 434 } 435 } 436 437 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 438 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 439 ret= psp_sysfs_init(adev); 440 if (ret) { 441 return ret; 442 } 443 } 444 445 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 446 amdgpu_sriov_vf(adev) ? 447 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 448 &psp->fw_pri_bo, 449 &psp->fw_pri_mc_addr, 450 &psp->fw_pri_buf); 451 if (ret) 452 return ret; 453 454 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 455 AMDGPU_GEM_DOMAIN_VRAM, 456 &psp->fence_buf_bo, 457 &psp->fence_buf_mc_addr, 458 &psp->fence_buf); 459 if (ret) 460 goto failed1; 461 462 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 463 AMDGPU_GEM_DOMAIN_VRAM, 464 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 465 (void **)&psp->cmd_buf_mem); 466 if (ret) 467 goto failed2; 468 469 return 0; 470 471 failed2: 472 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 473 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 474 failed1: 475 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 476 &psp->fence_buf_mc_addr, &psp->fence_buf); 477 return ret; 478 } 479 480 static int psp_sw_fini(void *handle) 481 { 482 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 483 struct psp_context *psp = &adev->psp; 484 struct psp_gfx_cmd_resp *cmd = psp->cmd; 485 486 psp_memory_training_fini(psp); 487 if (psp->sos_fw) { 488 release_firmware(psp->sos_fw); 489 psp->sos_fw = NULL; 490 } 491 if (psp->asd_fw) { 492 release_firmware(psp->asd_fw); 493 psp->asd_fw = NULL; 494 } 495 if (psp->ta_fw) { 496 release_firmware(psp->ta_fw); 497 psp->ta_fw = NULL; 498 } 499 if (psp->cap_fw) { 500 release_firmware(psp->cap_fw); 501 psp->cap_fw = NULL; 502 } 503 if (psp->toc_fw) { 504 release_firmware(psp->toc_fw); 505 psp->toc_fw = NULL; 506 } 507 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 508 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 509 psp_sysfs_fini(adev); 510 511 kfree(cmd); 512 cmd = NULL; 513 514 if (psp->km_ring.ring_mem) 515 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 516 &psp->km_ring.ring_mem_mc_addr, 517 (void **)&psp->km_ring.ring_mem); 518 519 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 520 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 521 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 522 &psp->fence_buf_mc_addr, &psp->fence_buf); 523 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 524 (void **)&psp->cmd_buf_mem); 525 526 return 0; 527 } 528 529 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 530 uint32_t reg_val, uint32_t mask, bool check_changed) 531 { 532 uint32_t val; 533 int i; 534 struct amdgpu_device *adev = psp->adev; 535 536 if (psp->adev->no_hw_access) 537 return 0; 538 539 for (i = 0; i < adev->usec_timeout; i++) { 540 val = RREG32(reg_index); 541 if (check_changed) { 542 if (val != reg_val) 543 return 0; 544 } else { 545 if ((val & mask) == reg_val) 546 return 0; 547 } 548 udelay(1); 549 } 550 551 return -ETIME; 552 } 553 554 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 555 { 556 switch (cmd_id) { 557 case GFX_CMD_ID_LOAD_TA: 558 return "LOAD_TA"; 559 case GFX_CMD_ID_UNLOAD_TA: 560 return "UNLOAD_TA"; 561 case GFX_CMD_ID_INVOKE_CMD: 562 return "INVOKE_CMD"; 563 case GFX_CMD_ID_LOAD_ASD: 564 return "LOAD_ASD"; 565 case GFX_CMD_ID_SETUP_TMR: 566 return "SETUP_TMR"; 567 case GFX_CMD_ID_LOAD_IP_FW: 568 return "LOAD_IP_FW"; 569 case GFX_CMD_ID_DESTROY_TMR: 570 return "DESTROY_TMR"; 571 case GFX_CMD_ID_SAVE_RESTORE: 572 return "SAVE_RESTORE_IP_FW"; 573 case GFX_CMD_ID_SETUP_VMR: 574 return "SETUP_VMR"; 575 case GFX_CMD_ID_DESTROY_VMR: 576 return "DESTROY_VMR"; 577 case GFX_CMD_ID_PROG_REG: 578 return "PROG_REG"; 579 case GFX_CMD_ID_GET_FW_ATTESTATION: 580 return "GET_FW_ATTESTATION"; 581 case GFX_CMD_ID_LOAD_TOC: 582 return "ID_LOAD_TOC"; 583 case GFX_CMD_ID_AUTOLOAD_RLC: 584 return "AUTOLOAD_RLC"; 585 case GFX_CMD_ID_BOOT_CFG: 586 return "BOOT_CFG"; 587 default: 588 return "UNKNOWN CMD"; 589 } 590 } 591 592 static int 593 psp_cmd_submit_buf(struct psp_context *psp, 594 struct amdgpu_firmware_info *ucode, 595 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 596 { 597 int ret; 598 int index, idx; 599 int timeout = 20000; 600 bool ras_intr = false; 601 bool skip_unsupport = false; 602 603 if (psp->adev->no_hw_access) 604 return 0; 605 606 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 607 return 0; 608 609 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 610 611 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 612 613 index = atomic_inc_return(&psp->fence_value); 614 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 615 if (ret) { 616 atomic_dec(&psp->fence_value); 617 goto exit; 618 } 619 620 amdgpu_device_invalidate_hdp(psp->adev, NULL); 621 while (*((unsigned int *)psp->fence_buf) != index) { 622 if (--timeout == 0) 623 break; 624 /* 625 * Shouldn't wait for timeout when err_event_athub occurs, 626 * because gpu reset thread triggered and lock resource should 627 * be released for psp resume sequence. 628 */ 629 ras_intr = amdgpu_ras_intr_triggered(); 630 if (ras_intr) 631 break; 632 usleep_range(10, 100); 633 amdgpu_device_invalidate_hdp(psp->adev, NULL); 634 } 635 636 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 637 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 638 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 639 640 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 641 642 /* In some cases, psp response status is not 0 even there is no 643 * problem while the command is submitted. Some version of PSP FW 644 * doesn't write 0 to that field. 645 * So here we would like to only print a warning instead of an error 646 * during psp initialization to avoid breaking hw_init and it doesn't 647 * return -EINVAL. 648 */ 649 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 650 if (ucode) 651 DRM_WARN("failed to load ucode %s(0x%X) ", 652 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 653 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 654 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 655 psp->cmd_buf_mem->resp.status); 656 /* If any firmware (including CAP) load fails under SRIOV, it should 657 * return failure to stop the VF from initializing. 658 * Also return failure in case of timeout 659 */ 660 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 661 ret = -EINVAL; 662 goto exit; 663 } 664 } 665 666 if (ucode) { 667 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 668 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 669 } 670 671 exit: 672 drm_dev_exit(idx); 673 return ret; 674 } 675 676 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 677 { 678 struct psp_gfx_cmd_resp *cmd = psp->cmd; 679 680 mutex_lock(&psp->mutex); 681 682 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 683 684 return cmd; 685 } 686 687 static void release_psp_cmd_buf(struct psp_context *psp) 688 { 689 mutex_unlock(&psp->mutex); 690 } 691 692 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 693 struct psp_gfx_cmd_resp *cmd, 694 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 695 { 696 struct amdgpu_device *adev = psp->adev; 697 uint32_t size = amdgpu_bo_size(tmr_bo); 698 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 699 700 if (amdgpu_sriov_vf(psp->adev)) 701 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 702 else 703 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 704 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 705 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 706 cmd->cmd.cmd_setup_tmr.buf_size = size; 707 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 708 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 709 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 710 } 711 712 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 713 uint64_t pri_buf_mc, uint32_t size) 714 { 715 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 716 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 717 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 718 cmd->cmd.cmd_load_toc.toc_size = size; 719 } 720 721 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 722 static int psp_load_toc(struct psp_context *psp, 723 uint32_t *tmr_size) 724 { 725 int ret; 726 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 727 728 /* Copy toc to psp firmware private buffer */ 729 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 730 731 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 732 733 ret = psp_cmd_submit_buf(psp, NULL, cmd, 734 psp->fence_buf_mc_addr); 735 if (!ret) 736 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 737 738 release_psp_cmd_buf(psp); 739 740 return ret; 741 } 742 743 /* Set up Trusted Memory Region */ 744 static int psp_tmr_init(struct psp_context *psp) 745 { 746 int ret; 747 int tmr_size; 748 void *tmr_buf; 749 void **pptr; 750 751 /* 752 * According to HW engineer, they prefer the TMR address be "naturally 753 * aligned" , e.g. the start address be an integer divide of TMR size. 754 * 755 * Note: this memory need be reserved till the driver 756 * uninitializes. 757 */ 758 tmr_size = PSP_TMR_SIZE(psp->adev); 759 760 /* For ASICs support RLC autoload, psp will parse the toc 761 * and calculate the total size of TMR needed */ 762 if (!amdgpu_sriov_vf(psp->adev) && 763 psp->toc.start_addr && 764 psp->toc.size_bytes && 765 psp->fw_pri_buf) { 766 ret = psp_load_toc(psp, &tmr_size); 767 if (ret) { 768 DRM_ERROR("Failed to load toc\n"); 769 return ret; 770 } 771 } 772 773 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 774 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT, 775 AMDGPU_GEM_DOMAIN_VRAM, 776 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 777 778 return ret; 779 } 780 781 static bool psp_skip_tmr(struct psp_context *psp) 782 { 783 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 784 case IP_VERSION(11, 0, 9): 785 case IP_VERSION(11, 0, 7): 786 case IP_VERSION(13, 0, 2): 787 case IP_VERSION(13, 0, 10): 788 return true; 789 default: 790 return false; 791 } 792 } 793 794 static int psp_tmr_load(struct psp_context *psp) 795 { 796 int ret; 797 struct psp_gfx_cmd_resp *cmd; 798 799 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 800 * Already set up by host driver. 801 */ 802 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 803 return 0; 804 805 cmd = acquire_psp_cmd_buf(psp); 806 807 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 808 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 809 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 810 811 ret = psp_cmd_submit_buf(psp, NULL, cmd, 812 psp->fence_buf_mc_addr); 813 814 release_psp_cmd_buf(psp); 815 816 return ret; 817 } 818 819 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 820 struct psp_gfx_cmd_resp *cmd) 821 { 822 if (amdgpu_sriov_vf(psp->adev)) 823 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 824 else 825 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 826 } 827 828 static int psp_tmr_unload(struct psp_context *psp) 829 { 830 int ret; 831 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 832 833 psp_prep_tmr_unload_cmd_buf(psp, cmd); 834 dev_info(psp->adev->dev, "free PSP TMR buffer\n"); 835 836 ret = psp_cmd_submit_buf(psp, NULL, cmd, 837 psp->fence_buf_mc_addr); 838 839 release_psp_cmd_buf(psp); 840 841 return ret; 842 } 843 844 static int psp_tmr_terminate(struct psp_context *psp) 845 { 846 return psp_tmr_unload(psp); 847 } 848 849 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 850 uint64_t *output_ptr) 851 { 852 int ret; 853 struct psp_gfx_cmd_resp *cmd; 854 855 if (!output_ptr) 856 return -EINVAL; 857 858 if (amdgpu_sriov_vf(psp->adev)) 859 return 0; 860 861 cmd = acquire_psp_cmd_buf(psp); 862 863 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 864 865 ret = psp_cmd_submit_buf(psp, NULL, cmd, 866 psp->fence_buf_mc_addr); 867 868 if (!ret) { 869 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 870 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 871 } 872 873 release_psp_cmd_buf(psp); 874 875 return ret; 876 } 877 878 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 879 { 880 struct psp_context *psp = &adev->psp; 881 struct psp_gfx_cmd_resp *cmd; 882 int ret; 883 884 if (amdgpu_sriov_vf(adev)) 885 return 0; 886 887 cmd = acquire_psp_cmd_buf(psp); 888 889 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 890 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 891 892 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 893 if (!ret) { 894 *boot_cfg = 895 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 896 } 897 898 release_psp_cmd_buf(psp); 899 900 return ret; 901 } 902 903 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 904 { 905 int ret; 906 struct psp_context *psp = &adev->psp; 907 struct psp_gfx_cmd_resp *cmd; 908 909 if (amdgpu_sriov_vf(adev)) 910 return 0; 911 912 cmd = acquire_psp_cmd_buf(psp); 913 914 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 915 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 916 cmd->cmd.boot_cfg.boot_config = boot_cfg; 917 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 918 919 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 920 921 release_psp_cmd_buf(psp); 922 923 return ret; 924 } 925 926 static int psp_rl_load(struct amdgpu_device *adev) 927 { 928 int ret; 929 struct psp_context *psp = &adev->psp; 930 struct psp_gfx_cmd_resp *cmd; 931 932 if (!is_psp_fw_valid(psp->rl)) 933 return 0; 934 935 cmd = acquire_psp_cmd_buf(psp); 936 937 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 938 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 939 940 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 941 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 942 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 943 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 944 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 945 946 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 947 948 release_psp_cmd_buf(psp); 949 950 return ret; 951 } 952 953 static int psp_asd_initialize(struct psp_context *psp) 954 { 955 int ret; 956 957 /* If PSP version doesn't match ASD version, asd loading will be failed. 958 * add workaround to bypass it for sriov now. 959 * TODO: add version check to make it common 960 */ 961 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 962 return 0; 963 964 psp->asd_context.mem_context.shared_mc_addr = 0; 965 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 966 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 967 968 ret = psp_ta_load(psp, &psp->asd_context); 969 if (!ret) 970 psp->asd_context.initialized = true; 971 972 return ret; 973 } 974 975 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 976 uint32_t session_id) 977 { 978 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 979 cmd->cmd.cmd_unload_ta.session_id = session_id; 980 } 981 982 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 983 { 984 int ret; 985 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 986 987 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 988 989 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 990 991 context->resp_status = cmd->resp.status; 992 993 release_psp_cmd_buf(psp); 994 995 return ret; 996 } 997 998 static int psp_asd_terminate(struct psp_context *psp) 999 { 1000 int ret; 1001 1002 if (amdgpu_sriov_vf(psp->adev)) 1003 return 0; 1004 1005 if (!psp->asd_context.initialized) 1006 return 0; 1007 1008 ret = psp_ta_unload(psp, &psp->asd_context); 1009 if (!ret) 1010 psp->asd_context.initialized = false; 1011 1012 return ret; 1013 } 1014 1015 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1016 uint32_t id, uint32_t value) 1017 { 1018 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1019 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1020 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1021 } 1022 1023 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1024 uint32_t value) 1025 { 1026 struct psp_gfx_cmd_resp *cmd; 1027 int ret = 0; 1028 1029 if (reg >= PSP_REG_LAST) 1030 return -EINVAL; 1031 1032 cmd = acquire_psp_cmd_buf(psp); 1033 1034 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1035 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1036 if (ret) 1037 DRM_ERROR("PSP failed to program reg id %d", reg); 1038 1039 release_psp_cmd_buf(psp); 1040 1041 return ret; 1042 } 1043 1044 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1045 uint64_t ta_bin_mc, 1046 struct ta_context *context) 1047 { 1048 cmd->cmd_id = context->ta_load_type; 1049 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1050 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1051 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1052 1053 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1054 lower_32_bits(context->mem_context.shared_mc_addr); 1055 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1056 upper_32_bits(context->mem_context.shared_mc_addr); 1057 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1058 } 1059 1060 int psp_ta_init_shared_buf(struct psp_context *psp, 1061 struct ta_mem_context *mem_ctx) 1062 { 1063 /* 1064 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1065 * physical) for ta to host memory 1066 */ 1067 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1068 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1069 &mem_ctx->shared_bo, 1070 &mem_ctx->shared_mc_addr, 1071 &mem_ctx->shared_buf); 1072 } 1073 1074 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1075 uint32_t ta_cmd_id, 1076 uint32_t session_id) 1077 { 1078 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1079 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1080 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1081 } 1082 1083 int psp_ta_invoke(struct psp_context *psp, 1084 uint32_t ta_cmd_id, 1085 struct ta_context *context) 1086 { 1087 int ret; 1088 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1089 1090 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1091 1092 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1093 psp->fence_buf_mc_addr); 1094 1095 context->resp_status = cmd->resp.status; 1096 1097 release_psp_cmd_buf(psp); 1098 1099 return ret; 1100 } 1101 1102 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1103 { 1104 int ret; 1105 struct psp_gfx_cmd_resp *cmd; 1106 1107 cmd = acquire_psp_cmd_buf(psp); 1108 1109 psp_copy_fw(psp, context->bin_desc.start_addr, 1110 context->bin_desc.size_bytes); 1111 1112 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1113 1114 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1115 psp->fence_buf_mc_addr); 1116 1117 context->resp_status = cmd->resp.status; 1118 1119 if (!ret) { 1120 context->session_id = cmd->resp.session_id; 1121 } 1122 1123 release_psp_cmd_buf(psp); 1124 1125 return ret; 1126 } 1127 1128 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1129 { 1130 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1131 } 1132 1133 int psp_xgmi_terminate(struct psp_context *psp) 1134 { 1135 int ret; 1136 struct amdgpu_device *adev = psp->adev; 1137 1138 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1139 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1140 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1141 adev->gmc.xgmi.connected_to_cpu)) 1142 return 0; 1143 1144 if (!psp->xgmi_context.context.initialized) 1145 return 0; 1146 1147 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1148 1149 psp->xgmi_context.context.initialized = false; 1150 1151 return ret; 1152 } 1153 1154 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1155 { 1156 struct ta_xgmi_shared_memory *xgmi_cmd; 1157 int ret; 1158 1159 if (!psp->ta_fw || 1160 !psp->xgmi_context.context.bin_desc.size_bytes || 1161 !psp->xgmi_context.context.bin_desc.start_addr) 1162 return -ENOENT; 1163 1164 if (!load_ta) 1165 goto invoke; 1166 1167 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1168 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1169 1170 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1171 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1172 if (ret) 1173 return ret; 1174 } 1175 1176 /* Load XGMI TA */ 1177 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1178 if (!ret) 1179 psp->xgmi_context.context.initialized = true; 1180 else 1181 return ret; 1182 1183 invoke: 1184 /* Initialize XGMI session */ 1185 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1186 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1187 xgmi_cmd->flag_extend_link_record = set_extended_data; 1188 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1189 1190 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1191 1192 return ret; 1193 } 1194 1195 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1196 { 1197 struct ta_xgmi_shared_memory *xgmi_cmd; 1198 int ret; 1199 1200 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1201 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1202 1203 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1204 1205 /* Invoke xgmi ta to get hive id */ 1206 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1207 if (ret) 1208 return ret; 1209 1210 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1211 1212 return 0; 1213 } 1214 1215 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1216 { 1217 struct ta_xgmi_shared_memory *xgmi_cmd; 1218 int ret; 1219 1220 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1221 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1222 1223 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1224 1225 /* Invoke xgmi ta to get the node id */ 1226 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1227 if (ret) 1228 return ret; 1229 1230 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1231 1232 return 0; 1233 } 1234 1235 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1236 { 1237 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1238 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1239 } 1240 1241 /* 1242 * Chips that support extended topology information require the driver to 1243 * reflect topology information in the opposite direction. This is 1244 * because the TA has already exceeded its link record limit and if the 1245 * TA holds bi-directional information, the driver would have to do 1246 * multiple fetches instead of just two. 1247 */ 1248 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1249 struct psp_xgmi_node_info node_info) 1250 { 1251 struct amdgpu_device *mirror_adev; 1252 struct amdgpu_hive_info *hive; 1253 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1254 uint64_t dst_node_id = node_info.node_id; 1255 uint8_t dst_num_hops = node_info.num_hops; 1256 uint8_t dst_num_links = node_info.num_links; 1257 1258 hive = amdgpu_get_xgmi_hive(psp->adev); 1259 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1260 struct psp_xgmi_topology_info *mirror_top_info; 1261 int j; 1262 1263 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1264 continue; 1265 1266 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1267 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1268 if (mirror_top_info->nodes[j].node_id != src_node_id) 1269 continue; 1270 1271 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1272 /* 1273 * prevent 0 num_links value re-reflection since reflection 1274 * criteria is based on num_hops (direct or indirect). 1275 * 1276 */ 1277 if (dst_num_links) 1278 mirror_top_info->nodes[j].num_links = dst_num_links; 1279 1280 break; 1281 } 1282 1283 break; 1284 } 1285 1286 amdgpu_put_xgmi_hive(hive); 1287 } 1288 1289 int psp_xgmi_get_topology_info(struct psp_context *psp, 1290 int number_devices, 1291 struct psp_xgmi_topology_info *topology, 1292 bool get_extended_data) 1293 { 1294 struct ta_xgmi_shared_memory *xgmi_cmd; 1295 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1296 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1297 int i; 1298 int ret; 1299 1300 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1301 return -EINVAL; 1302 1303 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1304 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1305 xgmi_cmd->flag_extend_link_record = get_extended_data; 1306 1307 /* Fill in the shared memory with topology information as input */ 1308 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1309 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1310 topology_info_input->num_nodes = number_devices; 1311 1312 for (i = 0; i < topology_info_input->num_nodes; i++) { 1313 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1314 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1315 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1316 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1317 } 1318 1319 /* Invoke xgmi ta to get the topology information */ 1320 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1321 if (ret) 1322 return ret; 1323 1324 /* Read the output topology information from the shared memory */ 1325 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1326 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1327 for (i = 0; i < topology->num_nodes; i++) { 1328 /* extended data will either be 0 or equal to non-extended data */ 1329 if (topology_info_output->nodes[i].num_hops) 1330 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1331 1332 /* non-extended data gets everything here so no need to update */ 1333 if (!get_extended_data) { 1334 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1335 topology->nodes[i].is_sharing_enabled = 1336 topology_info_output->nodes[i].is_sharing_enabled; 1337 topology->nodes[i].sdma_engine = 1338 topology_info_output->nodes[i].sdma_engine; 1339 } 1340 1341 } 1342 1343 /* Invoke xgmi ta again to get the link information */ 1344 if (psp_xgmi_peer_link_info_supported(psp)) { 1345 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1346 1347 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1348 1349 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1350 1351 if (ret) 1352 return ret; 1353 1354 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1355 for (i = 0; i < topology->num_nodes; i++) { 1356 /* accumulate num_links on extended data */ 1357 topology->nodes[i].num_links = get_extended_data ? 1358 topology->nodes[i].num_links + 1359 link_info_output->nodes[i].num_links : 1360 link_info_output->nodes[i].num_links; 1361 1362 /* reflect the topology information for bi-directionality */ 1363 if (psp->xgmi_context.supports_extended_data && 1364 get_extended_data && topology->nodes[i].num_hops) 1365 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1366 } 1367 } 1368 1369 return 0; 1370 } 1371 1372 int psp_xgmi_set_topology_info(struct psp_context *psp, 1373 int number_devices, 1374 struct psp_xgmi_topology_info *topology) 1375 { 1376 struct ta_xgmi_shared_memory *xgmi_cmd; 1377 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1378 int i; 1379 1380 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1381 return -EINVAL; 1382 1383 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1384 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1385 1386 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1387 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1388 topology_info_input->num_nodes = number_devices; 1389 1390 for (i = 0; i < topology_info_input->num_nodes; i++) { 1391 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1392 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1393 topology_info_input->nodes[i].is_sharing_enabled = 1; 1394 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1395 } 1396 1397 /* Invoke xgmi ta to set topology information */ 1398 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1399 } 1400 1401 // ras begin 1402 static void psp_ras_ta_check_status(struct psp_context *psp) 1403 { 1404 struct ta_ras_shared_memory *ras_cmd = 1405 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1406 1407 switch (ras_cmd->ras_status) { 1408 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1409 dev_warn(psp->adev->dev, 1410 "RAS WARNING: cmd failed due to unsupported ip\n"); 1411 break; 1412 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1413 dev_warn(psp->adev->dev, 1414 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1415 break; 1416 case TA_RAS_STATUS__SUCCESS: 1417 break; 1418 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1419 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1420 dev_warn(psp->adev->dev, 1421 "RAS WARNING: Inject error to critical region is not allowed\n"); 1422 break; 1423 default: 1424 dev_warn(psp->adev->dev, 1425 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1426 break; 1427 } 1428 } 1429 1430 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1431 { 1432 struct ta_ras_shared_memory *ras_cmd; 1433 int ret; 1434 1435 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1436 1437 /* 1438 * TODO: bypass the loading in sriov for now 1439 */ 1440 if (amdgpu_sriov_vf(psp->adev)) 1441 return 0; 1442 1443 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1444 1445 if (amdgpu_ras_intr_triggered()) 1446 return ret; 1447 1448 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1449 { 1450 DRM_WARN("RAS: Unsupported Interface"); 1451 return -EINVAL; 1452 } 1453 1454 if (!ret) { 1455 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1456 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1457 1458 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1459 } 1460 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1461 dev_warn(psp->adev->dev, 1462 "RAS internal register access blocked\n"); 1463 1464 psp_ras_ta_check_status(psp); 1465 } 1466 1467 return ret; 1468 } 1469 1470 int psp_ras_enable_features(struct psp_context *psp, 1471 union ta_ras_cmd_input *info, bool enable) 1472 { 1473 struct ta_ras_shared_memory *ras_cmd; 1474 int ret; 1475 1476 if (!psp->ras_context.context.initialized) 1477 return -EINVAL; 1478 1479 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1480 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1481 1482 if (enable) 1483 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1484 else 1485 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1486 1487 ras_cmd->ras_in_message = *info; 1488 1489 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1490 if (ret) 1491 return -EINVAL; 1492 1493 return 0; 1494 } 1495 1496 int psp_ras_terminate(struct psp_context *psp) 1497 { 1498 int ret; 1499 1500 /* 1501 * TODO: bypass the terminate in sriov for now 1502 */ 1503 if (amdgpu_sriov_vf(psp->adev)) 1504 return 0; 1505 1506 if (!psp->ras_context.context.initialized) 1507 return 0; 1508 1509 ret = psp_ta_unload(psp, &psp->ras_context.context); 1510 1511 psp->ras_context.context.initialized = false; 1512 1513 return ret; 1514 } 1515 1516 int psp_ras_initialize(struct psp_context *psp) 1517 { 1518 int ret; 1519 uint32_t boot_cfg = 0xFF; 1520 struct amdgpu_device *adev = psp->adev; 1521 struct ta_ras_shared_memory *ras_cmd; 1522 1523 /* 1524 * TODO: bypass the initialize in sriov for now 1525 */ 1526 if (amdgpu_sriov_vf(adev)) 1527 return 0; 1528 1529 if (psp->ras_context.context.initialized) { 1530 dev_warn(adev->dev, "RAS WARN: TA has already been loaded\n"); 1531 return 0; 1532 } 1533 1534 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1535 !adev->psp.ras_context.context.bin_desc.start_addr) { 1536 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1537 return 0; 1538 } 1539 1540 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1541 /* query GECC enablement status from boot config 1542 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1543 */ 1544 ret = psp_boot_config_get(adev, &boot_cfg); 1545 if (ret) 1546 dev_warn(adev->dev, "PSP get boot config failed\n"); 1547 1548 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1549 if (!boot_cfg) { 1550 dev_info(adev->dev, "GECC is disabled\n"); 1551 } else { 1552 /* disable GECC in next boot cycle if ras is 1553 * disabled by module parameter amdgpu_ras_enable 1554 * and/or amdgpu_ras_mask, or boot_config_get call 1555 * is failed 1556 */ 1557 ret = psp_boot_config_set(adev, 0); 1558 if (ret) 1559 dev_warn(adev->dev, "PSP set boot config failed\n"); 1560 else 1561 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1562 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1563 } 1564 } else { 1565 if (1 == boot_cfg) { 1566 dev_info(adev->dev, "GECC is enabled\n"); 1567 } else { 1568 /* enable GECC in next boot cycle if it is disabled 1569 * in boot config, or force enable GECC if failed to 1570 * get boot configuration 1571 */ 1572 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1573 if (ret) 1574 dev_warn(adev->dev, "PSP set boot config failed\n"); 1575 else 1576 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1577 } 1578 } 1579 } 1580 1581 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1582 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1583 1584 if (!psp->ras_context.context.mem_context.shared_buf) { 1585 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1586 if (ret) 1587 return ret; 1588 } 1589 1590 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1591 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1592 1593 if (amdgpu_ras_is_poison_mode_supported(adev)) 1594 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1595 if (!adev->gmc.xgmi.connected_to_cpu) 1596 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1597 1598 ret = psp_ta_load(psp, &psp->ras_context.context); 1599 1600 if (!ret && !ras_cmd->ras_status) 1601 psp->ras_context.context.initialized = true; 1602 else { 1603 if (ras_cmd->ras_status) 1604 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1605 } 1606 1607 return ret; 1608 } 1609 1610 int psp_ras_trigger_error(struct psp_context *psp, 1611 struct ta_ras_trigger_error_input *info) 1612 { 1613 struct ta_ras_shared_memory *ras_cmd; 1614 int ret; 1615 1616 if (!psp->ras_context.context.initialized) 1617 return -EINVAL; 1618 1619 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1620 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1621 1622 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1623 ras_cmd->ras_in_message.trigger_error = *info; 1624 1625 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1626 if (ret) 1627 return -EINVAL; 1628 1629 /* If err_event_athub occurs error inject was successful, however 1630 return status from TA is no long reliable */ 1631 if (amdgpu_ras_intr_triggered()) 1632 return 0; 1633 1634 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1635 return -EACCES; 1636 else if (ras_cmd->ras_status) 1637 return -EINVAL; 1638 1639 return 0; 1640 } 1641 // ras end 1642 1643 // HDCP start 1644 static int psp_hdcp_initialize(struct psp_context *psp) 1645 { 1646 int ret; 1647 1648 /* 1649 * TODO: bypass the initialize in sriov for now 1650 */ 1651 if (amdgpu_sriov_vf(psp->adev)) 1652 return 0; 1653 1654 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1655 !psp->hdcp_context.context.bin_desc.start_addr) { 1656 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1657 return 0; 1658 } 1659 1660 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1661 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1662 1663 if (!psp->hdcp_context.context.initialized) { 1664 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1665 if (ret) 1666 return ret; 1667 } 1668 1669 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1670 if (!ret) { 1671 psp->hdcp_context.context.initialized = true; 1672 mutex_init(&psp->hdcp_context.mutex); 1673 } 1674 1675 return ret; 1676 } 1677 1678 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1679 { 1680 /* 1681 * TODO: bypass the loading in sriov for now 1682 */ 1683 if (amdgpu_sriov_vf(psp->adev)) 1684 return 0; 1685 1686 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1687 } 1688 1689 static int psp_hdcp_terminate(struct psp_context *psp) 1690 { 1691 int ret; 1692 1693 /* 1694 * TODO: bypass the terminate in sriov for now 1695 */ 1696 if (amdgpu_sriov_vf(psp->adev)) 1697 return 0; 1698 1699 if (!psp->hdcp_context.context.initialized) 1700 return 0; 1701 1702 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1703 1704 psp->hdcp_context.context.initialized = false; 1705 1706 return ret; 1707 } 1708 // HDCP end 1709 1710 // DTM start 1711 static int psp_dtm_initialize(struct psp_context *psp) 1712 { 1713 int ret; 1714 1715 /* 1716 * TODO: bypass the initialize in sriov for now 1717 */ 1718 if (amdgpu_sriov_vf(psp->adev)) 1719 return 0; 1720 1721 if (!psp->dtm_context.context.bin_desc.size_bytes || 1722 !psp->dtm_context.context.bin_desc.start_addr) { 1723 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1724 return 0; 1725 } 1726 1727 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1728 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1729 1730 if (!psp->dtm_context.context.initialized) { 1731 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1732 if (ret) 1733 return ret; 1734 } 1735 1736 ret = psp_ta_load(psp, &psp->dtm_context.context); 1737 if (!ret) { 1738 psp->dtm_context.context.initialized = true; 1739 mutex_init(&psp->dtm_context.mutex); 1740 } 1741 1742 return ret; 1743 } 1744 1745 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1746 { 1747 /* 1748 * TODO: bypass the loading in sriov for now 1749 */ 1750 if (amdgpu_sriov_vf(psp->adev)) 1751 return 0; 1752 1753 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1754 } 1755 1756 static int psp_dtm_terminate(struct psp_context *psp) 1757 { 1758 int ret; 1759 1760 /* 1761 * TODO: bypass the terminate in sriov for now 1762 */ 1763 if (amdgpu_sriov_vf(psp->adev)) 1764 return 0; 1765 1766 if (!psp->dtm_context.context.initialized) 1767 return 0; 1768 1769 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1770 1771 psp->dtm_context.context.initialized = false; 1772 1773 return ret; 1774 } 1775 // DTM end 1776 1777 // RAP start 1778 static int psp_rap_initialize(struct psp_context *psp) 1779 { 1780 int ret; 1781 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1782 1783 /* 1784 * TODO: bypass the initialize in sriov for now 1785 */ 1786 if (amdgpu_sriov_vf(psp->adev)) 1787 return 0; 1788 1789 if (!psp->rap_context.context.bin_desc.size_bytes || 1790 !psp->rap_context.context.bin_desc.start_addr) { 1791 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1792 return 0; 1793 } 1794 1795 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1796 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1797 1798 if (!psp->rap_context.context.initialized) { 1799 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1800 if (ret) 1801 return ret; 1802 } 1803 1804 ret = psp_ta_load(psp, &psp->rap_context.context); 1805 if (!ret) { 1806 psp->rap_context.context.initialized = true; 1807 mutex_init(&psp->rap_context.mutex); 1808 } else 1809 return ret; 1810 1811 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1812 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1813 psp_rap_terminate(psp); 1814 /* free rap shared memory */ 1815 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1816 1817 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1818 ret, status); 1819 1820 return ret; 1821 } 1822 1823 return 0; 1824 } 1825 1826 static int psp_rap_terminate(struct psp_context *psp) 1827 { 1828 int ret; 1829 1830 if (!psp->rap_context.context.initialized) 1831 return 0; 1832 1833 ret = psp_ta_unload(psp, &psp->rap_context.context); 1834 1835 psp->rap_context.context.initialized = false; 1836 1837 return ret; 1838 } 1839 1840 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1841 { 1842 struct ta_rap_shared_memory *rap_cmd; 1843 int ret = 0; 1844 1845 if (!psp->rap_context.context.initialized) 1846 return 0; 1847 1848 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1849 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1850 return -EINVAL; 1851 1852 mutex_lock(&psp->rap_context.mutex); 1853 1854 rap_cmd = (struct ta_rap_shared_memory *) 1855 psp->rap_context.context.mem_context.shared_buf; 1856 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1857 1858 rap_cmd->cmd_id = ta_cmd_id; 1859 rap_cmd->validation_method_id = METHOD_A; 1860 1861 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1862 if (ret) 1863 goto out_unlock; 1864 1865 if (status) 1866 *status = rap_cmd->rap_status; 1867 1868 out_unlock: 1869 mutex_unlock(&psp->rap_context.mutex); 1870 1871 return ret; 1872 } 1873 // RAP end 1874 1875 /* securedisplay start */ 1876 static int psp_securedisplay_initialize(struct psp_context *psp) 1877 { 1878 int ret; 1879 struct securedisplay_cmd *securedisplay_cmd; 1880 1881 /* 1882 * TODO: bypass the initialize in sriov for now 1883 */ 1884 if (amdgpu_sriov_vf(psp->adev)) 1885 return 0; 1886 1887 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1888 !psp->securedisplay_context.context.bin_desc.start_addr) { 1889 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1890 return 0; 1891 } 1892 1893 psp->securedisplay_context.context.mem_context.shared_mem_size = 1894 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1895 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1896 1897 if (!psp->securedisplay_context.context.initialized) { 1898 ret = psp_ta_init_shared_buf(psp, 1899 &psp->securedisplay_context.context.mem_context); 1900 if (ret) 1901 return ret; 1902 } 1903 1904 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 1905 if (!ret) { 1906 psp->securedisplay_context.context.initialized = true; 1907 mutex_init(&psp->securedisplay_context.mutex); 1908 } else 1909 return ret; 1910 1911 mutex_lock(&psp->securedisplay_context.mutex); 1912 1913 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1914 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1915 1916 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1917 1918 mutex_unlock(&psp->securedisplay_context.mutex); 1919 1920 if (ret) { 1921 psp_securedisplay_terminate(psp); 1922 /* free securedisplay shared memory */ 1923 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1924 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1925 return -EINVAL; 1926 } 1927 1928 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1929 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1930 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1931 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1932 } 1933 1934 return 0; 1935 } 1936 1937 static int psp_securedisplay_terminate(struct psp_context *psp) 1938 { 1939 int ret; 1940 1941 /* 1942 * TODO:bypass the terminate in sriov for now 1943 */ 1944 if (amdgpu_sriov_vf(psp->adev)) 1945 return 0; 1946 1947 if (!psp->securedisplay_context.context.initialized) 1948 return 0; 1949 1950 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 1951 1952 psp->securedisplay_context.context.initialized = false; 1953 1954 return ret; 1955 } 1956 1957 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1958 { 1959 int ret; 1960 1961 if (!psp->securedisplay_context.context.initialized) 1962 return -EINVAL; 1963 1964 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1965 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1966 return -EINVAL; 1967 1968 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1969 1970 return ret; 1971 } 1972 /* SECUREDISPLAY end */ 1973 1974 static int psp_hw_start(struct psp_context *psp) 1975 { 1976 struct amdgpu_device *adev = psp->adev; 1977 int ret; 1978 1979 if (!amdgpu_sriov_vf(adev)) { 1980 if ((is_psp_fw_valid(psp->kdb)) && 1981 (psp->funcs->bootloader_load_kdb != NULL)) { 1982 ret = psp_bootloader_load_kdb(psp); 1983 if (ret) { 1984 DRM_ERROR("PSP load kdb failed!\n"); 1985 return ret; 1986 } 1987 } 1988 1989 if ((is_psp_fw_valid(psp->spl)) && 1990 (psp->funcs->bootloader_load_spl != NULL)) { 1991 ret = psp_bootloader_load_spl(psp); 1992 if (ret) { 1993 DRM_ERROR("PSP load spl failed!\n"); 1994 return ret; 1995 } 1996 } 1997 1998 if ((is_psp_fw_valid(psp->sys)) && 1999 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2000 ret = psp_bootloader_load_sysdrv(psp); 2001 if (ret) { 2002 DRM_ERROR("PSP load sys drv failed!\n"); 2003 return ret; 2004 } 2005 } 2006 2007 if ((is_psp_fw_valid(psp->soc_drv)) && 2008 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2009 ret = psp_bootloader_load_soc_drv(psp); 2010 if (ret) { 2011 DRM_ERROR("PSP load soc drv failed!\n"); 2012 return ret; 2013 } 2014 } 2015 2016 if ((is_psp_fw_valid(psp->intf_drv)) && 2017 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2018 ret = psp_bootloader_load_intf_drv(psp); 2019 if (ret) { 2020 DRM_ERROR("PSP load intf drv failed!\n"); 2021 return ret; 2022 } 2023 } 2024 2025 if ((is_psp_fw_valid(psp->dbg_drv)) && 2026 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2027 ret = psp_bootloader_load_dbg_drv(psp); 2028 if (ret) { 2029 DRM_ERROR("PSP load dbg drv failed!\n"); 2030 return ret; 2031 } 2032 } 2033 2034 if ((is_psp_fw_valid(psp->ras_drv)) && 2035 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2036 ret = psp_bootloader_load_ras_drv(psp); 2037 if (ret) { 2038 DRM_ERROR("PSP load ras_drv failed!\n"); 2039 return ret; 2040 } 2041 } 2042 2043 if ((is_psp_fw_valid(psp->sos)) && 2044 (psp->funcs->bootloader_load_sos != NULL)) { 2045 ret = psp_bootloader_load_sos(psp); 2046 if (ret) { 2047 DRM_ERROR("PSP load sos failed!\n"); 2048 return ret; 2049 } 2050 } 2051 } 2052 2053 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2054 if (ret) { 2055 DRM_ERROR("PSP create ring failed!\n"); 2056 return ret; 2057 } 2058 2059 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2060 goto skip_pin_bo; 2061 2062 ret = psp_tmr_init(psp); 2063 if (ret) { 2064 DRM_ERROR("PSP tmr init failed!\n"); 2065 return ret; 2066 } 2067 2068 skip_pin_bo: 2069 /* 2070 * For ASICs with DF Cstate management centralized 2071 * to PMFW, TMR setup should be performed after PMFW 2072 * loaded and before other non-psp firmware loaded. 2073 */ 2074 if (psp->pmfw_centralized_cstate_management) { 2075 ret = psp_load_smu_fw(psp); 2076 if (ret) 2077 return ret; 2078 } 2079 2080 ret = psp_tmr_load(psp); 2081 if (ret) { 2082 DRM_ERROR("PSP load tmr failed!\n"); 2083 return ret; 2084 } 2085 2086 return 0; 2087 } 2088 2089 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2090 enum psp_gfx_fw_type *type) 2091 { 2092 switch (ucode->ucode_id) { 2093 case AMDGPU_UCODE_ID_CAP: 2094 *type = GFX_FW_TYPE_CAP; 2095 break; 2096 case AMDGPU_UCODE_ID_SDMA0: 2097 *type = GFX_FW_TYPE_SDMA0; 2098 break; 2099 case AMDGPU_UCODE_ID_SDMA1: 2100 *type = GFX_FW_TYPE_SDMA1; 2101 break; 2102 case AMDGPU_UCODE_ID_SDMA2: 2103 *type = GFX_FW_TYPE_SDMA2; 2104 break; 2105 case AMDGPU_UCODE_ID_SDMA3: 2106 *type = GFX_FW_TYPE_SDMA3; 2107 break; 2108 case AMDGPU_UCODE_ID_SDMA4: 2109 *type = GFX_FW_TYPE_SDMA4; 2110 break; 2111 case AMDGPU_UCODE_ID_SDMA5: 2112 *type = GFX_FW_TYPE_SDMA5; 2113 break; 2114 case AMDGPU_UCODE_ID_SDMA6: 2115 *type = GFX_FW_TYPE_SDMA6; 2116 break; 2117 case AMDGPU_UCODE_ID_SDMA7: 2118 *type = GFX_FW_TYPE_SDMA7; 2119 break; 2120 case AMDGPU_UCODE_ID_CP_MES: 2121 *type = GFX_FW_TYPE_CP_MES; 2122 break; 2123 case AMDGPU_UCODE_ID_CP_MES_DATA: 2124 *type = GFX_FW_TYPE_MES_STACK; 2125 break; 2126 case AMDGPU_UCODE_ID_CP_MES1: 2127 *type = GFX_FW_TYPE_CP_MES_KIQ; 2128 break; 2129 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2130 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2131 break; 2132 case AMDGPU_UCODE_ID_CP_CE: 2133 *type = GFX_FW_TYPE_CP_CE; 2134 break; 2135 case AMDGPU_UCODE_ID_CP_PFP: 2136 *type = GFX_FW_TYPE_CP_PFP; 2137 break; 2138 case AMDGPU_UCODE_ID_CP_ME: 2139 *type = GFX_FW_TYPE_CP_ME; 2140 break; 2141 case AMDGPU_UCODE_ID_CP_MEC1: 2142 *type = GFX_FW_TYPE_CP_MEC; 2143 break; 2144 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2145 *type = GFX_FW_TYPE_CP_MEC_ME1; 2146 break; 2147 case AMDGPU_UCODE_ID_CP_MEC2: 2148 *type = GFX_FW_TYPE_CP_MEC; 2149 break; 2150 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2151 *type = GFX_FW_TYPE_CP_MEC_ME2; 2152 break; 2153 case AMDGPU_UCODE_ID_RLC_P: 2154 *type = GFX_FW_TYPE_RLC_P; 2155 break; 2156 case AMDGPU_UCODE_ID_RLC_V: 2157 *type = GFX_FW_TYPE_RLC_V; 2158 break; 2159 case AMDGPU_UCODE_ID_RLC_G: 2160 *type = GFX_FW_TYPE_RLC_G; 2161 break; 2162 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2163 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2164 break; 2165 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2166 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2167 break; 2168 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2169 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2170 break; 2171 case AMDGPU_UCODE_ID_RLC_IRAM: 2172 *type = GFX_FW_TYPE_RLC_IRAM; 2173 break; 2174 case AMDGPU_UCODE_ID_RLC_DRAM: 2175 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2176 break; 2177 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2178 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2179 break; 2180 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2181 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2182 break; 2183 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2184 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2185 break; 2186 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2187 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2188 break; 2189 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2190 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2191 break; 2192 case AMDGPU_UCODE_ID_SMC: 2193 *type = GFX_FW_TYPE_SMU; 2194 break; 2195 case AMDGPU_UCODE_ID_PPTABLE: 2196 *type = GFX_FW_TYPE_PPTABLE; 2197 break; 2198 case AMDGPU_UCODE_ID_UVD: 2199 *type = GFX_FW_TYPE_UVD; 2200 break; 2201 case AMDGPU_UCODE_ID_UVD1: 2202 *type = GFX_FW_TYPE_UVD1; 2203 break; 2204 case AMDGPU_UCODE_ID_VCE: 2205 *type = GFX_FW_TYPE_VCE; 2206 break; 2207 case AMDGPU_UCODE_ID_VCN: 2208 *type = GFX_FW_TYPE_VCN; 2209 break; 2210 case AMDGPU_UCODE_ID_VCN1: 2211 *type = GFX_FW_TYPE_VCN1; 2212 break; 2213 case AMDGPU_UCODE_ID_DMCU_ERAM: 2214 *type = GFX_FW_TYPE_DMCU_ERAM; 2215 break; 2216 case AMDGPU_UCODE_ID_DMCU_INTV: 2217 *type = GFX_FW_TYPE_DMCU_ISR; 2218 break; 2219 case AMDGPU_UCODE_ID_VCN0_RAM: 2220 *type = GFX_FW_TYPE_VCN0_RAM; 2221 break; 2222 case AMDGPU_UCODE_ID_VCN1_RAM: 2223 *type = GFX_FW_TYPE_VCN1_RAM; 2224 break; 2225 case AMDGPU_UCODE_ID_DMCUB: 2226 *type = GFX_FW_TYPE_DMUB; 2227 break; 2228 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2229 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2230 break; 2231 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2232 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2233 break; 2234 case AMDGPU_UCODE_ID_IMU_I: 2235 *type = GFX_FW_TYPE_IMU_I; 2236 break; 2237 case AMDGPU_UCODE_ID_IMU_D: 2238 *type = GFX_FW_TYPE_IMU_D; 2239 break; 2240 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2241 *type = GFX_FW_TYPE_RS64_PFP; 2242 break; 2243 case AMDGPU_UCODE_ID_CP_RS64_ME: 2244 *type = GFX_FW_TYPE_RS64_ME; 2245 break; 2246 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2247 *type = GFX_FW_TYPE_RS64_MEC; 2248 break; 2249 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2250 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2251 break; 2252 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2253 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2254 break; 2255 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2256 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2257 break; 2258 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2259 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2260 break; 2261 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2262 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2263 break; 2264 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2265 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2266 break; 2267 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2268 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2269 break; 2270 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2271 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2272 break; 2273 case AMDGPU_UCODE_ID_MAXIMUM: 2274 default: 2275 return -EINVAL; 2276 } 2277 2278 return 0; 2279 } 2280 2281 static void psp_print_fw_hdr(struct psp_context *psp, 2282 struct amdgpu_firmware_info *ucode) 2283 { 2284 struct amdgpu_device *adev = psp->adev; 2285 struct common_firmware_header *hdr; 2286 2287 switch (ucode->ucode_id) { 2288 case AMDGPU_UCODE_ID_SDMA0: 2289 case AMDGPU_UCODE_ID_SDMA1: 2290 case AMDGPU_UCODE_ID_SDMA2: 2291 case AMDGPU_UCODE_ID_SDMA3: 2292 case AMDGPU_UCODE_ID_SDMA4: 2293 case AMDGPU_UCODE_ID_SDMA5: 2294 case AMDGPU_UCODE_ID_SDMA6: 2295 case AMDGPU_UCODE_ID_SDMA7: 2296 hdr = (struct common_firmware_header *) 2297 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2298 amdgpu_ucode_print_sdma_hdr(hdr); 2299 break; 2300 case AMDGPU_UCODE_ID_CP_CE: 2301 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2302 amdgpu_ucode_print_gfx_hdr(hdr); 2303 break; 2304 case AMDGPU_UCODE_ID_CP_PFP: 2305 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2306 amdgpu_ucode_print_gfx_hdr(hdr); 2307 break; 2308 case AMDGPU_UCODE_ID_CP_ME: 2309 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2310 amdgpu_ucode_print_gfx_hdr(hdr); 2311 break; 2312 case AMDGPU_UCODE_ID_CP_MEC1: 2313 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2314 amdgpu_ucode_print_gfx_hdr(hdr); 2315 break; 2316 case AMDGPU_UCODE_ID_RLC_G: 2317 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2318 amdgpu_ucode_print_rlc_hdr(hdr); 2319 break; 2320 case AMDGPU_UCODE_ID_SMC: 2321 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2322 amdgpu_ucode_print_smc_hdr(hdr); 2323 break; 2324 default: 2325 break; 2326 } 2327 } 2328 2329 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2330 struct psp_gfx_cmd_resp *cmd) 2331 { 2332 int ret; 2333 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2334 2335 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2336 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2337 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2338 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2339 2340 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2341 if (ret) 2342 DRM_ERROR("Unknown firmware type\n"); 2343 2344 return ret; 2345 } 2346 2347 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2348 struct amdgpu_firmware_info *ucode) 2349 { 2350 int ret = 0; 2351 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2352 2353 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2354 if (!ret) { 2355 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2356 psp->fence_buf_mc_addr); 2357 } 2358 2359 release_psp_cmd_buf(psp); 2360 2361 return ret; 2362 } 2363 2364 static int psp_load_smu_fw(struct psp_context *psp) 2365 { 2366 int ret; 2367 struct amdgpu_device *adev = psp->adev; 2368 struct amdgpu_firmware_info *ucode = 2369 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2370 struct amdgpu_ras *ras = psp->ras_context.ras; 2371 2372 /* 2373 * Skip SMU FW reloading in case of using BACO for runpm only, 2374 * as SMU is always alive. 2375 */ 2376 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2377 return 0; 2378 2379 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2380 return 0; 2381 2382 if ((amdgpu_in_reset(adev) && 2383 ras && adev->ras_enabled && 2384 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2385 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2386 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2387 if (ret) { 2388 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2389 } 2390 } 2391 2392 ret = psp_execute_non_psp_fw_load(psp, ucode); 2393 2394 if (ret) 2395 DRM_ERROR("PSP load smu failed!\n"); 2396 2397 return ret; 2398 } 2399 2400 static bool fw_load_skip_check(struct psp_context *psp, 2401 struct amdgpu_firmware_info *ucode) 2402 { 2403 if (!ucode->fw || !ucode->ucode_size) 2404 return true; 2405 2406 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2407 (psp_smu_reload_quirk(psp) || 2408 psp->autoload_supported || 2409 psp->pmfw_centralized_cstate_management)) 2410 return true; 2411 2412 if (amdgpu_sriov_vf(psp->adev) && 2413 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2414 return true; 2415 2416 if (psp->autoload_supported && 2417 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2418 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2419 /* skip mec JT when autoload is enabled */ 2420 return true; 2421 2422 return false; 2423 } 2424 2425 int psp_load_fw_list(struct psp_context *psp, 2426 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2427 { 2428 int ret = 0, i; 2429 struct amdgpu_firmware_info *ucode; 2430 2431 for (i = 0; i < ucode_count; ++i) { 2432 ucode = ucode_list[i]; 2433 psp_print_fw_hdr(psp, ucode); 2434 ret = psp_execute_non_psp_fw_load(psp, ucode); 2435 if (ret) 2436 return ret; 2437 } 2438 return ret; 2439 } 2440 2441 static int psp_load_non_psp_fw(struct psp_context *psp) 2442 { 2443 int i, ret; 2444 struct amdgpu_firmware_info *ucode; 2445 struct amdgpu_device *adev = psp->adev; 2446 2447 if (psp->autoload_supported && 2448 !psp->pmfw_centralized_cstate_management) { 2449 ret = psp_load_smu_fw(psp); 2450 if (ret) 2451 return ret; 2452 } 2453 2454 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2455 ucode = &adev->firmware.ucode[i]; 2456 2457 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2458 !fw_load_skip_check(psp, ucode)) { 2459 ret = psp_load_smu_fw(psp); 2460 if (ret) 2461 return ret; 2462 continue; 2463 } 2464 2465 if (fw_load_skip_check(psp, ucode)) 2466 continue; 2467 2468 if (psp->autoload_supported && 2469 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2470 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2471 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2472 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2473 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2474 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2475 /* PSP only receive one SDMA fw for sienna_cichlid, 2476 * as all four sdma fw are same */ 2477 continue; 2478 2479 psp_print_fw_hdr(psp, ucode); 2480 2481 ret = psp_execute_non_psp_fw_load(psp, ucode); 2482 if (ret) 2483 return ret; 2484 2485 /* Start rlc autoload after psp recieved all the gfx firmware */ 2486 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2487 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2488 ret = psp_rlc_autoload_start(psp); 2489 if (ret) { 2490 DRM_ERROR("Failed to start rlc autoload\n"); 2491 return ret; 2492 } 2493 } 2494 } 2495 2496 return 0; 2497 } 2498 2499 static int psp_load_fw(struct amdgpu_device *adev) 2500 { 2501 int ret; 2502 struct psp_context *psp = &adev->psp; 2503 2504 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2505 /* should not destroy ring, only stop */ 2506 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2507 } else { 2508 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2509 2510 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2511 if (ret) { 2512 DRM_ERROR("PSP ring init failed!\n"); 2513 goto failed; 2514 } 2515 } 2516 2517 ret = psp_hw_start(psp); 2518 if (ret) 2519 goto failed; 2520 2521 ret = psp_load_non_psp_fw(psp); 2522 if (ret) 2523 goto failed1; 2524 2525 ret = psp_asd_initialize(psp); 2526 if (ret) { 2527 DRM_ERROR("PSP load asd failed!\n"); 2528 goto failed1; 2529 } 2530 2531 ret = psp_rl_load(adev); 2532 if (ret) { 2533 DRM_ERROR("PSP load RL failed!\n"); 2534 goto failed1; 2535 } 2536 2537 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2538 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2539 ret = psp_xgmi_initialize(psp, false, true); 2540 /* Warning the XGMI seesion initialize failure 2541 * Instead of stop driver initialization 2542 */ 2543 if (ret) 2544 dev_err(psp->adev->dev, 2545 "XGMI: Failed to initialize XGMI session\n"); 2546 } 2547 } 2548 2549 if (psp->ta_fw) { 2550 ret = psp_ras_initialize(psp); 2551 if (ret) 2552 dev_err(psp->adev->dev, 2553 "RAS: Failed to initialize RAS\n"); 2554 2555 ret = psp_hdcp_initialize(psp); 2556 if (ret) 2557 dev_err(psp->adev->dev, 2558 "HDCP: Failed to initialize HDCP\n"); 2559 2560 ret = psp_dtm_initialize(psp); 2561 if (ret) 2562 dev_err(psp->adev->dev, 2563 "DTM: Failed to initialize DTM\n"); 2564 2565 ret = psp_rap_initialize(psp); 2566 if (ret) 2567 dev_err(psp->adev->dev, 2568 "RAP: Failed to initialize RAP\n"); 2569 2570 ret = psp_securedisplay_initialize(psp); 2571 if (ret) 2572 dev_err(psp->adev->dev, 2573 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2574 } 2575 2576 return 0; 2577 2578 failed1: 2579 psp_free_shared_bufs(psp); 2580 failed: 2581 /* 2582 * all cleanup jobs (xgmi terminate, ras terminate, 2583 * ring destroy, cmd/fence/fw buffers destory, 2584 * psp->cmd destory) are delayed to psp_hw_fini 2585 */ 2586 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2587 return ret; 2588 } 2589 2590 static int psp_hw_init(void *handle) 2591 { 2592 int ret; 2593 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2594 2595 mutex_lock(&adev->firmware.mutex); 2596 /* 2597 * This sequence is just used on hw_init only once, no need on 2598 * resume. 2599 */ 2600 ret = amdgpu_ucode_init_bo(adev); 2601 if (ret) 2602 goto failed; 2603 2604 ret = psp_load_fw(adev); 2605 if (ret) { 2606 DRM_ERROR("PSP firmware loading failed\n"); 2607 goto failed; 2608 } 2609 2610 mutex_unlock(&adev->firmware.mutex); 2611 return 0; 2612 2613 failed: 2614 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2615 mutex_unlock(&adev->firmware.mutex); 2616 return -EINVAL; 2617 } 2618 2619 static int psp_hw_fini(void *handle) 2620 { 2621 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2622 struct psp_context *psp = &adev->psp; 2623 2624 if (psp->ta_fw) { 2625 psp_ras_terminate(psp); 2626 psp_securedisplay_terminate(psp); 2627 psp_rap_terminate(psp); 2628 psp_dtm_terminate(psp); 2629 psp_hdcp_terminate(psp); 2630 2631 if (adev->gmc.xgmi.num_physical_nodes > 1) 2632 psp_xgmi_terminate(psp); 2633 } 2634 2635 psp_asd_terminate(psp); 2636 psp_tmr_terminate(psp); 2637 2638 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2639 2640 psp_free_shared_bufs(psp); 2641 2642 return 0; 2643 } 2644 2645 static int psp_suspend(void *handle) 2646 { 2647 int ret = 0; 2648 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2649 struct psp_context *psp = &adev->psp; 2650 2651 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2652 psp->xgmi_context.context.initialized) { 2653 ret = psp_xgmi_terminate(psp); 2654 if (ret) { 2655 DRM_ERROR("Failed to terminate xgmi ta\n"); 2656 goto out; 2657 } 2658 } 2659 2660 if (psp->ta_fw) { 2661 ret = psp_ras_terminate(psp); 2662 if (ret) { 2663 DRM_ERROR("Failed to terminate ras ta\n"); 2664 goto out; 2665 } 2666 ret = psp_hdcp_terminate(psp); 2667 if (ret) { 2668 DRM_ERROR("Failed to terminate hdcp ta\n"); 2669 goto out; 2670 } 2671 ret = psp_dtm_terminate(psp); 2672 if (ret) { 2673 DRM_ERROR("Failed to terminate dtm ta\n"); 2674 goto out; 2675 } 2676 ret = psp_rap_terminate(psp); 2677 if (ret) { 2678 DRM_ERROR("Failed to terminate rap ta\n"); 2679 goto out; 2680 } 2681 ret = psp_securedisplay_terminate(psp); 2682 if (ret) { 2683 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2684 goto out; 2685 } 2686 } 2687 2688 ret = psp_asd_terminate(psp); 2689 if (ret) { 2690 DRM_ERROR("Failed to terminate asd\n"); 2691 goto out; 2692 } 2693 2694 ret = psp_tmr_terminate(psp); 2695 if (ret) { 2696 DRM_ERROR("Failed to terminate tmr\n"); 2697 goto out; 2698 } 2699 2700 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2701 if (ret) { 2702 DRM_ERROR("PSP ring stop failed\n"); 2703 } 2704 2705 out: 2706 psp_free_shared_bufs(psp); 2707 2708 return ret; 2709 } 2710 2711 static int psp_resume(void *handle) 2712 { 2713 int ret; 2714 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2715 struct psp_context *psp = &adev->psp; 2716 2717 DRM_INFO("PSP is resuming...\n"); 2718 2719 if (psp->mem_train_ctx.enable_mem_training) { 2720 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2721 if (ret) { 2722 DRM_ERROR("Failed to process memory training!\n"); 2723 return ret; 2724 } 2725 } 2726 2727 mutex_lock(&adev->firmware.mutex); 2728 2729 ret = psp_hw_start(psp); 2730 if (ret) 2731 goto failed; 2732 2733 ret = psp_load_non_psp_fw(psp); 2734 if (ret) 2735 goto failed; 2736 2737 ret = psp_asd_initialize(psp); 2738 if (ret) { 2739 DRM_ERROR("PSP load asd failed!\n"); 2740 goto failed; 2741 } 2742 2743 ret = psp_rl_load(adev); 2744 if (ret) { 2745 dev_err(adev->dev, "PSP load RL failed!\n"); 2746 goto failed; 2747 } 2748 2749 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2750 ret = psp_xgmi_initialize(psp, false, true); 2751 /* Warning the XGMI seesion initialize failure 2752 * Instead of stop driver initialization 2753 */ 2754 if (ret) 2755 dev_err(psp->adev->dev, 2756 "XGMI: Failed to initialize XGMI session\n"); 2757 } 2758 2759 if (psp->ta_fw) { 2760 ret = psp_ras_initialize(psp); 2761 if (ret) 2762 dev_err(psp->adev->dev, 2763 "RAS: Failed to initialize RAS\n"); 2764 2765 ret = psp_hdcp_initialize(psp); 2766 if (ret) 2767 dev_err(psp->adev->dev, 2768 "HDCP: Failed to initialize HDCP\n"); 2769 2770 ret = psp_dtm_initialize(psp); 2771 if (ret) 2772 dev_err(psp->adev->dev, 2773 "DTM: Failed to initialize DTM\n"); 2774 2775 ret = psp_rap_initialize(psp); 2776 if (ret) 2777 dev_err(psp->adev->dev, 2778 "RAP: Failed to initialize RAP\n"); 2779 2780 ret = psp_securedisplay_initialize(psp); 2781 if (ret) 2782 dev_err(psp->adev->dev, 2783 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2784 } 2785 2786 mutex_unlock(&adev->firmware.mutex); 2787 2788 return 0; 2789 2790 failed: 2791 DRM_ERROR("PSP resume failed\n"); 2792 mutex_unlock(&adev->firmware.mutex); 2793 return ret; 2794 } 2795 2796 int psp_gpu_reset(struct amdgpu_device *adev) 2797 { 2798 int ret; 2799 2800 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2801 return 0; 2802 2803 mutex_lock(&adev->psp.mutex); 2804 ret = psp_mode1_reset(&adev->psp); 2805 mutex_unlock(&adev->psp.mutex); 2806 2807 return ret; 2808 } 2809 2810 int psp_rlc_autoload_start(struct psp_context *psp) 2811 { 2812 int ret; 2813 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2814 2815 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2816 2817 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2818 psp->fence_buf_mc_addr); 2819 2820 release_psp_cmd_buf(psp); 2821 2822 return ret; 2823 } 2824 2825 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2826 uint64_t cmd_gpu_addr, int cmd_size) 2827 { 2828 struct amdgpu_firmware_info ucode = {0}; 2829 2830 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2831 AMDGPU_UCODE_ID_VCN0_RAM; 2832 ucode.mc_addr = cmd_gpu_addr; 2833 ucode.ucode_size = cmd_size; 2834 2835 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2836 } 2837 2838 int psp_ring_cmd_submit(struct psp_context *psp, 2839 uint64_t cmd_buf_mc_addr, 2840 uint64_t fence_mc_addr, 2841 int index) 2842 { 2843 unsigned int psp_write_ptr_reg = 0; 2844 struct psp_gfx_rb_frame *write_frame; 2845 struct psp_ring *ring = &psp->km_ring; 2846 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2847 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2848 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2849 struct amdgpu_device *adev = psp->adev; 2850 uint32_t ring_size_dw = ring->ring_size / 4; 2851 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2852 2853 /* KM (GPCOM) prepare write pointer */ 2854 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2855 2856 /* Update KM RB frame pointer to new frame */ 2857 /* write_frame ptr increments by size of rb_frame in bytes */ 2858 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2859 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2860 write_frame = ring_buffer_start; 2861 else 2862 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2863 /* Check invalid write_frame ptr address */ 2864 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2865 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2866 ring_buffer_start, ring_buffer_end, write_frame); 2867 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2868 return -EINVAL; 2869 } 2870 2871 /* Initialize KM RB frame */ 2872 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2873 2874 /* Update KM RB frame */ 2875 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2876 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2877 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2878 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2879 write_frame->fence_value = index; 2880 amdgpu_device_flush_hdp(adev, NULL); 2881 2882 /* Update the write Pointer in DWORDs */ 2883 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2884 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2885 return 0; 2886 } 2887 2888 int psp_init_asd_microcode(struct psp_context *psp, 2889 const char *chip_name) 2890 { 2891 struct amdgpu_device *adev = psp->adev; 2892 char fw_name[PSP_FW_NAME_LEN]; 2893 const struct psp_firmware_header_v1_0 *asd_hdr; 2894 int err = 0; 2895 2896 if (!chip_name) { 2897 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2898 return -EINVAL; 2899 } 2900 2901 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2902 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2903 if (err) 2904 goto out; 2905 2906 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2907 if (err) 2908 goto out; 2909 2910 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2911 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2912 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2913 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2914 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2915 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2916 return 0; 2917 out: 2918 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2919 release_firmware(adev->psp.asd_fw); 2920 adev->psp.asd_fw = NULL; 2921 return err; 2922 } 2923 2924 int psp_init_toc_microcode(struct psp_context *psp, 2925 const char *chip_name) 2926 { 2927 struct amdgpu_device *adev = psp->adev; 2928 char fw_name[PSP_FW_NAME_LEN]; 2929 const struct psp_firmware_header_v1_0 *toc_hdr; 2930 int err = 0; 2931 2932 if (!chip_name) { 2933 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2934 return -EINVAL; 2935 } 2936 2937 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2938 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2939 if (err) 2940 goto out; 2941 2942 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2943 if (err) 2944 goto out; 2945 2946 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2947 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2948 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2949 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2950 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2951 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2952 return 0; 2953 out: 2954 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2955 release_firmware(adev->psp.toc_fw); 2956 adev->psp.toc_fw = NULL; 2957 return err; 2958 } 2959 2960 static int parse_sos_bin_descriptor(struct psp_context *psp, 2961 const struct psp_fw_bin_desc *desc, 2962 const struct psp_firmware_header_v2_0 *sos_hdr) 2963 { 2964 uint8_t *ucode_start_addr = NULL; 2965 2966 if (!psp || !desc || !sos_hdr) 2967 return -EINVAL; 2968 2969 ucode_start_addr = (uint8_t *)sos_hdr + 2970 le32_to_cpu(desc->offset_bytes) + 2971 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2972 2973 switch (desc->fw_type) { 2974 case PSP_FW_TYPE_PSP_SOS: 2975 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2976 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2977 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2978 psp->sos.start_addr = ucode_start_addr; 2979 break; 2980 case PSP_FW_TYPE_PSP_SYS_DRV: 2981 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2982 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2983 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2984 psp->sys.start_addr = ucode_start_addr; 2985 break; 2986 case PSP_FW_TYPE_PSP_KDB: 2987 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2988 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2989 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2990 psp->kdb.start_addr = ucode_start_addr; 2991 break; 2992 case PSP_FW_TYPE_PSP_TOC: 2993 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2994 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2995 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 2996 psp->toc.start_addr = ucode_start_addr; 2997 break; 2998 case PSP_FW_TYPE_PSP_SPL: 2999 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3000 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3001 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3002 psp->spl.start_addr = ucode_start_addr; 3003 break; 3004 case PSP_FW_TYPE_PSP_RL: 3005 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3006 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3007 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3008 psp->rl.start_addr = ucode_start_addr; 3009 break; 3010 case PSP_FW_TYPE_PSP_SOC_DRV: 3011 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3012 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3013 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3014 psp->soc_drv.start_addr = ucode_start_addr; 3015 break; 3016 case PSP_FW_TYPE_PSP_INTF_DRV: 3017 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3018 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3019 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3020 psp->intf_drv.start_addr = ucode_start_addr; 3021 break; 3022 case PSP_FW_TYPE_PSP_DBG_DRV: 3023 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3024 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3025 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3026 psp->dbg_drv.start_addr = ucode_start_addr; 3027 break; 3028 case PSP_FW_TYPE_PSP_RAS_DRV: 3029 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3030 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3031 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3032 psp->ras_drv.start_addr = ucode_start_addr; 3033 break; 3034 default: 3035 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3036 break; 3037 } 3038 3039 return 0; 3040 } 3041 3042 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3043 { 3044 const struct psp_firmware_header_v1_0 *sos_hdr; 3045 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3046 uint8_t *ucode_array_start_addr; 3047 3048 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3049 ucode_array_start_addr = (uint8_t *)sos_hdr + 3050 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3051 3052 if (adev->gmc.xgmi.connected_to_cpu || 3053 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3054 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3055 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3056 3057 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3058 adev->psp.sys.start_addr = ucode_array_start_addr; 3059 3060 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3061 adev->psp.sos.start_addr = ucode_array_start_addr + 3062 le32_to_cpu(sos_hdr->sos.offset_bytes); 3063 } else { 3064 /* Load alternate PSP SOS FW */ 3065 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3066 3067 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3068 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3069 3070 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3071 adev->psp.sys.start_addr = ucode_array_start_addr + 3072 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3073 3074 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3075 adev->psp.sos.start_addr = ucode_array_start_addr + 3076 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3077 } 3078 3079 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3080 dev_warn(adev->dev, "PSP SOS FW not available"); 3081 return -EINVAL; 3082 } 3083 3084 return 0; 3085 } 3086 3087 int psp_init_sos_microcode(struct psp_context *psp, 3088 const char *chip_name) 3089 { 3090 struct amdgpu_device *adev = psp->adev; 3091 char fw_name[PSP_FW_NAME_LEN]; 3092 const struct psp_firmware_header_v1_0 *sos_hdr; 3093 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3094 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3095 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3096 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3097 int err = 0; 3098 uint8_t *ucode_array_start_addr; 3099 int fw_index = 0; 3100 3101 if (!chip_name) { 3102 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3103 return -EINVAL; 3104 } 3105 3106 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3107 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3108 if (err) 3109 goto out; 3110 3111 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3112 if (err) 3113 goto out; 3114 3115 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3116 ucode_array_start_addr = (uint8_t *)sos_hdr + 3117 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3118 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3119 3120 switch (sos_hdr->header.header_version_major) { 3121 case 1: 3122 err = psp_init_sos_base_fw(adev); 3123 if (err) 3124 goto out; 3125 3126 if (sos_hdr->header.header_version_minor == 1) { 3127 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3128 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3129 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3130 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3131 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3132 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3133 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3134 } 3135 if (sos_hdr->header.header_version_minor == 2) { 3136 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3137 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3138 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3139 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3140 } 3141 if (sos_hdr->header.header_version_minor == 3) { 3142 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3143 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3144 adev->psp.toc.start_addr = ucode_array_start_addr + 3145 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3146 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3147 adev->psp.kdb.start_addr = ucode_array_start_addr + 3148 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3149 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3150 adev->psp.spl.start_addr = ucode_array_start_addr + 3151 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3152 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3153 adev->psp.rl.start_addr = ucode_array_start_addr + 3154 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3155 } 3156 break; 3157 case 2: 3158 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3159 3160 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3161 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3162 err = -EINVAL; 3163 goto out; 3164 } 3165 3166 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3167 err = parse_sos_bin_descriptor(psp, 3168 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3169 sos_hdr_v2_0); 3170 if (err) 3171 goto out; 3172 } 3173 break; 3174 default: 3175 dev_err(adev->dev, 3176 "unsupported psp sos firmware\n"); 3177 err = -EINVAL; 3178 goto out; 3179 } 3180 3181 return 0; 3182 out: 3183 dev_err(adev->dev, 3184 "failed to init sos firmware\n"); 3185 release_firmware(adev->psp.sos_fw); 3186 adev->psp.sos_fw = NULL; 3187 3188 return err; 3189 } 3190 3191 static int parse_ta_bin_descriptor(struct psp_context *psp, 3192 const struct psp_fw_bin_desc *desc, 3193 const struct ta_firmware_header_v2_0 *ta_hdr) 3194 { 3195 uint8_t *ucode_start_addr = NULL; 3196 3197 if (!psp || !desc || !ta_hdr) 3198 return -EINVAL; 3199 3200 ucode_start_addr = (uint8_t *)ta_hdr + 3201 le32_to_cpu(desc->offset_bytes) + 3202 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3203 3204 switch (desc->fw_type) { 3205 case TA_FW_TYPE_PSP_ASD: 3206 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3207 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3208 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3209 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3210 break; 3211 case TA_FW_TYPE_PSP_XGMI: 3212 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3213 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3214 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3215 break; 3216 case TA_FW_TYPE_PSP_RAS: 3217 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3218 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3219 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3220 break; 3221 case TA_FW_TYPE_PSP_HDCP: 3222 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3223 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3224 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3225 break; 3226 case TA_FW_TYPE_PSP_DTM: 3227 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3228 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3229 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3230 break; 3231 case TA_FW_TYPE_PSP_RAP: 3232 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3233 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3234 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3235 break; 3236 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3237 psp->securedisplay_context.context.bin_desc.fw_version = 3238 le32_to_cpu(desc->fw_version); 3239 psp->securedisplay_context.context.bin_desc.size_bytes = 3240 le32_to_cpu(desc->size_bytes); 3241 psp->securedisplay_context.context.bin_desc.start_addr = 3242 ucode_start_addr; 3243 break; 3244 default: 3245 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3246 break; 3247 } 3248 3249 return 0; 3250 } 3251 3252 int psp_init_ta_microcode(struct psp_context *psp, 3253 const char *chip_name) 3254 { 3255 struct amdgpu_device *adev = psp->adev; 3256 char fw_name[PSP_FW_NAME_LEN]; 3257 const struct ta_firmware_header_v2_0 *ta_hdr; 3258 int err = 0; 3259 int ta_index = 0; 3260 3261 if (!chip_name) { 3262 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3263 return -EINVAL; 3264 } 3265 3266 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3267 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3268 if (err) 3269 goto out; 3270 3271 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3272 if (err) 3273 goto out; 3274 3275 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3276 3277 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3278 dev_err(adev->dev, "unsupported TA header version\n"); 3279 err = -EINVAL; 3280 goto out; 3281 } 3282 3283 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3284 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3285 err = -EINVAL; 3286 goto out; 3287 } 3288 3289 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3290 err = parse_ta_bin_descriptor(psp, 3291 &ta_hdr->ta_fw_bin[ta_index], 3292 ta_hdr); 3293 if (err) 3294 goto out; 3295 } 3296 3297 return 0; 3298 out: 3299 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3300 release_firmware(adev->psp.ta_fw); 3301 adev->psp.ta_fw = NULL; 3302 return err; 3303 } 3304 3305 int psp_init_cap_microcode(struct psp_context *psp, 3306 const char *chip_name) 3307 { 3308 struct amdgpu_device *adev = psp->adev; 3309 char fw_name[PSP_FW_NAME_LEN]; 3310 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3311 struct amdgpu_firmware_info *info = NULL; 3312 int err = 0; 3313 3314 if (!chip_name) { 3315 dev_err(adev->dev, "invalid chip name for cap microcode\n"); 3316 return -EINVAL; 3317 } 3318 3319 if (!amdgpu_sriov_vf(adev)) { 3320 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3321 return -EINVAL; 3322 } 3323 3324 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3325 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev); 3326 if (err) { 3327 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3328 err = 0; 3329 goto out; 3330 } 3331 3332 err = amdgpu_ucode_validate(adev->psp.cap_fw); 3333 if (err) { 3334 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3335 goto out; 3336 } 3337 3338 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3339 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3340 info->fw = adev->psp.cap_fw; 3341 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3342 adev->psp.cap_fw->data; 3343 adev->firmware.fw_size += ALIGN( 3344 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3345 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3346 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3347 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3348 3349 return 0; 3350 3351 out: 3352 release_firmware(adev->psp.cap_fw); 3353 adev->psp.cap_fw = NULL; 3354 return err; 3355 } 3356 3357 static int psp_set_clockgating_state(void *handle, 3358 enum amd_clockgating_state state) 3359 { 3360 return 0; 3361 } 3362 3363 static int psp_set_powergating_state(void *handle, 3364 enum amd_powergating_state state) 3365 { 3366 return 0; 3367 } 3368 3369 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3370 struct device_attribute *attr, 3371 char *buf) 3372 { 3373 struct drm_device *ddev = dev_get_drvdata(dev); 3374 struct amdgpu_device *adev = drm_to_adev(ddev); 3375 uint32_t fw_ver; 3376 int ret; 3377 3378 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3379 DRM_INFO("PSP block is not ready yet."); 3380 return -EBUSY; 3381 } 3382 3383 mutex_lock(&adev->psp.mutex); 3384 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3385 mutex_unlock(&adev->psp.mutex); 3386 3387 if (ret) { 3388 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3389 return ret; 3390 } 3391 3392 return sysfs_emit(buf, "%x\n", fw_ver); 3393 } 3394 3395 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3396 struct device_attribute *attr, 3397 const char *buf, 3398 size_t count) 3399 { 3400 struct drm_device *ddev = dev_get_drvdata(dev); 3401 struct amdgpu_device *adev = drm_to_adev(ddev); 3402 int ret, idx; 3403 char fw_name[100]; 3404 const struct firmware *usbc_pd_fw; 3405 struct amdgpu_bo *fw_buf_bo = NULL; 3406 uint64_t fw_pri_mc_addr; 3407 void *fw_pri_cpu_addr; 3408 3409 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3410 DRM_INFO("PSP block is not ready yet."); 3411 return -EBUSY; 3412 } 3413 3414 if (!drm_dev_enter(ddev, &idx)) 3415 return -ENODEV; 3416 3417 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3418 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3419 if (ret) 3420 goto fail; 3421 3422 /* LFB address which is aligned to 1MB boundary per PSP request */ 3423 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3424 AMDGPU_GEM_DOMAIN_VRAM, 3425 &fw_buf_bo, 3426 &fw_pri_mc_addr, 3427 &fw_pri_cpu_addr); 3428 if (ret) 3429 goto rel_buf; 3430 3431 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3432 3433 mutex_lock(&adev->psp.mutex); 3434 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3435 mutex_unlock(&adev->psp.mutex); 3436 3437 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3438 3439 rel_buf: 3440 release_firmware(usbc_pd_fw); 3441 fail: 3442 if (ret) { 3443 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3444 count = ret; 3445 } 3446 3447 drm_dev_exit(idx); 3448 return count; 3449 } 3450 3451 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3452 { 3453 int idx; 3454 3455 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3456 return; 3457 3458 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3459 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3460 3461 drm_dev_exit(idx); 3462 } 3463 3464 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3465 psp_usbc_pd_fw_sysfs_read, 3466 psp_usbc_pd_fw_sysfs_write); 3467 3468 int is_psp_fw_valid(struct psp_bin_desc bin) 3469 { 3470 return bin.size_bytes; 3471 } 3472 3473 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3474 struct bin_attribute *bin_attr, 3475 char *buffer, loff_t pos, size_t count) 3476 { 3477 struct device *dev = kobj_to_dev(kobj); 3478 struct drm_device *ddev = dev_get_drvdata(dev); 3479 struct amdgpu_device *adev = drm_to_adev(ddev); 3480 3481 adev->psp.vbflash_done = false; 3482 3483 /* Safeguard against memory drain */ 3484 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3485 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3486 kvfree(adev->psp.vbflash_tmp_buf); 3487 adev->psp.vbflash_tmp_buf = NULL; 3488 adev->psp.vbflash_image_size = 0; 3489 return -ENOMEM; 3490 } 3491 3492 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3493 if (!adev->psp.vbflash_tmp_buf) { 3494 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3495 if (!adev->psp.vbflash_tmp_buf) 3496 return -ENOMEM; 3497 } 3498 3499 mutex_lock(&adev->psp.mutex); 3500 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3501 adev->psp.vbflash_image_size += count; 3502 mutex_unlock(&adev->psp.mutex); 3503 3504 dev_info(adev->dev, "VBIOS flash write PSP done"); 3505 3506 return count; 3507 } 3508 3509 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3510 struct bin_attribute *bin_attr, char *buffer, 3511 loff_t pos, size_t count) 3512 { 3513 struct device *dev = kobj_to_dev(kobj); 3514 struct drm_device *ddev = dev_get_drvdata(dev); 3515 struct amdgpu_device *adev = drm_to_adev(ddev); 3516 struct amdgpu_bo *fw_buf_bo = NULL; 3517 uint64_t fw_pri_mc_addr; 3518 void *fw_pri_cpu_addr; 3519 int ret; 3520 3521 dev_info(adev->dev, "VBIOS flash to PSP started"); 3522 3523 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3524 AMDGPU_GPU_PAGE_SIZE, 3525 AMDGPU_GEM_DOMAIN_VRAM, 3526 &fw_buf_bo, 3527 &fw_pri_mc_addr, 3528 &fw_pri_cpu_addr); 3529 if (ret) 3530 goto rel_buf; 3531 3532 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3533 3534 mutex_lock(&adev->psp.mutex); 3535 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3536 mutex_unlock(&adev->psp.mutex); 3537 3538 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3539 3540 rel_buf: 3541 kvfree(adev->psp.vbflash_tmp_buf); 3542 adev->psp.vbflash_tmp_buf = NULL; 3543 adev->psp.vbflash_image_size = 0; 3544 3545 if (ret) { 3546 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret); 3547 return ret; 3548 } 3549 3550 dev_info(adev->dev, "VBIOS flash to PSP done"); 3551 return 0; 3552 } 3553 3554 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3555 struct device_attribute *attr, 3556 char *buf) 3557 { 3558 struct drm_device *ddev = dev_get_drvdata(dev); 3559 struct amdgpu_device *adev = drm_to_adev(ddev); 3560 uint32_t vbflash_status; 3561 3562 vbflash_status = psp_vbflash_status(&adev->psp); 3563 if (!adev->psp.vbflash_done) 3564 vbflash_status = 0; 3565 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3566 vbflash_status = 1; 3567 3568 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3569 } 3570 3571 static const struct bin_attribute psp_vbflash_bin_attr = { 3572 .attr = {.name = "psp_vbflash", .mode = 0664}, 3573 .size = 0, 3574 .write = amdgpu_psp_vbflash_write, 3575 .read = amdgpu_psp_vbflash_read, 3576 }; 3577 3578 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL); 3579 3580 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev) 3581 { 3582 int ret = 0; 3583 struct psp_context *psp = &adev->psp; 3584 3585 if (amdgpu_sriov_vf(adev)) 3586 return -EINVAL; 3587 3588 switch (adev->ip_versions[MP0_HWIP][0]) { 3589 case IP_VERSION(13, 0, 0): 3590 case IP_VERSION(13, 0, 7): 3591 if (!psp->adev) { 3592 psp->adev = adev; 3593 psp_v13_0_set_psp_funcs(psp); 3594 } 3595 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3596 if (ret) 3597 dev_err(adev->dev, "Failed to create device file psp_vbflash"); 3598 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status); 3599 if (ret) 3600 dev_err(adev->dev, "Failed to create device file psp_vbflash_status"); 3601 return ret; 3602 default: 3603 return 0; 3604 } 3605 } 3606 3607 const struct amd_ip_funcs psp_ip_funcs = { 3608 .name = "psp", 3609 .early_init = psp_early_init, 3610 .late_init = NULL, 3611 .sw_init = psp_sw_init, 3612 .sw_fini = psp_sw_fini, 3613 .hw_init = psp_hw_init, 3614 .hw_fini = psp_hw_fini, 3615 .suspend = psp_suspend, 3616 .resume = psp_resume, 3617 .is_idle = NULL, 3618 .check_soft_reset = NULL, 3619 .wait_for_idle = NULL, 3620 .soft_reset = NULL, 3621 .set_clockgating_state = psp_set_clockgating_state, 3622 .set_powergating_state = psp_set_powergating_state, 3623 }; 3624 3625 static int psp_sysfs_init(struct amdgpu_device *adev) 3626 { 3627 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3628 3629 if (ret) 3630 DRM_ERROR("Failed to create USBC PD FW control file!"); 3631 3632 return ret; 3633 } 3634 3635 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev) 3636 { 3637 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3638 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status); 3639 } 3640 3641 static void psp_sysfs_fini(struct amdgpu_device *adev) 3642 { 3643 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3644 } 3645 3646 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3647 { 3648 .type = AMD_IP_BLOCK_TYPE_PSP, 3649 .major = 3, 3650 .minor = 1, 3651 .rev = 0, 3652 .funcs = &psp_ip_funcs, 3653 }; 3654 3655 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3656 { 3657 .type = AMD_IP_BLOCK_TYPE_PSP, 3658 .major = 10, 3659 .minor = 0, 3660 .rev = 0, 3661 .funcs = &psp_ip_funcs, 3662 }; 3663 3664 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3665 { 3666 .type = AMD_IP_BLOCK_TYPE_PSP, 3667 .major = 11, 3668 .minor = 0, 3669 .rev = 0, 3670 .funcs = &psp_ip_funcs, 3671 }; 3672 3673 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3674 .type = AMD_IP_BLOCK_TYPE_PSP, 3675 .major = 11, 3676 .minor = 0, 3677 .rev = 8, 3678 .funcs = &psp_ip_funcs, 3679 }; 3680 3681 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3682 { 3683 .type = AMD_IP_BLOCK_TYPE_PSP, 3684 .major = 12, 3685 .minor = 0, 3686 .rev = 0, 3687 .funcs = &psp_ip_funcs, 3688 }; 3689 3690 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3691 .type = AMD_IP_BLOCK_TYPE_PSP, 3692 .major = 13, 3693 .minor = 0, 3694 .rev = 0, 3695 .funcs = &psp_ip_funcs, 3696 }; 3697 3698 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3699 .type = AMD_IP_BLOCK_TYPE_PSP, 3700 .major = 13, 3701 .minor = 0, 3702 .rev = 4, 3703 .funcs = &psp_ip_funcs, 3704 }; 3705