1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 42 #include "amdgpu_ras.h" 43 #include "amdgpu_securedisplay.h" 44 #include "amdgpu_atomfirmware.h" 45 46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 47 48 static int psp_sysfs_init(struct amdgpu_device *adev); 49 static void psp_sysfs_fini(struct amdgpu_device *adev); 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 static int psp_ring_init(struct psp_context *psp, 56 enum psp_ring_type ring_type) 57 { 58 int ret = 0; 59 struct psp_ring *ring; 60 struct amdgpu_device *adev = psp->adev; 61 62 ring = &psp->km_ring; 63 64 ring->ring_type = ring_type; 65 66 /* allocate 4k Page of Local Frame Buffer memory for ring */ 67 ring->ring_size = 0x1000; 68 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 69 AMDGPU_GEM_DOMAIN_VRAM, 70 &adev->firmware.rbuf, 71 &ring->ring_mem_mc_addr, 72 (void **)&ring->ring_mem); 73 if (ret) { 74 ring->ring_size = 0; 75 return ret; 76 } 77 78 return 0; 79 } 80 81 /* 82 * Due to DF Cstate management centralized to PMFW, the firmware 83 * loading sequence will be updated as below: 84 * - Load KDB 85 * - Load SYS_DRV 86 * - Load tOS 87 * - Load PMFW 88 * - Setup TMR 89 * - Load other non-psp fw 90 * - Load ASD 91 * - Load XGMI/RAS/HDCP/DTM TA if any 92 * 93 * This new sequence is required for 94 * - Arcturus and onwards 95 */ 96 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 97 { 98 struct amdgpu_device *adev = psp->adev; 99 100 if (amdgpu_sriov_vf(adev)) { 101 psp->pmfw_centralized_cstate_management = false; 102 return; 103 } 104 105 switch (adev->ip_versions[MP0_HWIP][0]) { 106 case IP_VERSION(11, 0, 0): 107 case IP_VERSION(11, 0, 4): 108 case IP_VERSION(11, 0, 5): 109 case IP_VERSION(11, 0, 7): 110 case IP_VERSION(11, 0, 9): 111 case IP_VERSION(11, 0, 11): 112 case IP_VERSION(11, 0, 12): 113 case IP_VERSION(11, 0, 13): 114 case IP_VERSION(13, 0, 0): 115 case IP_VERSION(13, 0, 2): 116 case IP_VERSION(13, 0, 7): 117 psp->pmfw_centralized_cstate_management = true; 118 break; 119 default: 120 psp->pmfw_centralized_cstate_management = false; 121 break; 122 } 123 } 124 125 static int psp_early_init(void *handle) 126 { 127 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 128 struct psp_context *psp = &adev->psp; 129 130 switch (adev->ip_versions[MP0_HWIP][0]) { 131 case IP_VERSION(9, 0, 0): 132 psp_v3_1_set_psp_funcs(psp); 133 psp->autoload_supported = false; 134 break; 135 case IP_VERSION(10, 0, 0): 136 case IP_VERSION(10, 0, 1): 137 psp_v10_0_set_psp_funcs(psp); 138 psp->autoload_supported = false; 139 break; 140 case IP_VERSION(11, 0, 2): 141 case IP_VERSION(11, 0, 4): 142 psp_v11_0_set_psp_funcs(psp); 143 psp->autoload_supported = false; 144 break; 145 case IP_VERSION(11, 0, 0): 146 case IP_VERSION(11, 0, 5): 147 case IP_VERSION(11, 0, 9): 148 case IP_VERSION(11, 0, 7): 149 case IP_VERSION(11, 0, 11): 150 case IP_VERSION(11, 5, 0): 151 case IP_VERSION(11, 0, 12): 152 case IP_VERSION(11, 0, 13): 153 psp_v11_0_set_psp_funcs(psp); 154 psp->autoload_supported = true; 155 break; 156 case IP_VERSION(11, 0, 3): 157 case IP_VERSION(12, 0, 1): 158 psp_v12_0_set_psp_funcs(psp); 159 break; 160 case IP_VERSION(13, 0, 2): 161 psp_v13_0_set_psp_funcs(psp); 162 break; 163 case IP_VERSION(13, 0, 1): 164 case IP_VERSION(13, 0, 3): 165 case IP_VERSION(13, 0, 5): 166 case IP_VERSION(13, 0, 8): 167 case IP_VERSION(13, 0, 10): 168 psp_v13_0_set_psp_funcs(psp); 169 psp->autoload_supported = true; 170 break; 171 case IP_VERSION(11, 0, 8): 172 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 173 psp_v11_0_8_set_psp_funcs(psp); 174 psp->autoload_supported = false; 175 } 176 break; 177 case IP_VERSION(13, 0, 0): 178 case IP_VERSION(13, 0, 7): 179 psp_v13_0_set_psp_funcs(psp); 180 psp->autoload_supported = true; 181 break; 182 case IP_VERSION(13, 0, 4): 183 psp_v13_0_4_set_psp_funcs(psp); 184 psp->autoload_supported = true; 185 break; 186 default: 187 return -EINVAL; 188 } 189 190 psp->adev = adev; 191 192 psp_check_pmfw_centralized_cstate_management(psp); 193 194 return 0; 195 } 196 197 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 198 { 199 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 200 &mem_ctx->shared_buf); 201 mem_ctx->shared_bo = NULL; 202 } 203 204 static void psp_free_shared_bufs(struct psp_context *psp) 205 { 206 void *tmr_buf; 207 void **pptr; 208 209 /* free TMR memory buffer */ 210 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 211 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 212 psp->tmr_bo = NULL; 213 214 /* free xgmi shared memory */ 215 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 216 217 /* free ras shared memory */ 218 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 219 220 /* free hdcp shared memory */ 221 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 222 223 /* free dtm shared memory */ 224 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 225 226 /* free rap shared memory */ 227 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 228 229 /* free securedisplay shared memory */ 230 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 231 232 233 } 234 235 static void psp_memory_training_fini(struct psp_context *psp) 236 { 237 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 238 239 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 240 kfree(ctx->sys_cache); 241 ctx->sys_cache = NULL; 242 } 243 244 static int psp_memory_training_init(struct psp_context *psp) 245 { 246 int ret; 247 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 248 249 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 250 DRM_DEBUG("memory training is not supported!\n"); 251 return 0; 252 } 253 254 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 255 if (ctx->sys_cache == NULL) { 256 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 257 ret = -ENOMEM; 258 goto Err_out; 259 } 260 261 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 262 ctx->train_data_size, 263 ctx->p2c_train_data_offset, 264 ctx->c2p_train_data_offset); 265 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 266 return 0; 267 268 Err_out: 269 psp_memory_training_fini(psp); 270 return ret; 271 } 272 273 /* 274 * Helper funciton to query psp runtime database entry 275 * 276 * @adev: amdgpu_device pointer 277 * @entry_type: the type of psp runtime database entry 278 * @db_entry: runtime database entry pointer 279 * 280 * Return false if runtime database doesn't exit or entry is invalid 281 * or true if the specific database entry is found, and copy to @db_entry 282 */ 283 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 284 enum psp_runtime_entry_type entry_type, 285 void *db_entry) 286 { 287 uint64_t db_header_pos, db_dir_pos; 288 struct psp_runtime_data_header db_header = {0}; 289 struct psp_runtime_data_directory db_dir = {0}; 290 bool ret = false; 291 int i; 292 293 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 294 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 295 296 /* read runtime db header from vram */ 297 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 298 sizeof(struct psp_runtime_data_header), false); 299 300 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 301 /* runtime db doesn't exist, exit */ 302 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 303 return false; 304 } 305 306 /* read runtime database entry from vram */ 307 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 308 sizeof(struct psp_runtime_data_directory), false); 309 310 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 311 /* invalid db entry count, exit */ 312 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 313 return false; 314 } 315 316 /* look up for requested entry type */ 317 for (i = 0; i < db_dir.entry_count && !ret; i++) { 318 if (db_dir.entry_list[i].entry_type == entry_type) { 319 switch (entry_type) { 320 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 321 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 322 /* invalid db entry size */ 323 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 324 return false; 325 } 326 /* read runtime database entry */ 327 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 328 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 329 ret = true; 330 break; 331 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 332 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 333 /* invalid db entry size */ 334 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 335 return false; 336 } 337 /* read runtime database entry */ 338 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 339 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 340 ret = true; 341 break; 342 default: 343 ret = false; 344 break; 345 } 346 } 347 } 348 349 return ret; 350 } 351 352 static int psp_init_sriov_microcode(struct psp_context *psp) 353 { 354 struct amdgpu_device *adev = psp->adev; 355 int ret = 0; 356 357 switch (adev->ip_versions[MP0_HWIP][0]) { 358 case IP_VERSION(9, 0, 0): 359 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 360 ret = psp_init_cap_microcode(psp, "vega10"); 361 break; 362 case IP_VERSION(11, 0, 9): 363 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 364 ret = psp_init_cap_microcode(psp, "navi12"); 365 break; 366 case IP_VERSION(11, 0, 7): 367 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 368 ret = psp_init_cap_microcode(psp, "sienna_cichlid"); 369 break; 370 case IP_VERSION(13, 0, 2): 371 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 372 ret = psp_init_cap_microcode(psp, "aldebaran"); 373 ret &= psp_init_ta_microcode(psp, "aldebaran"); 374 break; 375 case IP_VERSION(13, 0, 0): 376 adev->virt.autoload_ucode_id = 0; 377 break; 378 case IP_VERSION(13, 0, 10): 379 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 380 break; 381 default: 382 BUG(); 383 break; 384 } 385 return ret; 386 } 387 388 static int psp_sw_init(void *handle) 389 { 390 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 391 struct psp_context *psp = &adev->psp; 392 int ret; 393 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 394 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 395 struct psp_runtime_scpm_entry scpm_entry; 396 397 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 398 if (!psp->cmd) { 399 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 400 ret = -ENOMEM; 401 } 402 403 if (amdgpu_sriov_vf(adev)) 404 ret = psp_init_sriov_microcode(psp); 405 else 406 ret = psp_init_microcode(psp); 407 if (ret) { 408 DRM_ERROR("Failed to load psp firmware!\n"); 409 return ret; 410 } 411 412 adev->psp.xgmi_context.supports_extended_data = 413 !adev->gmc.xgmi.connected_to_cpu && 414 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 415 416 memset(&scpm_entry, 0, sizeof(scpm_entry)); 417 if ((psp_get_runtime_db_entry(adev, 418 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 419 &scpm_entry)) && 420 (SCPM_DISABLE != scpm_entry.scpm_status)) { 421 adev->scpm_enabled = true; 422 adev->scpm_status = scpm_entry.scpm_status; 423 } else { 424 adev->scpm_enabled = false; 425 adev->scpm_status = SCPM_DISABLE; 426 } 427 428 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 429 430 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 431 if (psp_get_runtime_db_entry(adev, 432 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 433 &boot_cfg_entry)) { 434 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 435 if ((psp->boot_cfg_bitmask) & 436 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 437 /* If psp runtime database exists, then 438 * only enable two stage memory training 439 * when TWO_STAGE_DRAM_TRAINING bit is set 440 * in runtime database */ 441 mem_training_ctx->enable_mem_training = true; 442 } 443 444 } else { 445 /* If psp runtime database doesn't exist or 446 * is invalid, force enable two stage memory 447 * training */ 448 mem_training_ctx->enable_mem_training = true; 449 } 450 451 if (mem_training_ctx->enable_mem_training) { 452 ret = psp_memory_training_init(psp); 453 if (ret) { 454 DRM_ERROR("Failed to initialize memory training!\n"); 455 return ret; 456 } 457 458 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 459 if (ret) { 460 DRM_ERROR("Failed to process memory training!\n"); 461 return ret; 462 } 463 } 464 465 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 466 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 467 ret= psp_sysfs_init(adev); 468 if (ret) { 469 return ret; 470 } 471 } 472 473 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 474 amdgpu_sriov_vf(adev) ? 475 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 476 &psp->fw_pri_bo, 477 &psp->fw_pri_mc_addr, 478 &psp->fw_pri_buf); 479 if (ret) 480 return ret; 481 482 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 483 AMDGPU_GEM_DOMAIN_VRAM, 484 &psp->fence_buf_bo, 485 &psp->fence_buf_mc_addr, 486 &psp->fence_buf); 487 if (ret) 488 goto failed1; 489 490 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 491 AMDGPU_GEM_DOMAIN_VRAM, 492 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 493 (void **)&psp->cmd_buf_mem); 494 if (ret) 495 goto failed2; 496 497 return 0; 498 499 failed2: 500 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 501 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 502 failed1: 503 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 504 &psp->fence_buf_mc_addr, &psp->fence_buf); 505 return ret; 506 } 507 508 static int psp_sw_fini(void *handle) 509 { 510 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 511 struct psp_context *psp = &adev->psp; 512 struct psp_gfx_cmd_resp *cmd = psp->cmd; 513 514 psp_memory_training_fini(psp); 515 if (psp->sos_fw) { 516 release_firmware(psp->sos_fw); 517 psp->sos_fw = NULL; 518 } 519 if (psp->asd_fw) { 520 release_firmware(psp->asd_fw); 521 psp->asd_fw = NULL; 522 } 523 if (psp->ta_fw) { 524 release_firmware(psp->ta_fw); 525 psp->ta_fw = NULL; 526 } 527 if (psp->cap_fw) { 528 release_firmware(psp->cap_fw); 529 psp->cap_fw = NULL; 530 } 531 if (psp->toc_fw) { 532 release_firmware(psp->toc_fw); 533 psp->toc_fw = NULL; 534 } 535 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 536 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 537 psp_sysfs_fini(adev); 538 539 kfree(cmd); 540 cmd = NULL; 541 542 if (psp->km_ring.ring_mem) 543 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 544 &psp->km_ring.ring_mem_mc_addr, 545 (void **)&psp->km_ring.ring_mem); 546 547 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 548 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 549 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 550 &psp->fence_buf_mc_addr, &psp->fence_buf); 551 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 552 (void **)&psp->cmd_buf_mem); 553 554 return 0; 555 } 556 557 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 558 uint32_t reg_val, uint32_t mask, bool check_changed) 559 { 560 uint32_t val; 561 int i; 562 struct amdgpu_device *adev = psp->adev; 563 564 if (psp->adev->no_hw_access) 565 return 0; 566 567 for (i = 0; i < adev->usec_timeout; i++) { 568 val = RREG32(reg_index); 569 if (check_changed) { 570 if (val != reg_val) 571 return 0; 572 } else { 573 if ((val & mask) == reg_val) 574 return 0; 575 } 576 udelay(1); 577 } 578 579 return -ETIME; 580 } 581 582 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 583 { 584 switch (cmd_id) { 585 case GFX_CMD_ID_LOAD_TA: 586 return "LOAD_TA"; 587 case GFX_CMD_ID_UNLOAD_TA: 588 return "UNLOAD_TA"; 589 case GFX_CMD_ID_INVOKE_CMD: 590 return "INVOKE_CMD"; 591 case GFX_CMD_ID_LOAD_ASD: 592 return "LOAD_ASD"; 593 case GFX_CMD_ID_SETUP_TMR: 594 return "SETUP_TMR"; 595 case GFX_CMD_ID_LOAD_IP_FW: 596 return "LOAD_IP_FW"; 597 case GFX_CMD_ID_DESTROY_TMR: 598 return "DESTROY_TMR"; 599 case GFX_CMD_ID_SAVE_RESTORE: 600 return "SAVE_RESTORE_IP_FW"; 601 case GFX_CMD_ID_SETUP_VMR: 602 return "SETUP_VMR"; 603 case GFX_CMD_ID_DESTROY_VMR: 604 return "DESTROY_VMR"; 605 case GFX_CMD_ID_PROG_REG: 606 return "PROG_REG"; 607 case GFX_CMD_ID_GET_FW_ATTESTATION: 608 return "GET_FW_ATTESTATION"; 609 case GFX_CMD_ID_LOAD_TOC: 610 return "ID_LOAD_TOC"; 611 case GFX_CMD_ID_AUTOLOAD_RLC: 612 return "AUTOLOAD_RLC"; 613 case GFX_CMD_ID_BOOT_CFG: 614 return "BOOT_CFG"; 615 default: 616 return "UNKNOWN CMD"; 617 } 618 } 619 620 static int 621 psp_cmd_submit_buf(struct psp_context *psp, 622 struct amdgpu_firmware_info *ucode, 623 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 624 { 625 int ret; 626 int index, idx; 627 int timeout = 20000; 628 bool ras_intr = false; 629 bool skip_unsupport = false; 630 631 if (psp->adev->no_hw_access) 632 return 0; 633 634 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 635 return 0; 636 637 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 638 639 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 640 641 index = atomic_inc_return(&psp->fence_value); 642 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 643 if (ret) { 644 atomic_dec(&psp->fence_value); 645 goto exit; 646 } 647 648 amdgpu_device_invalidate_hdp(psp->adev, NULL); 649 while (*((unsigned int *)psp->fence_buf) != index) { 650 if (--timeout == 0) 651 break; 652 /* 653 * Shouldn't wait for timeout when err_event_athub occurs, 654 * because gpu reset thread triggered and lock resource should 655 * be released for psp resume sequence. 656 */ 657 ras_intr = amdgpu_ras_intr_triggered(); 658 if (ras_intr) 659 break; 660 usleep_range(10, 100); 661 amdgpu_device_invalidate_hdp(psp->adev, NULL); 662 } 663 664 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 665 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 666 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 667 668 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 669 670 /* In some cases, psp response status is not 0 even there is no 671 * problem while the command is submitted. Some version of PSP FW 672 * doesn't write 0 to that field. 673 * So here we would like to only print a warning instead of an error 674 * during psp initialization to avoid breaking hw_init and it doesn't 675 * return -EINVAL. 676 */ 677 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 678 if (ucode) 679 DRM_WARN("failed to load ucode %s(0x%X) ", 680 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 681 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 682 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 683 psp->cmd_buf_mem->resp.status); 684 /* If any firmware (including CAP) load fails under SRIOV, it should 685 * return failure to stop the VF from initializing. 686 * Also return failure in case of timeout 687 */ 688 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 689 ret = -EINVAL; 690 goto exit; 691 } 692 } 693 694 if (ucode) { 695 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 696 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 697 } 698 699 exit: 700 drm_dev_exit(idx); 701 return ret; 702 } 703 704 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 705 { 706 struct psp_gfx_cmd_resp *cmd = psp->cmd; 707 708 mutex_lock(&psp->mutex); 709 710 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 711 712 return cmd; 713 } 714 715 static void release_psp_cmd_buf(struct psp_context *psp) 716 { 717 mutex_unlock(&psp->mutex); 718 } 719 720 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 721 struct psp_gfx_cmd_resp *cmd, 722 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 723 { 724 struct amdgpu_device *adev = psp->adev; 725 uint32_t size = amdgpu_bo_size(tmr_bo); 726 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 727 728 if (amdgpu_sriov_vf(psp->adev)) 729 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 730 else 731 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 732 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 733 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 734 cmd->cmd.cmd_setup_tmr.buf_size = size; 735 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 736 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 737 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 738 } 739 740 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 741 uint64_t pri_buf_mc, uint32_t size) 742 { 743 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 744 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 745 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 746 cmd->cmd.cmd_load_toc.toc_size = size; 747 } 748 749 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 750 static int psp_load_toc(struct psp_context *psp, 751 uint32_t *tmr_size) 752 { 753 int ret; 754 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 755 756 /* Copy toc to psp firmware private buffer */ 757 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 758 759 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 760 761 ret = psp_cmd_submit_buf(psp, NULL, cmd, 762 psp->fence_buf_mc_addr); 763 if (!ret) 764 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 765 766 release_psp_cmd_buf(psp); 767 768 return ret; 769 } 770 771 /* Set up Trusted Memory Region */ 772 static int psp_tmr_init(struct psp_context *psp) 773 { 774 int ret = 0; 775 int tmr_size; 776 void *tmr_buf; 777 void **pptr; 778 779 /* 780 * According to HW engineer, they prefer the TMR address be "naturally 781 * aligned" , e.g. the start address be an integer divide of TMR size. 782 * 783 * Note: this memory need be reserved till the driver 784 * uninitializes. 785 */ 786 tmr_size = PSP_TMR_SIZE(psp->adev); 787 788 /* For ASICs support RLC autoload, psp will parse the toc 789 * and calculate the total size of TMR needed */ 790 if (!amdgpu_sriov_vf(psp->adev) && 791 psp->toc.start_addr && 792 psp->toc.size_bytes && 793 psp->fw_pri_buf) { 794 ret = psp_load_toc(psp, &tmr_size); 795 if (ret) { 796 DRM_ERROR("Failed to load toc\n"); 797 return ret; 798 } 799 } 800 801 if (!psp->tmr_bo) { 802 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 803 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT, 804 AMDGPU_GEM_DOMAIN_VRAM, 805 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 806 } 807 808 return ret; 809 } 810 811 static bool psp_skip_tmr(struct psp_context *psp) 812 { 813 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 814 case IP_VERSION(11, 0, 9): 815 case IP_VERSION(11, 0, 7): 816 case IP_VERSION(13, 0, 2): 817 case IP_VERSION(13, 0, 10): 818 return true; 819 default: 820 return false; 821 } 822 } 823 824 static int psp_tmr_load(struct psp_context *psp) 825 { 826 int ret; 827 struct psp_gfx_cmd_resp *cmd; 828 829 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 830 * Already set up by host driver. 831 */ 832 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 833 return 0; 834 835 cmd = acquire_psp_cmd_buf(psp); 836 837 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 838 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 839 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 840 841 ret = psp_cmd_submit_buf(psp, NULL, cmd, 842 psp->fence_buf_mc_addr); 843 844 release_psp_cmd_buf(psp); 845 846 return ret; 847 } 848 849 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 850 struct psp_gfx_cmd_resp *cmd) 851 { 852 if (amdgpu_sriov_vf(psp->adev)) 853 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 854 else 855 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 856 } 857 858 static int psp_tmr_unload(struct psp_context *psp) 859 { 860 int ret; 861 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 862 863 psp_prep_tmr_unload_cmd_buf(psp, cmd); 864 dev_info(psp->adev->dev, "free PSP TMR buffer\n"); 865 866 ret = psp_cmd_submit_buf(psp, NULL, cmd, 867 psp->fence_buf_mc_addr); 868 869 release_psp_cmd_buf(psp); 870 871 return ret; 872 } 873 874 static int psp_tmr_terminate(struct psp_context *psp) 875 { 876 return psp_tmr_unload(psp); 877 } 878 879 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 880 uint64_t *output_ptr) 881 { 882 int ret; 883 struct psp_gfx_cmd_resp *cmd; 884 885 if (!output_ptr) 886 return -EINVAL; 887 888 if (amdgpu_sriov_vf(psp->adev)) 889 return 0; 890 891 cmd = acquire_psp_cmd_buf(psp); 892 893 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 894 895 ret = psp_cmd_submit_buf(psp, NULL, cmd, 896 psp->fence_buf_mc_addr); 897 898 if (!ret) { 899 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 900 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 901 } 902 903 release_psp_cmd_buf(psp); 904 905 return ret; 906 } 907 908 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 909 { 910 struct psp_context *psp = &adev->psp; 911 struct psp_gfx_cmd_resp *cmd; 912 int ret; 913 914 if (amdgpu_sriov_vf(adev)) 915 return 0; 916 917 cmd = acquire_psp_cmd_buf(psp); 918 919 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 920 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 921 922 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 923 if (!ret) { 924 *boot_cfg = 925 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 926 } 927 928 release_psp_cmd_buf(psp); 929 930 return ret; 931 } 932 933 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 934 { 935 int ret; 936 struct psp_context *psp = &adev->psp; 937 struct psp_gfx_cmd_resp *cmd; 938 939 if (amdgpu_sriov_vf(adev)) 940 return 0; 941 942 cmd = acquire_psp_cmd_buf(psp); 943 944 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 945 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 946 cmd->cmd.boot_cfg.boot_config = boot_cfg; 947 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 948 949 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 950 951 release_psp_cmd_buf(psp); 952 953 return ret; 954 } 955 956 static int psp_rl_load(struct amdgpu_device *adev) 957 { 958 int ret; 959 struct psp_context *psp = &adev->psp; 960 struct psp_gfx_cmd_resp *cmd; 961 962 if (!is_psp_fw_valid(psp->rl)) 963 return 0; 964 965 cmd = acquire_psp_cmd_buf(psp); 966 967 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 968 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 969 970 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 971 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 972 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 973 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 974 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 975 976 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 977 978 release_psp_cmd_buf(psp); 979 980 return ret; 981 } 982 983 static int psp_asd_initialize(struct psp_context *psp) 984 { 985 int ret; 986 987 /* If PSP version doesn't match ASD version, asd loading will be failed. 988 * add workaround to bypass it for sriov now. 989 * TODO: add version check to make it common 990 */ 991 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 992 return 0; 993 994 psp->asd_context.mem_context.shared_mc_addr = 0; 995 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 996 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 997 998 ret = psp_ta_load(psp, &psp->asd_context); 999 if (!ret) 1000 psp->asd_context.initialized = true; 1001 1002 return ret; 1003 } 1004 1005 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1006 uint32_t session_id) 1007 { 1008 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1009 cmd->cmd.cmd_unload_ta.session_id = session_id; 1010 } 1011 1012 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1013 { 1014 int ret; 1015 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1016 1017 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1018 1019 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1020 1021 context->resp_status = cmd->resp.status; 1022 1023 release_psp_cmd_buf(psp); 1024 1025 return ret; 1026 } 1027 1028 static int psp_asd_terminate(struct psp_context *psp) 1029 { 1030 int ret; 1031 1032 if (amdgpu_sriov_vf(psp->adev)) 1033 return 0; 1034 1035 if (!psp->asd_context.initialized) 1036 return 0; 1037 1038 ret = psp_ta_unload(psp, &psp->asd_context); 1039 if (!ret) 1040 psp->asd_context.initialized = false; 1041 1042 return ret; 1043 } 1044 1045 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1046 uint32_t id, uint32_t value) 1047 { 1048 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1049 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1050 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1051 } 1052 1053 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1054 uint32_t value) 1055 { 1056 struct psp_gfx_cmd_resp *cmd; 1057 int ret = 0; 1058 1059 if (reg >= PSP_REG_LAST) 1060 return -EINVAL; 1061 1062 cmd = acquire_psp_cmd_buf(psp); 1063 1064 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1065 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1066 if (ret) 1067 DRM_ERROR("PSP failed to program reg id %d", reg); 1068 1069 release_psp_cmd_buf(psp); 1070 1071 return ret; 1072 } 1073 1074 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1075 uint64_t ta_bin_mc, 1076 struct ta_context *context) 1077 { 1078 cmd->cmd_id = context->ta_load_type; 1079 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1080 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1081 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1082 1083 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1084 lower_32_bits(context->mem_context.shared_mc_addr); 1085 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1086 upper_32_bits(context->mem_context.shared_mc_addr); 1087 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1088 } 1089 1090 int psp_ta_init_shared_buf(struct psp_context *psp, 1091 struct ta_mem_context *mem_ctx) 1092 { 1093 /* 1094 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1095 * physical) for ta to host memory 1096 */ 1097 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1098 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1099 &mem_ctx->shared_bo, 1100 &mem_ctx->shared_mc_addr, 1101 &mem_ctx->shared_buf); 1102 } 1103 1104 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1105 uint32_t ta_cmd_id, 1106 uint32_t session_id) 1107 { 1108 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1109 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1110 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1111 } 1112 1113 int psp_ta_invoke(struct psp_context *psp, 1114 uint32_t ta_cmd_id, 1115 struct ta_context *context) 1116 { 1117 int ret; 1118 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1119 1120 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1121 1122 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1123 psp->fence_buf_mc_addr); 1124 1125 context->resp_status = cmd->resp.status; 1126 1127 release_psp_cmd_buf(psp); 1128 1129 return ret; 1130 } 1131 1132 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1133 { 1134 int ret; 1135 struct psp_gfx_cmd_resp *cmd; 1136 1137 cmd = acquire_psp_cmd_buf(psp); 1138 1139 psp_copy_fw(psp, context->bin_desc.start_addr, 1140 context->bin_desc.size_bytes); 1141 1142 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1143 1144 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1145 psp->fence_buf_mc_addr); 1146 1147 context->resp_status = cmd->resp.status; 1148 1149 if (!ret) { 1150 context->session_id = cmd->resp.session_id; 1151 } 1152 1153 release_psp_cmd_buf(psp); 1154 1155 return ret; 1156 } 1157 1158 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1159 { 1160 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1161 } 1162 1163 int psp_xgmi_terminate(struct psp_context *psp) 1164 { 1165 int ret; 1166 struct amdgpu_device *adev = psp->adev; 1167 1168 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1169 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1170 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1171 adev->gmc.xgmi.connected_to_cpu)) 1172 return 0; 1173 1174 if (!psp->xgmi_context.context.initialized) 1175 return 0; 1176 1177 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1178 1179 psp->xgmi_context.context.initialized = false; 1180 1181 return ret; 1182 } 1183 1184 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1185 { 1186 struct ta_xgmi_shared_memory *xgmi_cmd; 1187 int ret; 1188 1189 if (!psp->ta_fw || 1190 !psp->xgmi_context.context.bin_desc.size_bytes || 1191 !psp->xgmi_context.context.bin_desc.start_addr) 1192 return -ENOENT; 1193 1194 if (!load_ta) 1195 goto invoke; 1196 1197 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1198 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1199 1200 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1201 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1202 if (ret) 1203 return ret; 1204 } 1205 1206 /* Load XGMI TA */ 1207 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1208 if (!ret) 1209 psp->xgmi_context.context.initialized = true; 1210 else 1211 return ret; 1212 1213 invoke: 1214 /* Initialize XGMI session */ 1215 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1216 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1217 xgmi_cmd->flag_extend_link_record = set_extended_data; 1218 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1219 1220 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1221 1222 return ret; 1223 } 1224 1225 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1226 { 1227 struct ta_xgmi_shared_memory *xgmi_cmd; 1228 int ret; 1229 1230 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1231 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1232 1233 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1234 1235 /* Invoke xgmi ta to get hive id */ 1236 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1237 if (ret) 1238 return ret; 1239 1240 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1241 1242 return 0; 1243 } 1244 1245 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1246 { 1247 struct ta_xgmi_shared_memory *xgmi_cmd; 1248 int ret; 1249 1250 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1251 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1252 1253 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1254 1255 /* Invoke xgmi ta to get the node id */ 1256 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1257 if (ret) 1258 return ret; 1259 1260 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1261 1262 return 0; 1263 } 1264 1265 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1266 { 1267 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1268 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1269 } 1270 1271 /* 1272 * Chips that support extended topology information require the driver to 1273 * reflect topology information in the opposite direction. This is 1274 * because the TA has already exceeded its link record limit and if the 1275 * TA holds bi-directional information, the driver would have to do 1276 * multiple fetches instead of just two. 1277 */ 1278 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1279 struct psp_xgmi_node_info node_info) 1280 { 1281 struct amdgpu_device *mirror_adev; 1282 struct amdgpu_hive_info *hive; 1283 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1284 uint64_t dst_node_id = node_info.node_id; 1285 uint8_t dst_num_hops = node_info.num_hops; 1286 uint8_t dst_num_links = node_info.num_links; 1287 1288 hive = amdgpu_get_xgmi_hive(psp->adev); 1289 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1290 struct psp_xgmi_topology_info *mirror_top_info; 1291 int j; 1292 1293 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1294 continue; 1295 1296 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1297 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1298 if (mirror_top_info->nodes[j].node_id != src_node_id) 1299 continue; 1300 1301 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1302 /* 1303 * prevent 0 num_links value re-reflection since reflection 1304 * criteria is based on num_hops (direct or indirect). 1305 * 1306 */ 1307 if (dst_num_links) 1308 mirror_top_info->nodes[j].num_links = dst_num_links; 1309 1310 break; 1311 } 1312 1313 break; 1314 } 1315 1316 amdgpu_put_xgmi_hive(hive); 1317 } 1318 1319 int psp_xgmi_get_topology_info(struct psp_context *psp, 1320 int number_devices, 1321 struct psp_xgmi_topology_info *topology, 1322 bool get_extended_data) 1323 { 1324 struct ta_xgmi_shared_memory *xgmi_cmd; 1325 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1326 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1327 int i; 1328 int ret; 1329 1330 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1331 return -EINVAL; 1332 1333 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1334 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1335 xgmi_cmd->flag_extend_link_record = get_extended_data; 1336 1337 /* Fill in the shared memory with topology information as input */ 1338 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1339 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1340 topology_info_input->num_nodes = number_devices; 1341 1342 for (i = 0; i < topology_info_input->num_nodes; i++) { 1343 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1344 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1345 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1346 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1347 } 1348 1349 /* Invoke xgmi ta to get the topology information */ 1350 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1351 if (ret) 1352 return ret; 1353 1354 /* Read the output topology information from the shared memory */ 1355 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1356 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1357 for (i = 0; i < topology->num_nodes; i++) { 1358 /* extended data will either be 0 or equal to non-extended data */ 1359 if (topology_info_output->nodes[i].num_hops) 1360 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1361 1362 /* non-extended data gets everything here so no need to update */ 1363 if (!get_extended_data) { 1364 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1365 topology->nodes[i].is_sharing_enabled = 1366 topology_info_output->nodes[i].is_sharing_enabled; 1367 topology->nodes[i].sdma_engine = 1368 topology_info_output->nodes[i].sdma_engine; 1369 } 1370 1371 } 1372 1373 /* Invoke xgmi ta again to get the link information */ 1374 if (psp_xgmi_peer_link_info_supported(psp)) { 1375 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1376 1377 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1378 1379 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1380 1381 if (ret) 1382 return ret; 1383 1384 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1385 for (i = 0; i < topology->num_nodes; i++) { 1386 /* accumulate num_links on extended data */ 1387 topology->nodes[i].num_links = get_extended_data ? 1388 topology->nodes[i].num_links + 1389 link_info_output->nodes[i].num_links : 1390 link_info_output->nodes[i].num_links; 1391 1392 /* reflect the topology information for bi-directionality */ 1393 if (psp->xgmi_context.supports_extended_data && 1394 get_extended_data && topology->nodes[i].num_hops) 1395 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1396 } 1397 } 1398 1399 return 0; 1400 } 1401 1402 int psp_xgmi_set_topology_info(struct psp_context *psp, 1403 int number_devices, 1404 struct psp_xgmi_topology_info *topology) 1405 { 1406 struct ta_xgmi_shared_memory *xgmi_cmd; 1407 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1408 int i; 1409 1410 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1411 return -EINVAL; 1412 1413 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1414 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1415 1416 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1417 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1418 topology_info_input->num_nodes = number_devices; 1419 1420 for (i = 0; i < topology_info_input->num_nodes; i++) { 1421 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1422 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1423 topology_info_input->nodes[i].is_sharing_enabled = 1; 1424 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1425 } 1426 1427 /* Invoke xgmi ta to set topology information */ 1428 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1429 } 1430 1431 // ras begin 1432 static void psp_ras_ta_check_status(struct psp_context *psp) 1433 { 1434 struct ta_ras_shared_memory *ras_cmd = 1435 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1436 1437 switch (ras_cmd->ras_status) { 1438 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1439 dev_warn(psp->adev->dev, 1440 "RAS WARNING: cmd failed due to unsupported ip\n"); 1441 break; 1442 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1443 dev_warn(psp->adev->dev, 1444 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1445 break; 1446 case TA_RAS_STATUS__SUCCESS: 1447 break; 1448 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1449 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1450 dev_warn(psp->adev->dev, 1451 "RAS WARNING: Inject error to critical region is not allowed\n"); 1452 break; 1453 default: 1454 dev_warn(psp->adev->dev, 1455 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1456 break; 1457 } 1458 } 1459 1460 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1461 { 1462 struct ta_ras_shared_memory *ras_cmd; 1463 int ret; 1464 1465 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1466 1467 /* 1468 * TODO: bypass the loading in sriov for now 1469 */ 1470 if (amdgpu_sriov_vf(psp->adev)) 1471 return 0; 1472 1473 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1474 1475 if (amdgpu_ras_intr_triggered()) 1476 return ret; 1477 1478 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1479 { 1480 DRM_WARN("RAS: Unsupported Interface"); 1481 return -EINVAL; 1482 } 1483 1484 if (!ret) { 1485 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1486 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1487 1488 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1489 } 1490 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1491 dev_warn(psp->adev->dev, 1492 "RAS internal register access blocked\n"); 1493 1494 psp_ras_ta_check_status(psp); 1495 } 1496 1497 return ret; 1498 } 1499 1500 int psp_ras_enable_features(struct psp_context *psp, 1501 union ta_ras_cmd_input *info, bool enable) 1502 { 1503 struct ta_ras_shared_memory *ras_cmd; 1504 int ret; 1505 1506 if (!psp->ras_context.context.initialized) 1507 return -EINVAL; 1508 1509 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1510 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1511 1512 if (enable) 1513 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1514 else 1515 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1516 1517 ras_cmd->ras_in_message = *info; 1518 1519 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1520 if (ret) 1521 return -EINVAL; 1522 1523 return 0; 1524 } 1525 1526 int psp_ras_terminate(struct psp_context *psp) 1527 { 1528 int ret; 1529 1530 /* 1531 * TODO: bypass the terminate in sriov for now 1532 */ 1533 if (amdgpu_sriov_vf(psp->adev)) 1534 return 0; 1535 1536 if (!psp->ras_context.context.initialized) 1537 return 0; 1538 1539 ret = psp_ta_unload(psp, &psp->ras_context.context); 1540 1541 psp->ras_context.context.initialized = false; 1542 1543 return ret; 1544 } 1545 1546 int psp_ras_initialize(struct psp_context *psp) 1547 { 1548 int ret; 1549 uint32_t boot_cfg = 0xFF; 1550 struct amdgpu_device *adev = psp->adev; 1551 struct ta_ras_shared_memory *ras_cmd; 1552 1553 /* 1554 * TODO: bypass the initialize in sriov for now 1555 */ 1556 if (amdgpu_sriov_vf(adev)) 1557 return 0; 1558 1559 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1560 !adev->psp.ras_context.context.bin_desc.start_addr) { 1561 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1562 return 0; 1563 } 1564 1565 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1566 /* query GECC enablement status from boot config 1567 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1568 */ 1569 ret = psp_boot_config_get(adev, &boot_cfg); 1570 if (ret) 1571 dev_warn(adev->dev, "PSP get boot config failed\n"); 1572 1573 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1574 if (!boot_cfg) { 1575 dev_info(adev->dev, "GECC is disabled\n"); 1576 } else { 1577 /* disable GECC in next boot cycle if ras is 1578 * disabled by module parameter amdgpu_ras_enable 1579 * and/or amdgpu_ras_mask, or boot_config_get call 1580 * is failed 1581 */ 1582 ret = psp_boot_config_set(adev, 0); 1583 if (ret) 1584 dev_warn(adev->dev, "PSP set boot config failed\n"); 1585 else 1586 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1587 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1588 } 1589 } else { 1590 if (1 == boot_cfg) { 1591 dev_info(adev->dev, "GECC is enabled\n"); 1592 } else { 1593 /* enable GECC in next boot cycle if it is disabled 1594 * in boot config, or force enable GECC if failed to 1595 * get boot configuration 1596 */ 1597 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1598 if (ret) 1599 dev_warn(adev->dev, "PSP set boot config failed\n"); 1600 else 1601 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1602 } 1603 } 1604 } 1605 1606 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1607 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1608 1609 if (!psp->ras_context.context.mem_context.shared_buf) { 1610 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1611 if (ret) 1612 return ret; 1613 } 1614 1615 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1616 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1617 1618 if (amdgpu_ras_is_poison_mode_supported(adev)) 1619 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1620 if (!adev->gmc.xgmi.connected_to_cpu) 1621 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1622 1623 ret = psp_ta_load(psp, &psp->ras_context.context); 1624 1625 if (!ret && !ras_cmd->ras_status) 1626 psp->ras_context.context.initialized = true; 1627 else { 1628 if (ras_cmd->ras_status) 1629 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1630 1631 /* fail to load RAS TA */ 1632 psp->ras_context.context.initialized = false; 1633 } 1634 1635 return ret; 1636 } 1637 1638 int psp_ras_trigger_error(struct psp_context *psp, 1639 struct ta_ras_trigger_error_input *info) 1640 { 1641 struct ta_ras_shared_memory *ras_cmd; 1642 int ret; 1643 1644 if (!psp->ras_context.context.initialized) 1645 return -EINVAL; 1646 1647 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1648 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1649 1650 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1651 ras_cmd->ras_in_message.trigger_error = *info; 1652 1653 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1654 if (ret) 1655 return -EINVAL; 1656 1657 /* If err_event_athub occurs error inject was successful, however 1658 return status from TA is no long reliable */ 1659 if (amdgpu_ras_intr_triggered()) 1660 return 0; 1661 1662 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1663 return -EACCES; 1664 else if (ras_cmd->ras_status) 1665 return -EINVAL; 1666 1667 return 0; 1668 } 1669 // ras end 1670 1671 // HDCP start 1672 static int psp_hdcp_initialize(struct psp_context *psp) 1673 { 1674 int ret; 1675 1676 /* 1677 * TODO: bypass the initialize in sriov for now 1678 */ 1679 if (amdgpu_sriov_vf(psp->adev)) 1680 return 0; 1681 1682 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1683 !psp->hdcp_context.context.bin_desc.start_addr) { 1684 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1685 return 0; 1686 } 1687 1688 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1689 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1690 1691 if (!psp->hdcp_context.context.initialized) { 1692 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1693 if (ret) 1694 return ret; 1695 } 1696 1697 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1698 if (!ret) { 1699 psp->hdcp_context.context.initialized = true; 1700 mutex_init(&psp->hdcp_context.mutex); 1701 } 1702 1703 return ret; 1704 } 1705 1706 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1707 { 1708 /* 1709 * TODO: bypass the loading in sriov for now 1710 */ 1711 if (amdgpu_sriov_vf(psp->adev)) 1712 return 0; 1713 1714 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1715 } 1716 1717 static int psp_hdcp_terminate(struct psp_context *psp) 1718 { 1719 int ret; 1720 1721 /* 1722 * TODO: bypass the terminate in sriov for now 1723 */ 1724 if (amdgpu_sriov_vf(psp->adev)) 1725 return 0; 1726 1727 if (!psp->hdcp_context.context.initialized) 1728 return 0; 1729 1730 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1731 1732 psp->hdcp_context.context.initialized = false; 1733 1734 return ret; 1735 } 1736 // HDCP end 1737 1738 // DTM start 1739 static int psp_dtm_initialize(struct psp_context *psp) 1740 { 1741 int ret; 1742 1743 /* 1744 * TODO: bypass the initialize in sriov for now 1745 */ 1746 if (amdgpu_sriov_vf(psp->adev)) 1747 return 0; 1748 1749 if (!psp->dtm_context.context.bin_desc.size_bytes || 1750 !psp->dtm_context.context.bin_desc.start_addr) { 1751 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1752 return 0; 1753 } 1754 1755 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1756 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1757 1758 if (!psp->dtm_context.context.initialized) { 1759 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1760 if (ret) 1761 return ret; 1762 } 1763 1764 ret = psp_ta_load(psp, &psp->dtm_context.context); 1765 if (!ret) { 1766 psp->dtm_context.context.initialized = true; 1767 mutex_init(&psp->dtm_context.mutex); 1768 } 1769 1770 return ret; 1771 } 1772 1773 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1774 { 1775 /* 1776 * TODO: bypass the loading in sriov for now 1777 */ 1778 if (amdgpu_sriov_vf(psp->adev)) 1779 return 0; 1780 1781 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1782 } 1783 1784 static int psp_dtm_terminate(struct psp_context *psp) 1785 { 1786 int ret; 1787 1788 /* 1789 * TODO: bypass the terminate in sriov for now 1790 */ 1791 if (amdgpu_sriov_vf(psp->adev)) 1792 return 0; 1793 1794 if (!psp->dtm_context.context.initialized) 1795 return 0; 1796 1797 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1798 1799 psp->dtm_context.context.initialized = false; 1800 1801 return ret; 1802 } 1803 // DTM end 1804 1805 // RAP start 1806 static int psp_rap_initialize(struct psp_context *psp) 1807 { 1808 int ret; 1809 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1810 1811 /* 1812 * TODO: bypass the initialize in sriov for now 1813 */ 1814 if (amdgpu_sriov_vf(psp->adev)) 1815 return 0; 1816 1817 if (!psp->rap_context.context.bin_desc.size_bytes || 1818 !psp->rap_context.context.bin_desc.start_addr) { 1819 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1820 return 0; 1821 } 1822 1823 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1824 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1825 1826 if (!psp->rap_context.context.initialized) { 1827 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1828 if (ret) 1829 return ret; 1830 } 1831 1832 ret = psp_ta_load(psp, &psp->rap_context.context); 1833 if (!ret) { 1834 psp->rap_context.context.initialized = true; 1835 mutex_init(&psp->rap_context.mutex); 1836 } else 1837 return ret; 1838 1839 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1840 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1841 psp_rap_terminate(psp); 1842 /* free rap shared memory */ 1843 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1844 1845 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1846 ret, status); 1847 1848 return ret; 1849 } 1850 1851 return 0; 1852 } 1853 1854 static int psp_rap_terminate(struct psp_context *psp) 1855 { 1856 int ret; 1857 1858 if (!psp->rap_context.context.initialized) 1859 return 0; 1860 1861 ret = psp_ta_unload(psp, &psp->rap_context.context); 1862 1863 psp->rap_context.context.initialized = false; 1864 1865 return ret; 1866 } 1867 1868 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1869 { 1870 struct ta_rap_shared_memory *rap_cmd; 1871 int ret = 0; 1872 1873 if (!psp->rap_context.context.initialized) 1874 return 0; 1875 1876 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1877 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1878 return -EINVAL; 1879 1880 mutex_lock(&psp->rap_context.mutex); 1881 1882 rap_cmd = (struct ta_rap_shared_memory *) 1883 psp->rap_context.context.mem_context.shared_buf; 1884 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1885 1886 rap_cmd->cmd_id = ta_cmd_id; 1887 rap_cmd->validation_method_id = METHOD_A; 1888 1889 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1890 if (ret) 1891 goto out_unlock; 1892 1893 if (status) 1894 *status = rap_cmd->rap_status; 1895 1896 out_unlock: 1897 mutex_unlock(&psp->rap_context.mutex); 1898 1899 return ret; 1900 } 1901 // RAP end 1902 1903 /* securedisplay start */ 1904 static int psp_securedisplay_initialize(struct psp_context *psp) 1905 { 1906 int ret; 1907 struct securedisplay_cmd *securedisplay_cmd; 1908 1909 /* 1910 * TODO: bypass the initialize in sriov for now 1911 */ 1912 if (amdgpu_sriov_vf(psp->adev)) 1913 return 0; 1914 1915 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1916 !psp->securedisplay_context.context.bin_desc.start_addr) { 1917 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1918 return 0; 1919 } 1920 1921 psp->securedisplay_context.context.mem_context.shared_mem_size = 1922 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1923 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1924 1925 if (!psp->securedisplay_context.context.initialized) { 1926 ret = psp_ta_init_shared_buf(psp, 1927 &psp->securedisplay_context.context.mem_context); 1928 if (ret) 1929 return ret; 1930 } 1931 1932 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 1933 if (!ret) { 1934 psp->securedisplay_context.context.initialized = true; 1935 mutex_init(&psp->securedisplay_context.mutex); 1936 } else 1937 return ret; 1938 1939 mutex_lock(&psp->securedisplay_context.mutex); 1940 1941 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1942 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1943 1944 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1945 1946 mutex_unlock(&psp->securedisplay_context.mutex); 1947 1948 if (ret) { 1949 psp_securedisplay_terminate(psp); 1950 /* free securedisplay shared memory */ 1951 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1952 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1953 return -EINVAL; 1954 } 1955 1956 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1957 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1958 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1959 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1960 } 1961 1962 return 0; 1963 } 1964 1965 static int psp_securedisplay_terminate(struct psp_context *psp) 1966 { 1967 int ret; 1968 1969 /* 1970 * TODO:bypass the terminate in sriov for now 1971 */ 1972 if (amdgpu_sriov_vf(psp->adev)) 1973 return 0; 1974 1975 if (!psp->securedisplay_context.context.initialized) 1976 return 0; 1977 1978 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 1979 1980 psp->securedisplay_context.context.initialized = false; 1981 1982 return ret; 1983 } 1984 1985 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1986 { 1987 int ret; 1988 1989 if (!psp->securedisplay_context.context.initialized) 1990 return -EINVAL; 1991 1992 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1993 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1994 return -EINVAL; 1995 1996 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1997 1998 return ret; 1999 } 2000 /* SECUREDISPLAY end */ 2001 2002 static int psp_hw_start(struct psp_context *psp) 2003 { 2004 struct amdgpu_device *adev = psp->adev; 2005 int ret; 2006 2007 if (!amdgpu_sriov_vf(adev)) { 2008 if ((is_psp_fw_valid(psp->kdb)) && 2009 (psp->funcs->bootloader_load_kdb != NULL)) { 2010 ret = psp_bootloader_load_kdb(psp); 2011 if (ret) { 2012 DRM_ERROR("PSP load kdb failed!\n"); 2013 return ret; 2014 } 2015 } 2016 2017 if ((is_psp_fw_valid(psp->spl)) && 2018 (psp->funcs->bootloader_load_spl != NULL)) { 2019 ret = psp_bootloader_load_spl(psp); 2020 if (ret) { 2021 DRM_ERROR("PSP load spl failed!\n"); 2022 return ret; 2023 } 2024 } 2025 2026 if ((is_psp_fw_valid(psp->sys)) && 2027 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2028 ret = psp_bootloader_load_sysdrv(psp); 2029 if (ret) { 2030 DRM_ERROR("PSP load sys drv failed!\n"); 2031 return ret; 2032 } 2033 } 2034 2035 if ((is_psp_fw_valid(psp->soc_drv)) && 2036 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2037 ret = psp_bootloader_load_soc_drv(psp); 2038 if (ret) { 2039 DRM_ERROR("PSP load soc drv failed!\n"); 2040 return ret; 2041 } 2042 } 2043 2044 if ((is_psp_fw_valid(psp->intf_drv)) && 2045 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2046 ret = psp_bootloader_load_intf_drv(psp); 2047 if (ret) { 2048 DRM_ERROR("PSP load intf drv failed!\n"); 2049 return ret; 2050 } 2051 } 2052 2053 if ((is_psp_fw_valid(psp->dbg_drv)) && 2054 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2055 ret = psp_bootloader_load_dbg_drv(psp); 2056 if (ret) { 2057 DRM_ERROR("PSP load dbg drv failed!\n"); 2058 return ret; 2059 } 2060 } 2061 2062 if ((is_psp_fw_valid(psp->ras_drv)) && 2063 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2064 ret = psp_bootloader_load_ras_drv(psp); 2065 if (ret) { 2066 DRM_ERROR("PSP load ras_drv failed!\n"); 2067 return ret; 2068 } 2069 } 2070 2071 if ((is_psp_fw_valid(psp->sos)) && 2072 (psp->funcs->bootloader_load_sos != NULL)) { 2073 ret = psp_bootloader_load_sos(psp); 2074 if (ret) { 2075 DRM_ERROR("PSP load sos failed!\n"); 2076 return ret; 2077 } 2078 } 2079 } 2080 2081 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2082 if (ret) { 2083 DRM_ERROR("PSP create ring failed!\n"); 2084 return ret; 2085 } 2086 2087 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2088 goto skip_pin_bo; 2089 2090 ret = psp_tmr_init(psp); 2091 if (ret) { 2092 DRM_ERROR("PSP tmr init failed!\n"); 2093 return ret; 2094 } 2095 2096 skip_pin_bo: 2097 /* 2098 * For ASICs with DF Cstate management centralized 2099 * to PMFW, TMR setup should be performed after PMFW 2100 * loaded and before other non-psp firmware loaded. 2101 */ 2102 if (psp->pmfw_centralized_cstate_management) { 2103 ret = psp_load_smu_fw(psp); 2104 if (ret) 2105 return ret; 2106 } 2107 2108 ret = psp_tmr_load(psp); 2109 if (ret) { 2110 DRM_ERROR("PSP load tmr failed!\n"); 2111 return ret; 2112 } 2113 2114 return 0; 2115 } 2116 2117 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2118 enum psp_gfx_fw_type *type) 2119 { 2120 switch (ucode->ucode_id) { 2121 case AMDGPU_UCODE_ID_CAP: 2122 *type = GFX_FW_TYPE_CAP; 2123 break; 2124 case AMDGPU_UCODE_ID_SDMA0: 2125 *type = GFX_FW_TYPE_SDMA0; 2126 break; 2127 case AMDGPU_UCODE_ID_SDMA1: 2128 *type = GFX_FW_TYPE_SDMA1; 2129 break; 2130 case AMDGPU_UCODE_ID_SDMA2: 2131 *type = GFX_FW_TYPE_SDMA2; 2132 break; 2133 case AMDGPU_UCODE_ID_SDMA3: 2134 *type = GFX_FW_TYPE_SDMA3; 2135 break; 2136 case AMDGPU_UCODE_ID_SDMA4: 2137 *type = GFX_FW_TYPE_SDMA4; 2138 break; 2139 case AMDGPU_UCODE_ID_SDMA5: 2140 *type = GFX_FW_TYPE_SDMA5; 2141 break; 2142 case AMDGPU_UCODE_ID_SDMA6: 2143 *type = GFX_FW_TYPE_SDMA6; 2144 break; 2145 case AMDGPU_UCODE_ID_SDMA7: 2146 *type = GFX_FW_TYPE_SDMA7; 2147 break; 2148 case AMDGPU_UCODE_ID_CP_MES: 2149 *type = GFX_FW_TYPE_CP_MES; 2150 break; 2151 case AMDGPU_UCODE_ID_CP_MES_DATA: 2152 *type = GFX_FW_TYPE_MES_STACK; 2153 break; 2154 case AMDGPU_UCODE_ID_CP_MES1: 2155 *type = GFX_FW_TYPE_CP_MES_KIQ; 2156 break; 2157 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2158 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2159 break; 2160 case AMDGPU_UCODE_ID_CP_CE: 2161 *type = GFX_FW_TYPE_CP_CE; 2162 break; 2163 case AMDGPU_UCODE_ID_CP_PFP: 2164 *type = GFX_FW_TYPE_CP_PFP; 2165 break; 2166 case AMDGPU_UCODE_ID_CP_ME: 2167 *type = GFX_FW_TYPE_CP_ME; 2168 break; 2169 case AMDGPU_UCODE_ID_CP_MEC1: 2170 *type = GFX_FW_TYPE_CP_MEC; 2171 break; 2172 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2173 *type = GFX_FW_TYPE_CP_MEC_ME1; 2174 break; 2175 case AMDGPU_UCODE_ID_CP_MEC2: 2176 *type = GFX_FW_TYPE_CP_MEC; 2177 break; 2178 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2179 *type = GFX_FW_TYPE_CP_MEC_ME2; 2180 break; 2181 case AMDGPU_UCODE_ID_RLC_P: 2182 *type = GFX_FW_TYPE_RLC_P; 2183 break; 2184 case AMDGPU_UCODE_ID_RLC_V: 2185 *type = GFX_FW_TYPE_RLC_V; 2186 break; 2187 case AMDGPU_UCODE_ID_RLC_G: 2188 *type = GFX_FW_TYPE_RLC_G; 2189 break; 2190 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2191 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2192 break; 2193 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2194 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2195 break; 2196 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2197 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2198 break; 2199 case AMDGPU_UCODE_ID_RLC_IRAM: 2200 *type = GFX_FW_TYPE_RLC_IRAM; 2201 break; 2202 case AMDGPU_UCODE_ID_RLC_DRAM: 2203 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2204 break; 2205 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2206 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2207 break; 2208 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2209 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2210 break; 2211 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2212 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2213 break; 2214 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2215 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2216 break; 2217 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2218 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2219 break; 2220 case AMDGPU_UCODE_ID_SMC: 2221 *type = GFX_FW_TYPE_SMU; 2222 break; 2223 case AMDGPU_UCODE_ID_PPTABLE: 2224 *type = GFX_FW_TYPE_PPTABLE; 2225 break; 2226 case AMDGPU_UCODE_ID_UVD: 2227 *type = GFX_FW_TYPE_UVD; 2228 break; 2229 case AMDGPU_UCODE_ID_UVD1: 2230 *type = GFX_FW_TYPE_UVD1; 2231 break; 2232 case AMDGPU_UCODE_ID_VCE: 2233 *type = GFX_FW_TYPE_VCE; 2234 break; 2235 case AMDGPU_UCODE_ID_VCN: 2236 *type = GFX_FW_TYPE_VCN; 2237 break; 2238 case AMDGPU_UCODE_ID_VCN1: 2239 *type = GFX_FW_TYPE_VCN1; 2240 break; 2241 case AMDGPU_UCODE_ID_DMCU_ERAM: 2242 *type = GFX_FW_TYPE_DMCU_ERAM; 2243 break; 2244 case AMDGPU_UCODE_ID_DMCU_INTV: 2245 *type = GFX_FW_TYPE_DMCU_ISR; 2246 break; 2247 case AMDGPU_UCODE_ID_VCN0_RAM: 2248 *type = GFX_FW_TYPE_VCN0_RAM; 2249 break; 2250 case AMDGPU_UCODE_ID_VCN1_RAM: 2251 *type = GFX_FW_TYPE_VCN1_RAM; 2252 break; 2253 case AMDGPU_UCODE_ID_DMCUB: 2254 *type = GFX_FW_TYPE_DMUB; 2255 break; 2256 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2257 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2258 break; 2259 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2260 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2261 break; 2262 case AMDGPU_UCODE_ID_IMU_I: 2263 *type = GFX_FW_TYPE_IMU_I; 2264 break; 2265 case AMDGPU_UCODE_ID_IMU_D: 2266 *type = GFX_FW_TYPE_IMU_D; 2267 break; 2268 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2269 *type = GFX_FW_TYPE_RS64_PFP; 2270 break; 2271 case AMDGPU_UCODE_ID_CP_RS64_ME: 2272 *type = GFX_FW_TYPE_RS64_ME; 2273 break; 2274 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2275 *type = GFX_FW_TYPE_RS64_MEC; 2276 break; 2277 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2278 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2279 break; 2280 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2281 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2282 break; 2283 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2284 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2285 break; 2286 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2287 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2288 break; 2289 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2290 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2291 break; 2292 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2293 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2294 break; 2295 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2296 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2297 break; 2298 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2299 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2300 break; 2301 case AMDGPU_UCODE_ID_MAXIMUM: 2302 default: 2303 return -EINVAL; 2304 } 2305 2306 return 0; 2307 } 2308 2309 static void psp_print_fw_hdr(struct psp_context *psp, 2310 struct amdgpu_firmware_info *ucode) 2311 { 2312 struct amdgpu_device *adev = psp->adev; 2313 struct common_firmware_header *hdr; 2314 2315 switch (ucode->ucode_id) { 2316 case AMDGPU_UCODE_ID_SDMA0: 2317 case AMDGPU_UCODE_ID_SDMA1: 2318 case AMDGPU_UCODE_ID_SDMA2: 2319 case AMDGPU_UCODE_ID_SDMA3: 2320 case AMDGPU_UCODE_ID_SDMA4: 2321 case AMDGPU_UCODE_ID_SDMA5: 2322 case AMDGPU_UCODE_ID_SDMA6: 2323 case AMDGPU_UCODE_ID_SDMA7: 2324 hdr = (struct common_firmware_header *) 2325 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2326 amdgpu_ucode_print_sdma_hdr(hdr); 2327 break; 2328 case AMDGPU_UCODE_ID_CP_CE: 2329 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2330 amdgpu_ucode_print_gfx_hdr(hdr); 2331 break; 2332 case AMDGPU_UCODE_ID_CP_PFP: 2333 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2334 amdgpu_ucode_print_gfx_hdr(hdr); 2335 break; 2336 case AMDGPU_UCODE_ID_CP_ME: 2337 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2338 amdgpu_ucode_print_gfx_hdr(hdr); 2339 break; 2340 case AMDGPU_UCODE_ID_CP_MEC1: 2341 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2342 amdgpu_ucode_print_gfx_hdr(hdr); 2343 break; 2344 case AMDGPU_UCODE_ID_RLC_G: 2345 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2346 amdgpu_ucode_print_rlc_hdr(hdr); 2347 break; 2348 case AMDGPU_UCODE_ID_SMC: 2349 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2350 amdgpu_ucode_print_smc_hdr(hdr); 2351 break; 2352 default: 2353 break; 2354 } 2355 } 2356 2357 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2358 struct psp_gfx_cmd_resp *cmd) 2359 { 2360 int ret; 2361 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2362 2363 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2364 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2365 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2366 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2367 2368 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2369 if (ret) 2370 DRM_ERROR("Unknown firmware type\n"); 2371 2372 return ret; 2373 } 2374 2375 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2376 struct amdgpu_firmware_info *ucode) 2377 { 2378 int ret = 0; 2379 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2380 2381 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2382 if (!ret) { 2383 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2384 psp->fence_buf_mc_addr); 2385 } 2386 2387 release_psp_cmd_buf(psp); 2388 2389 return ret; 2390 } 2391 2392 static int psp_load_smu_fw(struct psp_context *psp) 2393 { 2394 int ret; 2395 struct amdgpu_device *adev = psp->adev; 2396 struct amdgpu_firmware_info *ucode = 2397 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2398 struct amdgpu_ras *ras = psp->ras_context.ras; 2399 2400 /* 2401 * Skip SMU FW reloading in case of using BACO for runpm only, 2402 * as SMU is always alive. 2403 */ 2404 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2405 return 0; 2406 2407 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2408 return 0; 2409 2410 if ((amdgpu_in_reset(adev) && 2411 ras && adev->ras_enabled && 2412 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2413 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2414 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2415 if (ret) { 2416 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2417 } 2418 } 2419 2420 ret = psp_execute_non_psp_fw_load(psp, ucode); 2421 2422 if (ret) 2423 DRM_ERROR("PSP load smu failed!\n"); 2424 2425 return ret; 2426 } 2427 2428 static bool fw_load_skip_check(struct psp_context *psp, 2429 struct amdgpu_firmware_info *ucode) 2430 { 2431 if (!ucode->fw || !ucode->ucode_size) 2432 return true; 2433 2434 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2435 (psp_smu_reload_quirk(psp) || 2436 psp->autoload_supported || 2437 psp->pmfw_centralized_cstate_management)) 2438 return true; 2439 2440 if (amdgpu_sriov_vf(psp->adev) && 2441 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2442 return true; 2443 2444 if (psp->autoload_supported && 2445 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2446 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2447 /* skip mec JT when autoload is enabled */ 2448 return true; 2449 2450 return false; 2451 } 2452 2453 int psp_load_fw_list(struct psp_context *psp, 2454 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2455 { 2456 int ret = 0, i; 2457 struct amdgpu_firmware_info *ucode; 2458 2459 for (i = 0; i < ucode_count; ++i) { 2460 ucode = ucode_list[i]; 2461 psp_print_fw_hdr(psp, ucode); 2462 ret = psp_execute_non_psp_fw_load(psp, ucode); 2463 if (ret) 2464 return ret; 2465 } 2466 return ret; 2467 } 2468 2469 static int psp_load_non_psp_fw(struct psp_context *psp) 2470 { 2471 int i, ret; 2472 struct amdgpu_firmware_info *ucode; 2473 struct amdgpu_device *adev = psp->adev; 2474 2475 if (psp->autoload_supported && 2476 !psp->pmfw_centralized_cstate_management) { 2477 ret = psp_load_smu_fw(psp); 2478 if (ret) 2479 return ret; 2480 } 2481 2482 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2483 ucode = &adev->firmware.ucode[i]; 2484 2485 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2486 !fw_load_skip_check(psp, ucode)) { 2487 ret = psp_load_smu_fw(psp); 2488 if (ret) 2489 return ret; 2490 continue; 2491 } 2492 2493 if (fw_load_skip_check(psp, ucode)) 2494 continue; 2495 2496 if (psp->autoload_supported && 2497 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2498 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2499 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2500 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2501 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2502 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2503 /* PSP only receive one SDMA fw for sienna_cichlid, 2504 * as all four sdma fw are same */ 2505 continue; 2506 2507 psp_print_fw_hdr(psp, ucode); 2508 2509 ret = psp_execute_non_psp_fw_load(psp, ucode); 2510 if (ret) 2511 return ret; 2512 2513 /* Start rlc autoload after psp recieved all the gfx firmware */ 2514 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2515 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2516 ret = psp_rlc_autoload_start(psp); 2517 if (ret) { 2518 DRM_ERROR("Failed to start rlc autoload\n"); 2519 return ret; 2520 } 2521 } 2522 } 2523 2524 return 0; 2525 } 2526 2527 static int psp_load_fw(struct amdgpu_device *adev) 2528 { 2529 int ret; 2530 struct psp_context *psp = &adev->psp; 2531 2532 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2533 /* should not destroy ring, only stop */ 2534 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2535 } else { 2536 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2537 2538 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2539 if (ret) { 2540 DRM_ERROR("PSP ring init failed!\n"); 2541 goto failed; 2542 } 2543 } 2544 2545 ret = psp_hw_start(psp); 2546 if (ret) 2547 goto failed; 2548 2549 ret = psp_load_non_psp_fw(psp); 2550 if (ret) 2551 goto failed1; 2552 2553 ret = psp_asd_initialize(psp); 2554 if (ret) { 2555 DRM_ERROR("PSP load asd failed!\n"); 2556 goto failed1; 2557 } 2558 2559 ret = psp_rl_load(adev); 2560 if (ret) { 2561 DRM_ERROR("PSP load RL failed!\n"); 2562 goto failed1; 2563 } 2564 2565 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2566 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2567 ret = psp_xgmi_initialize(psp, false, true); 2568 /* Warning the XGMI seesion initialize failure 2569 * Instead of stop driver initialization 2570 */ 2571 if (ret) 2572 dev_err(psp->adev->dev, 2573 "XGMI: Failed to initialize XGMI session\n"); 2574 } 2575 } 2576 2577 if (psp->ta_fw) { 2578 ret = psp_ras_initialize(psp); 2579 if (ret) 2580 dev_err(psp->adev->dev, 2581 "RAS: Failed to initialize RAS\n"); 2582 2583 ret = psp_hdcp_initialize(psp); 2584 if (ret) 2585 dev_err(psp->adev->dev, 2586 "HDCP: Failed to initialize HDCP\n"); 2587 2588 ret = psp_dtm_initialize(psp); 2589 if (ret) 2590 dev_err(psp->adev->dev, 2591 "DTM: Failed to initialize DTM\n"); 2592 2593 ret = psp_rap_initialize(psp); 2594 if (ret) 2595 dev_err(psp->adev->dev, 2596 "RAP: Failed to initialize RAP\n"); 2597 2598 ret = psp_securedisplay_initialize(psp); 2599 if (ret) 2600 dev_err(psp->adev->dev, 2601 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2602 } 2603 2604 return 0; 2605 2606 failed1: 2607 psp_free_shared_bufs(psp); 2608 failed: 2609 /* 2610 * all cleanup jobs (xgmi terminate, ras terminate, 2611 * ring destroy, cmd/fence/fw buffers destory, 2612 * psp->cmd destory) are delayed to psp_hw_fini 2613 */ 2614 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2615 return ret; 2616 } 2617 2618 static int psp_hw_init(void *handle) 2619 { 2620 int ret; 2621 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2622 2623 mutex_lock(&adev->firmware.mutex); 2624 /* 2625 * This sequence is just used on hw_init only once, no need on 2626 * resume. 2627 */ 2628 ret = amdgpu_ucode_init_bo(adev); 2629 if (ret) 2630 goto failed; 2631 2632 ret = psp_load_fw(adev); 2633 if (ret) { 2634 DRM_ERROR("PSP firmware loading failed\n"); 2635 goto failed; 2636 } 2637 2638 mutex_unlock(&adev->firmware.mutex); 2639 return 0; 2640 2641 failed: 2642 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2643 mutex_unlock(&adev->firmware.mutex); 2644 return -EINVAL; 2645 } 2646 2647 static int psp_hw_fini(void *handle) 2648 { 2649 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2650 struct psp_context *psp = &adev->psp; 2651 2652 if (psp->ta_fw) { 2653 psp_ras_terminate(psp); 2654 psp_securedisplay_terminate(psp); 2655 psp_rap_terminate(psp); 2656 psp_dtm_terminate(psp); 2657 psp_hdcp_terminate(psp); 2658 2659 if (adev->gmc.xgmi.num_physical_nodes > 1) 2660 psp_xgmi_terminate(psp); 2661 } 2662 2663 psp_asd_terminate(psp); 2664 psp_tmr_terminate(psp); 2665 2666 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2667 2668 psp_free_shared_bufs(psp); 2669 2670 return 0; 2671 } 2672 2673 static int psp_suspend(void *handle) 2674 { 2675 int ret = 0; 2676 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2677 struct psp_context *psp = &adev->psp; 2678 2679 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2680 psp->xgmi_context.context.initialized) { 2681 ret = psp_xgmi_terminate(psp); 2682 if (ret) { 2683 DRM_ERROR("Failed to terminate xgmi ta\n"); 2684 goto out; 2685 } 2686 } 2687 2688 if (psp->ta_fw) { 2689 ret = psp_ras_terminate(psp); 2690 if (ret) { 2691 DRM_ERROR("Failed to terminate ras ta\n"); 2692 goto out; 2693 } 2694 ret = psp_hdcp_terminate(psp); 2695 if (ret) { 2696 DRM_ERROR("Failed to terminate hdcp ta\n"); 2697 goto out; 2698 } 2699 ret = psp_dtm_terminate(psp); 2700 if (ret) { 2701 DRM_ERROR("Failed to terminate dtm ta\n"); 2702 goto out; 2703 } 2704 ret = psp_rap_terminate(psp); 2705 if (ret) { 2706 DRM_ERROR("Failed to terminate rap ta\n"); 2707 goto out; 2708 } 2709 ret = psp_securedisplay_terminate(psp); 2710 if (ret) { 2711 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2712 goto out; 2713 } 2714 } 2715 2716 ret = psp_asd_terminate(psp); 2717 if (ret) { 2718 DRM_ERROR("Failed to terminate asd\n"); 2719 goto out; 2720 } 2721 2722 ret = psp_tmr_terminate(psp); 2723 if (ret) { 2724 DRM_ERROR("Failed to terminate tmr\n"); 2725 goto out; 2726 } 2727 2728 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2729 if (ret) { 2730 DRM_ERROR("PSP ring stop failed\n"); 2731 } 2732 2733 out: 2734 return ret; 2735 } 2736 2737 static int psp_resume(void *handle) 2738 { 2739 int ret; 2740 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2741 struct psp_context *psp = &adev->psp; 2742 2743 DRM_INFO("PSP is resuming...\n"); 2744 2745 if (psp->mem_train_ctx.enable_mem_training) { 2746 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2747 if (ret) { 2748 DRM_ERROR("Failed to process memory training!\n"); 2749 return ret; 2750 } 2751 } 2752 2753 mutex_lock(&adev->firmware.mutex); 2754 2755 ret = psp_hw_start(psp); 2756 if (ret) 2757 goto failed; 2758 2759 ret = psp_load_non_psp_fw(psp); 2760 if (ret) 2761 goto failed; 2762 2763 ret = psp_asd_initialize(psp); 2764 if (ret) { 2765 DRM_ERROR("PSP load asd failed!\n"); 2766 goto failed; 2767 } 2768 2769 ret = psp_rl_load(adev); 2770 if (ret) { 2771 dev_err(adev->dev, "PSP load RL failed!\n"); 2772 goto failed; 2773 } 2774 2775 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2776 ret = psp_xgmi_initialize(psp, false, true); 2777 /* Warning the XGMI seesion initialize failure 2778 * Instead of stop driver initialization 2779 */ 2780 if (ret) 2781 dev_err(psp->adev->dev, 2782 "XGMI: Failed to initialize XGMI session\n"); 2783 } 2784 2785 if (psp->ta_fw) { 2786 ret = psp_ras_initialize(psp); 2787 if (ret) 2788 dev_err(psp->adev->dev, 2789 "RAS: Failed to initialize RAS\n"); 2790 2791 ret = psp_hdcp_initialize(psp); 2792 if (ret) 2793 dev_err(psp->adev->dev, 2794 "HDCP: Failed to initialize HDCP\n"); 2795 2796 ret = psp_dtm_initialize(psp); 2797 if (ret) 2798 dev_err(psp->adev->dev, 2799 "DTM: Failed to initialize DTM\n"); 2800 2801 ret = psp_rap_initialize(psp); 2802 if (ret) 2803 dev_err(psp->adev->dev, 2804 "RAP: Failed to initialize RAP\n"); 2805 2806 ret = psp_securedisplay_initialize(psp); 2807 if (ret) 2808 dev_err(psp->adev->dev, 2809 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2810 } 2811 2812 mutex_unlock(&adev->firmware.mutex); 2813 2814 return 0; 2815 2816 failed: 2817 DRM_ERROR("PSP resume failed\n"); 2818 mutex_unlock(&adev->firmware.mutex); 2819 return ret; 2820 } 2821 2822 int psp_gpu_reset(struct amdgpu_device *adev) 2823 { 2824 int ret; 2825 2826 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2827 return 0; 2828 2829 mutex_lock(&adev->psp.mutex); 2830 ret = psp_mode1_reset(&adev->psp); 2831 mutex_unlock(&adev->psp.mutex); 2832 2833 return ret; 2834 } 2835 2836 int psp_rlc_autoload_start(struct psp_context *psp) 2837 { 2838 int ret; 2839 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2840 2841 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2842 2843 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2844 psp->fence_buf_mc_addr); 2845 2846 release_psp_cmd_buf(psp); 2847 2848 return ret; 2849 } 2850 2851 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2852 uint64_t cmd_gpu_addr, int cmd_size) 2853 { 2854 struct amdgpu_firmware_info ucode = {0}; 2855 2856 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2857 AMDGPU_UCODE_ID_VCN0_RAM; 2858 ucode.mc_addr = cmd_gpu_addr; 2859 ucode.ucode_size = cmd_size; 2860 2861 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2862 } 2863 2864 int psp_ring_cmd_submit(struct psp_context *psp, 2865 uint64_t cmd_buf_mc_addr, 2866 uint64_t fence_mc_addr, 2867 int index) 2868 { 2869 unsigned int psp_write_ptr_reg = 0; 2870 struct psp_gfx_rb_frame *write_frame; 2871 struct psp_ring *ring = &psp->km_ring; 2872 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2873 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2874 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2875 struct amdgpu_device *adev = psp->adev; 2876 uint32_t ring_size_dw = ring->ring_size / 4; 2877 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2878 2879 /* KM (GPCOM) prepare write pointer */ 2880 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2881 2882 /* Update KM RB frame pointer to new frame */ 2883 /* write_frame ptr increments by size of rb_frame in bytes */ 2884 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2885 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2886 write_frame = ring_buffer_start; 2887 else 2888 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2889 /* Check invalid write_frame ptr address */ 2890 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2891 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2892 ring_buffer_start, ring_buffer_end, write_frame); 2893 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2894 return -EINVAL; 2895 } 2896 2897 /* Initialize KM RB frame */ 2898 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2899 2900 /* Update KM RB frame */ 2901 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2902 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2903 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2904 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2905 write_frame->fence_value = index; 2906 amdgpu_device_flush_hdp(adev, NULL); 2907 2908 /* Update the write Pointer in DWORDs */ 2909 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2910 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2911 return 0; 2912 } 2913 2914 int psp_init_asd_microcode(struct psp_context *psp, 2915 const char *chip_name) 2916 { 2917 struct amdgpu_device *adev = psp->adev; 2918 char fw_name[PSP_FW_NAME_LEN]; 2919 const struct psp_firmware_header_v1_0 *asd_hdr; 2920 int err = 0; 2921 2922 if (!chip_name) { 2923 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2924 return -EINVAL; 2925 } 2926 2927 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2928 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2929 if (err) 2930 goto out; 2931 2932 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2933 if (err) 2934 goto out; 2935 2936 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2937 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2938 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2939 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2940 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2941 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2942 return 0; 2943 out: 2944 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2945 release_firmware(adev->psp.asd_fw); 2946 adev->psp.asd_fw = NULL; 2947 return err; 2948 } 2949 2950 int psp_init_toc_microcode(struct psp_context *psp, 2951 const char *chip_name) 2952 { 2953 struct amdgpu_device *adev = psp->adev; 2954 char fw_name[PSP_FW_NAME_LEN]; 2955 const struct psp_firmware_header_v1_0 *toc_hdr; 2956 int err = 0; 2957 2958 if (!chip_name) { 2959 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2960 return -EINVAL; 2961 } 2962 2963 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2964 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2965 if (err) 2966 goto out; 2967 2968 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2969 if (err) 2970 goto out; 2971 2972 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2973 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2974 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2975 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2976 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2977 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2978 return 0; 2979 out: 2980 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2981 release_firmware(adev->psp.toc_fw); 2982 adev->psp.toc_fw = NULL; 2983 return err; 2984 } 2985 2986 static int parse_sos_bin_descriptor(struct psp_context *psp, 2987 const struct psp_fw_bin_desc *desc, 2988 const struct psp_firmware_header_v2_0 *sos_hdr) 2989 { 2990 uint8_t *ucode_start_addr = NULL; 2991 2992 if (!psp || !desc || !sos_hdr) 2993 return -EINVAL; 2994 2995 ucode_start_addr = (uint8_t *)sos_hdr + 2996 le32_to_cpu(desc->offset_bytes) + 2997 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2998 2999 switch (desc->fw_type) { 3000 case PSP_FW_TYPE_PSP_SOS: 3001 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3002 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3003 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3004 psp->sos.start_addr = ucode_start_addr; 3005 break; 3006 case PSP_FW_TYPE_PSP_SYS_DRV: 3007 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3008 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3009 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3010 psp->sys.start_addr = ucode_start_addr; 3011 break; 3012 case PSP_FW_TYPE_PSP_KDB: 3013 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3014 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3015 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3016 psp->kdb.start_addr = ucode_start_addr; 3017 break; 3018 case PSP_FW_TYPE_PSP_TOC: 3019 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3020 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3021 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3022 psp->toc.start_addr = ucode_start_addr; 3023 break; 3024 case PSP_FW_TYPE_PSP_SPL: 3025 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3026 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3027 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3028 psp->spl.start_addr = ucode_start_addr; 3029 break; 3030 case PSP_FW_TYPE_PSP_RL: 3031 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3032 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3033 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3034 psp->rl.start_addr = ucode_start_addr; 3035 break; 3036 case PSP_FW_TYPE_PSP_SOC_DRV: 3037 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3038 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3039 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3040 psp->soc_drv.start_addr = ucode_start_addr; 3041 break; 3042 case PSP_FW_TYPE_PSP_INTF_DRV: 3043 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3044 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3045 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3046 psp->intf_drv.start_addr = ucode_start_addr; 3047 break; 3048 case PSP_FW_TYPE_PSP_DBG_DRV: 3049 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3050 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3051 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3052 psp->dbg_drv.start_addr = ucode_start_addr; 3053 break; 3054 case PSP_FW_TYPE_PSP_RAS_DRV: 3055 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3056 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3057 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3058 psp->ras_drv.start_addr = ucode_start_addr; 3059 break; 3060 default: 3061 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3062 break; 3063 } 3064 3065 return 0; 3066 } 3067 3068 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3069 { 3070 const struct psp_firmware_header_v1_0 *sos_hdr; 3071 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3072 uint8_t *ucode_array_start_addr; 3073 3074 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3075 ucode_array_start_addr = (uint8_t *)sos_hdr + 3076 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3077 3078 if (adev->gmc.xgmi.connected_to_cpu || 3079 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3080 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3081 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3082 3083 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3084 adev->psp.sys.start_addr = ucode_array_start_addr; 3085 3086 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3087 adev->psp.sos.start_addr = ucode_array_start_addr + 3088 le32_to_cpu(sos_hdr->sos.offset_bytes); 3089 } else { 3090 /* Load alternate PSP SOS FW */ 3091 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3092 3093 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3094 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3095 3096 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3097 adev->psp.sys.start_addr = ucode_array_start_addr + 3098 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3099 3100 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3101 adev->psp.sos.start_addr = ucode_array_start_addr + 3102 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3103 } 3104 3105 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3106 dev_warn(adev->dev, "PSP SOS FW not available"); 3107 return -EINVAL; 3108 } 3109 3110 return 0; 3111 } 3112 3113 int psp_init_sos_microcode(struct psp_context *psp, 3114 const char *chip_name) 3115 { 3116 struct amdgpu_device *adev = psp->adev; 3117 char fw_name[PSP_FW_NAME_LEN]; 3118 const struct psp_firmware_header_v1_0 *sos_hdr; 3119 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3120 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3121 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3122 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3123 int err = 0; 3124 uint8_t *ucode_array_start_addr; 3125 int fw_index = 0; 3126 3127 if (!chip_name) { 3128 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3129 return -EINVAL; 3130 } 3131 3132 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3133 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3134 if (err) 3135 goto out; 3136 3137 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3138 if (err) 3139 goto out; 3140 3141 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3142 ucode_array_start_addr = (uint8_t *)sos_hdr + 3143 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3144 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3145 3146 switch (sos_hdr->header.header_version_major) { 3147 case 1: 3148 err = psp_init_sos_base_fw(adev); 3149 if (err) 3150 goto out; 3151 3152 if (sos_hdr->header.header_version_minor == 1) { 3153 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3154 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3155 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3156 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3157 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3158 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3159 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3160 } 3161 if (sos_hdr->header.header_version_minor == 2) { 3162 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3163 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3164 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3165 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3166 } 3167 if (sos_hdr->header.header_version_minor == 3) { 3168 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3169 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3170 adev->psp.toc.start_addr = ucode_array_start_addr + 3171 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3172 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3173 adev->psp.kdb.start_addr = ucode_array_start_addr + 3174 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3175 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3176 adev->psp.spl.start_addr = ucode_array_start_addr + 3177 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3178 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3179 adev->psp.rl.start_addr = ucode_array_start_addr + 3180 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3181 } 3182 break; 3183 case 2: 3184 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3185 3186 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3187 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3188 err = -EINVAL; 3189 goto out; 3190 } 3191 3192 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3193 err = parse_sos_bin_descriptor(psp, 3194 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3195 sos_hdr_v2_0); 3196 if (err) 3197 goto out; 3198 } 3199 break; 3200 default: 3201 dev_err(adev->dev, 3202 "unsupported psp sos firmware\n"); 3203 err = -EINVAL; 3204 goto out; 3205 } 3206 3207 return 0; 3208 out: 3209 dev_err(adev->dev, 3210 "failed to init sos firmware\n"); 3211 release_firmware(adev->psp.sos_fw); 3212 adev->psp.sos_fw = NULL; 3213 3214 return err; 3215 } 3216 3217 static int parse_ta_bin_descriptor(struct psp_context *psp, 3218 const struct psp_fw_bin_desc *desc, 3219 const struct ta_firmware_header_v2_0 *ta_hdr) 3220 { 3221 uint8_t *ucode_start_addr = NULL; 3222 3223 if (!psp || !desc || !ta_hdr) 3224 return -EINVAL; 3225 3226 ucode_start_addr = (uint8_t *)ta_hdr + 3227 le32_to_cpu(desc->offset_bytes) + 3228 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3229 3230 switch (desc->fw_type) { 3231 case TA_FW_TYPE_PSP_ASD: 3232 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3233 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3234 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3235 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3236 break; 3237 case TA_FW_TYPE_PSP_XGMI: 3238 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3239 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3240 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3241 break; 3242 case TA_FW_TYPE_PSP_RAS: 3243 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3244 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3245 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3246 break; 3247 case TA_FW_TYPE_PSP_HDCP: 3248 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3249 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3250 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3251 break; 3252 case TA_FW_TYPE_PSP_DTM: 3253 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3254 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3255 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3256 break; 3257 case TA_FW_TYPE_PSP_RAP: 3258 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3259 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3260 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3261 break; 3262 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3263 psp->securedisplay_context.context.bin_desc.fw_version = 3264 le32_to_cpu(desc->fw_version); 3265 psp->securedisplay_context.context.bin_desc.size_bytes = 3266 le32_to_cpu(desc->size_bytes); 3267 psp->securedisplay_context.context.bin_desc.start_addr = 3268 ucode_start_addr; 3269 break; 3270 default: 3271 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3272 break; 3273 } 3274 3275 return 0; 3276 } 3277 3278 int psp_init_ta_microcode(struct psp_context *psp, 3279 const char *chip_name) 3280 { 3281 struct amdgpu_device *adev = psp->adev; 3282 char fw_name[PSP_FW_NAME_LEN]; 3283 const struct ta_firmware_header_v2_0 *ta_hdr; 3284 int err = 0; 3285 int ta_index = 0; 3286 3287 if (!chip_name) { 3288 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3289 return -EINVAL; 3290 } 3291 3292 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3293 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3294 if (err) 3295 goto out; 3296 3297 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3298 if (err) 3299 goto out; 3300 3301 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3302 3303 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3304 dev_err(adev->dev, "unsupported TA header version\n"); 3305 err = -EINVAL; 3306 goto out; 3307 } 3308 3309 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3310 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3311 err = -EINVAL; 3312 goto out; 3313 } 3314 3315 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3316 err = parse_ta_bin_descriptor(psp, 3317 &ta_hdr->ta_fw_bin[ta_index], 3318 ta_hdr); 3319 if (err) 3320 goto out; 3321 } 3322 3323 return 0; 3324 out: 3325 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3326 release_firmware(adev->psp.ta_fw); 3327 adev->psp.ta_fw = NULL; 3328 return err; 3329 } 3330 3331 int psp_init_cap_microcode(struct psp_context *psp, 3332 const char *chip_name) 3333 { 3334 struct amdgpu_device *adev = psp->adev; 3335 char fw_name[PSP_FW_NAME_LEN]; 3336 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3337 struct amdgpu_firmware_info *info = NULL; 3338 int err = 0; 3339 3340 if (!chip_name) { 3341 dev_err(adev->dev, "invalid chip name for cap microcode\n"); 3342 return -EINVAL; 3343 } 3344 3345 if (!amdgpu_sriov_vf(adev)) { 3346 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3347 return -EINVAL; 3348 } 3349 3350 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3351 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev); 3352 if (err) { 3353 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3354 err = 0; 3355 goto out; 3356 } 3357 3358 err = amdgpu_ucode_validate(adev->psp.cap_fw); 3359 if (err) { 3360 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3361 goto out; 3362 } 3363 3364 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3365 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3366 info->fw = adev->psp.cap_fw; 3367 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3368 adev->psp.cap_fw->data; 3369 adev->firmware.fw_size += ALIGN( 3370 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3371 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3372 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3373 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3374 3375 return 0; 3376 3377 out: 3378 release_firmware(adev->psp.cap_fw); 3379 adev->psp.cap_fw = NULL; 3380 return err; 3381 } 3382 3383 static int psp_set_clockgating_state(void *handle, 3384 enum amd_clockgating_state state) 3385 { 3386 return 0; 3387 } 3388 3389 static int psp_set_powergating_state(void *handle, 3390 enum amd_powergating_state state) 3391 { 3392 return 0; 3393 } 3394 3395 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3396 struct device_attribute *attr, 3397 char *buf) 3398 { 3399 struct drm_device *ddev = dev_get_drvdata(dev); 3400 struct amdgpu_device *adev = drm_to_adev(ddev); 3401 uint32_t fw_ver; 3402 int ret; 3403 3404 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3405 DRM_INFO("PSP block is not ready yet."); 3406 return -EBUSY; 3407 } 3408 3409 mutex_lock(&adev->psp.mutex); 3410 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3411 mutex_unlock(&adev->psp.mutex); 3412 3413 if (ret) { 3414 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3415 return ret; 3416 } 3417 3418 return sysfs_emit(buf, "%x\n", fw_ver); 3419 } 3420 3421 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3422 struct device_attribute *attr, 3423 const char *buf, 3424 size_t count) 3425 { 3426 struct drm_device *ddev = dev_get_drvdata(dev); 3427 struct amdgpu_device *adev = drm_to_adev(ddev); 3428 int ret, idx; 3429 char fw_name[100]; 3430 const struct firmware *usbc_pd_fw; 3431 struct amdgpu_bo *fw_buf_bo = NULL; 3432 uint64_t fw_pri_mc_addr; 3433 void *fw_pri_cpu_addr; 3434 3435 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3436 DRM_INFO("PSP block is not ready yet."); 3437 return -EBUSY; 3438 } 3439 3440 if (!drm_dev_enter(ddev, &idx)) 3441 return -ENODEV; 3442 3443 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3444 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3445 if (ret) 3446 goto fail; 3447 3448 /* LFB address which is aligned to 1MB boundary per PSP request */ 3449 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3450 AMDGPU_GEM_DOMAIN_VRAM, 3451 &fw_buf_bo, 3452 &fw_pri_mc_addr, 3453 &fw_pri_cpu_addr); 3454 if (ret) 3455 goto rel_buf; 3456 3457 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3458 3459 mutex_lock(&adev->psp.mutex); 3460 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3461 mutex_unlock(&adev->psp.mutex); 3462 3463 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3464 3465 rel_buf: 3466 release_firmware(usbc_pd_fw); 3467 fail: 3468 if (ret) { 3469 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3470 count = ret; 3471 } 3472 3473 drm_dev_exit(idx); 3474 return count; 3475 } 3476 3477 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3478 { 3479 int idx; 3480 3481 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3482 return; 3483 3484 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3485 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3486 3487 drm_dev_exit(idx); 3488 } 3489 3490 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3491 psp_usbc_pd_fw_sysfs_read, 3492 psp_usbc_pd_fw_sysfs_write); 3493 3494 int is_psp_fw_valid(struct psp_bin_desc bin) 3495 { 3496 return bin.size_bytes; 3497 } 3498 3499 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3500 struct bin_attribute *bin_attr, 3501 char *buffer, loff_t pos, size_t count) 3502 { 3503 struct device *dev = kobj_to_dev(kobj); 3504 struct drm_device *ddev = dev_get_drvdata(dev); 3505 struct amdgpu_device *adev = drm_to_adev(ddev); 3506 3507 adev->psp.vbflash_done = false; 3508 3509 /* Safeguard against memory drain */ 3510 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3511 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3512 kvfree(adev->psp.vbflash_tmp_buf); 3513 adev->psp.vbflash_tmp_buf = NULL; 3514 adev->psp.vbflash_image_size = 0; 3515 return -ENOMEM; 3516 } 3517 3518 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3519 if (!adev->psp.vbflash_tmp_buf) { 3520 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3521 if (!adev->psp.vbflash_tmp_buf) 3522 return -ENOMEM; 3523 } 3524 3525 mutex_lock(&adev->psp.mutex); 3526 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3527 adev->psp.vbflash_image_size += count; 3528 mutex_unlock(&adev->psp.mutex); 3529 3530 dev_info(adev->dev, "VBIOS flash write PSP done"); 3531 3532 return count; 3533 } 3534 3535 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3536 struct bin_attribute *bin_attr, char *buffer, 3537 loff_t pos, size_t count) 3538 { 3539 struct device *dev = kobj_to_dev(kobj); 3540 struct drm_device *ddev = dev_get_drvdata(dev); 3541 struct amdgpu_device *adev = drm_to_adev(ddev); 3542 struct amdgpu_bo *fw_buf_bo = NULL; 3543 uint64_t fw_pri_mc_addr; 3544 void *fw_pri_cpu_addr; 3545 int ret; 3546 3547 dev_info(adev->dev, "VBIOS flash to PSP started"); 3548 3549 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3550 AMDGPU_GPU_PAGE_SIZE, 3551 AMDGPU_GEM_DOMAIN_VRAM, 3552 &fw_buf_bo, 3553 &fw_pri_mc_addr, 3554 &fw_pri_cpu_addr); 3555 if (ret) 3556 goto rel_buf; 3557 3558 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3559 3560 mutex_lock(&adev->psp.mutex); 3561 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3562 mutex_unlock(&adev->psp.mutex); 3563 3564 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3565 3566 rel_buf: 3567 kvfree(adev->psp.vbflash_tmp_buf); 3568 adev->psp.vbflash_tmp_buf = NULL; 3569 adev->psp.vbflash_image_size = 0; 3570 3571 if (ret) { 3572 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret); 3573 return ret; 3574 } 3575 3576 dev_info(adev->dev, "VBIOS flash to PSP done"); 3577 return 0; 3578 } 3579 3580 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3581 struct device_attribute *attr, 3582 char *buf) 3583 { 3584 struct drm_device *ddev = dev_get_drvdata(dev); 3585 struct amdgpu_device *adev = drm_to_adev(ddev); 3586 uint32_t vbflash_status; 3587 3588 vbflash_status = psp_vbflash_status(&adev->psp); 3589 if (!adev->psp.vbflash_done) 3590 vbflash_status = 0; 3591 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3592 vbflash_status = 1; 3593 3594 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3595 } 3596 3597 static const struct bin_attribute psp_vbflash_bin_attr = { 3598 .attr = {.name = "psp_vbflash", .mode = 0664}, 3599 .size = 0, 3600 .write = amdgpu_psp_vbflash_write, 3601 .read = amdgpu_psp_vbflash_read, 3602 }; 3603 3604 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL); 3605 3606 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev) 3607 { 3608 int ret = 0; 3609 struct psp_context *psp = &adev->psp; 3610 3611 if (amdgpu_sriov_vf(adev)) 3612 return -EINVAL; 3613 3614 switch (adev->ip_versions[MP0_HWIP][0]) { 3615 case IP_VERSION(13, 0, 0): 3616 case IP_VERSION(13, 0, 7): 3617 if (!psp->adev) { 3618 psp->adev = adev; 3619 psp_v13_0_set_psp_funcs(psp); 3620 } 3621 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3622 if (ret) 3623 dev_err(adev->dev, "Failed to create device file psp_vbflash"); 3624 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status); 3625 if (ret) 3626 dev_err(adev->dev, "Failed to create device file psp_vbflash_status"); 3627 return ret; 3628 default: 3629 return 0; 3630 } 3631 } 3632 3633 const struct amd_ip_funcs psp_ip_funcs = { 3634 .name = "psp", 3635 .early_init = psp_early_init, 3636 .late_init = NULL, 3637 .sw_init = psp_sw_init, 3638 .sw_fini = psp_sw_fini, 3639 .hw_init = psp_hw_init, 3640 .hw_fini = psp_hw_fini, 3641 .suspend = psp_suspend, 3642 .resume = psp_resume, 3643 .is_idle = NULL, 3644 .check_soft_reset = NULL, 3645 .wait_for_idle = NULL, 3646 .soft_reset = NULL, 3647 .set_clockgating_state = psp_set_clockgating_state, 3648 .set_powergating_state = psp_set_powergating_state, 3649 }; 3650 3651 static int psp_sysfs_init(struct amdgpu_device *adev) 3652 { 3653 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3654 3655 if (ret) 3656 DRM_ERROR("Failed to create USBC PD FW control file!"); 3657 3658 return ret; 3659 } 3660 3661 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev) 3662 { 3663 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3664 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status); 3665 } 3666 3667 static void psp_sysfs_fini(struct amdgpu_device *adev) 3668 { 3669 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3670 } 3671 3672 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3673 { 3674 .type = AMD_IP_BLOCK_TYPE_PSP, 3675 .major = 3, 3676 .minor = 1, 3677 .rev = 0, 3678 .funcs = &psp_ip_funcs, 3679 }; 3680 3681 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3682 { 3683 .type = AMD_IP_BLOCK_TYPE_PSP, 3684 .major = 10, 3685 .minor = 0, 3686 .rev = 0, 3687 .funcs = &psp_ip_funcs, 3688 }; 3689 3690 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3691 { 3692 .type = AMD_IP_BLOCK_TYPE_PSP, 3693 .major = 11, 3694 .minor = 0, 3695 .rev = 0, 3696 .funcs = &psp_ip_funcs, 3697 }; 3698 3699 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3700 .type = AMD_IP_BLOCK_TYPE_PSP, 3701 .major = 11, 3702 .minor = 0, 3703 .rev = 8, 3704 .funcs = &psp_ip_funcs, 3705 }; 3706 3707 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3708 { 3709 .type = AMD_IP_BLOCK_TYPE_PSP, 3710 .major = 12, 3711 .minor = 0, 3712 .rev = 0, 3713 .funcs = &psp_ip_funcs, 3714 }; 3715 3716 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3717 .type = AMD_IP_BLOCK_TYPE_PSP, 3718 .major = 13, 3719 .minor = 0, 3720 .rev = 0, 3721 .funcs = &psp_ip_funcs, 3722 }; 3723 3724 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3725 .type = AMD_IP_BLOCK_TYPE_PSP, 3726 .major = 13, 3727 .minor = 0, 3728 .rev = 4, 3729 .funcs = &psp_ip_funcs, 3730 }; 3731