1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 42 #include "amdgpu_ras.h" 43 #include "amdgpu_securedisplay.h" 44 #include "amdgpu_atomfirmware.h" 45 46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 47 48 static int psp_sysfs_init(struct amdgpu_device *adev); 49 static void psp_sysfs_fini(struct amdgpu_device *adev); 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 static int psp_ring_init(struct psp_context *psp, 56 enum psp_ring_type ring_type) 57 { 58 int ret = 0; 59 struct psp_ring *ring; 60 struct amdgpu_device *adev = psp->adev; 61 62 ring = &psp->km_ring; 63 64 ring->ring_type = ring_type; 65 66 /* allocate 4k Page of Local Frame Buffer memory for ring */ 67 ring->ring_size = 0x1000; 68 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 69 AMDGPU_GEM_DOMAIN_VRAM | 70 AMDGPU_GEM_DOMAIN_GTT, 71 &adev->firmware.rbuf, 72 &ring->ring_mem_mc_addr, 73 (void **)&ring->ring_mem); 74 if (ret) { 75 ring->ring_size = 0; 76 return ret; 77 } 78 79 return 0; 80 } 81 82 /* 83 * Due to DF Cstate management centralized to PMFW, the firmware 84 * loading sequence will be updated as below: 85 * - Load KDB 86 * - Load SYS_DRV 87 * - Load tOS 88 * - Load PMFW 89 * - Setup TMR 90 * - Load other non-psp fw 91 * - Load ASD 92 * - Load XGMI/RAS/HDCP/DTM TA if any 93 * 94 * This new sequence is required for 95 * - Arcturus and onwards 96 */ 97 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 98 { 99 struct amdgpu_device *adev = psp->adev; 100 101 if (amdgpu_sriov_vf(adev)) { 102 psp->pmfw_centralized_cstate_management = false; 103 return; 104 } 105 106 switch (adev->ip_versions[MP0_HWIP][0]) { 107 case IP_VERSION(11, 0, 0): 108 case IP_VERSION(11, 0, 4): 109 case IP_VERSION(11, 0, 5): 110 case IP_VERSION(11, 0, 7): 111 case IP_VERSION(11, 0, 9): 112 case IP_VERSION(11, 0, 11): 113 case IP_VERSION(11, 0, 12): 114 case IP_VERSION(11, 0, 13): 115 case IP_VERSION(13, 0, 0): 116 case IP_VERSION(13, 0, 2): 117 case IP_VERSION(13, 0, 7): 118 psp->pmfw_centralized_cstate_management = true; 119 break; 120 default: 121 psp->pmfw_centralized_cstate_management = false; 122 break; 123 } 124 } 125 126 static int psp_init_sriov_microcode(struct psp_context *psp) 127 { 128 struct amdgpu_device *adev = psp->adev; 129 char ucode_prefix[30]; 130 int ret = 0; 131 132 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 133 134 switch (adev->ip_versions[MP0_HWIP][0]) { 135 case IP_VERSION(9, 0, 0): 136 case IP_VERSION(11, 0, 7): 137 case IP_VERSION(11, 0, 9): 138 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 139 ret = psp_init_cap_microcode(psp, ucode_prefix); 140 break; 141 case IP_VERSION(13, 0, 2): 142 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 143 ret = psp_init_cap_microcode(psp, ucode_prefix); 144 ret &= psp_init_ta_microcode(psp, ucode_prefix); 145 break; 146 case IP_VERSION(13, 0, 0): 147 adev->virt.autoload_ucode_id = 0; 148 break; 149 case IP_VERSION(13, 0, 10): 150 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 151 break; 152 default: 153 return -EINVAL; 154 } 155 return ret; 156 } 157 158 static int psp_early_init(void *handle) 159 { 160 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 161 struct psp_context *psp = &adev->psp; 162 163 switch (adev->ip_versions[MP0_HWIP][0]) { 164 case IP_VERSION(9, 0, 0): 165 psp_v3_1_set_psp_funcs(psp); 166 psp->autoload_supported = false; 167 break; 168 case IP_VERSION(10, 0, 0): 169 case IP_VERSION(10, 0, 1): 170 psp_v10_0_set_psp_funcs(psp); 171 psp->autoload_supported = false; 172 break; 173 case IP_VERSION(11, 0, 2): 174 case IP_VERSION(11, 0, 4): 175 psp_v11_0_set_psp_funcs(psp); 176 psp->autoload_supported = false; 177 break; 178 case IP_VERSION(11, 0, 0): 179 case IP_VERSION(11, 0, 5): 180 case IP_VERSION(11, 0, 9): 181 case IP_VERSION(11, 0, 7): 182 case IP_VERSION(11, 0, 11): 183 case IP_VERSION(11, 5, 0): 184 case IP_VERSION(11, 0, 12): 185 case IP_VERSION(11, 0, 13): 186 psp_v11_0_set_psp_funcs(psp); 187 psp->autoload_supported = true; 188 break; 189 case IP_VERSION(11, 0, 3): 190 case IP_VERSION(12, 0, 1): 191 psp_v12_0_set_psp_funcs(psp); 192 break; 193 case IP_VERSION(13, 0, 2): 194 psp_v13_0_set_psp_funcs(psp); 195 break; 196 case IP_VERSION(13, 0, 1): 197 case IP_VERSION(13, 0, 3): 198 case IP_VERSION(13, 0, 5): 199 case IP_VERSION(13, 0, 8): 200 case IP_VERSION(13, 0, 10): 201 case IP_VERSION(13, 0, 11): 202 psp_v13_0_set_psp_funcs(psp); 203 psp->autoload_supported = true; 204 break; 205 case IP_VERSION(11, 0, 8): 206 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 207 psp_v11_0_8_set_psp_funcs(psp); 208 psp->autoload_supported = false; 209 } 210 break; 211 case IP_VERSION(13, 0, 0): 212 case IP_VERSION(13, 0, 7): 213 psp_v13_0_set_psp_funcs(psp); 214 psp->autoload_supported = true; 215 break; 216 case IP_VERSION(13, 0, 4): 217 psp_v13_0_4_set_psp_funcs(psp); 218 psp->autoload_supported = true; 219 break; 220 default: 221 return -EINVAL; 222 } 223 224 psp->adev = adev; 225 226 psp_check_pmfw_centralized_cstate_management(psp); 227 228 if (amdgpu_sriov_vf(adev)) 229 return psp_init_sriov_microcode(psp); 230 else 231 return psp_init_microcode(psp); 232 } 233 234 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 235 { 236 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 237 &mem_ctx->shared_buf); 238 mem_ctx->shared_bo = NULL; 239 } 240 241 static void psp_free_shared_bufs(struct psp_context *psp) 242 { 243 void *tmr_buf; 244 void **pptr; 245 246 /* free TMR memory buffer */ 247 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 248 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 249 psp->tmr_bo = NULL; 250 251 /* free xgmi shared memory */ 252 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 253 254 /* free ras shared memory */ 255 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 256 257 /* free hdcp shared memory */ 258 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 259 260 /* free dtm shared memory */ 261 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 262 263 /* free rap shared memory */ 264 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 265 266 /* free securedisplay shared memory */ 267 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 268 269 270 } 271 272 static void psp_memory_training_fini(struct psp_context *psp) 273 { 274 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 275 276 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 277 kfree(ctx->sys_cache); 278 ctx->sys_cache = NULL; 279 } 280 281 static int psp_memory_training_init(struct psp_context *psp) 282 { 283 int ret; 284 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 285 286 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 287 DRM_DEBUG("memory training is not supported!\n"); 288 return 0; 289 } 290 291 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 292 if (ctx->sys_cache == NULL) { 293 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 294 ret = -ENOMEM; 295 goto Err_out; 296 } 297 298 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 299 ctx->train_data_size, 300 ctx->p2c_train_data_offset, 301 ctx->c2p_train_data_offset); 302 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 303 return 0; 304 305 Err_out: 306 psp_memory_training_fini(psp); 307 return ret; 308 } 309 310 /* 311 * Helper funciton to query psp runtime database entry 312 * 313 * @adev: amdgpu_device pointer 314 * @entry_type: the type of psp runtime database entry 315 * @db_entry: runtime database entry pointer 316 * 317 * Return false if runtime database doesn't exit or entry is invalid 318 * or true if the specific database entry is found, and copy to @db_entry 319 */ 320 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 321 enum psp_runtime_entry_type entry_type, 322 void *db_entry) 323 { 324 uint64_t db_header_pos, db_dir_pos; 325 struct psp_runtime_data_header db_header = {0}; 326 struct psp_runtime_data_directory db_dir = {0}; 327 bool ret = false; 328 int i; 329 330 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 331 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 332 333 /* read runtime db header from vram */ 334 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 335 sizeof(struct psp_runtime_data_header), false); 336 337 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 338 /* runtime db doesn't exist, exit */ 339 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 340 return false; 341 } 342 343 /* read runtime database entry from vram */ 344 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 345 sizeof(struct psp_runtime_data_directory), false); 346 347 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 348 /* invalid db entry count, exit */ 349 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 350 return false; 351 } 352 353 /* look up for requested entry type */ 354 for (i = 0; i < db_dir.entry_count && !ret; i++) { 355 if (db_dir.entry_list[i].entry_type == entry_type) { 356 switch (entry_type) { 357 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 358 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 359 /* invalid db entry size */ 360 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 361 return false; 362 } 363 /* read runtime database entry */ 364 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 365 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 366 ret = true; 367 break; 368 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 369 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 370 /* invalid db entry size */ 371 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 372 return false; 373 } 374 /* read runtime database entry */ 375 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 376 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 377 ret = true; 378 break; 379 default: 380 ret = false; 381 break; 382 } 383 } 384 } 385 386 return ret; 387 } 388 389 static int psp_sw_init(void *handle) 390 { 391 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 392 struct psp_context *psp = &adev->psp; 393 int ret; 394 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 395 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 396 struct psp_runtime_scpm_entry scpm_entry; 397 398 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 399 if (!psp->cmd) { 400 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 401 ret = -ENOMEM; 402 } 403 404 adev->psp.xgmi_context.supports_extended_data = 405 !adev->gmc.xgmi.connected_to_cpu && 406 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 407 408 memset(&scpm_entry, 0, sizeof(scpm_entry)); 409 if ((psp_get_runtime_db_entry(adev, 410 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 411 &scpm_entry)) && 412 (SCPM_DISABLE != scpm_entry.scpm_status)) { 413 adev->scpm_enabled = true; 414 adev->scpm_status = scpm_entry.scpm_status; 415 } else { 416 adev->scpm_enabled = false; 417 adev->scpm_status = SCPM_DISABLE; 418 } 419 420 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 421 422 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 423 if (psp_get_runtime_db_entry(adev, 424 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 425 &boot_cfg_entry)) { 426 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 427 if ((psp->boot_cfg_bitmask) & 428 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 429 /* If psp runtime database exists, then 430 * only enable two stage memory training 431 * when TWO_STAGE_DRAM_TRAINING bit is set 432 * in runtime database */ 433 mem_training_ctx->enable_mem_training = true; 434 } 435 436 } else { 437 /* If psp runtime database doesn't exist or 438 * is invalid, force enable two stage memory 439 * training */ 440 mem_training_ctx->enable_mem_training = true; 441 } 442 443 if (mem_training_ctx->enable_mem_training) { 444 ret = psp_memory_training_init(psp); 445 if (ret) { 446 DRM_ERROR("Failed to initialize memory training!\n"); 447 return ret; 448 } 449 450 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 451 if (ret) { 452 DRM_ERROR("Failed to process memory training!\n"); 453 return ret; 454 } 455 } 456 457 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 458 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 459 ret= psp_sysfs_init(adev); 460 if (ret) { 461 return ret; 462 } 463 } 464 465 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 466 amdgpu_sriov_vf(adev) ? 467 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 468 &psp->fw_pri_bo, 469 &psp->fw_pri_mc_addr, 470 &psp->fw_pri_buf); 471 if (ret) 472 return ret; 473 474 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 475 AMDGPU_GEM_DOMAIN_VRAM, 476 &psp->fence_buf_bo, 477 &psp->fence_buf_mc_addr, 478 &psp->fence_buf); 479 if (ret) 480 goto failed1; 481 482 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 483 AMDGPU_GEM_DOMAIN_VRAM, 484 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 485 (void **)&psp->cmd_buf_mem); 486 if (ret) 487 goto failed2; 488 489 return 0; 490 491 failed2: 492 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 493 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 494 failed1: 495 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 496 &psp->fence_buf_mc_addr, &psp->fence_buf); 497 return ret; 498 } 499 500 static int psp_sw_fini(void *handle) 501 { 502 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 503 struct psp_context *psp = &adev->psp; 504 struct psp_gfx_cmd_resp *cmd = psp->cmd; 505 506 psp_memory_training_fini(psp); 507 508 amdgpu_ucode_release(&psp->sos_fw); 509 amdgpu_ucode_release(&psp->asd_fw); 510 amdgpu_ucode_release(&psp->ta_fw); 511 amdgpu_ucode_release(&psp->cap_fw); 512 amdgpu_ucode_release(&psp->toc_fw); 513 514 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 515 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 516 psp_sysfs_fini(adev); 517 518 kfree(cmd); 519 cmd = NULL; 520 521 if (psp->km_ring.ring_mem) 522 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 523 &psp->km_ring.ring_mem_mc_addr, 524 (void **)&psp->km_ring.ring_mem); 525 526 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 527 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 528 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 529 &psp->fence_buf_mc_addr, &psp->fence_buf); 530 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 531 (void **)&psp->cmd_buf_mem); 532 533 return 0; 534 } 535 536 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 537 uint32_t reg_val, uint32_t mask, bool check_changed) 538 { 539 uint32_t val; 540 int i; 541 struct amdgpu_device *adev = psp->adev; 542 543 if (psp->adev->no_hw_access) 544 return 0; 545 546 for (i = 0; i < adev->usec_timeout; i++) { 547 val = RREG32(reg_index); 548 if (check_changed) { 549 if (val != reg_val) 550 return 0; 551 } else { 552 if ((val & mask) == reg_val) 553 return 0; 554 } 555 udelay(1); 556 } 557 558 return -ETIME; 559 } 560 561 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 562 { 563 switch (cmd_id) { 564 case GFX_CMD_ID_LOAD_TA: 565 return "LOAD_TA"; 566 case GFX_CMD_ID_UNLOAD_TA: 567 return "UNLOAD_TA"; 568 case GFX_CMD_ID_INVOKE_CMD: 569 return "INVOKE_CMD"; 570 case GFX_CMD_ID_LOAD_ASD: 571 return "LOAD_ASD"; 572 case GFX_CMD_ID_SETUP_TMR: 573 return "SETUP_TMR"; 574 case GFX_CMD_ID_LOAD_IP_FW: 575 return "LOAD_IP_FW"; 576 case GFX_CMD_ID_DESTROY_TMR: 577 return "DESTROY_TMR"; 578 case GFX_CMD_ID_SAVE_RESTORE: 579 return "SAVE_RESTORE_IP_FW"; 580 case GFX_CMD_ID_SETUP_VMR: 581 return "SETUP_VMR"; 582 case GFX_CMD_ID_DESTROY_VMR: 583 return "DESTROY_VMR"; 584 case GFX_CMD_ID_PROG_REG: 585 return "PROG_REG"; 586 case GFX_CMD_ID_GET_FW_ATTESTATION: 587 return "GET_FW_ATTESTATION"; 588 case GFX_CMD_ID_LOAD_TOC: 589 return "ID_LOAD_TOC"; 590 case GFX_CMD_ID_AUTOLOAD_RLC: 591 return "AUTOLOAD_RLC"; 592 case GFX_CMD_ID_BOOT_CFG: 593 return "BOOT_CFG"; 594 default: 595 return "UNKNOWN CMD"; 596 } 597 } 598 599 static int 600 psp_cmd_submit_buf(struct psp_context *psp, 601 struct amdgpu_firmware_info *ucode, 602 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 603 { 604 int ret; 605 int index, idx; 606 int timeout = 20000; 607 bool ras_intr = false; 608 bool skip_unsupport = false; 609 610 if (psp->adev->no_hw_access) 611 return 0; 612 613 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 614 return 0; 615 616 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 617 618 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 619 620 index = atomic_inc_return(&psp->fence_value); 621 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 622 if (ret) { 623 atomic_dec(&psp->fence_value); 624 goto exit; 625 } 626 627 amdgpu_device_invalidate_hdp(psp->adev, NULL); 628 while (*((unsigned int *)psp->fence_buf) != index) { 629 if (--timeout == 0) 630 break; 631 /* 632 * Shouldn't wait for timeout when err_event_athub occurs, 633 * because gpu reset thread triggered and lock resource should 634 * be released for psp resume sequence. 635 */ 636 ras_intr = amdgpu_ras_intr_triggered(); 637 if (ras_intr) 638 break; 639 usleep_range(10, 100); 640 amdgpu_device_invalidate_hdp(psp->adev, NULL); 641 } 642 643 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 644 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 645 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 646 647 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 648 649 /* In some cases, psp response status is not 0 even there is no 650 * problem while the command is submitted. Some version of PSP FW 651 * doesn't write 0 to that field. 652 * So here we would like to only print a warning instead of an error 653 * during psp initialization to avoid breaking hw_init and it doesn't 654 * return -EINVAL. 655 */ 656 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 657 if (ucode) 658 DRM_WARN("failed to load ucode %s(0x%X) ", 659 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 660 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 661 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 662 psp->cmd_buf_mem->resp.status); 663 /* If any firmware (including CAP) load fails under SRIOV, it should 664 * return failure to stop the VF from initializing. 665 * Also return failure in case of timeout 666 */ 667 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 668 ret = -EINVAL; 669 goto exit; 670 } 671 } 672 673 if (ucode) { 674 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 675 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 676 } 677 678 exit: 679 drm_dev_exit(idx); 680 return ret; 681 } 682 683 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 684 { 685 struct psp_gfx_cmd_resp *cmd = psp->cmd; 686 687 mutex_lock(&psp->mutex); 688 689 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 690 691 return cmd; 692 } 693 694 static void release_psp_cmd_buf(struct psp_context *psp) 695 { 696 mutex_unlock(&psp->mutex); 697 } 698 699 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 700 struct psp_gfx_cmd_resp *cmd, 701 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 702 { 703 struct amdgpu_device *adev = psp->adev; 704 uint32_t size = amdgpu_bo_size(tmr_bo); 705 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 706 707 if (amdgpu_sriov_vf(psp->adev)) 708 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 709 else 710 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 711 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 712 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 713 cmd->cmd.cmd_setup_tmr.buf_size = size; 714 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 715 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 716 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 717 } 718 719 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 720 uint64_t pri_buf_mc, uint32_t size) 721 { 722 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 723 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 724 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 725 cmd->cmd.cmd_load_toc.toc_size = size; 726 } 727 728 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 729 static int psp_load_toc(struct psp_context *psp, 730 uint32_t *tmr_size) 731 { 732 int ret; 733 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 734 735 /* Copy toc to psp firmware private buffer */ 736 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 737 738 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 739 740 ret = psp_cmd_submit_buf(psp, NULL, cmd, 741 psp->fence_buf_mc_addr); 742 if (!ret) 743 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 744 745 release_psp_cmd_buf(psp); 746 747 return ret; 748 } 749 750 /* Set up Trusted Memory Region */ 751 static int psp_tmr_init(struct psp_context *psp) 752 { 753 int ret = 0; 754 int tmr_size; 755 void *tmr_buf; 756 void **pptr; 757 758 /* 759 * According to HW engineer, they prefer the TMR address be "naturally 760 * aligned" , e.g. the start address be an integer divide of TMR size. 761 * 762 * Note: this memory need be reserved till the driver 763 * uninitializes. 764 */ 765 tmr_size = PSP_TMR_SIZE(psp->adev); 766 767 /* For ASICs support RLC autoload, psp will parse the toc 768 * and calculate the total size of TMR needed */ 769 if (!amdgpu_sriov_vf(psp->adev) && 770 psp->toc.start_addr && 771 psp->toc.size_bytes && 772 psp->fw_pri_buf) { 773 ret = psp_load_toc(psp, &tmr_size); 774 if (ret) { 775 DRM_ERROR("Failed to load toc\n"); 776 return ret; 777 } 778 } 779 780 if (!psp->tmr_bo) { 781 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 782 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 783 PSP_TMR_ALIGNMENT, 784 AMDGPU_HAS_VRAM(psp->adev) ? 785 AMDGPU_GEM_DOMAIN_VRAM : 786 AMDGPU_GEM_DOMAIN_GTT, 787 &psp->tmr_bo, &psp->tmr_mc_addr, 788 pptr); 789 } 790 791 return ret; 792 } 793 794 static bool psp_skip_tmr(struct psp_context *psp) 795 { 796 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 797 case IP_VERSION(11, 0, 9): 798 case IP_VERSION(11, 0, 7): 799 case IP_VERSION(13, 0, 2): 800 case IP_VERSION(13, 0, 10): 801 return true; 802 default: 803 return false; 804 } 805 } 806 807 static int psp_tmr_load(struct psp_context *psp) 808 { 809 int ret; 810 struct psp_gfx_cmd_resp *cmd; 811 812 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 813 * Already set up by host driver. 814 */ 815 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 816 return 0; 817 818 cmd = acquire_psp_cmd_buf(psp); 819 820 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 821 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 822 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 823 824 ret = psp_cmd_submit_buf(psp, NULL, cmd, 825 psp->fence_buf_mc_addr); 826 827 release_psp_cmd_buf(psp); 828 829 return ret; 830 } 831 832 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 833 struct psp_gfx_cmd_resp *cmd) 834 { 835 if (amdgpu_sriov_vf(psp->adev)) 836 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 837 else 838 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 839 } 840 841 static int psp_tmr_unload(struct psp_context *psp) 842 { 843 int ret; 844 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 845 846 psp_prep_tmr_unload_cmd_buf(psp, cmd); 847 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 848 849 ret = psp_cmd_submit_buf(psp, NULL, cmd, 850 psp->fence_buf_mc_addr); 851 852 release_psp_cmd_buf(psp); 853 854 return ret; 855 } 856 857 static int psp_tmr_terminate(struct psp_context *psp) 858 { 859 return psp_tmr_unload(psp); 860 } 861 862 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 863 uint64_t *output_ptr) 864 { 865 int ret; 866 struct psp_gfx_cmd_resp *cmd; 867 868 if (!output_ptr) 869 return -EINVAL; 870 871 if (amdgpu_sriov_vf(psp->adev)) 872 return 0; 873 874 cmd = acquire_psp_cmd_buf(psp); 875 876 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 877 878 ret = psp_cmd_submit_buf(psp, NULL, cmd, 879 psp->fence_buf_mc_addr); 880 881 if (!ret) { 882 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 883 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 884 } 885 886 release_psp_cmd_buf(psp); 887 888 return ret; 889 } 890 891 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 892 { 893 struct psp_context *psp = &adev->psp; 894 struct psp_gfx_cmd_resp *cmd; 895 int ret; 896 897 if (amdgpu_sriov_vf(adev)) 898 return 0; 899 900 cmd = acquire_psp_cmd_buf(psp); 901 902 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 903 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 904 905 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 906 if (!ret) { 907 *boot_cfg = 908 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 909 } 910 911 release_psp_cmd_buf(psp); 912 913 return ret; 914 } 915 916 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 917 { 918 int ret; 919 struct psp_context *psp = &adev->psp; 920 struct psp_gfx_cmd_resp *cmd; 921 922 if (amdgpu_sriov_vf(adev)) 923 return 0; 924 925 cmd = acquire_psp_cmd_buf(psp); 926 927 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 928 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 929 cmd->cmd.boot_cfg.boot_config = boot_cfg; 930 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 931 932 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 933 934 release_psp_cmd_buf(psp); 935 936 return ret; 937 } 938 939 static int psp_rl_load(struct amdgpu_device *adev) 940 { 941 int ret; 942 struct psp_context *psp = &adev->psp; 943 struct psp_gfx_cmd_resp *cmd; 944 945 if (!is_psp_fw_valid(psp->rl)) 946 return 0; 947 948 cmd = acquire_psp_cmd_buf(psp); 949 950 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 951 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 952 953 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 954 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 955 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 956 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 957 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 958 959 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 960 961 release_psp_cmd_buf(psp); 962 963 return ret; 964 } 965 966 static int psp_asd_initialize(struct psp_context *psp) 967 { 968 int ret; 969 970 /* If PSP version doesn't match ASD version, asd loading will be failed. 971 * add workaround to bypass it for sriov now. 972 * TODO: add version check to make it common 973 */ 974 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 975 return 0; 976 977 psp->asd_context.mem_context.shared_mc_addr = 0; 978 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 979 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 980 981 ret = psp_ta_load(psp, &psp->asd_context); 982 if (!ret) 983 psp->asd_context.initialized = true; 984 985 return ret; 986 } 987 988 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 989 uint32_t session_id) 990 { 991 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 992 cmd->cmd.cmd_unload_ta.session_id = session_id; 993 } 994 995 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 996 { 997 int ret; 998 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 999 1000 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1001 1002 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1003 1004 context->resp_status = cmd->resp.status; 1005 1006 release_psp_cmd_buf(psp); 1007 1008 return ret; 1009 } 1010 1011 static int psp_asd_terminate(struct psp_context *psp) 1012 { 1013 int ret; 1014 1015 if (amdgpu_sriov_vf(psp->adev)) 1016 return 0; 1017 1018 if (!psp->asd_context.initialized) 1019 return 0; 1020 1021 ret = psp_ta_unload(psp, &psp->asd_context); 1022 if (!ret) 1023 psp->asd_context.initialized = false; 1024 1025 return ret; 1026 } 1027 1028 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1029 uint32_t id, uint32_t value) 1030 { 1031 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1032 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1033 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1034 } 1035 1036 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1037 uint32_t value) 1038 { 1039 struct psp_gfx_cmd_resp *cmd; 1040 int ret = 0; 1041 1042 if (reg >= PSP_REG_LAST) 1043 return -EINVAL; 1044 1045 cmd = acquire_psp_cmd_buf(psp); 1046 1047 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1048 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1049 if (ret) 1050 DRM_ERROR("PSP failed to program reg id %d", reg); 1051 1052 release_psp_cmd_buf(psp); 1053 1054 return ret; 1055 } 1056 1057 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1058 uint64_t ta_bin_mc, 1059 struct ta_context *context) 1060 { 1061 cmd->cmd_id = context->ta_load_type; 1062 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1063 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1064 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1065 1066 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1067 lower_32_bits(context->mem_context.shared_mc_addr); 1068 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1069 upper_32_bits(context->mem_context.shared_mc_addr); 1070 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1071 } 1072 1073 int psp_ta_init_shared_buf(struct psp_context *psp, 1074 struct ta_mem_context *mem_ctx) 1075 { 1076 /* 1077 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1078 * physical) for ta to host memory 1079 */ 1080 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1081 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1082 AMDGPU_GEM_DOMAIN_GTT, 1083 &mem_ctx->shared_bo, 1084 &mem_ctx->shared_mc_addr, 1085 &mem_ctx->shared_buf); 1086 } 1087 1088 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1089 uint32_t ta_cmd_id, 1090 uint32_t session_id) 1091 { 1092 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1093 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1094 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1095 } 1096 1097 int psp_ta_invoke(struct psp_context *psp, 1098 uint32_t ta_cmd_id, 1099 struct ta_context *context) 1100 { 1101 int ret; 1102 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1103 1104 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1105 1106 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1107 psp->fence_buf_mc_addr); 1108 1109 context->resp_status = cmd->resp.status; 1110 1111 release_psp_cmd_buf(psp); 1112 1113 return ret; 1114 } 1115 1116 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1117 { 1118 int ret; 1119 struct psp_gfx_cmd_resp *cmd; 1120 1121 cmd = acquire_psp_cmd_buf(psp); 1122 1123 psp_copy_fw(psp, context->bin_desc.start_addr, 1124 context->bin_desc.size_bytes); 1125 1126 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1127 1128 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1129 psp->fence_buf_mc_addr); 1130 1131 context->resp_status = cmd->resp.status; 1132 1133 if (!ret) { 1134 context->session_id = cmd->resp.session_id; 1135 } 1136 1137 release_psp_cmd_buf(psp); 1138 1139 return ret; 1140 } 1141 1142 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1143 { 1144 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1145 } 1146 1147 int psp_xgmi_terminate(struct psp_context *psp) 1148 { 1149 int ret; 1150 struct amdgpu_device *adev = psp->adev; 1151 1152 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1153 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1154 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1155 adev->gmc.xgmi.connected_to_cpu)) 1156 return 0; 1157 1158 if (!psp->xgmi_context.context.initialized) 1159 return 0; 1160 1161 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1162 1163 psp->xgmi_context.context.initialized = false; 1164 1165 return ret; 1166 } 1167 1168 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1169 { 1170 struct ta_xgmi_shared_memory *xgmi_cmd; 1171 int ret; 1172 1173 if (!psp->ta_fw || 1174 !psp->xgmi_context.context.bin_desc.size_bytes || 1175 !psp->xgmi_context.context.bin_desc.start_addr) 1176 return -ENOENT; 1177 1178 if (!load_ta) 1179 goto invoke; 1180 1181 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1182 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1183 1184 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1185 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1186 if (ret) 1187 return ret; 1188 } 1189 1190 /* Load XGMI TA */ 1191 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1192 if (!ret) 1193 psp->xgmi_context.context.initialized = true; 1194 else 1195 return ret; 1196 1197 invoke: 1198 /* Initialize XGMI session */ 1199 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1200 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1201 xgmi_cmd->flag_extend_link_record = set_extended_data; 1202 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1203 1204 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1205 1206 return ret; 1207 } 1208 1209 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1210 { 1211 struct ta_xgmi_shared_memory *xgmi_cmd; 1212 int ret; 1213 1214 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1215 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1216 1217 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1218 1219 /* Invoke xgmi ta to get hive id */ 1220 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1221 if (ret) 1222 return ret; 1223 1224 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1225 1226 return 0; 1227 } 1228 1229 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1230 { 1231 struct ta_xgmi_shared_memory *xgmi_cmd; 1232 int ret; 1233 1234 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1235 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1236 1237 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1238 1239 /* Invoke xgmi ta to get the node id */ 1240 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1241 if (ret) 1242 return ret; 1243 1244 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1245 1246 return 0; 1247 } 1248 1249 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1250 { 1251 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1252 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1253 } 1254 1255 /* 1256 * Chips that support extended topology information require the driver to 1257 * reflect topology information in the opposite direction. This is 1258 * because the TA has already exceeded its link record limit and if the 1259 * TA holds bi-directional information, the driver would have to do 1260 * multiple fetches instead of just two. 1261 */ 1262 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1263 struct psp_xgmi_node_info node_info) 1264 { 1265 struct amdgpu_device *mirror_adev; 1266 struct amdgpu_hive_info *hive; 1267 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1268 uint64_t dst_node_id = node_info.node_id; 1269 uint8_t dst_num_hops = node_info.num_hops; 1270 uint8_t dst_num_links = node_info.num_links; 1271 1272 hive = amdgpu_get_xgmi_hive(psp->adev); 1273 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1274 struct psp_xgmi_topology_info *mirror_top_info; 1275 int j; 1276 1277 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1278 continue; 1279 1280 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1281 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1282 if (mirror_top_info->nodes[j].node_id != src_node_id) 1283 continue; 1284 1285 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1286 /* 1287 * prevent 0 num_links value re-reflection since reflection 1288 * criteria is based on num_hops (direct or indirect). 1289 * 1290 */ 1291 if (dst_num_links) 1292 mirror_top_info->nodes[j].num_links = dst_num_links; 1293 1294 break; 1295 } 1296 1297 break; 1298 } 1299 1300 amdgpu_put_xgmi_hive(hive); 1301 } 1302 1303 int psp_xgmi_get_topology_info(struct psp_context *psp, 1304 int number_devices, 1305 struct psp_xgmi_topology_info *topology, 1306 bool get_extended_data) 1307 { 1308 struct ta_xgmi_shared_memory *xgmi_cmd; 1309 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1310 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1311 int i; 1312 int ret; 1313 1314 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1315 return -EINVAL; 1316 1317 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1318 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1319 xgmi_cmd->flag_extend_link_record = get_extended_data; 1320 1321 /* Fill in the shared memory with topology information as input */ 1322 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1323 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1324 topology_info_input->num_nodes = number_devices; 1325 1326 for (i = 0; i < topology_info_input->num_nodes; i++) { 1327 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1328 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1329 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1330 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1331 } 1332 1333 /* Invoke xgmi ta to get the topology information */ 1334 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1335 if (ret) 1336 return ret; 1337 1338 /* Read the output topology information from the shared memory */ 1339 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1340 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1341 for (i = 0; i < topology->num_nodes; i++) { 1342 /* extended data will either be 0 or equal to non-extended data */ 1343 if (topology_info_output->nodes[i].num_hops) 1344 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1345 1346 /* non-extended data gets everything here so no need to update */ 1347 if (!get_extended_data) { 1348 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1349 topology->nodes[i].is_sharing_enabled = 1350 topology_info_output->nodes[i].is_sharing_enabled; 1351 topology->nodes[i].sdma_engine = 1352 topology_info_output->nodes[i].sdma_engine; 1353 } 1354 1355 } 1356 1357 /* Invoke xgmi ta again to get the link information */ 1358 if (psp_xgmi_peer_link_info_supported(psp)) { 1359 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1360 1361 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1362 1363 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1364 1365 if (ret) 1366 return ret; 1367 1368 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1369 for (i = 0; i < topology->num_nodes; i++) { 1370 /* accumulate num_links on extended data */ 1371 topology->nodes[i].num_links = get_extended_data ? 1372 topology->nodes[i].num_links + 1373 link_info_output->nodes[i].num_links : 1374 link_info_output->nodes[i].num_links; 1375 1376 /* reflect the topology information for bi-directionality */ 1377 if (psp->xgmi_context.supports_extended_data && 1378 get_extended_data && topology->nodes[i].num_hops) 1379 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1380 } 1381 } 1382 1383 return 0; 1384 } 1385 1386 int psp_xgmi_set_topology_info(struct psp_context *psp, 1387 int number_devices, 1388 struct psp_xgmi_topology_info *topology) 1389 { 1390 struct ta_xgmi_shared_memory *xgmi_cmd; 1391 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1392 int i; 1393 1394 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1395 return -EINVAL; 1396 1397 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1398 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1399 1400 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1401 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1402 topology_info_input->num_nodes = number_devices; 1403 1404 for (i = 0; i < topology_info_input->num_nodes; i++) { 1405 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1406 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1407 topology_info_input->nodes[i].is_sharing_enabled = 1; 1408 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1409 } 1410 1411 /* Invoke xgmi ta to set topology information */ 1412 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1413 } 1414 1415 // ras begin 1416 static void psp_ras_ta_check_status(struct psp_context *psp) 1417 { 1418 struct ta_ras_shared_memory *ras_cmd = 1419 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1420 1421 switch (ras_cmd->ras_status) { 1422 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1423 dev_warn(psp->adev->dev, 1424 "RAS WARNING: cmd failed due to unsupported ip\n"); 1425 break; 1426 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1427 dev_warn(psp->adev->dev, 1428 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1429 break; 1430 case TA_RAS_STATUS__SUCCESS: 1431 break; 1432 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1433 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1434 dev_warn(psp->adev->dev, 1435 "RAS WARNING: Inject error to critical region is not allowed\n"); 1436 break; 1437 default: 1438 dev_warn(psp->adev->dev, 1439 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1440 break; 1441 } 1442 } 1443 1444 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1445 { 1446 struct ta_ras_shared_memory *ras_cmd; 1447 int ret; 1448 1449 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1450 1451 /* 1452 * TODO: bypass the loading in sriov for now 1453 */ 1454 if (amdgpu_sriov_vf(psp->adev)) 1455 return 0; 1456 1457 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1458 1459 if (amdgpu_ras_intr_triggered()) 1460 return ret; 1461 1462 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1463 { 1464 DRM_WARN("RAS: Unsupported Interface"); 1465 return -EINVAL; 1466 } 1467 1468 if (!ret) { 1469 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1470 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1471 1472 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1473 } 1474 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1475 dev_warn(psp->adev->dev, 1476 "RAS internal register access blocked\n"); 1477 1478 psp_ras_ta_check_status(psp); 1479 } 1480 1481 return ret; 1482 } 1483 1484 int psp_ras_enable_features(struct psp_context *psp, 1485 union ta_ras_cmd_input *info, bool enable) 1486 { 1487 struct ta_ras_shared_memory *ras_cmd; 1488 int ret; 1489 1490 if (!psp->ras_context.context.initialized) 1491 return -EINVAL; 1492 1493 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1494 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1495 1496 if (enable) 1497 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1498 else 1499 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1500 1501 ras_cmd->ras_in_message = *info; 1502 1503 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1504 if (ret) 1505 return -EINVAL; 1506 1507 return 0; 1508 } 1509 1510 int psp_ras_terminate(struct psp_context *psp) 1511 { 1512 int ret; 1513 1514 /* 1515 * TODO: bypass the terminate in sriov for now 1516 */ 1517 if (amdgpu_sriov_vf(psp->adev)) 1518 return 0; 1519 1520 if (!psp->ras_context.context.initialized) 1521 return 0; 1522 1523 ret = psp_ta_unload(psp, &psp->ras_context.context); 1524 1525 psp->ras_context.context.initialized = false; 1526 1527 return ret; 1528 } 1529 1530 int psp_ras_initialize(struct psp_context *psp) 1531 { 1532 int ret; 1533 uint32_t boot_cfg = 0xFF; 1534 struct amdgpu_device *adev = psp->adev; 1535 struct ta_ras_shared_memory *ras_cmd; 1536 1537 /* 1538 * TODO: bypass the initialize in sriov for now 1539 */ 1540 if (amdgpu_sriov_vf(adev)) 1541 return 0; 1542 1543 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1544 !adev->psp.ras_context.context.bin_desc.start_addr) { 1545 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1546 return 0; 1547 } 1548 1549 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1550 /* query GECC enablement status from boot config 1551 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1552 */ 1553 ret = psp_boot_config_get(adev, &boot_cfg); 1554 if (ret) 1555 dev_warn(adev->dev, "PSP get boot config failed\n"); 1556 1557 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1558 if (!boot_cfg) { 1559 dev_info(adev->dev, "GECC is disabled\n"); 1560 } else { 1561 /* disable GECC in next boot cycle if ras is 1562 * disabled by module parameter amdgpu_ras_enable 1563 * and/or amdgpu_ras_mask, or boot_config_get call 1564 * is failed 1565 */ 1566 ret = psp_boot_config_set(adev, 0); 1567 if (ret) 1568 dev_warn(adev->dev, "PSP set boot config failed\n"); 1569 else 1570 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1571 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1572 } 1573 } else { 1574 if (1 == boot_cfg) { 1575 dev_info(adev->dev, "GECC is enabled\n"); 1576 } else { 1577 /* enable GECC in next boot cycle if it is disabled 1578 * in boot config, or force enable GECC if failed to 1579 * get boot configuration 1580 */ 1581 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1582 if (ret) 1583 dev_warn(adev->dev, "PSP set boot config failed\n"); 1584 else 1585 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1586 } 1587 } 1588 } 1589 1590 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1591 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1592 1593 if (!psp->ras_context.context.mem_context.shared_buf) { 1594 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1595 if (ret) 1596 return ret; 1597 } 1598 1599 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1600 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1601 1602 if (amdgpu_ras_is_poison_mode_supported(adev)) 1603 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1604 if (!adev->gmc.xgmi.connected_to_cpu) 1605 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1606 1607 ret = psp_ta_load(psp, &psp->ras_context.context); 1608 1609 if (!ret && !ras_cmd->ras_status) 1610 psp->ras_context.context.initialized = true; 1611 else { 1612 if (ras_cmd->ras_status) 1613 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1614 1615 /* fail to load RAS TA */ 1616 psp->ras_context.context.initialized = false; 1617 } 1618 1619 return ret; 1620 } 1621 1622 int psp_ras_trigger_error(struct psp_context *psp, 1623 struct ta_ras_trigger_error_input *info) 1624 { 1625 struct ta_ras_shared_memory *ras_cmd; 1626 int ret; 1627 1628 if (!psp->ras_context.context.initialized) 1629 return -EINVAL; 1630 1631 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1632 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1633 1634 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1635 ras_cmd->ras_in_message.trigger_error = *info; 1636 1637 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1638 if (ret) 1639 return -EINVAL; 1640 1641 /* If err_event_athub occurs error inject was successful, however 1642 return status from TA is no long reliable */ 1643 if (amdgpu_ras_intr_triggered()) 1644 return 0; 1645 1646 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1647 return -EACCES; 1648 else if (ras_cmd->ras_status) 1649 return -EINVAL; 1650 1651 return 0; 1652 } 1653 // ras end 1654 1655 // HDCP start 1656 static int psp_hdcp_initialize(struct psp_context *psp) 1657 { 1658 int ret; 1659 1660 /* 1661 * TODO: bypass the initialize in sriov for now 1662 */ 1663 if (amdgpu_sriov_vf(psp->adev)) 1664 return 0; 1665 1666 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1667 !psp->hdcp_context.context.bin_desc.start_addr) { 1668 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1669 return 0; 1670 } 1671 1672 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1673 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1674 1675 if (!psp->hdcp_context.context.initialized) { 1676 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1677 if (ret) 1678 return ret; 1679 } 1680 1681 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1682 if (!ret) { 1683 psp->hdcp_context.context.initialized = true; 1684 mutex_init(&psp->hdcp_context.mutex); 1685 } 1686 1687 return ret; 1688 } 1689 1690 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1691 { 1692 /* 1693 * TODO: bypass the loading in sriov for now 1694 */ 1695 if (amdgpu_sriov_vf(psp->adev)) 1696 return 0; 1697 1698 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1699 } 1700 1701 static int psp_hdcp_terminate(struct psp_context *psp) 1702 { 1703 int ret; 1704 1705 /* 1706 * TODO: bypass the terminate in sriov for now 1707 */ 1708 if (amdgpu_sriov_vf(psp->adev)) 1709 return 0; 1710 1711 if (!psp->hdcp_context.context.initialized) 1712 return 0; 1713 1714 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1715 1716 psp->hdcp_context.context.initialized = false; 1717 1718 return ret; 1719 } 1720 // HDCP end 1721 1722 // DTM start 1723 static int psp_dtm_initialize(struct psp_context *psp) 1724 { 1725 int ret; 1726 1727 /* 1728 * TODO: bypass the initialize in sriov for now 1729 */ 1730 if (amdgpu_sriov_vf(psp->adev)) 1731 return 0; 1732 1733 if (!psp->dtm_context.context.bin_desc.size_bytes || 1734 !psp->dtm_context.context.bin_desc.start_addr) { 1735 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1736 return 0; 1737 } 1738 1739 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1740 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1741 1742 if (!psp->dtm_context.context.initialized) { 1743 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1744 if (ret) 1745 return ret; 1746 } 1747 1748 ret = psp_ta_load(psp, &psp->dtm_context.context); 1749 if (!ret) { 1750 psp->dtm_context.context.initialized = true; 1751 mutex_init(&psp->dtm_context.mutex); 1752 } 1753 1754 return ret; 1755 } 1756 1757 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1758 { 1759 /* 1760 * TODO: bypass the loading in sriov for now 1761 */ 1762 if (amdgpu_sriov_vf(psp->adev)) 1763 return 0; 1764 1765 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1766 } 1767 1768 static int psp_dtm_terminate(struct psp_context *psp) 1769 { 1770 int ret; 1771 1772 /* 1773 * TODO: bypass the terminate in sriov for now 1774 */ 1775 if (amdgpu_sriov_vf(psp->adev)) 1776 return 0; 1777 1778 if (!psp->dtm_context.context.initialized) 1779 return 0; 1780 1781 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1782 1783 psp->dtm_context.context.initialized = false; 1784 1785 return ret; 1786 } 1787 // DTM end 1788 1789 // RAP start 1790 static int psp_rap_initialize(struct psp_context *psp) 1791 { 1792 int ret; 1793 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1794 1795 /* 1796 * TODO: bypass the initialize in sriov for now 1797 */ 1798 if (amdgpu_sriov_vf(psp->adev)) 1799 return 0; 1800 1801 if (!psp->rap_context.context.bin_desc.size_bytes || 1802 !psp->rap_context.context.bin_desc.start_addr) { 1803 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1804 return 0; 1805 } 1806 1807 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1808 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1809 1810 if (!psp->rap_context.context.initialized) { 1811 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1812 if (ret) 1813 return ret; 1814 } 1815 1816 ret = psp_ta_load(psp, &psp->rap_context.context); 1817 if (!ret) { 1818 psp->rap_context.context.initialized = true; 1819 mutex_init(&psp->rap_context.mutex); 1820 } else 1821 return ret; 1822 1823 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1824 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1825 psp_rap_terminate(psp); 1826 /* free rap shared memory */ 1827 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1828 1829 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1830 ret, status); 1831 1832 return ret; 1833 } 1834 1835 return 0; 1836 } 1837 1838 static int psp_rap_terminate(struct psp_context *psp) 1839 { 1840 int ret; 1841 1842 if (!psp->rap_context.context.initialized) 1843 return 0; 1844 1845 ret = psp_ta_unload(psp, &psp->rap_context.context); 1846 1847 psp->rap_context.context.initialized = false; 1848 1849 return ret; 1850 } 1851 1852 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1853 { 1854 struct ta_rap_shared_memory *rap_cmd; 1855 int ret = 0; 1856 1857 if (!psp->rap_context.context.initialized) 1858 return 0; 1859 1860 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1861 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1862 return -EINVAL; 1863 1864 mutex_lock(&psp->rap_context.mutex); 1865 1866 rap_cmd = (struct ta_rap_shared_memory *) 1867 psp->rap_context.context.mem_context.shared_buf; 1868 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1869 1870 rap_cmd->cmd_id = ta_cmd_id; 1871 rap_cmd->validation_method_id = METHOD_A; 1872 1873 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1874 if (ret) 1875 goto out_unlock; 1876 1877 if (status) 1878 *status = rap_cmd->rap_status; 1879 1880 out_unlock: 1881 mutex_unlock(&psp->rap_context.mutex); 1882 1883 return ret; 1884 } 1885 // RAP end 1886 1887 /* securedisplay start */ 1888 static int psp_securedisplay_initialize(struct psp_context *psp) 1889 { 1890 int ret; 1891 struct ta_securedisplay_cmd *securedisplay_cmd; 1892 1893 /* 1894 * TODO: bypass the initialize in sriov for now 1895 */ 1896 if (amdgpu_sriov_vf(psp->adev)) 1897 return 0; 1898 1899 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1900 !psp->securedisplay_context.context.bin_desc.start_addr) { 1901 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1902 return 0; 1903 } 1904 1905 psp->securedisplay_context.context.mem_context.shared_mem_size = 1906 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1907 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1908 1909 if (!psp->securedisplay_context.context.initialized) { 1910 ret = psp_ta_init_shared_buf(psp, 1911 &psp->securedisplay_context.context.mem_context); 1912 if (ret) 1913 return ret; 1914 } 1915 1916 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 1917 if (!ret) { 1918 psp->securedisplay_context.context.initialized = true; 1919 mutex_init(&psp->securedisplay_context.mutex); 1920 } else 1921 return ret; 1922 1923 mutex_lock(&psp->securedisplay_context.mutex); 1924 1925 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1926 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1927 1928 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1929 1930 mutex_unlock(&psp->securedisplay_context.mutex); 1931 1932 if (ret) { 1933 psp_securedisplay_terminate(psp); 1934 /* free securedisplay shared memory */ 1935 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1936 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1937 return -EINVAL; 1938 } 1939 1940 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1941 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1942 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1943 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1944 } 1945 1946 return 0; 1947 } 1948 1949 static int psp_securedisplay_terminate(struct psp_context *psp) 1950 { 1951 int ret; 1952 1953 /* 1954 * TODO:bypass the terminate in sriov for now 1955 */ 1956 if (amdgpu_sriov_vf(psp->adev)) 1957 return 0; 1958 1959 if (!psp->securedisplay_context.context.initialized) 1960 return 0; 1961 1962 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 1963 1964 psp->securedisplay_context.context.initialized = false; 1965 1966 return ret; 1967 } 1968 1969 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1970 { 1971 int ret; 1972 1973 if (!psp->securedisplay_context.context.initialized) 1974 return -EINVAL; 1975 1976 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1977 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1978 return -EINVAL; 1979 1980 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1981 1982 return ret; 1983 } 1984 /* SECUREDISPLAY end */ 1985 1986 static int psp_hw_start(struct psp_context *psp) 1987 { 1988 struct amdgpu_device *adev = psp->adev; 1989 int ret; 1990 1991 if (!amdgpu_sriov_vf(adev)) { 1992 if ((is_psp_fw_valid(psp->kdb)) && 1993 (psp->funcs->bootloader_load_kdb != NULL)) { 1994 ret = psp_bootloader_load_kdb(psp); 1995 if (ret) { 1996 DRM_ERROR("PSP load kdb failed!\n"); 1997 return ret; 1998 } 1999 } 2000 2001 if ((is_psp_fw_valid(psp->spl)) && 2002 (psp->funcs->bootloader_load_spl != NULL)) { 2003 ret = psp_bootloader_load_spl(psp); 2004 if (ret) { 2005 DRM_ERROR("PSP load spl failed!\n"); 2006 return ret; 2007 } 2008 } 2009 2010 if ((is_psp_fw_valid(psp->sys)) && 2011 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2012 ret = psp_bootloader_load_sysdrv(psp); 2013 if (ret) { 2014 DRM_ERROR("PSP load sys drv failed!\n"); 2015 return ret; 2016 } 2017 } 2018 2019 if ((is_psp_fw_valid(psp->soc_drv)) && 2020 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2021 ret = psp_bootloader_load_soc_drv(psp); 2022 if (ret) { 2023 DRM_ERROR("PSP load soc drv failed!\n"); 2024 return ret; 2025 } 2026 } 2027 2028 if ((is_psp_fw_valid(psp->intf_drv)) && 2029 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2030 ret = psp_bootloader_load_intf_drv(psp); 2031 if (ret) { 2032 DRM_ERROR("PSP load intf drv failed!\n"); 2033 return ret; 2034 } 2035 } 2036 2037 if ((is_psp_fw_valid(psp->dbg_drv)) && 2038 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2039 ret = psp_bootloader_load_dbg_drv(psp); 2040 if (ret) { 2041 DRM_ERROR("PSP load dbg drv failed!\n"); 2042 return ret; 2043 } 2044 } 2045 2046 if ((is_psp_fw_valid(psp->ras_drv)) && 2047 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2048 ret = psp_bootloader_load_ras_drv(psp); 2049 if (ret) { 2050 DRM_ERROR("PSP load ras_drv failed!\n"); 2051 return ret; 2052 } 2053 } 2054 2055 if ((is_psp_fw_valid(psp->sos)) && 2056 (psp->funcs->bootloader_load_sos != NULL)) { 2057 ret = psp_bootloader_load_sos(psp); 2058 if (ret) { 2059 DRM_ERROR("PSP load sos failed!\n"); 2060 return ret; 2061 } 2062 } 2063 } 2064 2065 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2066 if (ret) { 2067 DRM_ERROR("PSP create ring failed!\n"); 2068 return ret; 2069 } 2070 2071 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2072 goto skip_pin_bo; 2073 2074 ret = psp_tmr_init(psp); 2075 if (ret) { 2076 DRM_ERROR("PSP tmr init failed!\n"); 2077 return ret; 2078 } 2079 2080 skip_pin_bo: 2081 /* 2082 * For ASICs with DF Cstate management centralized 2083 * to PMFW, TMR setup should be performed after PMFW 2084 * loaded and before other non-psp firmware loaded. 2085 */ 2086 if (psp->pmfw_centralized_cstate_management) { 2087 ret = psp_load_smu_fw(psp); 2088 if (ret) 2089 return ret; 2090 } 2091 2092 ret = psp_tmr_load(psp); 2093 if (ret) { 2094 DRM_ERROR("PSP load tmr failed!\n"); 2095 return ret; 2096 } 2097 2098 return 0; 2099 } 2100 2101 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2102 enum psp_gfx_fw_type *type) 2103 { 2104 switch (ucode->ucode_id) { 2105 case AMDGPU_UCODE_ID_CAP: 2106 *type = GFX_FW_TYPE_CAP; 2107 break; 2108 case AMDGPU_UCODE_ID_SDMA0: 2109 *type = GFX_FW_TYPE_SDMA0; 2110 break; 2111 case AMDGPU_UCODE_ID_SDMA1: 2112 *type = GFX_FW_TYPE_SDMA1; 2113 break; 2114 case AMDGPU_UCODE_ID_SDMA2: 2115 *type = GFX_FW_TYPE_SDMA2; 2116 break; 2117 case AMDGPU_UCODE_ID_SDMA3: 2118 *type = GFX_FW_TYPE_SDMA3; 2119 break; 2120 case AMDGPU_UCODE_ID_SDMA4: 2121 *type = GFX_FW_TYPE_SDMA4; 2122 break; 2123 case AMDGPU_UCODE_ID_SDMA5: 2124 *type = GFX_FW_TYPE_SDMA5; 2125 break; 2126 case AMDGPU_UCODE_ID_SDMA6: 2127 *type = GFX_FW_TYPE_SDMA6; 2128 break; 2129 case AMDGPU_UCODE_ID_SDMA7: 2130 *type = GFX_FW_TYPE_SDMA7; 2131 break; 2132 case AMDGPU_UCODE_ID_CP_MES: 2133 *type = GFX_FW_TYPE_CP_MES; 2134 break; 2135 case AMDGPU_UCODE_ID_CP_MES_DATA: 2136 *type = GFX_FW_TYPE_MES_STACK; 2137 break; 2138 case AMDGPU_UCODE_ID_CP_MES1: 2139 *type = GFX_FW_TYPE_CP_MES_KIQ; 2140 break; 2141 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2142 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2143 break; 2144 case AMDGPU_UCODE_ID_CP_CE: 2145 *type = GFX_FW_TYPE_CP_CE; 2146 break; 2147 case AMDGPU_UCODE_ID_CP_PFP: 2148 *type = GFX_FW_TYPE_CP_PFP; 2149 break; 2150 case AMDGPU_UCODE_ID_CP_ME: 2151 *type = GFX_FW_TYPE_CP_ME; 2152 break; 2153 case AMDGPU_UCODE_ID_CP_MEC1: 2154 *type = GFX_FW_TYPE_CP_MEC; 2155 break; 2156 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2157 *type = GFX_FW_TYPE_CP_MEC_ME1; 2158 break; 2159 case AMDGPU_UCODE_ID_CP_MEC2: 2160 *type = GFX_FW_TYPE_CP_MEC; 2161 break; 2162 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2163 *type = GFX_FW_TYPE_CP_MEC_ME2; 2164 break; 2165 case AMDGPU_UCODE_ID_RLC_P: 2166 *type = GFX_FW_TYPE_RLC_P; 2167 break; 2168 case AMDGPU_UCODE_ID_RLC_V: 2169 *type = GFX_FW_TYPE_RLC_V; 2170 break; 2171 case AMDGPU_UCODE_ID_RLC_G: 2172 *type = GFX_FW_TYPE_RLC_G; 2173 break; 2174 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2175 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2176 break; 2177 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2178 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2179 break; 2180 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2181 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2182 break; 2183 case AMDGPU_UCODE_ID_RLC_IRAM: 2184 *type = GFX_FW_TYPE_RLC_IRAM; 2185 break; 2186 case AMDGPU_UCODE_ID_RLC_DRAM: 2187 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2188 break; 2189 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2190 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2191 break; 2192 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2193 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2194 break; 2195 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2196 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2197 break; 2198 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2199 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2200 break; 2201 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2202 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2203 break; 2204 case AMDGPU_UCODE_ID_SMC: 2205 *type = GFX_FW_TYPE_SMU; 2206 break; 2207 case AMDGPU_UCODE_ID_PPTABLE: 2208 *type = GFX_FW_TYPE_PPTABLE; 2209 break; 2210 case AMDGPU_UCODE_ID_UVD: 2211 *type = GFX_FW_TYPE_UVD; 2212 break; 2213 case AMDGPU_UCODE_ID_UVD1: 2214 *type = GFX_FW_TYPE_UVD1; 2215 break; 2216 case AMDGPU_UCODE_ID_VCE: 2217 *type = GFX_FW_TYPE_VCE; 2218 break; 2219 case AMDGPU_UCODE_ID_VCN: 2220 *type = GFX_FW_TYPE_VCN; 2221 break; 2222 case AMDGPU_UCODE_ID_VCN1: 2223 *type = GFX_FW_TYPE_VCN1; 2224 break; 2225 case AMDGPU_UCODE_ID_DMCU_ERAM: 2226 *type = GFX_FW_TYPE_DMCU_ERAM; 2227 break; 2228 case AMDGPU_UCODE_ID_DMCU_INTV: 2229 *type = GFX_FW_TYPE_DMCU_ISR; 2230 break; 2231 case AMDGPU_UCODE_ID_VCN0_RAM: 2232 *type = GFX_FW_TYPE_VCN0_RAM; 2233 break; 2234 case AMDGPU_UCODE_ID_VCN1_RAM: 2235 *type = GFX_FW_TYPE_VCN1_RAM; 2236 break; 2237 case AMDGPU_UCODE_ID_DMCUB: 2238 *type = GFX_FW_TYPE_DMUB; 2239 break; 2240 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2241 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2242 break; 2243 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2244 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2245 break; 2246 case AMDGPU_UCODE_ID_IMU_I: 2247 *type = GFX_FW_TYPE_IMU_I; 2248 break; 2249 case AMDGPU_UCODE_ID_IMU_D: 2250 *type = GFX_FW_TYPE_IMU_D; 2251 break; 2252 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2253 *type = GFX_FW_TYPE_RS64_PFP; 2254 break; 2255 case AMDGPU_UCODE_ID_CP_RS64_ME: 2256 *type = GFX_FW_TYPE_RS64_ME; 2257 break; 2258 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2259 *type = GFX_FW_TYPE_RS64_MEC; 2260 break; 2261 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2262 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2263 break; 2264 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2265 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2266 break; 2267 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2268 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2269 break; 2270 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2271 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2272 break; 2273 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2274 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2275 break; 2276 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2277 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2278 break; 2279 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2280 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2281 break; 2282 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2283 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2284 break; 2285 case AMDGPU_UCODE_ID_MAXIMUM: 2286 default: 2287 return -EINVAL; 2288 } 2289 2290 return 0; 2291 } 2292 2293 static void psp_print_fw_hdr(struct psp_context *psp, 2294 struct amdgpu_firmware_info *ucode) 2295 { 2296 struct amdgpu_device *adev = psp->adev; 2297 struct common_firmware_header *hdr; 2298 2299 switch (ucode->ucode_id) { 2300 case AMDGPU_UCODE_ID_SDMA0: 2301 case AMDGPU_UCODE_ID_SDMA1: 2302 case AMDGPU_UCODE_ID_SDMA2: 2303 case AMDGPU_UCODE_ID_SDMA3: 2304 case AMDGPU_UCODE_ID_SDMA4: 2305 case AMDGPU_UCODE_ID_SDMA5: 2306 case AMDGPU_UCODE_ID_SDMA6: 2307 case AMDGPU_UCODE_ID_SDMA7: 2308 hdr = (struct common_firmware_header *) 2309 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2310 amdgpu_ucode_print_sdma_hdr(hdr); 2311 break; 2312 case AMDGPU_UCODE_ID_CP_CE: 2313 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2314 amdgpu_ucode_print_gfx_hdr(hdr); 2315 break; 2316 case AMDGPU_UCODE_ID_CP_PFP: 2317 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2318 amdgpu_ucode_print_gfx_hdr(hdr); 2319 break; 2320 case AMDGPU_UCODE_ID_CP_ME: 2321 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2322 amdgpu_ucode_print_gfx_hdr(hdr); 2323 break; 2324 case AMDGPU_UCODE_ID_CP_MEC1: 2325 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2326 amdgpu_ucode_print_gfx_hdr(hdr); 2327 break; 2328 case AMDGPU_UCODE_ID_RLC_G: 2329 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2330 amdgpu_ucode_print_rlc_hdr(hdr); 2331 break; 2332 case AMDGPU_UCODE_ID_SMC: 2333 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2334 amdgpu_ucode_print_smc_hdr(hdr); 2335 break; 2336 default: 2337 break; 2338 } 2339 } 2340 2341 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2342 struct psp_gfx_cmd_resp *cmd) 2343 { 2344 int ret; 2345 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2346 2347 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2348 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2349 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2350 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2351 2352 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2353 if (ret) 2354 DRM_ERROR("Unknown firmware type\n"); 2355 2356 return ret; 2357 } 2358 2359 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2360 struct amdgpu_firmware_info *ucode) 2361 { 2362 int ret = 0; 2363 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2364 2365 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2366 if (!ret) { 2367 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2368 psp->fence_buf_mc_addr); 2369 } 2370 2371 release_psp_cmd_buf(psp); 2372 2373 return ret; 2374 } 2375 2376 static int psp_load_smu_fw(struct psp_context *psp) 2377 { 2378 int ret; 2379 struct amdgpu_device *adev = psp->adev; 2380 struct amdgpu_firmware_info *ucode = 2381 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2382 struct amdgpu_ras *ras = psp->ras_context.ras; 2383 2384 /* 2385 * Skip SMU FW reloading in case of using BACO for runpm only, 2386 * as SMU is always alive. 2387 */ 2388 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2389 return 0; 2390 2391 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2392 return 0; 2393 2394 if ((amdgpu_in_reset(adev) && 2395 ras && adev->ras_enabled && 2396 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2397 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2398 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2399 if (ret) { 2400 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2401 } 2402 } 2403 2404 ret = psp_execute_non_psp_fw_load(psp, ucode); 2405 2406 if (ret) 2407 DRM_ERROR("PSP load smu failed!\n"); 2408 2409 return ret; 2410 } 2411 2412 static bool fw_load_skip_check(struct psp_context *psp, 2413 struct amdgpu_firmware_info *ucode) 2414 { 2415 if (!ucode->fw || !ucode->ucode_size) 2416 return true; 2417 2418 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2419 (psp_smu_reload_quirk(psp) || 2420 psp->autoload_supported || 2421 psp->pmfw_centralized_cstate_management)) 2422 return true; 2423 2424 if (amdgpu_sriov_vf(psp->adev) && 2425 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2426 return true; 2427 2428 if (psp->autoload_supported && 2429 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2430 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2431 /* skip mec JT when autoload is enabled */ 2432 return true; 2433 2434 return false; 2435 } 2436 2437 int psp_load_fw_list(struct psp_context *psp, 2438 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2439 { 2440 int ret = 0, i; 2441 struct amdgpu_firmware_info *ucode; 2442 2443 for (i = 0; i < ucode_count; ++i) { 2444 ucode = ucode_list[i]; 2445 psp_print_fw_hdr(psp, ucode); 2446 ret = psp_execute_non_psp_fw_load(psp, ucode); 2447 if (ret) 2448 return ret; 2449 } 2450 return ret; 2451 } 2452 2453 static int psp_load_non_psp_fw(struct psp_context *psp) 2454 { 2455 int i, ret; 2456 struct amdgpu_firmware_info *ucode; 2457 struct amdgpu_device *adev = psp->adev; 2458 2459 if (psp->autoload_supported && 2460 !psp->pmfw_centralized_cstate_management) { 2461 ret = psp_load_smu_fw(psp); 2462 if (ret) 2463 return ret; 2464 } 2465 2466 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2467 ucode = &adev->firmware.ucode[i]; 2468 2469 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2470 !fw_load_skip_check(psp, ucode)) { 2471 ret = psp_load_smu_fw(psp); 2472 if (ret) 2473 return ret; 2474 continue; 2475 } 2476 2477 if (fw_load_skip_check(psp, ucode)) 2478 continue; 2479 2480 if (psp->autoload_supported && 2481 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2482 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2483 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2484 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2485 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2486 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2487 /* PSP only receive one SDMA fw for sienna_cichlid, 2488 * as all four sdma fw are same */ 2489 continue; 2490 2491 psp_print_fw_hdr(psp, ucode); 2492 2493 ret = psp_execute_non_psp_fw_load(psp, ucode); 2494 if (ret) 2495 return ret; 2496 2497 /* Start rlc autoload after psp recieved all the gfx firmware */ 2498 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2499 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2500 ret = psp_rlc_autoload_start(psp); 2501 if (ret) { 2502 DRM_ERROR("Failed to start rlc autoload\n"); 2503 return ret; 2504 } 2505 } 2506 } 2507 2508 return 0; 2509 } 2510 2511 static int psp_load_fw(struct amdgpu_device *adev) 2512 { 2513 int ret; 2514 struct psp_context *psp = &adev->psp; 2515 2516 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2517 /* should not destroy ring, only stop */ 2518 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2519 } else { 2520 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2521 2522 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2523 if (ret) { 2524 DRM_ERROR("PSP ring init failed!\n"); 2525 goto failed; 2526 } 2527 } 2528 2529 ret = psp_hw_start(psp); 2530 if (ret) 2531 goto failed; 2532 2533 ret = psp_load_non_psp_fw(psp); 2534 if (ret) 2535 goto failed1; 2536 2537 ret = psp_asd_initialize(psp); 2538 if (ret) { 2539 DRM_ERROR("PSP load asd failed!\n"); 2540 goto failed1; 2541 } 2542 2543 ret = psp_rl_load(adev); 2544 if (ret) { 2545 DRM_ERROR("PSP load RL failed!\n"); 2546 goto failed1; 2547 } 2548 2549 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2550 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2551 ret = psp_xgmi_initialize(psp, false, true); 2552 /* Warning the XGMI seesion initialize failure 2553 * Instead of stop driver initialization 2554 */ 2555 if (ret) 2556 dev_err(psp->adev->dev, 2557 "XGMI: Failed to initialize XGMI session\n"); 2558 } 2559 } 2560 2561 if (psp->ta_fw) { 2562 ret = psp_ras_initialize(psp); 2563 if (ret) 2564 dev_err(psp->adev->dev, 2565 "RAS: Failed to initialize RAS\n"); 2566 2567 ret = psp_hdcp_initialize(psp); 2568 if (ret) 2569 dev_err(psp->adev->dev, 2570 "HDCP: Failed to initialize HDCP\n"); 2571 2572 ret = psp_dtm_initialize(psp); 2573 if (ret) 2574 dev_err(psp->adev->dev, 2575 "DTM: Failed to initialize DTM\n"); 2576 2577 ret = psp_rap_initialize(psp); 2578 if (ret) 2579 dev_err(psp->adev->dev, 2580 "RAP: Failed to initialize RAP\n"); 2581 2582 ret = psp_securedisplay_initialize(psp); 2583 if (ret) 2584 dev_err(psp->adev->dev, 2585 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2586 } 2587 2588 return 0; 2589 2590 failed1: 2591 psp_free_shared_bufs(psp); 2592 failed: 2593 /* 2594 * all cleanup jobs (xgmi terminate, ras terminate, 2595 * ring destroy, cmd/fence/fw buffers destory, 2596 * psp->cmd destory) are delayed to psp_hw_fini 2597 */ 2598 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2599 return ret; 2600 } 2601 2602 static int psp_hw_init(void *handle) 2603 { 2604 int ret; 2605 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2606 2607 mutex_lock(&adev->firmware.mutex); 2608 /* 2609 * This sequence is just used on hw_init only once, no need on 2610 * resume. 2611 */ 2612 ret = amdgpu_ucode_init_bo(adev); 2613 if (ret) 2614 goto failed; 2615 2616 ret = psp_load_fw(adev); 2617 if (ret) { 2618 DRM_ERROR("PSP firmware loading failed\n"); 2619 goto failed; 2620 } 2621 2622 mutex_unlock(&adev->firmware.mutex); 2623 return 0; 2624 2625 failed: 2626 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2627 mutex_unlock(&adev->firmware.mutex); 2628 return -EINVAL; 2629 } 2630 2631 static int psp_hw_fini(void *handle) 2632 { 2633 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2634 struct psp_context *psp = &adev->psp; 2635 2636 if (psp->ta_fw) { 2637 psp_ras_terminate(psp); 2638 psp_securedisplay_terminate(psp); 2639 psp_rap_terminate(psp); 2640 psp_dtm_terminate(psp); 2641 psp_hdcp_terminate(psp); 2642 2643 if (adev->gmc.xgmi.num_physical_nodes > 1) 2644 psp_xgmi_terminate(psp); 2645 } 2646 2647 psp_asd_terminate(psp); 2648 psp_tmr_terminate(psp); 2649 2650 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2651 2652 psp_free_shared_bufs(psp); 2653 2654 return 0; 2655 } 2656 2657 static int psp_suspend(void *handle) 2658 { 2659 int ret = 0; 2660 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2661 struct psp_context *psp = &adev->psp; 2662 2663 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2664 psp->xgmi_context.context.initialized) { 2665 ret = psp_xgmi_terminate(psp); 2666 if (ret) { 2667 DRM_ERROR("Failed to terminate xgmi ta\n"); 2668 goto out; 2669 } 2670 } 2671 2672 if (psp->ta_fw) { 2673 ret = psp_ras_terminate(psp); 2674 if (ret) { 2675 DRM_ERROR("Failed to terminate ras ta\n"); 2676 goto out; 2677 } 2678 ret = psp_hdcp_terminate(psp); 2679 if (ret) { 2680 DRM_ERROR("Failed to terminate hdcp ta\n"); 2681 goto out; 2682 } 2683 ret = psp_dtm_terminate(psp); 2684 if (ret) { 2685 DRM_ERROR("Failed to terminate dtm ta\n"); 2686 goto out; 2687 } 2688 ret = psp_rap_terminate(psp); 2689 if (ret) { 2690 DRM_ERROR("Failed to terminate rap ta\n"); 2691 goto out; 2692 } 2693 ret = psp_securedisplay_terminate(psp); 2694 if (ret) { 2695 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2696 goto out; 2697 } 2698 } 2699 2700 ret = psp_asd_terminate(psp); 2701 if (ret) { 2702 DRM_ERROR("Failed to terminate asd\n"); 2703 goto out; 2704 } 2705 2706 ret = psp_tmr_terminate(psp); 2707 if (ret) { 2708 DRM_ERROR("Failed to terminate tmr\n"); 2709 goto out; 2710 } 2711 2712 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2713 if (ret) { 2714 DRM_ERROR("PSP ring stop failed\n"); 2715 } 2716 2717 out: 2718 return ret; 2719 } 2720 2721 static int psp_resume(void *handle) 2722 { 2723 int ret; 2724 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2725 struct psp_context *psp = &adev->psp; 2726 2727 DRM_INFO("PSP is resuming...\n"); 2728 2729 if (psp->mem_train_ctx.enable_mem_training) { 2730 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2731 if (ret) { 2732 DRM_ERROR("Failed to process memory training!\n"); 2733 return ret; 2734 } 2735 } 2736 2737 mutex_lock(&adev->firmware.mutex); 2738 2739 ret = psp_hw_start(psp); 2740 if (ret) 2741 goto failed; 2742 2743 ret = psp_load_non_psp_fw(psp); 2744 if (ret) 2745 goto failed; 2746 2747 ret = psp_asd_initialize(psp); 2748 if (ret) { 2749 DRM_ERROR("PSP load asd failed!\n"); 2750 goto failed; 2751 } 2752 2753 ret = psp_rl_load(adev); 2754 if (ret) { 2755 dev_err(adev->dev, "PSP load RL failed!\n"); 2756 goto failed; 2757 } 2758 2759 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2760 ret = psp_xgmi_initialize(psp, false, true); 2761 /* Warning the XGMI seesion initialize failure 2762 * Instead of stop driver initialization 2763 */ 2764 if (ret) 2765 dev_err(psp->adev->dev, 2766 "XGMI: Failed to initialize XGMI session\n"); 2767 } 2768 2769 if (psp->ta_fw) { 2770 ret = psp_ras_initialize(psp); 2771 if (ret) 2772 dev_err(psp->adev->dev, 2773 "RAS: Failed to initialize RAS\n"); 2774 2775 ret = psp_hdcp_initialize(psp); 2776 if (ret) 2777 dev_err(psp->adev->dev, 2778 "HDCP: Failed to initialize HDCP\n"); 2779 2780 ret = psp_dtm_initialize(psp); 2781 if (ret) 2782 dev_err(psp->adev->dev, 2783 "DTM: Failed to initialize DTM\n"); 2784 2785 ret = psp_rap_initialize(psp); 2786 if (ret) 2787 dev_err(psp->adev->dev, 2788 "RAP: Failed to initialize RAP\n"); 2789 2790 ret = psp_securedisplay_initialize(psp); 2791 if (ret) 2792 dev_err(psp->adev->dev, 2793 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2794 } 2795 2796 mutex_unlock(&adev->firmware.mutex); 2797 2798 return 0; 2799 2800 failed: 2801 DRM_ERROR("PSP resume failed\n"); 2802 mutex_unlock(&adev->firmware.mutex); 2803 return ret; 2804 } 2805 2806 int psp_gpu_reset(struct amdgpu_device *adev) 2807 { 2808 int ret; 2809 2810 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2811 return 0; 2812 2813 mutex_lock(&adev->psp.mutex); 2814 ret = psp_mode1_reset(&adev->psp); 2815 mutex_unlock(&adev->psp.mutex); 2816 2817 return ret; 2818 } 2819 2820 int psp_rlc_autoload_start(struct psp_context *psp) 2821 { 2822 int ret; 2823 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2824 2825 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2826 2827 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2828 psp->fence_buf_mc_addr); 2829 2830 release_psp_cmd_buf(psp); 2831 2832 return ret; 2833 } 2834 2835 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2836 uint64_t cmd_gpu_addr, int cmd_size) 2837 { 2838 struct amdgpu_firmware_info ucode = {0}; 2839 2840 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2841 AMDGPU_UCODE_ID_VCN0_RAM; 2842 ucode.mc_addr = cmd_gpu_addr; 2843 ucode.ucode_size = cmd_size; 2844 2845 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2846 } 2847 2848 int psp_ring_cmd_submit(struct psp_context *psp, 2849 uint64_t cmd_buf_mc_addr, 2850 uint64_t fence_mc_addr, 2851 int index) 2852 { 2853 unsigned int psp_write_ptr_reg = 0; 2854 struct psp_gfx_rb_frame *write_frame; 2855 struct psp_ring *ring = &psp->km_ring; 2856 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2857 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2858 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2859 struct amdgpu_device *adev = psp->adev; 2860 uint32_t ring_size_dw = ring->ring_size / 4; 2861 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2862 2863 /* KM (GPCOM) prepare write pointer */ 2864 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2865 2866 /* Update KM RB frame pointer to new frame */ 2867 /* write_frame ptr increments by size of rb_frame in bytes */ 2868 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2869 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2870 write_frame = ring_buffer_start; 2871 else 2872 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2873 /* Check invalid write_frame ptr address */ 2874 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2875 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2876 ring_buffer_start, ring_buffer_end, write_frame); 2877 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2878 return -EINVAL; 2879 } 2880 2881 /* Initialize KM RB frame */ 2882 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2883 2884 /* Update KM RB frame */ 2885 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2886 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2887 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2888 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2889 write_frame->fence_value = index; 2890 amdgpu_device_flush_hdp(adev, NULL); 2891 2892 /* Update the write Pointer in DWORDs */ 2893 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2894 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2895 return 0; 2896 } 2897 2898 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 2899 { 2900 struct amdgpu_device *adev = psp->adev; 2901 char fw_name[PSP_FW_NAME_LEN]; 2902 const struct psp_firmware_header_v1_0 *asd_hdr; 2903 int err = 0; 2904 2905 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2906 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name); 2907 if (err) 2908 goto out; 2909 2910 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2911 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2912 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2913 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2914 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2915 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2916 return 0; 2917 out: 2918 amdgpu_ucode_release(&adev->psp.asd_fw); 2919 return err; 2920 } 2921 2922 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 2923 { 2924 struct amdgpu_device *adev = psp->adev; 2925 char fw_name[PSP_FW_NAME_LEN]; 2926 const struct psp_firmware_header_v1_0 *toc_hdr; 2927 int err = 0; 2928 2929 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2930 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 2931 if (err) 2932 goto out; 2933 2934 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2935 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2936 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2937 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2938 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2939 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2940 return 0; 2941 out: 2942 amdgpu_ucode_release(&adev->psp.toc_fw); 2943 return err; 2944 } 2945 2946 static int parse_sos_bin_descriptor(struct psp_context *psp, 2947 const struct psp_fw_bin_desc *desc, 2948 const struct psp_firmware_header_v2_0 *sos_hdr) 2949 { 2950 uint8_t *ucode_start_addr = NULL; 2951 2952 if (!psp || !desc || !sos_hdr) 2953 return -EINVAL; 2954 2955 ucode_start_addr = (uint8_t *)sos_hdr + 2956 le32_to_cpu(desc->offset_bytes) + 2957 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2958 2959 switch (desc->fw_type) { 2960 case PSP_FW_TYPE_PSP_SOS: 2961 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2962 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2963 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2964 psp->sos.start_addr = ucode_start_addr; 2965 break; 2966 case PSP_FW_TYPE_PSP_SYS_DRV: 2967 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2968 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2969 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2970 psp->sys.start_addr = ucode_start_addr; 2971 break; 2972 case PSP_FW_TYPE_PSP_KDB: 2973 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2974 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2975 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2976 psp->kdb.start_addr = ucode_start_addr; 2977 break; 2978 case PSP_FW_TYPE_PSP_TOC: 2979 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2980 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2981 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 2982 psp->toc.start_addr = ucode_start_addr; 2983 break; 2984 case PSP_FW_TYPE_PSP_SPL: 2985 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 2986 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 2987 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 2988 psp->spl.start_addr = ucode_start_addr; 2989 break; 2990 case PSP_FW_TYPE_PSP_RL: 2991 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 2992 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 2993 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 2994 psp->rl.start_addr = ucode_start_addr; 2995 break; 2996 case PSP_FW_TYPE_PSP_SOC_DRV: 2997 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 2998 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 2999 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3000 psp->soc_drv.start_addr = ucode_start_addr; 3001 break; 3002 case PSP_FW_TYPE_PSP_INTF_DRV: 3003 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3004 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3005 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3006 psp->intf_drv.start_addr = ucode_start_addr; 3007 break; 3008 case PSP_FW_TYPE_PSP_DBG_DRV: 3009 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3010 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3011 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3012 psp->dbg_drv.start_addr = ucode_start_addr; 3013 break; 3014 case PSP_FW_TYPE_PSP_RAS_DRV: 3015 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3016 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3017 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3018 psp->ras_drv.start_addr = ucode_start_addr; 3019 break; 3020 default: 3021 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3022 break; 3023 } 3024 3025 return 0; 3026 } 3027 3028 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3029 { 3030 const struct psp_firmware_header_v1_0 *sos_hdr; 3031 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3032 uint8_t *ucode_array_start_addr; 3033 3034 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3035 ucode_array_start_addr = (uint8_t *)sos_hdr + 3036 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3037 3038 if (adev->gmc.xgmi.connected_to_cpu || 3039 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3040 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3041 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3042 3043 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3044 adev->psp.sys.start_addr = ucode_array_start_addr; 3045 3046 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3047 adev->psp.sos.start_addr = ucode_array_start_addr + 3048 le32_to_cpu(sos_hdr->sos.offset_bytes); 3049 } else { 3050 /* Load alternate PSP SOS FW */ 3051 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3052 3053 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3054 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3055 3056 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3057 adev->psp.sys.start_addr = ucode_array_start_addr + 3058 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3059 3060 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3061 adev->psp.sos.start_addr = ucode_array_start_addr + 3062 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3063 } 3064 3065 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3066 dev_warn(adev->dev, "PSP SOS FW not available"); 3067 return -EINVAL; 3068 } 3069 3070 return 0; 3071 } 3072 3073 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3074 { 3075 struct amdgpu_device *adev = psp->adev; 3076 char fw_name[PSP_FW_NAME_LEN]; 3077 const struct psp_firmware_header_v1_0 *sos_hdr; 3078 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3079 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3080 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3081 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3082 int err = 0; 3083 uint8_t *ucode_array_start_addr; 3084 int fw_index = 0; 3085 3086 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3087 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name); 3088 if (err) 3089 goto out; 3090 3091 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3092 ucode_array_start_addr = (uint8_t *)sos_hdr + 3093 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3094 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3095 3096 switch (sos_hdr->header.header_version_major) { 3097 case 1: 3098 err = psp_init_sos_base_fw(adev); 3099 if (err) 3100 goto out; 3101 3102 if (sos_hdr->header.header_version_minor == 1) { 3103 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3104 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3105 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3106 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3107 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3108 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3109 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3110 } 3111 if (sos_hdr->header.header_version_minor == 2) { 3112 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3113 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3114 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3115 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3116 } 3117 if (sos_hdr->header.header_version_minor == 3) { 3118 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3119 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3120 adev->psp.toc.start_addr = ucode_array_start_addr + 3121 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3122 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3123 adev->psp.kdb.start_addr = ucode_array_start_addr + 3124 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3125 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3126 adev->psp.spl.start_addr = ucode_array_start_addr + 3127 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3128 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3129 adev->psp.rl.start_addr = ucode_array_start_addr + 3130 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3131 } 3132 break; 3133 case 2: 3134 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3135 3136 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3137 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3138 err = -EINVAL; 3139 goto out; 3140 } 3141 3142 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3143 err = parse_sos_bin_descriptor(psp, 3144 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3145 sos_hdr_v2_0); 3146 if (err) 3147 goto out; 3148 } 3149 break; 3150 default: 3151 dev_err(adev->dev, 3152 "unsupported psp sos firmware\n"); 3153 err = -EINVAL; 3154 goto out; 3155 } 3156 3157 return 0; 3158 out: 3159 amdgpu_ucode_release(&adev->psp.sos_fw); 3160 3161 return err; 3162 } 3163 3164 static int parse_ta_bin_descriptor(struct psp_context *psp, 3165 const struct psp_fw_bin_desc *desc, 3166 const struct ta_firmware_header_v2_0 *ta_hdr) 3167 { 3168 uint8_t *ucode_start_addr = NULL; 3169 3170 if (!psp || !desc || !ta_hdr) 3171 return -EINVAL; 3172 3173 ucode_start_addr = (uint8_t *)ta_hdr + 3174 le32_to_cpu(desc->offset_bytes) + 3175 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3176 3177 switch (desc->fw_type) { 3178 case TA_FW_TYPE_PSP_ASD: 3179 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3180 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3181 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3182 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3183 break; 3184 case TA_FW_TYPE_PSP_XGMI: 3185 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3186 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3187 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3188 break; 3189 case TA_FW_TYPE_PSP_RAS: 3190 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3191 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3192 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3193 break; 3194 case TA_FW_TYPE_PSP_HDCP: 3195 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3196 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3197 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3198 break; 3199 case TA_FW_TYPE_PSP_DTM: 3200 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3201 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3202 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3203 break; 3204 case TA_FW_TYPE_PSP_RAP: 3205 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3206 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3207 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3208 break; 3209 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3210 psp->securedisplay_context.context.bin_desc.fw_version = 3211 le32_to_cpu(desc->fw_version); 3212 psp->securedisplay_context.context.bin_desc.size_bytes = 3213 le32_to_cpu(desc->size_bytes); 3214 psp->securedisplay_context.context.bin_desc.start_addr = 3215 ucode_start_addr; 3216 break; 3217 default: 3218 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3219 break; 3220 } 3221 3222 return 0; 3223 } 3224 3225 static int parse_ta_v1_microcode(struct psp_context *psp) 3226 { 3227 const struct ta_firmware_header_v1_0 *ta_hdr; 3228 struct amdgpu_device *adev = psp->adev; 3229 3230 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3231 3232 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3233 return -EINVAL; 3234 3235 adev->psp.xgmi_context.context.bin_desc.fw_version = 3236 le32_to_cpu(ta_hdr->xgmi.fw_version); 3237 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3238 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3239 adev->psp.xgmi_context.context.bin_desc.start_addr = 3240 (uint8_t *)ta_hdr + 3241 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3242 3243 adev->psp.ras_context.context.bin_desc.fw_version = 3244 le32_to_cpu(ta_hdr->ras.fw_version); 3245 adev->psp.ras_context.context.bin_desc.size_bytes = 3246 le32_to_cpu(ta_hdr->ras.size_bytes); 3247 adev->psp.ras_context.context.bin_desc.start_addr = 3248 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3249 le32_to_cpu(ta_hdr->ras.offset_bytes); 3250 3251 adev->psp.hdcp_context.context.bin_desc.fw_version = 3252 le32_to_cpu(ta_hdr->hdcp.fw_version); 3253 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3254 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3255 adev->psp.hdcp_context.context.bin_desc.start_addr = 3256 (uint8_t *)ta_hdr + 3257 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3258 3259 adev->psp.dtm_context.context.bin_desc.fw_version = 3260 le32_to_cpu(ta_hdr->dtm.fw_version); 3261 adev->psp.dtm_context.context.bin_desc.size_bytes = 3262 le32_to_cpu(ta_hdr->dtm.size_bytes); 3263 adev->psp.dtm_context.context.bin_desc.start_addr = 3264 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3265 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3266 3267 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3268 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3269 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3270 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3271 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3272 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3273 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3274 3275 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3276 3277 return 0; 3278 } 3279 3280 static int parse_ta_v2_microcode(struct psp_context *psp) 3281 { 3282 const struct ta_firmware_header_v2_0 *ta_hdr; 3283 struct amdgpu_device *adev = psp->adev; 3284 int err = 0; 3285 int ta_index = 0; 3286 3287 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3288 3289 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3290 return -EINVAL; 3291 3292 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3293 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3294 return -EINVAL; 3295 } 3296 3297 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3298 err = parse_ta_bin_descriptor(psp, 3299 &ta_hdr->ta_fw_bin[ta_index], 3300 ta_hdr); 3301 if (err) 3302 return err; 3303 } 3304 3305 return 0; 3306 } 3307 3308 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3309 { 3310 const struct common_firmware_header *hdr; 3311 struct amdgpu_device *adev = psp->adev; 3312 char fw_name[PSP_FW_NAME_LEN]; 3313 int err; 3314 3315 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3316 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name); 3317 if (err) 3318 return err; 3319 3320 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3321 switch (le16_to_cpu(hdr->header_version_major)) { 3322 case 1: 3323 err = parse_ta_v1_microcode(psp); 3324 break; 3325 case 2: 3326 err = parse_ta_v2_microcode(psp); 3327 break; 3328 default: 3329 dev_err(adev->dev, "unsupported TA header version\n"); 3330 err = -EINVAL; 3331 } 3332 3333 if (err) 3334 amdgpu_ucode_release(&adev->psp.ta_fw); 3335 3336 return err; 3337 } 3338 3339 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 3340 { 3341 struct amdgpu_device *adev = psp->adev; 3342 char fw_name[PSP_FW_NAME_LEN]; 3343 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3344 struct amdgpu_firmware_info *info = NULL; 3345 int err = 0; 3346 3347 if (!amdgpu_sriov_vf(adev)) { 3348 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3349 return -EINVAL; 3350 } 3351 3352 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3353 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name); 3354 if (err) { 3355 if (err == -ENODEV) { 3356 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3357 err = 0; 3358 goto out; 3359 } 3360 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3361 } 3362 3363 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3364 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3365 info->fw = adev->psp.cap_fw; 3366 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3367 adev->psp.cap_fw->data; 3368 adev->firmware.fw_size += ALIGN( 3369 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3370 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3371 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3372 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3373 3374 return 0; 3375 3376 out: 3377 amdgpu_ucode_release(&adev->psp.cap_fw); 3378 return err; 3379 } 3380 3381 static int psp_set_clockgating_state(void *handle, 3382 enum amd_clockgating_state state) 3383 { 3384 return 0; 3385 } 3386 3387 static int psp_set_powergating_state(void *handle, 3388 enum amd_powergating_state state) 3389 { 3390 return 0; 3391 } 3392 3393 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3394 struct device_attribute *attr, 3395 char *buf) 3396 { 3397 struct drm_device *ddev = dev_get_drvdata(dev); 3398 struct amdgpu_device *adev = drm_to_adev(ddev); 3399 uint32_t fw_ver; 3400 int ret; 3401 3402 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3403 DRM_INFO("PSP block is not ready yet."); 3404 return -EBUSY; 3405 } 3406 3407 mutex_lock(&adev->psp.mutex); 3408 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3409 mutex_unlock(&adev->psp.mutex); 3410 3411 if (ret) { 3412 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3413 return ret; 3414 } 3415 3416 return sysfs_emit(buf, "%x\n", fw_ver); 3417 } 3418 3419 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3420 struct device_attribute *attr, 3421 const char *buf, 3422 size_t count) 3423 { 3424 struct drm_device *ddev = dev_get_drvdata(dev); 3425 struct amdgpu_device *adev = drm_to_adev(ddev); 3426 int ret, idx; 3427 char fw_name[100]; 3428 const struct firmware *usbc_pd_fw; 3429 struct amdgpu_bo *fw_buf_bo = NULL; 3430 uint64_t fw_pri_mc_addr; 3431 void *fw_pri_cpu_addr; 3432 3433 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3434 DRM_INFO("PSP block is not ready yet."); 3435 return -EBUSY; 3436 } 3437 3438 if (!drm_dev_enter(ddev, &idx)) 3439 return -ENODEV; 3440 3441 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3442 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3443 if (ret) 3444 goto fail; 3445 3446 /* LFB address which is aligned to 1MB boundary per PSP request */ 3447 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3448 AMDGPU_GEM_DOMAIN_VRAM | 3449 AMDGPU_GEM_DOMAIN_GTT, 3450 &fw_buf_bo, &fw_pri_mc_addr, 3451 &fw_pri_cpu_addr); 3452 if (ret) 3453 goto rel_buf; 3454 3455 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3456 3457 mutex_lock(&adev->psp.mutex); 3458 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3459 mutex_unlock(&adev->psp.mutex); 3460 3461 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3462 3463 rel_buf: 3464 release_firmware(usbc_pd_fw); 3465 fail: 3466 if (ret) { 3467 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3468 count = ret; 3469 } 3470 3471 drm_dev_exit(idx); 3472 return count; 3473 } 3474 3475 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3476 { 3477 int idx; 3478 3479 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3480 return; 3481 3482 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3483 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3484 3485 drm_dev_exit(idx); 3486 } 3487 3488 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3489 psp_usbc_pd_fw_sysfs_read, 3490 psp_usbc_pd_fw_sysfs_write); 3491 3492 int is_psp_fw_valid(struct psp_bin_desc bin) 3493 { 3494 return bin.size_bytes; 3495 } 3496 3497 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3498 struct bin_attribute *bin_attr, 3499 char *buffer, loff_t pos, size_t count) 3500 { 3501 struct device *dev = kobj_to_dev(kobj); 3502 struct drm_device *ddev = dev_get_drvdata(dev); 3503 struct amdgpu_device *adev = drm_to_adev(ddev); 3504 3505 adev->psp.vbflash_done = false; 3506 3507 /* Safeguard against memory drain */ 3508 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3509 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3510 kvfree(adev->psp.vbflash_tmp_buf); 3511 adev->psp.vbflash_tmp_buf = NULL; 3512 adev->psp.vbflash_image_size = 0; 3513 return -ENOMEM; 3514 } 3515 3516 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3517 if (!adev->psp.vbflash_tmp_buf) { 3518 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3519 if (!adev->psp.vbflash_tmp_buf) 3520 return -ENOMEM; 3521 } 3522 3523 mutex_lock(&adev->psp.mutex); 3524 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3525 adev->psp.vbflash_image_size += count; 3526 mutex_unlock(&adev->psp.mutex); 3527 3528 dev_info(adev->dev, "VBIOS flash write PSP done"); 3529 3530 return count; 3531 } 3532 3533 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3534 struct bin_attribute *bin_attr, char *buffer, 3535 loff_t pos, size_t count) 3536 { 3537 struct device *dev = kobj_to_dev(kobj); 3538 struct drm_device *ddev = dev_get_drvdata(dev); 3539 struct amdgpu_device *adev = drm_to_adev(ddev); 3540 struct amdgpu_bo *fw_buf_bo = NULL; 3541 uint64_t fw_pri_mc_addr; 3542 void *fw_pri_cpu_addr; 3543 int ret; 3544 3545 dev_info(adev->dev, "VBIOS flash to PSP started"); 3546 3547 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3548 AMDGPU_GPU_PAGE_SIZE, 3549 AMDGPU_GEM_DOMAIN_VRAM, 3550 &fw_buf_bo, 3551 &fw_pri_mc_addr, 3552 &fw_pri_cpu_addr); 3553 if (ret) 3554 goto rel_buf; 3555 3556 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3557 3558 mutex_lock(&adev->psp.mutex); 3559 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3560 mutex_unlock(&adev->psp.mutex); 3561 3562 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3563 3564 rel_buf: 3565 kvfree(adev->psp.vbflash_tmp_buf); 3566 adev->psp.vbflash_tmp_buf = NULL; 3567 adev->psp.vbflash_image_size = 0; 3568 3569 if (ret) { 3570 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret); 3571 return ret; 3572 } 3573 3574 dev_info(adev->dev, "VBIOS flash to PSP done"); 3575 return 0; 3576 } 3577 3578 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3579 struct device_attribute *attr, 3580 char *buf) 3581 { 3582 struct drm_device *ddev = dev_get_drvdata(dev); 3583 struct amdgpu_device *adev = drm_to_adev(ddev); 3584 uint32_t vbflash_status; 3585 3586 vbflash_status = psp_vbflash_status(&adev->psp); 3587 if (!adev->psp.vbflash_done) 3588 vbflash_status = 0; 3589 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3590 vbflash_status = 1; 3591 3592 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3593 } 3594 3595 static const struct bin_attribute psp_vbflash_bin_attr = { 3596 .attr = {.name = "psp_vbflash", .mode = 0664}, 3597 .size = 0, 3598 .write = amdgpu_psp_vbflash_write, 3599 .read = amdgpu_psp_vbflash_read, 3600 }; 3601 3602 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL); 3603 3604 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev) 3605 { 3606 int ret = 0; 3607 struct psp_context *psp = &adev->psp; 3608 3609 if (amdgpu_sriov_vf(adev)) 3610 return -EINVAL; 3611 3612 switch (adev->ip_versions[MP0_HWIP][0]) { 3613 case IP_VERSION(13, 0, 0): 3614 case IP_VERSION(13, 0, 7): 3615 if (!psp->adev) { 3616 psp->adev = adev; 3617 psp_v13_0_set_psp_funcs(psp); 3618 } 3619 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3620 if (ret) 3621 dev_err(adev->dev, "Failed to create device file psp_vbflash"); 3622 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status); 3623 if (ret) 3624 dev_err(adev->dev, "Failed to create device file psp_vbflash_status"); 3625 return ret; 3626 default: 3627 return 0; 3628 } 3629 } 3630 3631 const struct amd_ip_funcs psp_ip_funcs = { 3632 .name = "psp", 3633 .early_init = psp_early_init, 3634 .late_init = NULL, 3635 .sw_init = psp_sw_init, 3636 .sw_fini = psp_sw_fini, 3637 .hw_init = psp_hw_init, 3638 .hw_fini = psp_hw_fini, 3639 .suspend = psp_suspend, 3640 .resume = psp_resume, 3641 .is_idle = NULL, 3642 .check_soft_reset = NULL, 3643 .wait_for_idle = NULL, 3644 .soft_reset = NULL, 3645 .set_clockgating_state = psp_set_clockgating_state, 3646 .set_powergating_state = psp_set_powergating_state, 3647 }; 3648 3649 static int psp_sysfs_init(struct amdgpu_device *adev) 3650 { 3651 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3652 3653 if (ret) 3654 DRM_ERROR("Failed to create USBC PD FW control file!"); 3655 3656 return ret; 3657 } 3658 3659 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev) 3660 { 3661 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3662 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status); 3663 } 3664 3665 static void psp_sysfs_fini(struct amdgpu_device *adev) 3666 { 3667 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3668 } 3669 3670 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3671 { 3672 .type = AMD_IP_BLOCK_TYPE_PSP, 3673 .major = 3, 3674 .minor = 1, 3675 .rev = 0, 3676 .funcs = &psp_ip_funcs, 3677 }; 3678 3679 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3680 { 3681 .type = AMD_IP_BLOCK_TYPE_PSP, 3682 .major = 10, 3683 .minor = 0, 3684 .rev = 0, 3685 .funcs = &psp_ip_funcs, 3686 }; 3687 3688 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3689 { 3690 .type = AMD_IP_BLOCK_TYPE_PSP, 3691 .major = 11, 3692 .minor = 0, 3693 .rev = 0, 3694 .funcs = &psp_ip_funcs, 3695 }; 3696 3697 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3698 .type = AMD_IP_BLOCK_TYPE_PSP, 3699 .major = 11, 3700 .minor = 0, 3701 .rev = 8, 3702 .funcs = &psp_ip_funcs, 3703 }; 3704 3705 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3706 { 3707 .type = AMD_IP_BLOCK_TYPE_PSP, 3708 .major = 12, 3709 .minor = 0, 3710 .rev = 0, 3711 .funcs = &psp_ip_funcs, 3712 }; 3713 3714 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3715 .type = AMD_IP_BLOCK_TYPE_PSP, 3716 .major = 13, 3717 .minor = 0, 3718 .rev = 0, 3719 .funcs = &psp_ip_funcs, 3720 }; 3721 3722 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3723 .type = AMD_IP_BLOCK_TYPE_PSP, 3724 .major = 13, 3725 .minor = 0, 3726 .rev = 4, 3727 .funcs = &psp_ip_funcs, 3728 }; 3729