1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 41 #include "amdgpu_ras.h" 42 #include "amdgpu_securedisplay.h" 43 #include "amdgpu_atomfirmware.h" 44 45 static int psp_sysfs_init(struct amdgpu_device *adev); 46 static void psp_sysfs_fini(struct amdgpu_device *adev); 47 48 static int psp_load_smu_fw(struct psp_context *psp); 49 static int psp_ta_unload(struct psp_context *psp, uint32_t session_id); 50 static int psp_rap_terminate(struct psp_context *psp); 51 static int psp_securedisplay_terminate(struct psp_context *psp); 52 53 /* 54 * Due to DF Cstate management centralized to PMFW, the firmware 55 * loading sequence will be updated as below: 56 * - Load KDB 57 * - Load SYS_DRV 58 * - Load tOS 59 * - Load PMFW 60 * - Setup TMR 61 * - Load other non-psp fw 62 * - Load ASD 63 * - Load XGMI/RAS/HDCP/DTM TA if any 64 * 65 * This new sequence is required for 66 * - Arcturus and onwards 67 * - Navi12 and onwards 68 */ 69 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 70 { 71 struct amdgpu_device *adev = psp->adev; 72 73 psp->pmfw_centralized_cstate_management = false; 74 75 if (amdgpu_sriov_vf(adev)) 76 return; 77 78 if (adev->flags & AMD_IS_APU) 79 return; 80 81 if ((adev->asic_type >= CHIP_ARCTURUS) || 82 (adev->asic_type >= CHIP_NAVI12)) 83 psp->pmfw_centralized_cstate_management = true; 84 } 85 86 static int psp_early_init(void *handle) 87 { 88 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 89 struct psp_context *psp = &adev->psp; 90 91 switch (adev->asic_type) { 92 case CHIP_VEGA10: 93 case CHIP_VEGA12: 94 psp_v3_1_set_psp_funcs(psp); 95 psp->autoload_supported = false; 96 break; 97 case CHIP_RAVEN: 98 psp_v10_0_set_psp_funcs(psp); 99 psp->autoload_supported = false; 100 break; 101 case CHIP_VEGA20: 102 case CHIP_ARCTURUS: 103 psp_v11_0_set_psp_funcs(psp); 104 psp->autoload_supported = false; 105 break; 106 case CHIP_NAVI10: 107 case CHIP_NAVI14: 108 case CHIP_NAVI12: 109 case CHIP_SIENNA_CICHLID: 110 case CHIP_NAVY_FLOUNDER: 111 case CHIP_VANGOGH: 112 case CHIP_DIMGREY_CAVEFISH: 113 case CHIP_BEIGE_GOBY: 114 psp_v11_0_set_psp_funcs(psp); 115 psp->autoload_supported = true; 116 break; 117 case CHIP_RENOIR: 118 psp_v12_0_set_psp_funcs(psp); 119 break; 120 case CHIP_ALDEBARAN: 121 psp_v13_0_set_psp_funcs(psp); 122 break; 123 case CHIP_YELLOW_CARP: 124 psp_v13_0_set_psp_funcs(psp); 125 psp->autoload_supported = true; 126 break; 127 case CHIP_CYAN_SKILLFISH: 128 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 129 psp_v11_0_8_set_psp_funcs(psp); 130 psp->autoload_supported = false; 131 } 132 break; 133 default: 134 return -EINVAL; 135 } 136 137 psp->adev = adev; 138 139 psp_check_pmfw_centralized_cstate_management(psp); 140 141 return 0; 142 } 143 144 static void psp_memory_training_fini(struct psp_context *psp) 145 { 146 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 147 148 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 149 kfree(ctx->sys_cache); 150 ctx->sys_cache = NULL; 151 } 152 153 static int psp_memory_training_init(struct psp_context *psp) 154 { 155 int ret; 156 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 157 158 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 159 DRM_DEBUG("memory training is not supported!\n"); 160 return 0; 161 } 162 163 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 164 if (ctx->sys_cache == NULL) { 165 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 166 ret = -ENOMEM; 167 goto Err_out; 168 } 169 170 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 171 ctx->train_data_size, 172 ctx->p2c_train_data_offset, 173 ctx->c2p_train_data_offset); 174 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 175 return 0; 176 177 Err_out: 178 psp_memory_training_fini(psp); 179 return ret; 180 } 181 182 /* 183 * Helper funciton to query psp runtime database entry 184 * 185 * @adev: amdgpu_device pointer 186 * @entry_type: the type of psp runtime database entry 187 * @db_entry: runtime database entry pointer 188 * 189 * Return false if runtime database doesn't exit or entry is invalid 190 * or true if the specific database entry is found, and copy to @db_entry 191 */ 192 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 193 enum psp_runtime_entry_type entry_type, 194 void *db_entry) 195 { 196 uint64_t db_header_pos, db_dir_pos; 197 struct psp_runtime_data_header db_header = {0}; 198 struct psp_runtime_data_directory db_dir = {0}; 199 bool ret = false; 200 int i; 201 202 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 203 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 204 205 /* read runtime db header from vram */ 206 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 207 sizeof(struct psp_runtime_data_header), false); 208 209 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 210 /* runtime db doesn't exist, exit */ 211 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 212 return false; 213 } 214 215 /* read runtime database entry from vram */ 216 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 217 sizeof(struct psp_runtime_data_directory), false); 218 219 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 220 /* invalid db entry count, exit */ 221 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 222 return false; 223 } 224 225 /* look up for requested entry type */ 226 for (i = 0; i < db_dir.entry_count && !ret; i++) { 227 if (db_dir.entry_list[i].entry_type == entry_type) { 228 switch (entry_type) { 229 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 230 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 231 /* invalid db entry size */ 232 dev_warn(adev->dev, "Invalid PSP runtime database entry size\n"); 233 return false; 234 } 235 /* read runtime database entry */ 236 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 237 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 238 ret = true; 239 break; 240 default: 241 ret = false; 242 break; 243 } 244 } 245 } 246 247 return ret; 248 } 249 250 static int psp_sw_init(void *handle) 251 { 252 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 253 struct psp_context *psp = &adev->psp; 254 int ret; 255 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 256 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 257 258 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 259 if (!psp->cmd) { 260 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 261 ret = -ENOMEM; 262 } 263 264 if (!amdgpu_sriov_vf(adev)) { 265 ret = psp_init_microcode(psp); 266 if (ret) { 267 DRM_ERROR("Failed to load psp firmware!\n"); 268 return ret; 269 } 270 } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) { 271 ret = psp_init_ta_microcode(psp, "aldebaran"); 272 if (ret) { 273 DRM_ERROR("Failed to initialize ta microcode!\n"); 274 return ret; 275 } 276 } 277 278 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 279 if (psp_get_runtime_db_entry(adev, 280 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 281 &boot_cfg_entry)) { 282 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 283 if ((psp->boot_cfg_bitmask) & 284 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 285 /* If psp runtime database exists, then 286 * only enable two stage memory training 287 * when TWO_STAGE_DRAM_TRAINING bit is set 288 * in runtime database */ 289 mem_training_ctx->enable_mem_training = true; 290 } 291 292 } else { 293 /* If psp runtime database doesn't exist or 294 * is invalid, force enable two stage memory 295 * training */ 296 mem_training_ctx->enable_mem_training = true; 297 } 298 299 if (mem_training_ctx->enable_mem_training) { 300 ret = psp_memory_training_init(psp); 301 if (ret) { 302 DRM_ERROR("Failed to initialize memory training!\n"); 303 return ret; 304 } 305 306 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 307 if (ret) { 308 DRM_ERROR("Failed to process memory training!\n"); 309 return ret; 310 } 311 } 312 313 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 314 ret= psp_sysfs_init(adev); 315 if (ret) { 316 return ret; 317 } 318 } 319 320 return 0; 321 } 322 323 static int psp_sw_fini(void *handle) 324 { 325 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 326 struct psp_context *psp = &adev->psp; 327 struct psp_gfx_cmd_resp *cmd = psp->cmd; 328 329 psp_memory_training_fini(psp); 330 if (psp->sos_fw) { 331 release_firmware(psp->sos_fw); 332 psp->sos_fw = NULL; 333 } 334 if (psp->asd_fw) { 335 release_firmware(psp->asd_fw); 336 psp->asd_fw = NULL; 337 } 338 if (psp->ta_fw) { 339 release_firmware(psp->ta_fw); 340 psp->ta_fw = NULL; 341 } 342 343 if (adev->asic_type == CHIP_NAVI10 || 344 adev->asic_type == CHIP_SIENNA_CICHLID) 345 psp_sysfs_fini(adev); 346 347 kfree(cmd); 348 cmd = NULL; 349 350 return 0; 351 } 352 353 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 354 uint32_t reg_val, uint32_t mask, bool check_changed) 355 { 356 uint32_t val; 357 int i; 358 struct amdgpu_device *adev = psp->adev; 359 360 if (psp->adev->no_hw_access) 361 return 0; 362 363 for (i = 0; i < adev->usec_timeout; i++) { 364 val = RREG32(reg_index); 365 if (check_changed) { 366 if (val != reg_val) 367 return 0; 368 } else { 369 if ((val & mask) == reg_val) 370 return 0; 371 } 372 udelay(1); 373 } 374 375 return -ETIME; 376 } 377 378 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 379 { 380 switch (cmd_id) { 381 case GFX_CMD_ID_LOAD_TA: 382 return "LOAD_TA"; 383 case GFX_CMD_ID_UNLOAD_TA: 384 return "UNLOAD_TA"; 385 case GFX_CMD_ID_INVOKE_CMD: 386 return "INVOKE_CMD"; 387 case GFX_CMD_ID_LOAD_ASD: 388 return "LOAD_ASD"; 389 case GFX_CMD_ID_SETUP_TMR: 390 return "SETUP_TMR"; 391 case GFX_CMD_ID_LOAD_IP_FW: 392 return "LOAD_IP_FW"; 393 case GFX_CMD_ID_DESTROY_TMR: 394 return "DESTROY_TMR"; 395 case GFX_CMD_ID_SAVE_RESTORE: 396 return "SAVE_RESTORE_IP_FW"; 397 case GFX_CMD_ID_SETUP_VMR: 398 return "SETUP_VMR"; 399 case GFX_CMD_ID_DESTROY_VMR: 400 return "DESTROY_VMR"; 401 case GFX_CMD_ID_PROG_REG: 402 return "PROG_REG"; 403 case GFX_CMD_ID_GET_FW_ATTESTATION: 404 return "GET_FW_ATTESTATION"; 405 case GFX_CMD_ID_LOAD_TOC: 406 return "ID_LOAD_TOC"; 407 case GFX_CMD_ID_AUTOLOAD_RLC: 408 return "AUTOLOAD_RLC"; 409 case GFX_CMD_ID_BOOT_CFG: 410 return "BOOT_CFG"; 411 default: 412 return "UNKNOWN CMD"; 413 } 414 } 415 416 static int 417 psp_cmd_submit_buf(struct psp_context *psp, 418 struct amdgpu_firmware_info *ucode, 419 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 420 { 421 int ret; 422 int index, idx; 423 int timeout = 20000; 424 bool ras_intr = false; 425 bool skip_unsupport = false; 426 427 if (psp->adev->no_hw_access) 428 return 0; 429 430 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 431 return 0; 432 433 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 434 435 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 436 437 index = atomic_inc_return(&psp->fence_value); 438 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 439 if (ret) { 440 atomic_dec(&psp->fence_value); 441 goto exit; 442 } 443 444 amdgpu_device_invalidate_hdp(psp->adev, NULL); 445 while (*((unsigned int *)psp->fence_buf) != index) { 446 if (--timeout == 0) 447 break; 448 /* 449 * Shouldn't wait for timeout when err_event_athub occurs, 450 * because gpu reset thread triggered and lock resource should 451 * be released for psp resume sequence. 452 */ 453 ras_intr = amdgpu_ras_intr_triggered(); 454 if (ras_intr) 455 break; 456 usleep_range(10, 100); 457 amdgpu_device_invalidate_hdp(psp->adev, NULL); 458 } 459 460 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 461 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 462 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 463 464 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 465 466 /* In some cases, psp response status is not 0 even there is no 467 * problem while the command is submitted. Some version of PSP FW 468 * doesn't write 0 to that field. 469 * So here we would like to only print a warning instead of an error 470 * during psp initialization to avoid breaking hw_init and it doesn't 471 * return -EINVAL. 472 */ 473 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 474 if (ucode) 475 DRM_WARN("failed to load ucode %s(0x%X) ", 476 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 477 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 478 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 479 psp->cmd_buf_mem->resp.status); 480 if (!timeout) { 481 ret = -EINVAL; 482 goto exit; 483 } 484 } 485 486 if (ucode) { 487 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 488 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 489 } 490 491 exit: 492 drm_dev_exit(idx); 493 return ret; 494 } 495 496 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 497 { 498 struct psp_gfx_cmd_resp *cmd = psp->cmd; 499 500 mutex_lock(&psp->mutex); 501 502 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 503 504 return cmd; 505 } 506 507 void release_psp_cmd_buf(struct psp_context *psp) 508 { 509 mutex_unlock(&psp->mutex); 510 } 511 512 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 513 struct psp_gfx_cmd_resp *cmd, 514 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 515 { 516 struct amdgpu_device *adev = psp->adev; 517 uint32_t size = amdgpu_bo_size(tmr_bo); 518 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 519 520 if (amdgpu_sriov_vf(psp->adev)) 521 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 522 else 523 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 524 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 525 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 526 cmd->cmd.cmd_setup_tmr.buf_size = size; 527 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 528 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 529 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 530 } 531 532 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 533 uint64_t pri_buf_mc, uint32_t size) 534 { 535 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 536 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 537 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 538 cmd->cmd.cmd_load_toc.toc_size = size; 539 } 540 541 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 542 static int psp_load_toc(struct psp_context *psp, 543 uint32_t *tmr_size) 544 { 545 int ret; 546 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 547 548 /* Copy toc to psp firmware private buffer */ 549 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 550 551 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 552 553 ret = psp_cmd_submit_buf(psp, NULL, cmd, 554 psp->fence_buf_mc_addr); 555 if (!ret) 556 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 557 558 release_psp_cmd_buf(psp); 559 560 return ret; 561 } 562 563 /* Set up Trusted Memory Region */ 564 static int psp_tmr_init(struct psp_context *psp) 565 { 566 int ret; 567 int tmr_size; 568 void *tmr_buf; 569 void **pptr; 570 571 /* 572 * According to HW engineer, they prefer the TMR address be "naturally 573 * aligned" , e.g. the start address be an integer divide of TMR size. 574 * 575 * Note: this memory need be reserved till the driver 576 * uninitializes. 577 */ 578 tmr_size = PSP_TMR_SIZE(psp->adev); 579 580 /* For ASICs support RLC autoload, psp will parse the toc 581 * and calculate the total size of TMR needed */ 582 if (!amdgpu_sriov_vf(psp->adev) && 583 psp->toc.start_addr && 584 psp->toc.size_bytes && 585 psp->fw_pri_buf) { 586 ret = psp_load_toc(psp, &tmr_size); 587 if (ret) { 588 DRM_ERROR("Failed to load toc\n"); 589 return ret; 590 } 591 } 592 593 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 594 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 595 AMDGPU_GEM_DOMAIN_VRAM, 596 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 597 598 return ret; 599 } 600 601 static bool psp_skip_tmr(struct psp_context *psp) 602 { 603 switch (psp->adev->asic_type) { 604 case CHIP_NAVI12: 605 case CHIP_SIENNA_CICHLID: 606 case CHIP_ALDEBARAN: 607 return true; 608 default: 609 return false; 610 } 611 } 612 613 static int psp_tmr_load(struct psp_context *psp) 614 { 615 int ret; 616 struct psp_gfx_cmd_resp *cmd; 617 618 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 619 * Already set up by host driver. 620 */ 621 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 622 return 0; 623 624 cmd = acquire_psp_cmd_buf(psp); 625 626 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 627 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 628 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 629 630 ret = psp_cmd_submit_buf(psp, NULL, cmd, 631 psp->fence_buf_mc_addr); 632 633 release_psp_cmd_buf(psp); 634 635 return ret; 636 } 637 638 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 639 struct psp_gfx_cmd_resp *cmd) 640 { 641 if (amdgpu_sriov_vf(psp->adev)) 642 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 643 else 644 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 645 } 646 647 static int psp_tmr_unload(struct psp_context *psp) 648 { 649 int ret; 650 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 651 652 psp_prep_tmr_unload_cmd_buf(psp, cmd); 653 DRM_INFO("free PSP TMR buffer\n"); 654 655 ret = psp_cmd_submit_buf(psp, NULL, cmd, 656 psp->fence_buf_mc_addr); 657 658 release_psp_cmd_buf(psp); 659 660 return ret; 661 } 662 663 static int psp_tmr_terminate(struct psp_context *psp) 664 { 665 int ret; 666 void *tmr_buf; 667 void **pptr; 668 669 ret = psp_tmr_unload(psp); 670 if (ret) 671 return ret; 672 673 /* free TMR memory buffer */ 674 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 675 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 676 677 return 0; 678 } 679 680 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 681 uint64_t *output_ptr) 682 { 683 int ret; 684 struct psp_gfx_cmd_resp *cmd; 685 686 if (!output_ptr) 687 return -EINVAL; 688 689 if (amdgpu_sriov_vf(psp->adev)) 690 return 0; 691 692 cmd = acquire_psp_cmd_buf(psp); 693 694 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 695 696 ret = psp_cmd_submit_buf(psp, NULL, cmd, 697 psp->fence_buf_mc_addr); 698 699 if (!ret) { 700 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 701 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 702 } 703 704 release_psp_cmd_buf(psp); 705 706 return ret; 707 } 708 709 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 710 { 711 struct psp_context *psp = &adev->psp; 712 struct psp_gfx_cmd_resp *cmd; 713 int ret; 714 715 if (amdgpu_sriov_vf(adev)) 716 return 0; 717 718 cmd = acquire_psp_cmd_buf(psp); 719 720 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 721 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 722 723 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 724 if (!ret) { 725 *boot_cfg = 726 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 727 } 728 729 release_psp_cmd_buf(psp); 730 731 return ret; 732 } 733 734 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 735 { 736 int ret; 737 struct psp_context *psp = &adev->psp; 738 struct psp_gfx_cmd_resp *cmd; 739 740 if (amdgpu_sriov_vf(adev)) 741 return 0; 742 743 cmd = acquire_psp_cmd_buf(psp); 744 745 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 746 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 747 cmd->cmd.boot_cfg.boot_config = boot_cfg; 748 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 749 750 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 751 752 release_psp_cmd_buf(psp); 753 754 return ret; 755 } 756 757 static int psp_rl_load(struct amdgpu_device *adev) 758 { 759 int ret; 760 struct psp_context *psp = &adev->psp; 761 struct psp_gfx_cmd_resp *cmd; 762 763 if (!is_psp_fw_valid(psp->rl)) 764 return 0; 765 766 cmd = acquire_psp_cmd_buf(psp); 767 768 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 769 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 770 771 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 772 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 773 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 774 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 775 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 776 777 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 778 779 release_psp_cmd_buf(psp); 780 781 return ret; 782 } 783 784 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 785 uint64_t asd_mc, uint32_t size) 786 { 787 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 788 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 789 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 790 cmd->cmd.cmd_load_ta.app_len = size; 791 792 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 793 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 794 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 795 } 796 797 static int psp_asd_load(struct psp_context *psp) 798 { 799 int ret; 800 struct psp_gfx_cmd_resp *cmd; 801 802 /* If PSP version doesn't match ASD version, asd loading will be failed. 803 * add workaround to bypass it for sriov now. 804 * TODO: add version check to make it common 805 */ 806 if (amdgpu_sriov_vf(psp->adev) || !psp->asd.size_bytes) 807 return 0; 808 809 cmd = acquire_psp_cmd_buf(psp); 810 811 psp_copy_fw(psp, psp->asd.start_addr, psp->asd.size_bytes); 812 813 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 814 psp->asd.size_bytes); 815 816 ret = psp_cmd_submit_buf(psp, NULL, cmd, 817 psp->fence_buf_mc_addr); 818 if (!ret) { 819 psp->asd_context.asd_initialized = true; 820 psp->asd_context.session_id = cmd->resp.session_id; 821 } 822 823 release_psp_cmd_buf(psp); 824 825 return ret; 826 } 827 828 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 829 uint32_t session_id) 830 { 831 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 832 cmd->cmd.cmd_unload_ta.session_id = session_id; 833 } 834 835 static int psp_ta_unload(struct psp_context *psp, uint32_t session_id) 836 { 837 int ret; 838 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 839 840 psp_prep_ta_unload_cmd_buf(cmd, session_id); 841 842 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 843 844 release_psp_cmd_buf(psp); 845 846 return ret; 847 } 848 849 static int psp_asd_unload(struct psp_context *psp) 850 { 851 return psp_ta_unload(psp, psp->asd_context.session_id); 852 } 853 854 static int psp_asd_terminate(struct psp_context *psp) 855 { 856 int ret; 857 858 if (amdgpu_sriov_vf(psp->adev)) 859 return 0; 860 861 if (!psp->asd_context.asd_initialized) 862 return 0; 863 864 ret = psp_asd_unload(psp); 865 866 if (!ret) 867 psp->asd_context.asd_initialized = false; 868 869 return ret; 870 } 871 872 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 873 uint32_t id, uint32_t value) 874 { 875 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 876 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 877 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 878 } 879 880 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 881 uint32_t value) 882 { 883 struct psp_gfx_cmd_resp *cmd; 884 int ret = 0; 885 886 if (reg >= PSP_REG_LAST) 887 return -EINVAL; 888 889 cmd = acquire_psp_cmd_buf(psp); 890 891 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 892 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 893 if (ret) 894 DRM_ERROR("PSP failed to program reg id %d", reg); 895 896 release_psp_cmd_buf(psp); 897 898 return ret; 899 } 900 901 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 902 uint64_t ta_bin_mc, 903 uint32_t ta_bin_size, 904 struct ta_mem_context *mem_ctx) 905 { 906 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 907 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 908 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 909 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 910 911 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(mem_ctx->shared_mc_addr); 912 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(mem_ctx->shared_mc_addr); 913 cmd->cmd.cmd_load_ta.cmd_buf_len = mem_ctx->shared_mem_size; 914 } 915 916 static int psp_ta_init_shared_buf(struct psp_context *psp, 917 struct ta_mem_context *mem_ctx) 918 { 919 int ret; 920 921 /* 922 * Allocate 16k memory aligned to 4k from Frame Buffer (local 923 * physical) for ta to host memory 924 */ 925 ret = amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 926 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 927 &mem_ctx->shared_bo, 928 &mem_ctx->shared_mc_addr, 929 &mem_ctx->shared_buf); 930 931 return ret; 932 } 933 934 static void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 935 { 936 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 937 &mem_ctx->shared_buf); 938 } 939 940 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 941 { 942 return psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 943 } 944 945 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 946 uint32_t ta_cmd_id, 947 uint32_t session_id) 948 { 949 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 950 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 951 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 952 } 953 954 static int psp_ta_invoke(struct psp_context *psp, 955 uint32_t ta_cmd_id, 956 uint32_t session_id) 957 { 958 int ret; 959 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 960 961 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 962 963 ret = psp_cmd_submit_buf(psp, NULL, cmd, 964 psp->fence_buf_mc_addr); 965 966 release_psp_cmd_buf(psp); 967 968 return ret; 969 } 970 971 static int psp_ta_load(struct psp_context *psp, 972 struct psp_bin_desc *bin_desc, 973 struct ta_context *context) 974 { 975 int ret; 976 struct psp_gfx_cmd_resp *cmd; 977 978 cmd = acquire_psp_cmd_buf(psp); 979 980 psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes); 981 982 psp_prep_ta_load_cmd_buf(cmd, 983 psp->fw_pri_mc_addr, 984 bin_desc->size_bytes, 985 &context->mem_context); 986 987 ret = psp_cmd_submit_buf(psp, NULL, cmd, 988 psp->fence_buf_mc_addr); 989 990 if (!ret) { 991 context->session_id = cmd->resp.session_id; 992 } 993 994 release_psp_cmd_buf(psp); 995 996 return ret; 997 } 998 999 static int psp_xgmi_load(struct psp_context *psp) 1000 { 1001 return psp_ta_load(psp, &psp->xgmi, &psp->xgmi_context.context); 1002 } 1003 1004 static int psp_xgmi_unload(struct psp_context *psp) 1005 { 1006 return psp_ta_unload(psp, psp->xgmi_context.context.session_id); 1007 } 1008 1009 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1010 { 1011 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.context.session_id); 1012 } 1013 1014 int psp_xgmi_terminate(struct psp_context *psp) 1015 { 1016 int ret; 1017 struct amdgpu_device *adev = psp->adev; 1018 1019 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1020 if (adev->asic_type == CHIP_ARCTURUS || 1021 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu)) 1022 return 0; 1023 1024 if (!psp->xgmi_context.context.initialized) 1025 return 0; 1026 1027 ret = psp_xgmi_unload(psp); 1028 if (ret) 1029 return ret; 1030 1031 psp->xgmi_context.context.initialized = false; 1032 1033 /* free xgmi shared memory */ 1034 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 1035 1036 return 0; 1037 } 1038 1039 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1040 { 1041 struct ta_xgmi_shared_memory *xgmi_cmd; 1042 int ret; 1043 1044 if (!psp->ta_fw || 1045 !psp->xgmi.size_bytes || 1046 !psp->xgmi.start_addr) 1047 return -ENOENT; 1048 1049 if (!load_ta) 1050 goto invoke; 1051 1052 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1053 1054 if (!psp->xgmi_context.context.initialized) { 1055 ret = psp_xgmi_init_shared_buf(psp); 1056 if (ret) 1057 return ret; 1058 } 1059 1060 /* Load XGMI TA */ 1061 ret = psp_xgmi_load(psp); 1062 if (!ret) 1063 psp->xgmi_context.context.initialized = true; 1064 else 1065 return ret; 1066 1067 invoke: 1068 /* Initialize XGMI session */ 1069 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1070 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1071 xgmi_cmd->flag_extend_link_record = set_extended_data; 1072 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1073 1074 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1075 1076 return ret; 1077 } 1078 1079 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1080 { 1081 struct ta_xgmi_shared_memory *xgmi_cmd; 1082 int ret; 1083 1084 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1085 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1086 1087 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1088 1089 /* Invoke xgmi ta to get hive id */ 1090 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1091 if (ret) 1092 return ret; 1093 1094 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1095 1096 return 0; 1097 } 1098 1099 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1100 { 1101 struct ta_xgmi_shared_memory *xgmi_cmd; 1102 int ret; 1103 1104 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1105 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1106 1107 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1108 1109 /* Invoke xgmi ta to get the node id */ 1110 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1111 if (ret) 1112 return ret; 1113 1114 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1115 1116 return 0; 1117 } 1118 1119 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1120 { 1121 return psp->adev->asic_type == CHIP_ALDEBARAN && 1122 psp->xgmi.feature_version >= 0x2000000b; 1123 } 1124 1125 /* 1126 * Chips that support extended topology information require the driver to 1127 * reflect topology information in the opposite direction. This is 1128 * because the TA has already exceeded its link record limit and if the 1129 * TA holds bi-directional information, the driver would have to do 1130 * multiple fetches instead of just two. 1131 */ 1132 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1133 struct psp_xgmi_node_info node_info) 1134 { 1135 struct amdgpu_device *mirror_adev; 1136 struct amdgpu_hive_info *hive; 1137 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1138 uint64_t dst_node_id = node_info.node_id; 1139 uint8_t dst_num_hops = node_info.num_hops; 1140 uint8_t dst_num_links = node_info.num_links; 1141 1142 hive = amdgpu_get_xgmi_hive(psp->adev); 1143 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1144 struct psp_xgmi_topology_info *mirror_top_info; 1145 int j; 1146 1147 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1148 continue; 1149 1150 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1151 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1152 if (mirror_top_info->nodes[j].node_id != src_node_id) 1153 continue; 1154 1155 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1156 /* 1157 * prevent 0 num_links value re-reflection since reflection 1158 * criteria is based on num_hops (direct or indirect). 1159 * 1160 */ 1161 if (dst_num_links) 1162 mirror_top_info->nodes[j].num_links = dst_num_links; 1163 1164 break; 1165 } 1166 1167 break; 1168 } 1169 } 1170 1171 int psp_xgmi_get_topology_info(struct psp_context *psp, 1172 int number_devices, 1173 struct psp_xgmi_topology_info *topology, 1174 bool get_extended_data) 1175 { 1176 struct ta_xgmi_shared_memory *xgmi_cmd; 1177 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1178 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1179 int i; 1180 int ret; 1181 1182 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1183 return -EINVAL; 1184 1185 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1186 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1187 xgmi_cmd->flag_extend_link_record = get_extended_data; 1188 1189 /* Fill in the shared memory with topology information as input */ 1190 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1191 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1192 topology_info_input->num_nodes = number_devices; 1193 1194 for (i = 0; i < topology_info_input->num_nodes; i++) { 1195 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1196 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1197 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1198 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1199 } 1200 1201 /* Invoke xgmi ta to get the topology information */ 1202 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1203 if (ret) 1204 return ret; 1205 1206 /* Read the output topology information from the shared memory */ 1207 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1208 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1209 for (i = 0; i < topology->num_nodes; i++) { 1210 /* extended data will either be 0 or equal to non-extended data */ 1211 if (topology_info_output->nodes[i].num_hops) 1212 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1213 1214 /* non-extended data gets everything here so no need to update */ 1215 if (!get_extended_data) { 1216 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1217 topology->nodes[i].is_sharing_enabled = 1218 topology_info_output->nodes[i].is_sharing_enabled; 1219 topology->nodes[i].sdma_engine = 1220 topology_info_output->nodes[i].sdma_engine; 1221 } 1222 1223 } 1224 1225 /* Invoke xgmi ta again to get the link information */ 1226 if (psp_xgmi_peer_link_info_supported(psp)) { 1227 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1228 1229 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1230 1231 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1232 1233 if (ret) 1234 return ret; 1235 1236 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1237 for (i = 0; i < topology->num_nodes; i++) { 1238 /* accumulate num_links on extended data */ 1239 topology->nodes[i].num_links = get_extended_data ? 1240 topology->nodes[i].num_links + 1241 link_info_output->nodes[i].num_links : 1242 link_info_output->nodes[i].num_links; 1243 1244 /* reflect the topology information for bi-directionality */ 1245 if (psp->xgmi_context.supports_extended_data && 1246 get_extended_data && topology->nodes[i].num_hops) 1247 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1248 } 1249 } 1250 1251 return 0; 1252 } 1253 1254 int psp_xgmi_set_topology_info(struct psp_context *psp, 1255 int number_devices, 1256 struct psp_xgmi_topology_info *topology) 1257 { 1258 struct ta_xgmi_shared_memory *xgmi_cmd; 1259 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1260 int i; 1261 1262 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1263 return -EINVAL; 1264 1265 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1266 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1267 1268 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1269 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1270 topology_info_input->num_nodes = number_devices; 1271 1272 for (i = 0; i < topology_info_input->num_nodes; i++) { 1273 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1274 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1275 topology_info_input->nodes[i].is_sharing_enabled = 1; 1276 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1277 } 1278 1279 /* Invoke xgmi ta to set topology information */ 1280 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1281 } 1282 1283 // ras begin 1284 static int psp_ras_init_shared_buf(struct psp_context *psp) 1285 { 1286 return psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1287 } 1288 1289 static int psp_ras_load(struct psp_context *psp) 1290 { 1291 return psp_ta_load(psp, &psp->ras, &psp->ras_context.context); 1292 } 1293 1294 static int psp_ras_unload(struct psp_context *psp) 1295 { 1296 return psp_ta_unload(psp, psp->ras_context.context.session_id); 1297 } 1298 1299 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1300 { 1301 struct ta_ras_shared_memory *ras_cmd; 1302 int ret; 1303 1304 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1305 1306 /* 1307 * TODO: bypass the loading in sriov for now 1308 */ 1309 if (amdgpu_sriov_vf(psp->adev)) 1310 return 0; 1311 1312 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras_context.context.session_id); 1313 1314 if (amdgpu_ras_intr_triggered()) 1315 return ret; 1316 1317 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1318 { 1319 DRM_WARN("RAS: Unsupported Interface"); 1320 return -EINVAL; 1321 } 1322 1323 if (!ret) { 1324 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1325 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1326 1327 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1328 } 1329 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1330 dev_warn(psp->adev->dev, 1331 "RAS internal register access blocked\n"); 1332 } 1333 1334 return ret; 1335 } 1336 1337 int psp_ras_enable_features(struct psp_context *psp, 1338 union ta_ras_cmd_input *info, bool enable) 1339 { 1340 struct ta_ras_shared_memory *ras_cmd; 1341 int ret; 1342 1343 if (!psp->ras_context.context.initialized) 1344 return -EINVAL; 1345 1346 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1347 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1348 1349 if (enable) 1350 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1351 else 1352 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1353 1354 ras_cmd->ras_in_message = *info; 1355 1356 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1357 if (ret) 1358 return -EINVAL; 1359 1360 if (ras_cmd->ras_status) 1361 dev_warn(psp->adev->dev, "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1362 1363 return 0; 1364 } 1365 1366 static int psp_ras_terminate(struct psp_context *psp) 1367 { 1368 int ret; 1369 1370 /* 1371 * TODO: bypass the terminate in sriov for now 1372 */ 1373 if (amdgpu_sriov_vf(psp->adev)) 1374 return 0; 1375 1376 if (!psp->ras_context.context.initialized) 1377 return 0; 1378 1379 ret = psp_ras_unload(psp); 1380 if (ret) 1381 return ret; 1382 1383 psp->ras_context.context.initialized = false; 1384 1385 /* free ras shared memory */ 1386 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 1387 1388 return 0; 1389 } 1390 1391 static int psp_ras_initialize(struct psp_context *psp) 1392 { 1393 int ret; 1394 uint32_t boot_cfg = 0xFF; 1395 struct amdgpu_device *adev = psp->adev; 1396 struct ta_ras_shared_memory *ras_cmd; 1397 1398 /* 1399 * TODO: bypass the initialize in sriov for now 1400 */ 1401 if (amdgpu_sriov_vf(adev)) 1402 return 0; 1403 1404 if (!adev->psp.ras.size_bytes || 1405 !adev->psp.ras.start_addr) { 1406 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1407 return 0; 1408 } 1409 1410 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1411 /* query GECC enablement status from boot config 1412 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1413 */ 1414 ret = psp_boot_config_get(adev, &boot_cfg); 1415 if (ret) 1416 dev_warn(adev->dev, "PSP get boot config failed\n"); 1417 1418 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1419 if (!boot_cfg) { 1420 dev_info(adev->dev, "GECC is disabled\n"); 1421 } else { 1422 /* disable GECC in next boot cycle if ras is 1423 * disabled by module parameter amdgpu_ras_enable 1424 * and/or amdgpu_ras_mask, or boot_config_get call 1425 * is failed 1426 */ 1427 ret = psp_boot_config_set(adev, 0); 1428 if (ret) 1429 dev_warn(adev->dev, "PSP set boot config failed\n"); 1430 else 1431 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1432 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1433 } 1434 } else { 1435 if (1 == boot_cfg) { 1436 dev_info(adev->dev, "GECC is enabled\n"); 1437 } else { 1438 /* enable GECC in next boot cycle if it is disabled 1439 * in boot config, or force enable GECC if failed to 1440 * get boot configuration 1441 */ 1442 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1443 if (ret) 1444 dev_warn(adev->dev, "PSP set boot config failed\n"); 1445 else 1446 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1447 } 1448 } 1449 } 1450 1451 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1452 1453 if (!psp->ras_context.context.initialized) { 1454 ret = psp_ras_init_shared_buf(psp); 1455 if (ret) 1456 return ret; 1457 } 1458 1459 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1460 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1461 1462 if (psp->adev->gmc.xgmi.connected_to_cpu) 1463 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1464 else 1465 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1466 1467 ret = psp_ras_load(psp); 1468 1469 if (!ret && !ras_cmd->ras_status) 1470 psp->ras_context.context.initialized = true; 1471 else { 1472 if (ras_cmd->ras_status) 1473 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1474 amdgpu_ras_fini(psp->adev); 1475 } 1476 1477 return ret; 1478 } 1479 1480 int psp_ras_trigger_error(struct psp_context *psp, 1481 struct ta_ras_trigger_error_input *info) 1482 { 1483 struct ta_ras_shared_memory *ras_cmd; 1484 int ret; 1485 1486 if (!psp->ras_context.context.initialized) 1487 return -EINVAL; 1488 1489 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1490 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1491 1492 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1493 ras_cmd->ras_in_message.trigger_error = *info; 1494 1495 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1496 if (ret) 1497 return -EINVAL; 1498 1499 /* If err_event_athub occurs error inject was successful, however 1500 return status from TA is no long reliable */ 1501 if (amdgpu_ras_intr_triggered()) 1502 return 0; 1503 1504 if (ras_cmd->ras_status) { 1505 dev_warn(psp->adev->dev, "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1506 return -EINVAL; 1507 } 1508 1509 return 0; 1510 } 1511 // ras end 1512 1513 // HDCP start 1514 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1515 { 1516 return psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1517 } 1518 1519 static int psp_hdcp_load(struct psp_context *psp) 1520 { 1521 return psp_ta_load(psp, &psp->hdcp, &psp->hdcp_context.context); 1522 } 1523 static int psp_hdcp_initialize(struct psp_context *psp) 1524 { 1525 int ret; 1526 1527 /* 1528 * TODO: bypass the initialize in sriov for now 1529 */ 1530 if (amdgpu_sriov_vf(psp->adev)) 1531 return 0; 1532 1533 if (!psp->hdcp.size_bytes || 1534 !psp->hdcp.start_addr) { 1535 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1536 return 0; 1537 } 1538 1539 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1540 1541 if (!psp->hdcp_context.context.initialized) { 1542 ret = psp_hdcp_init_shared_buf(psp); 1543 if (ret) 1544 return ret; 1545 } 1546 1547 ret = psp_hdcp_load(psp); 1548 if (!ret) { 1549 psp->hdcp_context.context.initialized = true; 1550 mutex_init(&psp->hdcp_context.mutex); 1551 } 1552 1553 return ret; 1554 } 1555 1556 static int psp_hdcp_unload(struct psp_context *psp) 1557 { 1558 return psp_ta_unload(psp, psp->hdcp_context.context.session_id); 1559 } 1560 1561 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1562 { 1563 /* 1564 * TODO: bypass the loading in sriov for now 1565 */ 1566 if (amdgpu_sriov_vf(psp->adev)) 1567 return 0; 1568 1569 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.context.session_id); 1570 } 1571 1572 static int psp_hdcp_terminate(struct psp_context *psp) 1573 { 1574 int ret; 1575 1576 /* 1577 * TODO: bypass the terminate in sriov for now 1578 */ 1579 if (amdgpu_sriov_vf(psp->adev)) 1580 return 0; 1581 1582 if (!psp->hdcp_context.context.initialized) { 1583 if (psp->hdcp_context.context.mem_context.shared_buf) 1584 goto out; 1585 else 1586 return 0; 1587 } 1588 1589 ret = psp_hdcp_unload(psp); 1590 if (ret) 1591 return ret; 1592 1593 psp->hdcp_context.context.initialized = false; 1594 1595 out: 1596 /* free hdcp shared memory */ 1597 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 1598 1599 return 0; 1600 } 1601 // HDCP end 1602 1603 // DTM start 1604 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1605 { 1606 return psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1607 } 1608 1609 static int psp_dtm_load(struct psp_context *psp) 1610 { 1611 return psp_ta_load(psp, &psp->dtm, &psp->dtm_context.context); 1612 } 1613 1614 static int psp_dtm_initialize(struct psp_context *psp) 1615 { 1616 int ret; 1617 1618 /* 1619 * TODO: bypass the initialize in sriov for now 1620 */ 1621 if (amdgpu_sriov_vf(psp->adev)) 1622 return 0; 1623 1624 if (!psp->dtm.size_bytes || 1625 !psp->dtm.start_addr) { 1626 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1627 return 0; 1628 } 1629 1630 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1631 1632 if (!psp->dtm_context.context.initialized) { 1633 ret = psp_dtm_init_shared_buf(psp); 1634 if (ret) 1635 return ret; 1636 } 1637 1638 ret = psp_dtm_load(psp); 1639 if (!ret) { 1640 psp->dtm_context.context.initialized = true; 1641 mutex_init(&psp->dtm_context.mutex); 1642 } 1643 1644 return ret; 1645 } 1646 1647 static int psp_dtm_unload(struct psp_context *psp) 1648 { 1649 return psp_ta_unload(psp, psp->dtm_context.context.session_id); 1650 } 1651 1652 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1653 { 1654 /* 1655 * TODO: bypass the loading in sriov for now 1656 */ 1657 if (amdgpu_sriov_vf(psp->adev)) 1658 return 0; 1659 1660 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.context.session_id); 1661 } 1662 1663 static int psp_dtm_terminate(struct psp_context *psp) 1664 { 1665 int ret; 1666 1667 /* 1668 * TODO: bypass the terminate in sriov for now 1669 */ 1670 if (amdgpu_sriov_vf(psp->adev)) 1671 return 0; 1672 1673 if (!psp->dtm_context.context.initialized) { 1674 if (psp->dtm_context.context.mem_context.shared_buf) 1675 goto out; 1676 else 1677 return 0; 1678 } 1679 1680 ret = psp_dtm_unload(psp); 1681 if (ret) 1682 return ret; 1683 1684 psp->dtm_context.context.initialized = false; 1685 1686 out: 1687 /* free dtm shared memory */ 1688 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 1689 1690 return 0; 1691 } 1692 // DTM end 1693 1694 // RAP start 1695 static int psp_rap_init_shared_buf(struct psp_context *psp) 1696 { 1697 return psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1698 } 1699 1700 static int psp_rap_load(struct psp_context *psp) 1701 { 1702 return psp_ta_load(psp, &psp->rap, &psp->rap_context.context); 1703 } 1704 1705 static int psp_rap_unload(struct psp_context *psp) 1706 { 1707 return psp_ta_unload(psp, psp->rap_context.context.session_id); 1708 } 1709 1710 static int psp_rap_initialize(struct psp_context *psp) 1711 { 1712 int ret; 1713 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1714 1715 /* 1716 * TODO: bypass the initialize in sriov for now 1717 */ 1718 if (amdgpu_sriov_vf(psp->adev)) 1719 return 0; 1720 1721 if (!psp->rap.size_bytes || 1722 !psp->rap.start_addr) { 1723 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1724 return 0; 1725 } 1726 1727 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1728 1729 if (!psp->rap_context.context.initialized) { 1730 ret = psp_rap_init_shared_buf(psp); 1731 if (ret) 1732 return ret; 1733 } 1734 1735 ret = psp_rap_load(psp); 1736 if (!ret) { 1737 psp->rap_context.context.initialized = true; 1738 mutex_init(&psp->rap_context.mutex); 1739 } else 1740 return ret; 1741 1742 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1743 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1744 psp_rap_terminate(psp); 1745 1746 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1747 ret, status); 1748 1749 return ret; 1750 } 1751 1752 return 0; 1753 } 1754 1755 static int psp_rap_terminate(struct psp_context *psp) 1756 { 1757 int ret; 1758 1759 if (!psp->rap_context.context.initialized) 1760 return 0; 1761 1762 ret = psp_rap_unload(psp); 1763 1764 psp->rap_context.context.initialized = false; 1765 1766 /* free rap shared memory */ 1767 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1768 1769 return ret; 1770 } 1771 1772 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1773 { 1774 struct ta_rap_shared_memory *rap_cmd; 1775 int ret = 0; 1776 1777 if (!psp->rap_context.context.initialized) 1778 return 0; 1779 1780 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1781 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1782 return -EINVAL; 1783 1784 mutex_lock(&psp->rap_context.mutex); 1785 1786 rap_cmd = (struct ta_rap_shared_memory *) 1787 psp->rap_context.context.mem_context.shared_buf; 1788 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1789 1790 rap_cmd->cmd_id = ta_cmd_id; 1791 rap_cmd->validation_method_id = METHOD_A; 1792 1793 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.context.session_id); 1794 if (ret) 1795 goto out_unlock; 1796 1797 if (status) 1798 *status = rap_cmd->rap_status; 1799 1800 out_unlock: 1801 mutex_unlock(&psp->rap_context.mutex); 1802 1803 return ret; 1804 } 1805 // RAP end 1806 1807 /* securedisplay start */ 1808 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1809 { 1810 return psp_ta_init_shared_buf( 1811 psp, &psp->securedisplay_context.context.mem_context); 1812 } 1813 1814 static int psp_securedisplay_load(struct psp_context *psp) 1815 { 1816 return psp_ta_load(psp, &psp->securedisplay, 1817 &psp->securedisplay_context.context); 1818 } 1819 1820 static int psp_securedisplay_unload(struct psp_context *psp) 1821 { 1822 return psp_ta_unload(psp, psp->securedisplay_context.context.session_id); 1823 } 1824 1825 static int psp_securedisplay_initialize(struct psp_context *psp) 1826 { 1827 int ret; 1828 struct securedisplay_cmd *securedisplay_cmd; 1829 1830 /* 1831 * TODO: bypass the initialize in sriov for now 1832 */ 1833 if (amdgpu_sriov_vf(psp->adev)) 1834 return 0; 1835 1836 if (!psp->securedisplay.size_bytes || 1837 !psp->securedisplay.start_addr) { 1838 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1839 return 0; 1840 } 1841 1842 psp->securedisplay_context.context.mem_context.shared_mem_size = 1843 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1844 1845 if (!psp->securedisplay_context.context.initialized) { 1846 ret = psp_securedisplay_init_shared_buf(psp); 1847 if (ret) 1848 return ret; 1849 } 1850 1851 ret = psp_securedisplay_load(psp); 1852 if (!ret) { 1853 psp->securedisplay_context.context.initialized = true; 1854 mutex_init(&psp->securedisplay_context.mutex); 1855 } else 1856 return ret; 1857 1858 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1859 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1860 1861 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1862 if (ret) { 1863 psp_securedisplay_terminate(psp); 1864 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1865 return -EINVAL; 1866 } 1867 1868 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1869 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1870 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1871 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1872 } 1873 1874 return 0; 1875 } 1876 1877 static int psp_securedisplay_terminate(struct psp_context *psp) 1878 { 1879 int ret; 1880 1881 /* 1882 * TODO:bypass the terminate in sriov for now 1883 */ 1884 if (amdgpu_sriov_vf(psp->adev)) 1885 return 0; 1886 1887 if (!psp->securedisplay_context.context.initialized) 1888 return 0; 1889 1890 ret = psp_securedisplay_unload(psp); 1891 if (ret) 1892 return ret; 1893 1894 psp->securedisplay_context.context.initialized = false; 1895 1896 /* free securedisplay shared memory */ 1897 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1898 1899 return ret; 1900 } 1901 1902 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1903 { 1904 int ret; 1905 1906 if (!psp->securedisplay_context.context.initialized) 1907 return -EINVAL; 1908 1909 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1910 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1911 return -EINVAL; 1912 1913 mutex_lock(&psp->securedisplay_context.mutex); 1914 1915 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.context.session_id); 1916 1917 mutex_unlock(&psp->securedisplay_context.mutex); 1918 1919 return ret; 1920 } 1921 /* SECUREDISPLAY end */ 1922 1923 static int psp_hw_start(struct psp_context *psp) 1924 { 1925 struct amdgpu_device *adev = psp->adev; 1926 int ret; 1927 1928 if (!amdgpu_sriov_vf(adev)) { 1929 if ((is_psp_fw_valid(psp->kdb)) && 1930 (psp->funcs->bootloader_load_kdb != NULL)) { 1931 ret = psp_bootloader_load_kdb(psp); 1932 if (ret) { 1933 DRM_ERROR("PSP load kdb failed!\n"); 1934 return ret; 1935 } 1936 } 1937 1938 if ((is_psp_fw_valid(psp->spl)) && 1939 (psp->funcs->bootloader_load_spl != NULL)) { 1940 ret = psp_bootloader_load_spl(psp); 1941 if (ret) { 1942 DRM_ERROR("PSP load spl failed!\n"); 1943 return ret; 1944 } 1945 } 1946 1947 if ((is_psp_fw_valid(psp->sys)) && 1948 (psp->funcs->bootloader_load_sysdrv != NULL)) { 1949 ret = psp_bootloader_load_sysdrv(psp); 1950 if (ret) { 1951 DRM_ERROR("PSP load sys drv failed!\n"); 1952 return ret; 1953 } 1954 } 1955 1956 if ((is_psp_fw_valid(psp->soc_drv)) && 1957 (psp->funcs->bootloader_load_soc_drv != NULL)) { 1958 ret = psp_bootloader_load_soc_drv(psp); 1959 if (ret) { 1960 DRM_ERROR("PSP load soc drv failed!\n"); 1961 return ret; 1962 } 1963 } 1964 1965 if ((is_psp_fw_valid(psp->intf_drv)) && 1966 (psp->funcs->bootloader_load_intf_drv != NULL)) { 1967 ret = psp_bootloader_load_intf_drv(psp); 1968 if (ret) { 1969 DRM_ERROR("PSP load intf drv failed!\n"); 1970 return ret; 1971 } 1972 } 1973 1974 if ((is_psp_fw_valid(psp->dbg_drv)) && 1975 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 1976 ret = psp_bootloader_load_dbg_drv(psp); 1977 if (ret) { 1978 DRM_ERROR("PSP load dbg drv failed!\n"); 1979 return ret; 1980 } 1981 } 1982 1983 if ((is_psp_fw_valid(psp->sos)) && 1984 (psp->funcs->bootloader_load_sos != NULL)) { 1985 ret = psp_bootloader_load_sos(psp); 1986 if (ret) { 1987 DRM_ERROR("PSP load sos failed!\n"); 1988 return ret; 1989 } 1990 } 1991 } 1992 1993 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1994 if (ret) { 1995 DRM_ERROR("PSP create ring failed!\n"); 1996 return ret; 1997 } 1998 1999 ret = psp_tmr_init(psp); 2000 if (ret) { 2001 DRM_ERROR("PSP tmr init failed!\n"); 2002 return ret; 2003 } 2004 2005 /* 2006 * For ASICs with DF Cstate management centralized 2007 * to PMFW, TMR setup should be performed after PMFW 2008 * loaded and before other non-psp firmware loaded. 2009 */ 2010 if (psp->pmfw_centralized_cstate_management) { 2011 ret = psp_load_smu_fw(psp); 2012 if (ret) 2013 return ret; 2014 } 2015 2016 ret = psp_tmr_load(psp); 2017 if (ret) { 2018 DRM_ERROR("PSP load tmr failed!\n"); 2019 return ret; 2020 } 2021 2022 return 0; 2023 } 2024 2025 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2026 enum psp_gfx_fw_type *type) 2027 { 2028 switch (ucode->ucode_id) { 2029 case AMDGPU_UCODE_ID_SDMA0: 2030 *type = GFX_FW_TYPE_SDMA0; 2031 break; 2032 case AMDGPU_UCODE_ID_SDMA1: 2033 *type = GFX_FW_TYPE_SDMA1; 2034 break; 2035 case AMDGPU_UCODE_ID_SDMA2: 2036 *type = GFX_FW_TYPE_SDMA2; 2037 break; 2038 case AMDGPU_UCODE_ID_SDMA3: 2039 *type = GFX_FW_TYPE_SDMA3; 2040 break; 2041 case AMDGPU_UCODE_ID_SDMA4: 2042 *type = GFX_FW_TYPE_SDMA4; 2043 break; 2044 case AMDGPU_UCODE_ID_SDMA5: 2045 *type = GFX_FW_TYPE_SDMA5; 2046 break; 2047 case AMDGPU_UCODE_ID_SDMA6: 2048 *type = GFX_FW_TYPE_SDMA6; 2049 break; 2050 case AMDGPU_UCODE_ID_SDMA7: 2051 *type = GFX_FW_TYPE_SDMA7; 2052 break; 2053 case AMDGPU_UCODE_ID_CP_MES: 2054 *type = GFX_FW_TYPE_CP_MES; 2055 break; 2056 case AMDGPU_UCODE_ID_CP_MES_DATA: 2057 *type = GFX_FW_TYPE_MES_STACK; 2058 break; 2059 case AMDGPU_UCODE_ID_CP_CE: 2060 *type = GFX_FW_TYPE_CP_CE; 2061 break; 2062 case AMDGPU_UCODE_ID_CP_PFP: 2063 *type = GFX_FW_TYPE_CP_PFP; 2064 break; 2065 case AMDGPU_UCODE_ID_CP_ME: 2066 *type = GFX_FW_TYPE_CP_ME; 2067 break; 2068 case AMDGPU_UCODE_ID_CP_MEC1: 2069 *type = GFX_FW_TYPE_CP_MEC; 2070 break; 2071 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2072 *type = GFX_FW_TYPE_CP_MEC_ME1; 2073 break; 2074 case AMDGPU_UCODE_ID_CP_MEC2: 2075 *type = GFX_FW_TYPE_CP_MEC; 2076 break; 2077 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2078 *type = GFX_FW_TYPE_CP_MEC_ME2; 2079 break; 2080 case AMDGPU_UCODE_ID_RLC_G: 2081 *type = GFX_FW_TYPE_RLC_G; 2082 break; 2083 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2084 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2085 break; 2086 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2087 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2088 break; 2089 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2090 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2091 break; 2092 case AMDGPU_UCODE_ID_RLC_IRAM: 2093 *type = GFX_FW_TYPE_RLC_IRAM; 2094 break; 2095 case AMDGPU_UCODE_ID_RLC_DRAM: 2096 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2097 break; 2098 case AMDGPU_UCODE_ID_SMC: 2099 *type = GFX_FW_TYPE_SMU; 2100 break; 2101 case AMDGPU_UCODE_ID_UVD: 2102 *type = GFX_FW_TYPE_UVD; 2103 break; 2104 case AMDGPU_UCODE_ID_UVD1: 2105 *type = GFX_FW_TYPE_UVD1; 2106 break; 2107 case AMDGPU_UCODE_ID_VCE: 2108 *type = GFX_FW_TYPE_VCE; 2109 break; 2110 case AMDGPU_UCODE_ID_VCN: 2111 *type = GFX_FW_TYPE_VCN; 2112 break; 2113 case AMDGPU_UCODE_ID_VCN1: 2114 *type = GFX_FW_TYPE_VCN1; 2115 break; 2116 case AMDGPU_UCODE_ID_DMCU_ERAM: 2117 *type = GFX_FW_TYPE_DMCU_ERAM; 2118 break; 2119 case AMDGPU_UCODE_ID_DMCU_INTV: 2120 *type = GFX_FW_TYPE_DMCU_ISR; 2121 break; 2122 case AMDGPU_UCODE_ID_VCN0_RAM: 2123 *type = GFX_FW_TYPE_VCN0_RAM; 2124 break; 2125 case AMDGPU_UCODE_ID_VCN1_RAM: 2126 *type = GFX_FW_TYPE_VCN1_RAM; 2127 break; 2128 case AMDGPU_UCODE_ID_DMCUB: 2129 *type = GFX_FW_TYPE_DMUB; 2130 break; 2131 case AMDGPU_UCODE_ID_MAXIMUM: 2132 default: 2133 return -EINVAL; 2134 } 2135 2136 return 0; 2137 } 2138 2139 static void psp_print_fw_hdr(struct psp_context *psp, 2140 struct amdgpu_firmware_info *ucode) 2141 { 2142 struct amdgpu_device *adev = psp->adev; 2143 struct common_firmware_header *hdr; 2144 2145 switch (ucode->ucode_id) { 2146 case AMDGPU_UCODE_ID_SDMA0: 2147 case AMDGPU_UCODE_ID_SDMA1: 2148 case AMDGPU_UCODE_ID_SDMA2: 2149 case AMDGPU_UCODE_ID_SDMA3: 2150 case AMDGPU_UCODE_ID_SDMA4: 2151 case AMDGPU_UCODE_ID_SDMA5: 2152 case AMDGPU_UCODE_ID_SDMA6: 2153 case AMDGPU_UCODE_ID_SDMA7: 2154 hdr = (struct common_firmware_header *) 2155 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2156 amdgpu_ucode_print_sdma_hdr(hdr); 2157 break; 2158 case AMDGPU_UCODE_ID_CP_CE: 2159 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2160 amdgpu_ucode_print_gfx_hdr(hdr); 2161 break; 2162 case AMDGPU_UCODE_ID_CP_PFP: 2163 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2164 amdgpu_ucode_print_gfx_hdr(hdr); 2165 break; 2166 case AMDGPU_UCODE_ID_CP_ME: 2167 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2168 amdgpu_ucode_print_gfx_hdr(hdr); 2169 break; 2170 case AMDGPU_UCODE_ID_CP_MEC1: 2171 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2172 amdgpu_ucode_print_gfx_hdr(hdr); 2173 break; 2174 case AMDGPU_UCODE_ID_RLC_G: 2175 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2176 amdgpu_ucode_print_rlc_hdr(hdr); 2177 break; 2178 case AMDGPU_UCODE_ID_SMC: 2179 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2180 amdgpu_ucode_print_smc_hdr(hdr); 2181 break; 2182 default: 2183 break; 2184 } 2185 } 2186 2187 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2188 struct psp_gfx_cmd_resp *cmd) 2189 { 2190 int ret; 2191 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2192 2193 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2194 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2195 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2196 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2197 2198 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2199 if (ret) 2200 DRM_ERROR("Unknown firmware type\n"); 2201 2202 return ret; 2203 } 2204 2205 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2206 struct amdgpu_firmware_info *ucode) 2207 { 2208 int ret = 0; 2209 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2210 2211 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2212 if (!ret) { 2213 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2214 psp->fence_buf_mc_addr); 2215 } 2216 2217 release_psp_cmd_buf(psp); 2218 2219 return ret; 2220 } 2221 2222 static int psp_load_smu_fw(struct psp_context *psp) 2223 { 2224 int ret; 2225 struct amdgpu_device *adev = psp->adev; 2226 struct amdgpu_firmware_info *ucode = 2227 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2228 struct amdgpu_ras *ras = psp->ras_context.ras; 2229 2230 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2231 return 0; 2232 2233 if ((amdgpu_in_reset(adev) && 2234 ras && adev->ras_enabled && 2235 (adev->asic_type == CHIP_ARCTURUS || 2236 adev->asic_type == CHIP_VEGA20))) { 2237 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2238 if (ret) { 2239 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2240 } 2241 } 2242 2243 ret = psp_execute_non_psp_fw_load(psp, ucode); 2244 2245 if (ret) 2246 DRM_ERROR("PSP load smu failed!\n"); 2247 2248 return ret; 2249 } 2250 2251 static bool fw_load_skip_check(struct psp_context *psp, 2252 struct amdgpu_firmware_info *ucode) 2253 { 2254 if (!ucode->fw) 2255 return true; 2256 2257 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2258 (psp_smu_reload_quirk(psp) || 2259 psp->autoload_supported || 2260 psp->pmfw_centralized_cstate_management)) 2261 return true; 2262 2263 if (amdgpu_sriov_vf(psp->adev) && 2264 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2265 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2266 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2267 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2268 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2269 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2270 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2271 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2272 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2273 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2274 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2275 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2276 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2277 /*skip ucode loading in SRIOV VF */ 2278 return true; 2279 2280 if (psp->autoload_supported && 2281 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2282 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2283 /* skip mec JT when autoload is enabled */ 2284 return true; 2285 2286 return false; 2287 } 2288 2289 int psp_load_fw_list(struct psp_context *psp, 2290 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2291 { 2292 int ret = 0, i; 2293 struct amdgpu_firmware_info *ucode; 2294 2295 for (i = 0; i < ucode_count; ++i) { 2296 ucode = ucode_list[i]; 2297 psp_print_fw_hdr(psp, ucode); 2298 ret = psp_execute_non_psp_fw_load(psp, ucode); 2299 if (ret) 2300 return ret; 2301 } 2302 return ret; 2303 } 2304 2305 static int psp_load_non_psp_fw(struct psp_context *psp) 2306 { 2307 int i, ret; 2308 struct amdgpu_firmware_info *ucode; 2309 struct amdgpu_device *adev = psp->adev; 2310 2311 if (psp->autoload_supported && 2312 !psp->pmfw_centralized_cstate_management) { 2313 ret = psp_load_smu_fw(psp); 2314 if (ret) 2315 return ret; 2316 } 2317 2318 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2319 ucode = &adev->firmware.ucode[i]; 2320 2321 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2322 !fw_load_skip_check(psp, ucode)) { 2323 ret = psp_load_smu_fw(psp); 2324 if (ret) 2325 return ret; 2326 continue; 2327 } 2328 2329 if (fw_load_skip_check(psp, ucode)) 2330 continue; 2331 2332 if (psp->autoload_supported && 2333 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2334 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2335 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2336 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2337 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2338 /* PSP only receive one SDMA fw for sienna_cichlid, 2339 * as all four sdma fw are same */ 2340 continue; 2341 2342 psp_print_fw_hdr(psp, ucode); 2343 2344 ret = psp_execute_non_psp_fw_load(psp, ucode); 2345 if (ret) 2346 return ret; 2347 2348 /* Start rlc autoload after psp recieved all the gfx firmware */ 2349 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2350 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2351 ret = psp_rlc_autoload_start(psp); 2352 if (ret) { 2353 DRM_ERROR("Failed to start rlc autoload\n"); 2354 return ret; 2355 } 2356 } 2357 } 2358 2359 return 0; 2360 } 2361 2362 static int psp_load_fw(struct amdgpu_device *adev) 2363 { 2364 int ret; 2365 struct psp_context *psp = &adev->psp; 2366 2367 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2368 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2369 goto skip_memalloc; 2370 } 2371 2372 if (amdgpu_sriov_vf(adev)) { 2373 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2374 AMDGPU_GEM_DOMAIN_VRAM, 2375 &psp->fw_pri_bo, 2376 &psp->fw_pri_mc_addr, 2377 &psp->fw_pri_buf); 2378 } else { 2379 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2380 AMDGPU_GEM_DOMAIN_GTT, 2381 &psp->fw_pri_bo, 2382 &psp->fw_pri_mc_addr, 2383 &psp->fw_pri_buf); 2384 } 2385 2386 if (ret) 2387 goto failed; 2388 2389 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2390 AMDGPU_GEM_DOMAIN_VRAM, 2391 &psp->fence_buf_bo, 2392 &psp->fence_buf_mc_addr, 2393 &psp->fence_buf); 2394 if (ret) 2395 goto failed; 2396 2397 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2398 AMDGPU_GEM_DOMAIN_VRAM, 2399 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2400 (void **)&psp->cmd_buf_mem); 2401 if (ret) 2402 goto failed; 2403 2404 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2405 2406 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2407 if (ret) { 2408 DRM_ERROR("PSP ring init failed!\n"); 2409 goto failed; 2410 } 2411 2412 skip_memalloc: 2413 ret = psp_hw_start(psp); 2414 if (ret) 2415 goto failed; 2416 2417 ret = psp_load_non_psp_fw(psp); 2418 if (ret) 2419 goto failed; 2420 2421 ret = psp_asd_load(psp); 2422 if (ret) { 2423 DRM_ERROR("PSP load asd failed!\n"); 2424 return ret; 2425 } 2426 2427 ret = psp_rl_load(adev); 2428 if (ret) { 2429 DRM_ERROR("PSP load RL failed!\n"); 2430 return ret; 2431 } 2432 2433 if (psp->ta_fw) { 2434 ret = psp_ras_initialize(psp); 2435 if (ret) 2436 dev_err(psp->adev->dev, 2437 "RAS: Failed to initialize RAS\n"); 2438 2439 ret = psp_hdcp_initialize(psp); 2440 if (ret) 2441 dev_err(psp->adev->dev, 2442 "HDCP: Failed to initialize HDCP\n"); 2443 2444 ret = psp_dtm_initialize(psp); 2445 if (ret) 2446 dev_err(psp->adev->dev, 2447 "DTM: Failed to initialize DTM\n"); 2448 2449 ret = psp_rap_initialize(psp); 2450 if (ret) 2451 dev_err(psp->adev->dev, 2452 "RAP: Failed to initialize RAP\n"); 2453 2454 ret = psp_securedisplay_initialize(psp); 2455 if (ret) 2456 dev_err(psp->adev->dev, 2457 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2458 } 2459 2460 return 0; 2461 2462 failed: 2463 /* 2464 * all cleanup jobs (xgmi terminate, ras terminate, 2465 * ring destroy, cmd/fence/fw buffers destory, 2466 * psp->cmd destory) are delayed to psp_hw_fini 2467 */ 2468 return ret; 2469 } 2470 2471 static int psp_hw_init(void *handle) 2472 { 2473 int ret; 2474 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2475 2476 mutex_lock(&adev->firmware.mutex); 2477 /* 2478 * This sequence is just used on hw_init only once, no need on 2479 * resume. 2480 */ 2481 ret = amdgpu_ucode_init_bo(adev); 2482 if (ret) 2483 goto failed; 2484 2485 ret = psp_load_fw(adev); 2486 if (ret) { 2487 DRM_ERROR("PSP firmware loading failed\n"); 2488 goto failed; 2489 } 2490 2491 mutex_unlock(&adev->firmware.mutex); 2492 return 0; 2493 2494 failed: 2495 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2496 mutex_unlock(&adev->firmware.mutex); 2497 return -EINVAL; 2498 } 2499 2500 static int psp_hw_fini(void *handle) 2501 { 2502 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2503 struct psp_context *psp = &adev->psp; 2504 2505 if (psp->ta_fw) { 2506 psp_ras_terminate(psp); 2507 psp_securedisplay_terminate(psp); 2508 psp_rap_terminate(psp); 2509 psp_dtm_terminate(psp); 2510 psp_hdcp_terminate(psp); 2511 } 2512 2513 psp_asd_terminate(psp); 2514 2515 psp_tmr_terminate(psp); 2516 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2517 2518 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2519 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2520 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2521 &psp->fence_buf_mc_addr, &psp->fence_buf); 2522 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2523 (void **)&psp->cmd_buf_mem); 2524 2525 return 0; 2526 } 2527 2528 static int psp_suspend(void *handle) 2529 { 2530 int ret; 2531 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2532 struct psp_context *psp = &adev->psp; 2533 2534 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2535 psp->xgmi_context.context.initialized) { 2536 ret = psp_xgmi_terminate(psp); 2537 if (ret) { 2538 DRM_ERROR("Failed to terminate xgmi ta\n"); 2539 return ret; 2540 } 2541 } 2542 2543 if (psp->ta_fw) { 2544 ret = psp_ras_terminate(psp); 2545 if (ret) { 2546 DRM_ERROR("Failed to terminate ras ta\n"); 2547 return ret; 2548 } 2549 ret = psp_hdcp_terminate(psp); 2550 if (ret) { 2551 DRM_ERROR("Failed to terminate hdcp ta\n"); 2552 return ret; 2553 } 2554 ret = psp_dtm_terminate(psp); 2555 if (ret) { 2556 DRM_ERROR("Failed to terminate dtm ta\n"); 2557 return ret; 2558 } 2559 ret = psp_rap_terminate(psp); 2560 if (ret) { 2561 DRM_ERROR("Failed to terminate rap ta\n"); 2562 return ret; 2563 } 2564 ret = psp_securedisplay_terminate(psp); 2565 if (ret) { 2566 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2567 return ret; 2568 } 2569 } 2570 2571 ret = psp_asd_terminate(psp); 2572 if (ret) { 2573 DRM_ERROR("Failed to terminate asd\n"); 2574 return ret; 2575 } 2576 2577 ret = psp_tmr_terminate(psp); 2578 if (ret) { 2579 DRM_ERROR("Failed to terminate tmr\n"); 2580 return ret; 2581 } 2582 2583 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2584 if (ret) { 2585 DRM_ERROR("PSP ring stop failed\n"); 2586 return ret; 2587 } 2588 2589 return 0; 2590 } 2591 2592 static int psp_resume(void *handle) 2593 { 2594 int ret; 2595 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2596 struct psp_context *psp = &adev->psp; 2597 2598 DRM_INFO("PSP is resuming...\n"); 2599 2600 if (psp->mem_train_ctx.enable_mem_training) { 2601 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2602 if (ret) { 2603 DRM_ERROR("Failed to process memory training!\n"); 2604 return ret; 2605 } 2606 } 2607 2608 mutex_lock(&adev->firmware.mutex); 2609 2610 ret = psp_hw_start(psp); 2611 if (ret) 2612 goto failed; 2613 2614 ret = psp_load_non_psp_fw(psp); 2615 if (ret) 2616 goto failed; 2617 2618 ret = psp_asd_load(psp); 2619 if (ret) { 2620 DRM_ERROR("PSP load asd failed!\n"); 2621 goto failed; 2622 } 2623 2624 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2625 ret = psp_xgmi_initialize(psp, false, true); 2626 /* Warning the XGMI seesion initialize failure 2627 * Instead of stop driver initialization 2628 */ 2629 if (ret) 2630 dev_err(psp->adev->dev, 2631 "XGMI: Failed to initialize XGMI session\n"); 2632 } 2633 2634 if (psp->ta_fw) { 2635 ret = psp_ras_initialize(psp); 2636 if (ret) 2637 dev_err(psp->adev->dev, 2638 "RAS: Failed to initialize RAS\n"); 2639 2640 ret = psp_hdcp_initialize(psp); 2641 if (ret) 2642 dev_err(psp->adev->dev, 2643 "HDCP: Failed to initialize HDCP\n"); 2644 2645 ret = psp_dtm_initialize(psp); 2646 if (ret) 2647 dev_err(psp->adev->dev, 2648 "DTM: Failed to initialize DTM\n"); 2649 2650 ret = psp_rap_initialize(psp); 2651 if (ret) 2652 dev_err(psp->adev->dev, 2653 "RAP: Failed to initialize RAP\n"); 2654 2655 ret = psp_securedisplay_initialize(psp); 2656 if (ret) 2657 dev_err(psp->adev->dev, 2658 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2659 } 2660 2661 mutex_unlock(&adev->firmware.mutex); 2662 2663 return 0; 2664 2665 failed: 2666 DRM_ERROR("PSP resume failed\n"); 2667 mutex_unlock(&adev->firmware.mutex); 2668 return ret; 2669 } 2670 2671 int psp_gpu_reset(struct amdgpu_device *adev) 2672 { 2673 int ret; 2674 2675 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2676 return 0; 2677 2678 mutex_lock(&adev->psp.mutex); 2679 ret = psp_mode1_reset(&adev->psp); 2680 mutex_unlock(&adev->psp.mutex); 2681 2682 return ret; 2683 } 2684 2685 int psp_rlc_autoload_start(struct psp_context *psp) 2686 { 2687 int ret; 2688 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2689 2690 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2691 2692 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2693 psp->fence_buf_mc_addr); 2694 2695 release_psp_cmd_buf(psp); 2696 2697 return ret; 2698 } 2699 2700 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2701 uint64_t cmd_gpu_addr, int cmd_size) 2702 { 2703 struct amdgpu_firmware_info ucode = {0}; 2704 2705 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2706 AMDGPU_UCODE_ID_VCN0_RAM; 2707 ucode.mc_addr = cmd_gpu_addr; 2708 ucode.ucode_size = cmd_size; 2709 2710 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2711 } 2712 2713 int psp_ring_cmd_submit(struct psp_context *psp, 2714 uint64_t cmd_buf_mc_addr, 2715 uint64_t fence_mc_addr, 2716 int index) 2717 { 2718 unsigned int psp_write_ptr_reg = 0; 2719 struct psp_gfx_rb_frame *write_frame; 2720 struct psp_ring *ring = &psp->km_ring; 2721 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2722 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2723 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2724 struct amdgpu_device *adev = psp->adev; 2725 uint32_t ring_size_dw = ring->ring_size / 4; 2726 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2727 2728 /* KM (GPCOM) prepare write pointer */ 2729 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2730 2731 /* Update KM RB frame pointer to new frame */ 2732 /* write_frame ptr increments by size of rb_frame in bytes */ 2733 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2734 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2735 write_frame = ring_buffer_start; 2736 else 2737 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2738 /* Check invalid write_frame ptr address */ 2739 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2740 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2741 ring_buffer_start, ring_buffer_end, write_frame); 2742 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2743 return -EINVAL; 2744 } 2745 2746 /* Initialize KM RB frame */ 2747 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2748 2749 /* Update KM RB frame */ 2750 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2751 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2752 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2753 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2754 write_frame->fence_value = index; 2755 amdgpu_device_flush_hdp(adev, NULL); 2756 2757 /* Update the write Pointer in DWORDs */ 2758 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2759 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2760 return 0; 2761 } 2762 2763 int psp_init_asd_microcode(struct psp_context *psp, 2764 const char *chip_name) 2765 { 2766 struct amdgpu_device *adev = psp->adev; 2767 char fw_name[PSP_FW_NAME_LEN]; 2768 const struct psp_firmware_header_v1_0 *asd_hdr; 2769 int err = 0; 2770 2771 if (!chip_name) { 2772 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2773 return -EINVAL; 2774 } 2775 2776 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2777 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2778 if (err) 2779 goto out; 2780 2781 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2782 if (err) 2783 goto out; 2784 2785 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2786 adev->psp.asd.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2787 adev->psp.asd.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2788 adev->psp.asd.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2789 adev->psp.asd.start_addr = (uint8_t *)asd_hdr + 2790 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2791 return 0; 2792 out: 2793 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2794 release_firmware(adev->psp.asd_fw); 2795 adev->psp.asd_fw = NULL; 2796 return err; 2797 } 2798 2799 int psp_init_toc_microcode(struct psp_context *psp, 2800 const char *chip_name) 2801 { 2802 struct amdgpu_device *adev = psp->adev; 2803 char fw_name[PSP_FW_NAME_LEN]; 2804 const struct psp_firmware_header_v1_0 *toc_hdr; 2805 int err = 0; 2806 2807 if (!chip_name) { 2808 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2809 return -EINVAL; 2810 } 2811 2812 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2813 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2814 if (err) 2815 goto out; 2816 2817 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2818 if (err) 2819 goto out; 2820 2821 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2822 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2823 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2824 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2825 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2826 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2827 return 0; 2828 out: 2829 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2830 release_firmware(adev->psp.toc_fw); 2831 adev->psp.toc_fw = NULL; 2832 return err; 2833 } 2834 2835 static int parse_sos_bin_descriptor(struct psp_context *psp, 2836 const struct psp_fw_bin_desc *desc, 2837 const struct psp_firmware_header_v2_0 *sos_hdr) 2838 { 2839 uint8_t *ucode_start_addr = NULL; 2840 2841 if (!psp || !desc || !sos_hdr) 2842 return -EINVAL; 2843 2844 ucode_start_addr = (uint8_t *)sos_hdr + 2845 le32_to_cpu(desc->offset_bytes) + 2846 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2847 2848 switch (desc->fw_type) { 2849 case PSP_FW_TYPE_PSP_SOS: 2850 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2851 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2852 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2853 psp->sos.start_addr = ucode_start_addr; 2854 break; 2855 case PSP_FW_TYPE_PSP_SYS_DRV: 2856 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2857 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2858 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2859 psp->sys.start_addr = ucode_start_addr; 2860 break; 2861 case PSP_FW_TYPE_PSP_KDB: 2862 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2863 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2864 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2865 psp->kdb.start_addr = ucode_start_addr; 2866 break; 2867 case PSP_FW_TYPE_PSP_TOC: 2868 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2869 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2870 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 2871 psp->toc.start_addr = ucode_start_addr; 2872 break; 2873 case PSP_FW_TYPE_PSP_SPL: 2874 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 2875 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 2876 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 2877 psp->spl.start_addr = ucode_start_addr; 2878 break; 2879 case PSP_FW_TYPE_PSP_RL: 2880 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 2881 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 2882 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 2883 psp->rl.start_addr = ucode_start_addr; 2884 break; 2885 case PSP_FW_TYPE_PSP_SOC_DRV: 2886 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 2887 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 2888 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2889 psp->soc_drv.start_addr = ucode_start_addr; 2890 break; 2891 case PSP_FW_TYPE_PSP_INTF_DRV: 2892 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 2893 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 2894 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2895 psp->intf_drv.start_addr = ucode_start_addr; 2896 break; 2897 case PSP_FW_TYPE_PSP_DBG_DRV: 2898 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 2899 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 2900 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2901 psp->dbg_drv.start_addr = ucode_start_addr; 2902 break; 2903 default: 2904 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 2905 break; 2906 } 2907 2908 return 0; 2909 } 2910 2911 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 2912 { 2913 const struct psp_firmware_header_v1_0 *sos_hdr; 2914 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2915 uint8_t *ucode_array_start_addr; 2916 2917 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2918 ucode_array_start_addr = (uint8_t *)sos_hdr + 2919 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2920 2921 if (adev->gmc.xgmi.connected_to_cpu || (adev->asic_type != CHIP_ALDEBARAN)) { 2922 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 2923 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 2924 2925 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 2926 adev->psp.sys.start_addr = ucode_array_start_addr; 2927 2928 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 2929 adev->psp.sos.start_addr = ucode_array_start_addr + 2930 le32_to_cpu(sos_hdr->sos.offset_bytes); 2931 adev->psp.xgmi_context.supports_extended_data = false; 2932 } else { 2933 /* Load alternate PSP SOS FW */ 2934 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 2935 2936 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 2937 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 2938 2939 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 2940 adev->psp.sys.start_addr = ucode_array_start_addr + 2941 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 2942 2943 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 2944 adev->psp.sos.start_addr = ucode_array_start_addr + 2945 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 2946 adev->psp.xgmi_context.supports_extended_data = true; 2947 } 2948 2949 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 2950 dev_warn(adev->dev, "PSP SOS FW not available"); 2951 return -EINVAL; 2952 } 2953 2954 return 0; 2955 } 2956 2957 int psp_init_sos_microcode(struct psp_context *psp, 2958 const char *chip_name) 2959 { 2960 struct amdgpu_device *adev = psp->adev; 2961 char fw_name[PSP_FW_NAME_LEN]; 2962 const struct psp_firmware_header_v1_0 *sos_hdr; 2963 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 2964 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 2965 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2966 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 2967 int err = 0; 2968 uint8_t *ucode_array_start_addr; 2969 int fw_index = 0; 2970 2971 if (!chip_name) { 2972 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 2973 return -EINVAL; 2974 } 2975 2976 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 2977 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 2978 if (err) 2979 goto out; 2980 2981 err = amdgpu_ucode_validate(adev->psp.sos_fw); 2982 if (err) 2983 goto out; 2984 2985 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2986 ucode_array_start_addr = (uint8_t *)sos_hdr + 2987 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2988 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 2989 2990 switch (sos_hdr->header.header_version_major) { 2991 case 1: 2992 err = psp_init_sos_base_fw(adev); 2993 if (err) 2994 goto out; 2995 2996 if (sos_hdr->header.header_version_minor == 1) { 2997 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 2998 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 2999 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3000 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3001 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3002 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3003 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3004 } 3005 if (sos_hdr->header.header_version_minor == 2) { 3006 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3007 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3008 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3009 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3010 } 3011 if (sos_hdr->header.header_version_minor == 3) { 3012 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3013 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3014 adev->psp.toc.start_addr = ucode_array_start_addr + 3015 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3016 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3017 adev->psp.kdb.start_addr = ucode_array_start_addr + 3018 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3019 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3020 adev->psp.spl.start_addr = ucode_array_start_addr + 3021 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3022 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3023 adev->psp.rl.start_addr = ucode_array_start_addr + 3024 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3025 } 3026 break; 3027 case 2: 3028 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3029 3030 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3031 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3032 err = -EINVAL; 3033 goto out; 3034 } 3035 3036 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3037 err = parse_sos_bin_descriptor(psp, 3038 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3039 sos_hdr_v2_0); 3040 if (err) 3041 goto out; 3042 } 3043 break; 3044 default: 3045 dev_err(adev->dev, 3046 "unsupported psp sos firmware\n"); 3047 err = -EINVAL; 3048 goto out; 3049 } 3050 3051 return 0; 3052 out: 3053 dev_err(adev->dev, 3054 "failed to init sos firmware\n"); 3055 release_firmware(adev->psp.sos_fw); 3056 adev->psp.sos_fw = NULL; 3057 3058 return err; 3059 } 3060 3061 static int parse_ta_bin_descriptor(struct psp_context *psp, 3062 const struct psp_fw_bin_desc *desc, 3063 const struct ta_firmware_header_v2_0 *ta_hdr) 3064 { 3065 uint8_t *ucode_start_addr = NULL; 3066 3067 if (!psp || !desc || !ta_hdr) 3068 return -EINVAL; 3069 3070 ucode_start_addr = (uint8_t *)ta_hdr + 3071 le32_to_cpu(desc->offset_bytes) + 3072 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3073 3074 switch (desc->fw_type) { 3075 case TA_FW_TYPE_PSP_ASD: 3076 psp->asd.fw_version = le32_to_cpu(desc->fw_version); 3077 psp->asd.feature_version = le32_to_cpu(desc->fw_version); 3078 psp->asd.size_bytes = le32_to_cpu(desc->size_bytes); 3079 psp->asd.start_addr = ucode_start_addr; 3080 break; 3081 case TA_FW_TYPE_PSP_XGMI: 3082 psp->xgmi.feature_version = le32_to_cpu(desc->fw_version); 3083 psp->xgmi.size_bytes = le32_to_cpu(desc->size_bytes); 3084 psp->xgmi.start_addr = ucode_start_addr; 3085 break; 3086 case TA_FW_TYPE_PSP_RAS: 3087 psp->ras.feature_version = le32_to_cpu(desc->fw_version); 3088 psp->ras.size_bytes = le32_to_cpu(desc->size_bytes); 3089 psp->ras.start_addr = ucode_start_addr; 3090 break; 3091 case TA_FW_TYPE_PSP_HDCP: 3092 psp->hdcp.feature_version = le32_to_cpu(desc->fw_version); 3093 psp->hdcp.size_bytes = le32_to_cpu(desc->size_bytes); 3094 psp->hdcp.start_addr = ucode_start_addr; 3095 break; 3096 case TA_FW_TYPE_PSP_DTM: 3097 psp->dtm.feature_version = le32_to_cpu(desc->fw_version); 3098 psp->dtm.size_bytes = le32_to_cpu(desc->size_bytes); 3099 psp->dtm.start_addr = ucode_start_addr; 3100 break; 3101 case TA_FW_TYPE_PSP_RAP: 3102 psp->rap.feature_version = le32_to_cpu(desc->fw_version); 3103 psp->rap.size_bytes = le32_to_cpu(desc->size_bytes); 3104 psp->rap.start_addr = ucode_start_addr; 3105 break; 3106 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3107 psp->securedisplay.feature_version = le32_to_cpu(desc->fw_version); 3108 psp->securedisplay.size_bytes = le32_to_cpu(desc->size_bytes); 3109 psp->securedisplay.start_addr = ucode_start_addr; 3110 break; 3111 default: 3112 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3113 break; 3114 } 3115 3116 return 0; 3117 } 3118 3119 int psp_init_ta_microcode(struct psp_context *psp, 3120 const char *chip_name) 3121 { 3122 struct amdgpu_device *adev = psp->adev; 3123 char fw_name[PSP_FW_NAME_LEN]; 3124 const struct ta_firmware_header_v2_0 *ta_hdr; 3125 int err = 0; 3126 int ta_index = 0; 3127 3128 if (!chip_name) { 3129 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3130 return -EINVAL; 3131 } 3132 3133 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3134 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3135 if (err) 3136 goto out; 3137 3138 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3139 if (err) 3140 goto out; 3141 3142 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3143 3144 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3145 dev_err(adev->dev, "unsupported TA header version\n"); 3146 err = -EINVAL; 3147 goto out; 3148 } 3149 3150 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3151 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3152 err = -EINVAL; 3153 goto out; 3154 } 3155 3156 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3157 err = parse_ta_bin_descriptor(psp, 3158 &ta_hdr->ta_fw_bin[ta_index], 3159 ta_hdr); 3160 if (err) 3161 goto out; 3162 } 3163 3164 return 0; 3165 out: 3166 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3167 release_firmware(adev->psp.ta_fw); 3168 adev->psp.ta_fw = NULL; 3169 return err; 3170 } 3171 3172 static int psp_set_clockgating_state(void *handle, 3173 enum amd_clockgating_state state) 3174 { 3175 return 0; 3176 } 3177 3178 static int psp_set_powergating_state(void *handle, 3179 enum amd_powergating_state state) 3180 { 3181 return 0; 3182 } 3183 3184 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3185 struct device_attribute *attr, 3186 char *buf) 3187 { 3188 struct drm_device *ddev = dev_get_drvdata(dev); 3189 struct amdgpu_device *adev = drm_to_adev(ddev); 3190 uint32_t fw_ver; 3191 int ret; 3192 3193 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3194 DRM_INFO("PSP block is not ready yet."); 3195 return -EBUSY; 3196 } 3197 3198 mutex_lock(&adev->psp.mutex); 3199 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3200 mutex_unlock(&adev->psp.mutex); 3201 3202 if (ret) { 3203 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3204 return ret; 3205 } 3206 3207 return sysfs_emit(buf, "%x\n", fw_ver); 3208 } 3209 3210 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3211 struct device_attribute *attr, 3212 const char *buf, 3213 size_t count) 3214 { 3215 struct drm_device *ddev = dev_get_drvdata(dev); 3216 struct amdgpu_device *adev = drm_to_adev(ddev); 3217 int ret, idx; 3218 char fw_name[100]; 3219 const struct firmware *usbc_pd_fw; 3220 struct amdgpu_bo *fw_buf_bo = NULL; 3221 uint64_t fw_pri_mc_addr; 3222 void *fw_pri_cpu_addr; 3223 3224 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3225 DRM_INFO("PSP block is not ready yet."); 3226 return -EBUSY; 3227 } 3228 3229 if (!drm_dev_enter(ddev, &idx)) 3230 return -ENODEV; 3231 3232 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3233 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3234 if (ret) 3235 goto fail; 3236 3237 /* LFB address which is aligned to 1MB boundary per PSP request */ 3238 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3239 AMDGPU_GEM_DOMAIN_VRAM, 3240 &fw_buf_bo, 3241 &fw_pri_mc_addr, 3242 &fw_pri_cpu_addr); 3243 if (ret) 3244 goto rel_buf; 3245 3246 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3247 3248 mutex_lock(&adev->psp.mutex); 3249 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3250 mutex_unlock(&adev->psp.mutex); 3251 3252 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3253 3254 rel_buf: 3255 release_firmware(usbc_pd_fw); 3256 fail: 3257 if (ret) { 3258 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3259 count = ret; 3260 } 3261 3262 drm_dev_exit(idx); 3263 return count; 3264 } 3265 3266 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3267 { 3268 int idx; 3269 3270 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 3271 return; 3272 3273 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3274 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3275 3276 drm_dev_exit(idx); 3277 } 3278 3279 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3280 psp_usbc_pd_fw_sysfs_read, 3281 psp_usbc_pd_fw_sysfs_write); 3282 3283 int is_psp_fw_valid(struct psp_bin_desc bin) 3284 { 3285 return bin.size_bytes; 3286 } 3287 3288 const struct amd_ip_funcs psp_ip_funcs = { 3289 .name = "psp", 3290 .early_init = psp_early_init, 3291 .late_init = NULL, 3292 .sw_init = psp_sw_init, 3293 .sw_fini = psp_sw_fini, 3294 .hw_init = psp_hw_init, 3295 .hw_fini = psp_hw_fini, 3296 .suspend = psp_suspend, 3297 .resume = psp_resume, 3298 .is_idle = NULL, 3299 .check_soft_reset = NULL, 3300 .wait_for_idle = NULL, 3301 .soft_reset = NULL, 3302 .set_clockgating_state = psp_set_clockgating_state, 3303 .set_powergating_state = psp_set_powergating_state, 3304 }; 3305 3306 static int psp_sysfs_init(struct amdgpu_device *adev) 3307 { 3308 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3309 3310 if (ret) 3311 DRM_ERROR("Failed to create USBC PD FW control file!"); 3312 3313 return ret; 3314 } 3315 3316 static void psp_sysfs_fini(struct amdgpu_device *adev) 3317 { 3318 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3319 } 3320 3321 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3322 { 3323 .type = AMD_IP_BLOCK_TYPE_PSP, 3324 .major = 3, 3325 .minor = 1, 3326 .rev = 0, 3327 .funcs = &psp_ip_funcs, 3328 }; 3329 3330 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3331 { 3332 .type = AMD_IP_BLOCK_TYPE_PSP, 3333 .major = 10, 3334 .minor = 0, 3335 .rev = 0, 3336 .funcs = &psp_ip_funcs, 3337 }; 3338 3339 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3340 { 3341 .type = AMD_IP_BLOCK_TYPE_PSP, 3342 .major = 11, 3343 .minor = 0, 3344 .rev = 0, 3345 .funcs = &psp_ip_funcs, 3346 }; 3347 3348 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3349 .type = AMD_IP_BLOCK_TYPE_PSP, 3350 .major = 11, 3351 .minor = 0, 3352 .rev = 8, 3353 .funcs = &psp_ip_funcs, 3354 }; 3355 3356 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3357 { 3358 .type = AMD_IP_BLOCK_TYPE_PSP, 3359 .major = 12, 3360 .minor = 0, 3361 .rev = 0, 3362 .funcs = &psp_ip_funcs, 3363 }; 3364 3365 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3366 .type = AMD_IP_BLOCK_TYPE_PSP, 3367 .major = 13, 3368 .minor = 0, 3369 .rev = 0, 3370 .funcs = &psp_ip_funcs, 3371 }; 3372