1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/dma-mapping.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v3_1.h" 34 #include "psp_v10_0.h" 35 #include "psp_v11_0.h" 36 #include "psp_v12_0.h" 37 38 #include "amdgpu_ras.h" 39 #include "amdgpu_securedisplay.h" 40 41 static int psp_sysfs_init(struct amdgpu_device *adev); 42 static void psp_sysfs_fini(struct amdgpu_device *adev); 43 44 static int psp_load_smu_fw(struct psp_context *psp); 45 46 /* 47 * Due to DF Cstate management centralized to PMFW, the firmware 48 * loading sequence will be updated as below: 49 * - Load KDB 50 * - Load SYS_DRV 51 * - Load tOS 52 * - Load PMFW 53 * - Setup TMR 54 * - Load other non-psp fw 55 * - Load ASD 56 * - Load XGMI/RAS/HDCP/DTM TA if any 57 * 58 * This new sequence is required for 59 * - Arcturus 60 * - Navi12 and onwards 61 */ 62 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 63 { 64 struct amdgpu_device *adev = psp->adev; 65 66 psp->pmfw_centralized_cstate_management = false; 67 68 if (amdgpu_sriov_vf(adev)) 69 return; 70 71 if (adev->flags & AMD_IS_APU) 72 return; 73 74 if ((adev->asic_type == CHIP_ARCTURUS) || 75 (adev->asic_type >= CHIP_NAVI12)) 76 psp->pmfw_centralized_cstate_management = true; 77 } 78 79 static int psp_early_init(void *handle) 80 { 81 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 82 struct psp_context *psp = &adev->psp; 83 84 switch (adev->asic_type) { 85 case CHIP_VEGA10: 86 case CHIP_VEGA12: 87 psp_v3_1_set_psp_funcs(psp); 88 psp->autoload_supported = false; 89 break; 90 case CHIP_RAVEN: 91 psp_v10_0_set_psp_funcs(psp); 92 psp->autoload_supported = false; 93 break; 94 case CHIP_VEGA20: 95 case CHIP_ARCTURUS: 96 psp_v11_0_set_psp_funcs(psp); 97 psp->autoload_supported = false; 98 break; 99 case CHIP_NAVI10: 100 case CHIP_NAVI14: 101 case CHIP_NAVI12: 102 case CHIP_SIENNA_CICHLID: 103 case CHIP_NAVY_FLOUNDER: 104 case CHIP_VANGOGH: 105 case CHIP_DIMGREY_CAVEFISH: 106 psp_v11_0_set_psp_funcs(psp); 107 psp->autoload_supported = true; 108 break; 109 case CHIP_RENOIR: 110 psp_v12_0_set_psp_funcs(psp); 111 break; 112 default: 113 return -EINVAL; 114 } 115 116 psp->adev = adev; 117 118 psp_check_pmfw_centralized_cstate_management(psp); 119 120 return 0; 121 } 122 123 static void psp_memory_training_fini(struct psp_context *psp) 124 { 125 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 126 127 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 128 kfree(ctx->sys_cache); 129 ctx->sys_cache = NULL; 130 } 131 132 static int psp_memory_training_init(struct psp_context *psp) 133 { 134 int ret; 135 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 136 137 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 138 DRM_DEBUG("memory training is not supported!\n"); 139 return 0; 140 } 141 142 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 143 if (ctx->sys_cache == NULL) { 144 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 145 ret = -ENOMEM; 146 goto Err_out; 147 } 148 149 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 150 ctx->train_data_size, 151 ctx->p2c_train_data_offset, 152 ctx->c2p_train_data_offset); 153 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 154 return 0; 155 156 Err_out: 157 psp_memory_training_fini(psp); 158 return ret; 159 } 160 161 static int psp_sw_init(void *handle) 162 { 163 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 164 struct psp_context *psp = &adev->psp; 165 int ret; 166 167 if (!amdgpu_sriov_vf(adev)) { 168 ret = psp_init_microcode(psp); 169 if (ret) { 170 DRM_ERROR("Failed to load psp firmware!\n"); 171 return ret; 172 } 173 } 174 175 ret = psp_memory_training_init(psp); 176 if (ret) { 177 DRM_ERROR("Failed to initialize memory training!\n"); 178 return ret; 179 } 180 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 181 if (ret) { 182 DRM_ERROR("Failed to process memory training!\n"); 183 return ret; 184 } 185 186 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 187 ret= psp_sysfs_init(adev); 188 if (ret) { 189 return ret; 190 } 191 } 192 193 return 0; 194 } 195 196 static int psp_sw_fini(void *handle) 197 { 198 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 199 200 psp_memory_training_fini(&adev->psp); 201 if (adev->psp.sos_fw) { 202 release_firmware(adev->psp.sos_fw); 203 adev->psp.sos_fw = NULL; 204 } 205 if (adev->psp.asd_fw) { 206 release_firmware(adev->psp.asd_fw); 207 adev->psp.asd_fw = NULL; 208 } 209 if (adev->psp.ta_fw) { 210 release_firmware(adev->psp.ta_fw); 211 adev->psp.ta_fw = NULL; 212 } 213 214 if (adev->asic_type == CHIP_NAVI10 || 215 adev->asic_type == CHIP_SIENNA_CICHLID) 216 psp_sysfs_fini(adev); 217 218 return 0; 219 } 220 221 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 222 uint32_t reg_val, uint32_t mask, bool check_changed) 223 { 224 uint32_t val; 225 int i; 226 struct amdgpu_device *adev = psp->adev; 227 228 if (psp->adev->in_pci_err_recovery) 229 return 0; 230 231 for (i = 0; i < adev->usec_timeout; i++) { 232 val = RREG32(reg_index); 233 if (check_changed) { 234 if (val != reg_val) 235 return 0; 236 } else { 237 if ((val & mask) == reg_val) 238 return 0; 239 } 240 udelay(1); 241 } 242 243 return -ETIME; 244 } 245 246 static int 247 psp_cmd_submit_buf(struct psp_context *psp, 248 struct amdgpu_firmware_info *ucode, 249 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 250 { 251 int ret; 252 int index; 253 int timeout = 20000; 254 bool ras_intr = false; 255 bool skip_unsupport = false; 256 257 if (psp->adev->in_pci_err_recovery) 258 return 0; 259 260 mutex_lock(&psp->mutex); 261 262 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 263 264 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 265 266 index = atomic_inc_return(&psp->fence_value); 267 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 268 if (ret) { 269 atomic_dec(&psp->fence_value); 270 mutex_unlock(&psp->mutex); 271 return ret; 272 } 273 274 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 275 while (*((unsigned int *)psp->fence_buf) != index) { 276 if (--timeout == 0) 277 break; 278 /* 279 * Shouldn't wait for timeout when err_event_athub occurs, 280 * because gpu reset thread triggered and lock resource should 281 * be released for psp resume sequence. 282 */ 283 ras_intr = amdgpu_ras_intr_triggered(); 284 if (ras_intr) 285 break; 286 usleep_range(10, 100); 287 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 288 } 289 290 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 291 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 292 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 293 294 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 295 296 /* In some cases, psp response status is not 0 even there is no 297 * problem while the command is submitted. Some version of PSP FW 298 * doesn't write 0 to that field. 299 * So here we would like to only print a warning instead of an error 300 * during psp initialization to avoid breaking hw_init and it doesn't 301 * return -EINVAL. 302 */ 303 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 304 if (ucode) 305 DRM_WARN("failed to load ucode id (%d) ", 306 ucode->ucode_id); 307 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n", 308 psp->cmd_buf_mem->cmd_id, 309 psp->cmd_buf_mem->resp.status); 310 if (!timeout) { 311 mutex_unlock(&psp->mutex); 312 return -EINVAL; 313 } 314 } 315 316 if (ucode) { 317 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 318 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 319 } 320 mutex_unlock(&psp->mutex); 321 322 return ret; 323 } 324 325 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 326 struct psp_gfx_cmd_resp *cmd, 327 uint64_t tmr_mc, uint32_t size) 328 { 329 if (amdgpu_sriov_vf(psp->adev)) 330 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 331 else 332 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 333 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 334 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 335 cmd->cmd.cmd_setup_tmr.buf_size = size; 336 } 337 338 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 339 uint64_t pri_buf_mc, uint32_t size) 340 { 341 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 342 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 343 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 344 cmd->cmd.cmd_load_toc.toc_size = size; 345 } 346 347 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 348 static int psp_load_toc(struct psp_context *psp, 349 uint32_t *tmr_size) 350 { 351 int ret; 352 struct psp_gfx_cmd_resp *cmd; 353 354 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 355 if (!cmd) 356 return -ENOMEM; 357 /* Copy toc to psp firmware private buffer */ 358 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 359 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size); 360 361 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 362 363 ret = psp_cmd_submit_buf(psp, NULL, cmd, 364 psp->fence_buf_mc_addr); 365 if (!ret) 366 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 367 kfree(cmd); 368 return ret; 369 } 370 371 /* Set up Trusted Memory Region */ 372 static int psp_tmr_init(struct psp_context *psp) 373 { 374 int ret; 375 int tmr_size; 376 void *tmr_buf; 377 void **pptr; 378 379 /* 380 * According to HW engineer, they prefer the TMR address be "naturally 381 * aligned" , e.g. the start address be an integer divide of TMR size. 382 * 383 * Note: this memory need be reserved till the driver 384 * uninitializes. 385 */ 386 tmr_size = PSP_TMR_SIZE; 387 388 /* For ASICs support RLC autoload, psp will parse the toc 389 * and calculate the total size of TMR needed */ 390 if (!amdgpu_sriov_vf(psp->adev) && 391 psp->toc_start_addr && 392 psp->toc_bin_size && 393 psp->fw_pri_buf) { 394 ret = psp_load_toc(psp, &tmr_size); 395 if (ret) { 396 DRM_ERROR("Failed to load toc\n"); 397 return ret; 398 } 399 } 400 401 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 402 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE, 403 AMDGPU_GEM_DOMAIN_VRAM, 404 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 405 406 return ret; 407 } 408 409 static int psp_clear_vf_fw(struct psp_context *psp) 410 { 411 int ret; 412 struct psp_gfx_cmd_resp *cmd; 413 414 if (!amdgpu_sriov_vf(psp->adev) || psp->adev->asic_type != CHIP_NAVI12) 415 return 0; 416 417 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 418 if (!cmd) 419 return -ENOMEM; 420 421 cmd->cmd_id = GFX_CMD_ID_CLEAR_VF_FW; 422 423 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 424 kfree(cmd); 425 426 return ret; 427 } 428 429 static bool psp_skip_tmr(struct psp_context *psp) 430 { 431 switch (psp->adev->asic_type) { 432 case CHIP_NAVI12: 433 case CHIP_SIENNA_CICHLID: 434 return true; 435 default: 436 return false; 437 } 438 } 439 440 static int psp_tmr_load(struct psp_context *psp) 441 { 442 int ret; 443 struct psp_gfx_cmd_resp *cmd; 444 445 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 446 * Already set up by host driver. 447 */ 448 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 449 return 0; 450 451 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 452 if (!cmd) 453 return -ENOMEM; 454 455 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, 456 amdgpu_bo_size(psp->tmr_bo)); 457 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 458 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 459 460 ret = psp_cmd_submit_buf(psp, NULL, cmd, 461 psp->fence_buf_mc_addr); 462 463 kfree(cmd); 464 465 return ret; 466 } 467 468 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 469 struct psp_gfx_cmd_resp *cmd) 470 { 471 if (amdgpu_sriov_vf(psp->adev)) 472 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 473 else 474 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 475 } 476 477 static int psp_tmr_unload(struct psp_context *psp) 478 { 479 int ret; 480 struct psp_gfx_cmd_resp *cmd; 481 482 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 483 if (!cmd) 484 return -ENOMEM; 485 486 psp_prep_tmr_unload_cmd_buf(psp, cmd); 487 DRM_INFO("free PSP TMR buffer\n"); 488 489 ret = psp_cmd_submit_buf(psp, NULL, cmd, 490 psp->fence_buf_mc_addr); 491 492 kfree(cmd); 493 494 return ret; 495 } 496 497 static int psp_tmr_terminate(struct psp_context *psp) 498 { 499 int ret; 500 void *tmr_buf; 501 void **pptr; 502 503 ret = psp_tmr_unload(psp); 504 if (ret) 505 return ret; 506 507 /* free TMR memory buffer */ 508 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 509 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 510 511 return 0; 512 } 513 514 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 515 uint64_t *output_ptr) 516 { 517 int ret; 518 struct psp_gfx_cmd_resp *cmd; 519 520 if (!output_ptr) 521 return -EINVAL; 522 523 if (amdgpu_sriov_vf(psp->adev)) 524 return 0; 525 526 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 527 if (!cmd) 528 return -ENOMEM; 529 530 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 531 532 ret = psp_cmd_submit_buf(psp, NULL, cmd, 533 psp->fence_buf_mc_addr); 534 535 if (!ret) { 536 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 537 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 538 } 539 540 kfree(cmd); 541 542 return ret; 543 } 544 545 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 546 uint64_t asd_mc, uint32_t size) 547 { 548 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 549 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 550 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 551 cmd->cmd.cmd_load_ta.app_len = size; 552 553 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 554 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 555 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 556 } 557 558 static int psp_asd_load(struct psp_context *psp) 559 { 560 int ret; 561 struct psp_gfx_cmd_resp *cmd; 562 563 /* If PSP version doesn't match ASD version, asd loading will be failed. 564 * add workaround to bypass it for sriov now. 565 * TODO: add version check to make it common 566 */ 567 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size) 568 return 0; 569 570 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 571 if (!cmd) 572 return -ENOMEM; 573 574 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 575 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 576 577 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 578 psp->asd_ucode_size); 579 580 ret = psp_cmd_submit_buf(psp, NULL, cmd, 581 psp->fence_buf_mc_addr); 582 if (!ret) { 583 psp->asd_context.asd_initialized = true; 584 psp->asd_context.session_id = cmd->resp.session_id; 585 } 586 587 kfree(cmd); 588 589 return ret; 590 } 591 592 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 593 uint32_t session_id) 594 { 595 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 596 cmd->cmd.cmd_unload_ta.session_id = session_id; 597 } 598 599 static int psp_asd_unload(struct psp_context *psp) 600 { 601 int ret; 602 struct psp_gfx_cmd_resp *cmd; 603 604 if (amdgpu_sriov_vf(psp->adev)) 605 return 0; 606 607 if (!psp->asd_context.asd_initialized) 608 return 0; 609 610 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 611 if (!cmd) 612 return -ENOMEM; 613 614 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 615 616 ret = psp_cmd_submit_buf(psp, NULL, cmd, 617 psp->fence_buf_mc_addr); 618 if (!ret) 619 psp->asd_context.asd_initialized = false; 620 621 kfree(cmd); 622 623 return ret; 624 } 625 626 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 627 uint32_t id, uint32_t value) 628 { 629 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 630 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 631 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 632 } 633 634 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 635 uint32_t value) 636 { 637 struct psp_gfx_cmd_resp *cmd = NULL; 638 int ret = 0; 639 640 if (reg >= PSP_REG_LAST) 641 return -EINVAL; 642 643 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 644 if (!cmd) 645 return -ENOMEM; 646 647 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 648 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 649 650 kfree(cmd); 651 return ret; 652 } 653 654 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 655 uint64_t ta_bin_mc, 656 uint32_t ta_bin_size, 657 uint64_t ta_shared_mc, 658 uint32_t ta_shared_size) 659 { 660 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 661 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 662 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 663 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 664 665 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 666 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 667 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 668 } 669 670 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 671 { 672 int ret; 673 674 /* 675 * Allocate 16k memory aligned to 4k from Frame Buffer (local 676 * physical) for xgmi ta <-> Driver 677 */ 678 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 679 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 680 &psp->xgmi_context.xgmi_shared_bo, 681 &psp->xgmi_context.xgmi_shared_mc_addr, 682 &psp->xgmi_context.xgmi_shared_buf); 683 684 return ret; 685 } 686 687 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 688 uint32_t ta_cmd_id, 689 uint32_t session_id) 690 { 691 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 692 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 693 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 694 } 695 696 static int psp_ta_invoke(struct psp_context *psp, 697 uint32_t ta_cmd_id, 698 uint32_t session_id) 699 { 700 int ret; 701 struct psp_gfx_cmd_resp *cmd; 702 703 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 704 if (!cmd) 705 return -ENOMEM; 706 707 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 708 709 ret = psp_cmd_submit_buf(psp, NULL, cmd, 710 psp->fence_buf_mc_addr); 711 712 kfree(cmd); 713 714 return ret; 715 } 716 717 static int psp_xgmi_load(struct psp_context *psp) 718 { 719 int ret; 720 struct psp_gfx_cmd_resp *cmd; 721 722 /* 723 * TODO: bypass the loading in sriov for now 724 */ 725 726 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 727 if (!cmd) 728 return -ENOMEM; 729 730 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 731 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 732 733 psp_prep_ta_load_cmd_buf(cmd, 734 psp->fw_pri_mc_addr, 735 psp->ta_xgmi_ucode_size, 736 psp->xgmi_context.xgmi_shared_mc_addr, 737 PSP_XGMI_SHARED_MEM_SIZE); 738 739 ret = psp_cmd_submit_buf(psp, NULL, cmd, 740 psp->fence_buf_mc_addr); 741 742 if (!ret) { 743 psp->xgmi_context.initialized = 1; 744 psp->xgmi_context.session_id = cmd->resp.session_id; 745 } 746 747 kfree(cmd); 748 749 return ret; 750 } 751 752 static int psp_xgmi_unload(struct psp_context *psp) 753 { 754 int ret; 755 struct psp_gfx_cmd_resp *cmd; 756 struct amdgpu_device *adev = psp->adev; 757 758 /* XGMI TA unload currently is not supported on Arcturus */ 759 if (adev->asic_type == CHIP_ARCTURUS) 760 return 0; 761 762 /* 763 * TODO: bypass the unloading in sriov for now 764 */ 765 766 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 767 if (!cmd) 768 return -ENOMEM; 769 770 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 771 772 ret = psp_cmd_submit_buf(psp, NULL, cmd, 773 psp->fence_buf_mc_addr); 774 775 kfree(cmd); 776 777 return ret; 778 } 779 780 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 781 { 782 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 783 } 784 785 int psp_xgmi_terminate(struct psp_context *psp) 786 { 787 int ret; 788 789 if (!psp->xgmi_context.initialized) 790 return 0; 791 792 ret = psp_xgmi_unload(psp); 793 if (ret) 794 return ret; 795 796 psp->xgmi_context.initialized = 0; 797 798 /* free xgmi shared memory */ 799 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 800 &psp->xgmi_context.xgmi_shared_mc_addr, 801 &psp->xgmi_context.xgmi_shared_buf); 802 803 return 0; 804 } 805 806 int psp_xgmi_initialize(struct psp_context *psp) 807 { 808 struct ta_xgmi_shared_memory *xgmi_cmd; 809 int ret; 810 811 if (!psp->adev->psp.ta_fw || 812 !psp->adev->psp.ta_xgmi_ucode_size || 813 !psp->adev->psp.ta_xgmi_start_addr) 814 return -ENOENT; 815 816 if (!psp->xgmi_context.initialized) { 817 ret = psp_xgmi_init_shared_buf(psp); 818 if (ret) 819 return ret; 820 } 821 822 /* Load XGMI TA */ 823 ret = psp_xgmi_load(psp); 824 if (ret) 825 return ret; 826 827 /* Initialize XGMI session */ 828 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 829 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 830 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 831 832 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 833 834 return ret; 835 } 836 837 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 838 { 839 struct ta_xgmi_shared_memory *xgmi_cmd; 840 int ret; 841 842 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 843 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 844 845 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 846 847 /* Invoke xgmi ta to get hive id */ 848 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 849 if (ret) 850 return ret; 851 852 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 853 854 return 0; 855 } 856 857 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 858 { 859 struct ta_xgmi_shared_memory *xgmi_cmd; 860 int ret; 861 862 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 863 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 864 865 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 866 867 /* Invoke xgmi ta to get the node id */ 868 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 869 if (ret) 870 return ret; 871 872 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 873 874 return 0; 875 } 876 877 int psp_xgmi_get_topology_info(struct psp_context *psp, 878 int number_devices, 879 struct psp_xgmi_topology_info *topology) 880 { 881 struct ta_xgmi_shared_memory *xgmi_cmd; 882 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 883 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 884 int i; 885 int ret; 886 887 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 888 return -EINVAL; 889 890 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 891 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 892 893 /* Fill in the shared memory with topology information as input */ 894 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 895 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 896 topology_info_input->num_nodes = number_devices; 897 898 for (i = 0; i < topology_info_input->num_nodes; i++) { 899 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 900 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 901 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 902 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 903 } 904 905 /* Invoke xgmi ta to get the topology information */ 906 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 907 if (ret) 908 return ret; 909 910 /* Read the output topology information from the shared memory */ 911 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 912 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 913 for (i = 0; i < topology->num_nodes; i++) { 914 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 915 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 916 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 917 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 918 } 919 920 return 0; 921 } 922 923 int psp_xgmi_set_topology_info(struct psp_context *psp, 924 int number_devices, 925 struct psp_xgmi_topology_info *topology) 926 { 927 struct ta_xgmi_shared_memory *xgmi_cmd; 928 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 929 int i; 930 931 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 932 return -EINVAL; 933 934 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 935 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 936 937 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 938 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 939 topology_info_input->num_nodes = number_devices; 940 941 for (i = 0; i < topology_info_input->num_nodes; i++) { 942 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 943 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 944 topology_info_input->nodes[i].is_sharing_enabled = 1; 945 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 946 } 947 948 /* Invoke xgmi ta to set topology information */ 949 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 950 } 951 952 // ras begin 953 static int psp_ras_init_shared_buf(struct psp_context *psp) 954 { 955 int ret; 956 957 /* 958 * Allocate 16k memory aligned to 4k from Frame Buffer (local 959 * physical) for ras ta <-> Driver 960 */ 961 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 962 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 963 &psp->ras.ras_shared_bo, 964 &psp->ras.ras_shared_mc_addr, 965 &psp->ras.ras_shared_buf); 966 967 return ret; 968 } 969 970 static int psp_ras_load(struct psp_context *psp) 971 { 972 int ret; 973 struct psp_gfx_cmd_resp *cmd; 974 struct ta_ras_shared_memory *ras_cmd; 975 976 /* 977 * TODO: bypass the loading in sriov for now 978 */ 979 if (amdgpu_sriov_vf(psp->adev)) 980 return 0; 981 982 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 983 if (!cmd) 984 return -ENOMEM; 985 986 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 987 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 988 989 psp_prep_ta_load_cmd_buf(cmd, 990 psp->fw_pri_mc_addr, 991 psp->ta_ras_ucode_size, 992 psp->ras.ras_shared_mc_addr, 993 PSP_RAS_SHARED_MEM_SIZE); 994 995 ret = psp_cmd_submit_buf(psp, NULL, cmd, 996 psp->fence_buf_mc_addr); 997 998 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 999 1000 if (!ret) { 1001 psp->ras.session_id = cmd->resp.session_id; 1002 1003 if (!ras_cmd->ras_status) 1004 psp->ras.ras_initialized = true; 1005 else 1006 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1007 } 1008 1009 if (ret || ras_cmd->ras_status) 1010 amdgpu_ras_fini(psp->adev); 1011 1012 kfree(cmd); 1013 1014 return ret; 1015 } 1016 1017 static int psp_ras_unload(struct psp_context *psp) 1018 { 1019 int ret; 1020 struct psp_gfx_cmd_resp *cmd; 1021 1022 /* 1023 * TODO: bypass the unloading in sriov for now 1024 */ 1025 if (amdgpu_sriov_vf(psp->adev)) 1026 return 0; 1027 1028 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1029 if (!cmd) 1030 return -ENOMEM; 1031 1032 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 1033 1034 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1035 psp->fence_buf_mc_addr); 1036 1037 kfree(cmd); 1038 1039 return ret; 1040 } 1041 1042 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1043 { 1044 struct ta_ras_shared_memory *ras_cmd; 1045 int ret; 1046 1047 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1048 1049 /* 1050 * TODO: bypass the loading in sriov for now 1051 */ 1052 if (amdgpu_sriov_vf(psp->adev)) 1053 return 0; 1054 1055 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 1056 1057 if (amdgpu_ras_intr_triggered()) 1058 return ret; 1059 1060 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1061 { 1062 DRM_WARN("RAS: Unsupported Interface"); 1063 return -EINVAL; 1064 } 1065 1066 if (!ret) { 1067 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1068 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1069 1070 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1071 } 1072 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1073 dev_warn(psp->adev->dev, 1074 "RAS internal register access blocked\n"); 1075 } 1076 1077 return ret; 1078 } 1079 1080 int psp_ras_enable_features(struct psp_context *psp, 1081 union ta_ras_cmd_input *info, bool enable) 1082 { 1083 struct ta_ras_shared_memory *ras_cmd; 1084 int ret; 1085 1086 if (!psp->ras.ras_initialized) 1087 return -EINVAL; 1088 1089 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1090 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1091 1092 if (enable) 1093 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1094 else 1095 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1096 1097 ras_cmd->ras_in_message = *info; 1098 1099 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1100 if (ret) 1101 return -EINVAL; 1102 1103 return ras_cmd->ras_status; 1104 } 1105 1106 static int psp_ras_terminate(struct psp_context *psp) 1107 { 1108 int ret; 1109 1110 /* 1111 * TODO: bypass the terminate in sriov for now 1112 */ 1113 if (amdgpu_sriov_vf(psp->adev)) 1114 return 0; 1115 1116 if (!psp->ras.ras_initialized) 1117 return 0; 1118 1119 ret = psp_ras_unload(psp); 1120 if (ret) 1121 return ret; 1122 1123 psp->ras.ras_initialized = false; 1124 1125 /* free ras shared memory */ 1126 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1127 &psp->ras.ras_shared_mc_addr, 1128 &psp->ras.ras_shared_buf); 1129 1130 return 0; 1131 } 1132 1133 static int psp_ras_initialize(struct psp_context *psp) 1134 { 1135 int ret; 1136 1137 /* 1138 * TODO: bypass the initialize in sriov for now 1139 */ 1140 if (amdgpu_sriov_vf(psp->adev)) 1141 return 0; 1142 1143 if (!psp->adev->psp.ta_ras_ucode_size || 1144 !psp->adev->psp.ta_ras_start_addr) { 1145 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n"); 1146 return 0; 1147 } 1148 1149 if (!psp->ras.ras_initialized) { 1150 ret = psp_ras_init_shared_buf(psp); 1151 if (ret) 1152 return ret; 1153 } 1154 1155 ret = psp_ras_load(psp); 1156 if (ret) 1157 return ret; 1158 1159 return 0; 1160 } 1161 1162 int psp_ras_trigger_error(struct psp_context *psp, 1163 struct ta_ras_trigger_error_input *info) 1164 { 1165 struct ta_ras_shared_memory *ras_cmd; 1166 int ret; 1167 1168 if (!psp->ras.ras_initialized) 1169 return -EINVAL; 1170 1171 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1172 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1173 1174 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1175 ras_cmd->ras_in_message.trigger_error = *info; 1176 1177 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1178 if (ret) 1179 return -EINVAL; 1180 1181 /* If err_event_athub occurs error inject was successful, however 1182 return status from TA is no long reliable */ 1183 if (amdgpu_ras_intr_triggered()) 1184 return 0; 1185 1186 return ras_cmd->ras_status; 1187 } 1188 // ras end 1189 1190 // HDCP start 1191 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1192 { 1193 int ret; 1194 1195 /* 1196 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1197 * physical) for hdcp ta <-> Driver 1198 */ 1199 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1200 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1201 &psp->hdcp_context.hdcp_shared_bo, 1202 &psp->hdcp_context.hdcp_shared_mc_addr, 1203 &psp->hdcp_context.hdcp_shared_buf); 1204 1205 return ret; 1206 } 1207 1208 static int psp_hdcp_load(struct psp_context *psp) 1209 { 1210 int ret; 1211 struct psp_gfx_cmd_resp *cmd; 1212 1213 /* 1214 * TODO: bypass the loading in sriov for now 1215 */ 1216 if (amdgpu_sriov_vf(psp->adev)) 1217 return 0; 1218 1219 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1220 if (!cmd) 1221 return -ENOMEM; 1222 1223 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1224 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr, 1225 psp->ta_hdcp_ucode_size); 1226 1227 psp_prep_ta_load_cmd_buf(cmd, 1228 psp->fw_pri_mc_addr, 1229 psp->ta_hdcp_ucode_size, 1230 psp->hdcp_context.hdcp_shared_mc_addr, 1231 PSP_HDCP_SHARED_MEM_SIZE); 1232 1233 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1234 1235 if (!ret) { 1236 psp->hdcp_context.hdcp_initialized = true; 1237 psp->hdcp_context.session_id = cmd->resp.session_id; 1238 mutex_init(&psp->hdcp_context.mutex); 1239 } 1240 1241 kfree(cmd); 1242 1243 return ret; 1244 } 1245 static int psp_hdcp_initialize(struct psp_context *psp) 1246 { 1247 int ret; 1248 1249 /* 1250 * TODO: bypass the initialize in sriov for now 1251 */ 1252 if (amdgpu_sriov_vf(psp->adev)) 1253 return 0; 1254 1255 if (!psp->adev->psp.ta_hdcp_ucode_size || 1256 !psp->adev->psp.ta_hdcp_start_addr) { 1257 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1258 return 0; 1259 } 1260 1261 if (!psp->hdcp_context.hdcp_initialized) { 1262 ret = psp_hdcp_init_shared_buf(psp); 1263 if (ret) 1264 return ret; 1265 } 1266 1267 ret = psp_hdcp_load(psp); 1268 if (ret) 1269 return ret; 1270 1271 return 0; 1272 } 1273 1274 static int psp_hdcp_unload(struct psp_context *psp) 1275 { 1276 int ret; 1277 struct psp_gfx_cmd_resp *cmd; 1278 1279 /* 1280 * TODO: bypass the unloading in sriov for now 1281 */ 1282 if (amdgpu_sriov_vf(psp->adev)) 1283 return 0; 1284 1285 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1286 if (!cmd) 1287 return -ENOMEM; 1288 1289 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1290 1291 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1292 1293 kfree(cmd); 1294 1295 return ret; 1296 } 1297 1298 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1299 { 1300 /* 1301 * TODO: bypass the loading in sriov for now 1302 */ 1303 if (amdgpu_sriov_vf(psp->adev)) 1304 return 0; 1305 1306 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1307 } 1308 1309 static int psp_hdcp_terminate(struct psp_context *psp) 1310 { 1311 int ret; 1312 1313 /* 1314 * TODO: bypass the terminate in sriov for now 1315 */ 1316 if (amdgpu_sriov_vf(psp->adev)) 1317 return 0; 1318 1319 if (!psp->hdcp_context.hdcp_initialized) { 1320 if (psp->hdcp_context.hdcp_shared_buf) 1321 goto out; 1322 else 1323 return 0; 1324 } 1325 1326 ret = psp_hdcp_unload(psp); 1327 if (ret) 1328 return ret; 1329 1330 psp->hdcp_context.hdcp_initialized = false; 1331 1332 out: 1333 /* free hdcp shared memory */ 1334 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1335 &psp->hdcp_context.hdcp_shared_mc_addr, 1336 &psp->hdcp_context.hdcp_shared_buf); 1337 1338 return 0; 1339 } 1340 // HDCP end 1341 1342 // DTM start 1343 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1344 { 1345 int ret; 1346 1347 /* 1348 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1349 * physical) for dtm ta <-> Driver 1350 */ 1351 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1352 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1353 &psp->dtm_context.dtm_shared_bo, 1354 &psp->dtm_context.dtm_shared_mc_addr, 1355 &psp->dtm_context.dtm_shared_buf); 1356 1357 return ret; 1358 } 1359 1360 static int psp_dtm_load(struct psp_context *psp) 1361 { 1362 int ret; 1363 struct psp_gfx_cmd_resp *cmd; 1364 1365 /* 1366 * TODO: bypass the loading in sriov for now 1367 */ 1368 if (amdgpu_sriov_vf(psp->adev)) 1369 return 0; 1370 1371 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1372 if (!cmd) 1373 return -ENOMEM; 1374 1375 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1376 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1377 1378 psp_prep_ta_load_cmd_buf(cmd, 1379 psp->fw_pri_mc_addr, 1380 psp->ta_dtm_ucode_size, 1381 psp->dtm_context.dtm_shared_mc_addr, 1382 PSP_DTM_SHARED_MEM_SIZE); 1383 1384 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1385 1386 if (!ret) { 1387 psp->dtm_context.dtm_initialized = true; 1388 psp->dtm_context.session_id = cmd->resp.session_id; 1389 mutex_init(&psp->dtm_context.mutex); 1390 } 1391 1392 kfree(cmd); 1393 1394 return ret; 1395 } 1396 1397 static int psp_dtm_initialize(struct psp_context *psp) 1398 { 1399 int ret; 1400 1401 /* 1402 * TODO: bypass the initialize in sriov for now 1403 */ 1404 if (amdgpu_sriov_vf(psp->adev)) 1405 return 0; 1406 1407 if (!psp->adev->psp.ta_dtm_ucode_size || 1408 !psp->adev->psp.ta_dtm_start_addr) { 1409 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1410 return 0; 1411 } 1412 1413 if (!psp->dtm_context.dtm_initialized) { 1414 ret = psp_dtm_init_shared_buf(psp); 1415 if (ret) 1416 return ret; 1417 } 1418 1419 ret = psp_dtm_load(psp); 1420 if (ret) 1421 return ret; 1422 1423 return 0; 1424 } 1425 1426 static int psp_dtm_unload(struct psp_context *psp) 1427 { 1428 int ret; 1429 struct psp_gfx_cmd_resp *cmd; 1430 1431 /* 1432 * TODO: bypass the unloading in sriov for now 1433 */ 1434 if (amdgpu_sriov_vf(psp->adev)) 1435 return 0; 1436 1437 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1438 if (!cmd) 1439 return -ENOMEM; 1440 1441 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1442 1443 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1444 1445 kfree(cmd); 1446 1447 return ret; 1448 } 1449 1450 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1451 { 1452 /* 1453 * TODO: bypass the loading in sriov for now 1454 */ 1455 if (amdgpu_sriov_vf(psp->adev)) 1456 return 0; 1457 1458 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1459 } 1460 1461 static int psp_dtm_terminate(struct psp_context *psp) 1462 { 1463 int ret; 1464 1465 /* 1466 * TODO: bypass the terminate in sriov for now 1467 */ 1468 if (amdgpu_sriov_vf(psp->adev)) 1469 return 0; 1470 1471 if (!psp->dtm_context.dtm_initialized) { 1472 if (psp->dtm_context.dtm_shared_buf) 1473 goto out; 1474 else 1475 return 0; 1476 } 1477 1478 ret = psp_dtm_unload(psp); 1479 if (ret) 1480 return ret; 1481 1482 psp->dtm_context.dtm_initialized = false; 1483 1484 out: 1485 /* free hdcp shared memory */ 1486 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1487 &psp->dtm_context.dtm_shared_mc_addr, 1488 &psp->dtm_context.dtm_shared_buf); 1489 1490 return 0; 1491 } 1492 // DTM end 1493 1494 // RAP start 1495 static int psp_rap_init_shared_buf(struct psp_context *psp) 1496 { 1497 int ret; 1498 1499 /* 1500 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1501 * physical) for rap ta <-> Driver 1502 */ 1503 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE, 1504 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1505 &psp->rap_context.rap_shared_bo, 1506 &psp->rap_context.rap_shared_mc_addr, 1507 &psp->rap_context.rap_shared_buf); 1508 1509 return ret; 1510 } 1511 1512 static int psp_rap_load(struct psp_context *psp) 1513 { 1514 int ret; 1515 struct psp_gfx_cmd_resp *cmd; 1516 1517 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1518 if (!cmd) 1519 return -ENOMEM; 1520 1521 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1522 memcpy(psp->fw_pri_buf, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); 1523 1524 psp_prep_ta_load_cmd_buf(cmd, 1525 psp->fw_pri_mc_addr, 1526 psp->ta_rap_ucode_size, 1527 psp->rap_context.rap_shared_mc_addr, 1528 PSP_RAP_SHARED_MEM_SIZE); 1529 1530 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1531 1532 if (!ret) { 1533 psp->rap_context.rap_initialized = true; 1534 psp->rap_context.session_id = cmd->resp.session_id; 1535 mutex_init(&psp->rap_context.mutex); 1536 } 1537 1538 kfree(cmd); 1539 1540 return ret; 1541 } 1542 1543 static int psp_rap_unload(struct psp_context *psp) 1544 { 1545 int ret; 1546 struct psp_gfx_cmd_resp *cmd; 1547 1548 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1549 if (!cmd) 1550 return -ENOMEM; 1551 1552 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id); 1553 1554 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1555 1556 kfree(cmd); 1557 1558 return ret; 1559 } 1560 1561 static int psp_rap_initialize(struct psp_context *psp) 1562 { 1563 int ret; 1564 1565 /* 1566 * TODO: bypass the initialize in sriov for now 1567 */ 1568 if (amdgpu_sriov_vf(psp->adev)) 1569 return 0; 1570 1571 if (!psp->adev->psp.ta_rap_ucode_size || 1572 !psp->adev->psp.ta_rap_start_addr) { 1573 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1574 return 0; 1575 } 1576 1577 if (!psp->rap_context.rap_initialized) { 1578 ret = psp_rap_init_shared_buf(psp); 1579 if (ret) 1580 return ret; 1581 } 1582 1583 ret = psp_rap_load(psp); 1584 if (ret) 1585 return ret; 1586 1587 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE); 1588 if (ret != TA_RAP_STATUS__SUCCESS) { 1589 psp_rap_unload(psp); 1590 1591 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1592 &psp->rap_context.rap_shared_mc_addr, 1593 &psp->rap_context.rap_shared_buf); 1594 1595 psp->rap_context.rap_initialized = false; 1596 1597 dev_warn(psp->adev->dev, "RAP TA initialize fail.\n"); 1598 return -EINVAL; 1599 } 1600 1601 return 0; 1602 } 1603 1604 static int psp_rap_terminate(struct psp_context *psp) 1605 { 1606 int ret; 1607 1608 if (!psp->rap_context.rap_initialized) 1609 return 0; 1610 1611 ret = psp_rap_unload(psp); 1612 1613 psp->rap_context.rap_initialized = false; 1614 1615 /* free rap shared memory */ 1616 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1617 &psp->rap_context.rap_shared_mc_addr, 1618 &psp->rap_context.rap_shared_buf); 1619 1620 return ret; 1621 } 1622 1623 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1624 { 1625 struct ta_rap_shared_memory *rap_cmd; 1626 int ret; 1627 1628 if (!psp->rap_context.rap_initialized) 1629 return -EINVAL; 1630 1631 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1632 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1633 return -EINVAL; 1634 1635 mutex_lock(&psp->rap_context.mutex); 1636 1637 rap_cmd = (struct ta_rap_shared_memory *) 1638 psp->rap_context.rap_shared_buf; 1639 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1640 1641 rap_cmd->cmd_id = ta_cmd_id; 1642 rap_cmd->validation_method_id = METHOD_A; 1643 1644 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id); 1645 if (ret) { 1646 mutex_unlock(&psp->rap_context.mutex); 1647 return ret; 1648 } 1649 1650 mutex_unlock(&psp->rap_context.mutex); 1651 1652 return rap_cmd->rap_status; 1653 } 1654 // RAP end 1655 1656 /* securedisplay start */ 1657 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1658 { 1659 int ret; 1660 1661 /* 1662 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1663 * physical) for sa ta <-> Driver 1664 */ 1665 ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE, 1666 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1667 &psp->securedisplay_context.securedisplay_shared_bo, 1668 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1669 &psp->securedisplay_context.securedisplay_shared_buf); 1670 1671 return ret; 1672 } 1673 1674 static int psp_securedisplay_load(struct psp_context *psp) 1675 { 1676 int ret; 1677 struct psp_gfx_cmd_resp *cmd; 1678 1679 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1680 if (!cmd) 1681 return -ENOMEM; 1682 1683 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1684 memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size); 1685 1686 psp_prep_ta_load_cmd_buf(cmd, 1687 psp->fw_pri_mc_addr, 1688 psp->ta_securedisplay_ucode_size, 1689 psp->securedisplay_context.securedisplay_shared_mc_addr, 1690 PSP_SECUREDISPLAY_SHARED_MEM_SIZE); 1691 1692 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1693 1694 if (ret) 1695 goto failed; 1696 1697 psp->securedisplay_context.securedisplay_initialized = true; 1698 psp->securedisplay_context.session_id = cmd->resp.session_id; 1699 mutex_init(&psp->securedisplay_context.mutex); 1700 1701 failed: 1702 kfree(cmd); 1703 return ret; 1704 } 1705 1706 static int psp_securedisplay_unload(struct psp_context *psp) 1707 { 1708 int ret; 1709 struct psp_gfx_cmd_resp *cmd; 1710 1711 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1712 if (!cmd) 1713 return -ENOMEM; 1714 1715 psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id); 1716 1717 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1718 1719 kfree(cmd); 1720 1721 return ret; 1722 } 1723 1724 static int psp_securedisplay_initialize(struct psp_context *psp) 1725 { 1726 int ret; 1727 struct securedisplay_cmd *securedisplay_cmd; 1728 1729 /* 1730 * TODO: bypass the initialize in sriov for now 1731 */ 1732 if (amdgpu_sriov_vf(psp->adev)) 1733 return 0; 1734 1735 if (!psp->adev->psp.ta_securedisplay_ucode_size || 1736 !psp->adev->psp.ta_securedisplay_start_addr) { 1737 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1738 return 0; 1739 } 1740 1741 if (!psp->securedisplay_context.securedisplay_initialized) { 1742 ret = psp_securedisplay_init_shared_buf(psp); 1743 if (ret) 1744 return ret; 1745 } 1746 1747 ret = psp_securedisplay_load(psp); 1748 if (ret) 1749 return ret; 1750 1751 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1752 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1753 1754 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1755 if (ret) { 1756 psp_securedisplay_unload(psp); 1757 1758 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 1759 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1760 &psp->securedisplay_context.securedisplay_shared_buf); 1761 1762 psp->securedisplay_context.securedisplay_initialized = false; 1763 1764 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1765 return -EINVAL; 1766 } 1767 1768 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1769 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1770 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1771 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1772 } 1773 1774 return 0; 1775 } 1776 1777 static int psp_securedisplay_terminate(struct psp_context *psp) 1778 { 1779 int ret; 1780 1781 /* 1782 * TODO:bypass the terminate in sriov for now 1783 */ 1784 if (amdgpu_sriov_vf(psp->adev)) 1785 return 0; 1786 1787 if (!psp->securedisplay_context.securedisplay_initialized) 1788 return 0; 1789 1790 ret = psp_securedisplay_unload(psp); 1791 if (ret) 1792 return ret; 1793 1794 psp->securedisplay_context.securedisplay_initialized = false; 1795 1796 /* free securedisplay shared memory */ 1797 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 1798 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1799 &psp->securedisplay_context.securedisplay_shared_buf); 1800 1801 return ret; 1802 } 1803 1804 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1805 { 1806 int ret; 1807 1808 if (!psp->securedisplay_context.securedisplay_initialized) 1809 return -EINVAL; 1810 1811 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1812 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1813 return -EINVAL; 1814 1815 mutex_lock(&psp->securedisplay_context.mutex); 1816 1817 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id); 1818 1819 mutex_unlock(&psp->securedisplay_context.mutex); 1820 1821 return ret; 1822 } 1823 /* SECUREDISPLAY end */ 1824 1825 static int psp_hw_start(struct psp_context *psp) 1826 { 1827 struct amdgpu_device *adev = psp->adev; 1828 int ret; 1829 1830 if (!amdgpu_sriov_vf(adev)) { 1831 if (psp->kdb_bin_size && 1832 (psp->funcs->bootloader_load_kdb != NULL)) { 1833 ret = psp_bootloader_load_kdb(psp); 1834 if (ret) { 1835 DRM_ERROR("PSP load kdb failed!\n"); 1836 return ret; 1837 } 1838 } 1839 1840 if (psp->spl_bin_size) { 1841 ret = psp_bootloader_load_spl(psp); 1842 if (ret) { 1843 DRM_ERROR("PSP load spl failed!\n"); 1844 return ret; 1845 } 1846 } 1847 1848 ret = psp_bootloader_load_sysdrv(psp); 1849 if (ret) { 1850 DRM_ERROR("PSP load sysdrv failed!\n"); 1851 return ret; 1852 } 1853 1854 ret = psp_bootloader_load_sos(psp); 1855 if (ret) { 1856 DRM_ERROR("PSP load sos failed!\n"); 1857 return ret; 1858 } 1859 } 1860 1861 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1862 if (ret) { 1863 DRM_ERROR("PSP create ring failed!\n"); 1864 return ret; 1865 } 1866 1867 ret = psp_clear_vf_fw(psp); 1868 if (ret) { 1869 DRM_ERROR("PSP clear vf fw!\n"); 1870 return ret; 1871 } 1872 1873 ret = psp_tmr_init(psp); 1874 if (ret) { 1875 DRM_ERROR("PSP tmr init failed!\n"); 1876 return ret; 1877 } 1878 1879 /* 1880 * For ASICs with DF Cstate management centralized 1881 * to PMFW, TMR setup should be performed after PMFW 1882 * loaded and before other non-psp firmware loaded. 1883 */ 1884 if (psp->pmfw_centralized_cstate_management) { 1885 ret = psp_load_smu_fw(psp); 1886 if (ret) 1887 return ret; 1888 } 1889 1890 ret = psp_tmr_load(psp); 1891 if (ret) { 1892 DRM_ERROR("PSP load tmr failed!\n"); 1893 return ret; 1894 } 1895 1896 return 0; 1897 } 1898 1899 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 1900 enum psp_gfx_fw_type *type) 1901 { 1902 switch (ucode->ucode_id) { 1903 case AMDGPU_UCODE_ID_SDMA0: 1904 *type = GFX_FW_TYPE_SDMA0; 1905 break; 1906 case AMDGPU_UCODE_ID_SDMA1: 1907 *type = GFX_FW_TYPE_SDMA1; 1908 break; 1909 case AMDGPU_UCODE_ID_SDMA2: 1910 *type = GFX_FW_TYPE_SDMA2; 1911 break; 1912 case AMDGPU_UCODE_ID_SDMA3: 1913 *type = GFX_FW_TYPE_SDMA3; 1914 break; 1915 case AMDGPU_UCODE_ID_SDMA4: 1916 *type = GFX_FW_TYPE_SDMA4; 1917 break; 1918 case AMDGPU_UCODE_ID_SDMA5: 1919 *type = GFX_FW_TYPE_SDMA5; 1920 break; 1921 case AMDGPU_UCODE_ID_SDMA6: 1922 *type = GFX_FW_TYPE_SDMA6; 1923 break; 1924 case AMDGPU_UCODE_ID_SDMA7: 1925 *type = GFX_FW_TYPE_SDMA7; 1926 break; 1927 case AMDGPU_UCODE_ID_CP_MES: 1928 *type = GFX_FW_TYPE_CP_MES; 1929 break; 1930 case AMDGPU_UCODE_ID_CP_MES_DATA: 1931 *type = GFX_FW_TYPE_MES_STACK; 1932 break; 1933 case AMDGPU_UCODE_ID_CP_CE: 1934 *type = GFX_FW_TYPE_CP_CE; 1935 break; 1936 case AMDGPU_UCODE_ID_CP_PFP: 1937 *type = GFX_FW_TYPE_CP_PFP; 1938 break; 1939 case AMDGPU_UCODE_ID_CP_ME: 1940 *type = GFX_FW_TYPE_CP_ME; 1941 break; 1942 case AMDGPU_UCODE_ID_CP_MEC1: 1943 *type = GFX_FW_TYPE_CP_MEC; 1944 break; 1945 case AMDGPU_UCODE_ID_CP_MEC1_JT: 1946 *type = GFX_FW_TYPE_CP_MEC_ME1; 1947 break; 1948 case AMDGPU_UCODE_ID_CP_MEC2: 1949 *type = GFX_FW_TYPE_CP_MEC; 1950 break; 1951 case AMDGPU_UCODE_ID_CP_MEC2_JT: 1952 *type = GFX_FW_TYPE_CP_MEC_ME2; 1953 break; 1954 case AMDGPU_UCODE_ID_RLC_G: 1955 *type = GFX_FW_TYPE_RLC_G; 1956 break; 1957 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 1958 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 1959 break; 1960 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 1961 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 1962 break; 1963 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 1964 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 1965 break; 1966 case AMDGPU_UCODE_ID_RLC_IRAM: 1967 *type = GFX_FW_TYPE_RLC_IRAM; 1968 break; 1969 case AMDGPU_UCODE_ID_RLC_DRAM: 1970 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 1971 break; 1972 case AMDGPU_UCODE_ID_SMC: 1973 *type = GFX_FW_TYPE_SMU; 1974 break; 1975 case AMDGPU_UCODE_ID_UVD: 1976 *type = GFX_FW_TYPE_UVD; 1977 break; 1978 case AMDGPU_UCODE_ID_UVD1: 1979 *type = GFX_FW_TYPE_UVD1; 1980 break; 1981 case AMDGPU_UCODE_ID_VCE: 1982 *type = GFX_FW_TYPE_VCE; 1983 break; 1984 case AMDGPU_UCODE_ID_VCN: 1985 *type = GFX_FW_TYPE_VCN; 1986 break; 1987 case AMDGPU_UCODE_ID_VCN1: 1988 *type = GFX_FW_TYPE_VCN1; 1989 break; 1990 case AMDGPU_UCODE_ID_DMCU_ERAM: 1991 *type = GFX_FW_TYPE_DMCU_ERAM; 1992 break; 1993 case AMDGPU_UCODE_ID_DMCU_INTV: 1994 *type = GFX_FW_TYPE_DMCU_ISR; 1995 break; 1996 case AMDGPU_UCODE_ID_VCN0_RAM: 1997 *type = GFX_FW_TYPE_VCN0_RAM; 1998 break; 1999 case AMDGPU_UCODE_ID_VCN1_RAM: 2000 *type = GFX_FW_TYPE_VCN1_RAM; 2001 break; 2002 case AMDGPU_UCODE_ID_DMCUB: 2003 *type = GFX_FW_TYPE_DMUB; 2004 break; 2005 case AMDGPU_UCODE_ID_MAXIMUM: 2006 default: 2007 return -EINVAL; 2008 } 2009 2010 return 0; 2011 } 2012 2013 static void psp_print_fw_hdr(struct psp_context *psp, 2014 struct amdgpu_firmware_info *ucode) 2015 { 2016 struct amdgpu_device *adev = psp->adev; 2017 struct common_firmware_header *hdr; 2018 2019 switch (ucode->ucode_id) { 2020 case AMDGPU_UCODE_ID_SDMA0: 2021 case AMDGPU_UCODE_ID_SDMA1: 2022 case AMDGPU_UCODE_ID_SDMA2: 2023 case AMDGPU_UCODE_ID_SDMA3: 2024 case AMDGPU_UCODE_ID_SDMA4: 2025 case AMDGPU_UCODE_ID_SDMA5: 2026 case AMDGPU_UCODE_ID_SDMA6: 2027 case AMDGPU_UCODE_ID_SDMA7: 2028 hdr = (struct common_firmware_header *) 2029 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2030 amdgpu_ucode_print_sdma_hdr(hdr); 2031 break; 2032 case AMDGPU_UCODE_ID_CP_CE: 2033 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2034 amdgpu_ucode_print_gfx_hdr(hdr); 2035 break; 2036 case AMDGPU_UCODE_ID_CP_PFP: 2037 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2038 amdgpu_ucode_print_gfx_hdr(hdr); 2039 break; 2040 case AMDGPU_UCODE_ID_CP_ME: 2041 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2042 amdgpu_ucode_print_gfx_hdr(hdr); 2043 break; 2044 case AMDGPU_UCODE_ID_CP_MEC1: 2045 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2046 amdgpu_ucode_print_gfx_hdr(hdr); 2047 break; 2048 case AMDGPU_UCODE_ID_RLC_G: 2049 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2050 amdgpu_ucode_print_rlc_hdr(hdr); 2051 break; 2052 case AMDGPU_UCODE_ID_SMC: 2053 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2054 amdgpu_ucode_print_smc_hdr(hdr); 2055 break; 2056 default: 2057 break; 2058 } 2059 } 2060 2061 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2062 struct psp_gfx_cmd_resp *cmd) 2063 { 2064 int ret; 2065 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2066 2067 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 2068 2069 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2070 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2071 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2072 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2073 2074 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2075 if (ret) 2076 DRM_ERROR("Unknown firmware type\n"); 2077 2078 return ret; 2079 } 2080 2081 static int psp_execute_np_fw_load(struct psp_context *psp, 2082 struct amdgpu_firmware_info *ucode) 2083 { 2084 int ret = 0; 2085 2086 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 2087 if (ret) 2088 return ret; 2089 2090 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 2091 psp->fence_buf_mc_addr); 2092 2093 return ret; 2094 } 2095 2096 static int psp_load_smu_fw(struct psp_context *psp) 2097 { 2098 int ret; 2099 struct amdgpu_device *adev = psp->adev; 2100 struct amdgpu_firmware_info *ucode = 2101 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2102 struct amdgpu_ras *ras = psp->ras.ras; 2103 2104 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2105 return 0; 2106 2107 2108 if (amdgpu_in_reset(adev) && ras && ras->supported && 2109 adev->asic_type == CHIP_ARCTURUS) { 2110 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2111 if (ret) { 2112 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2113 } 2114 } 2115 2116 ret = psp_execute_np_fw_load(psp, ucode); 2117 2118 if (ret) 2119 DRM_ERROR("PSP load smu failed!\n"); 2120 2121 return ret; 2122 } 2123 2124 static bool fw_load_skip_check(struct psp_context *psp, 2125 struct amdgpu_firmware_info *ucode) 2126 { 2127 if (!ucode->fw) 2128 return true; 2129 2130 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2131 (psp_smu_reload_quirk(psp) || 2132 psp->autoload_supported || 2133 psp->pmfw_centralized_cstate_management)) 2134 return true; 2135 2136 if (amdgpu_sriov_vf(psp->adev) && 2137 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2138 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2139 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2140 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2141 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2142 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2143 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2144 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2145 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2146 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2147 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2148 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2149 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2150 /*skip ucode loading in SRIOV VF */ 2151 return true; 2152 2153 if (psp->autoload_supported && 2154 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2155 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2156 /* skip mec JT when autoload is enabled */ 2157 return true; 2158 2159 return false; 2160 } 2161 2162 static int psp_np_fw_load(struct psp_context *psp) 2163 { 2164 int i, ret; 2165 struct amdgpu_firmware_info *ucode; 2166 struct amdgpu_device *adev = psp->adev; 2167 2168 if (psp->autoload_supported && 2169 !psp->pmfw_centralized_cstate_management) { 2170 ret = psp_load_smu_fw(psp); 2171 if (ret) 2172 return ret; 2173 } 2174 2175 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2176 ucode = &adev->firmware.ucode[i]; 2177 2178 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2179 !fw_load_skip_check(psp, ucode)) { 2180 ret = psp_load_smu_fw(psp); 2181 if (ret) 2182 return ret; 2183 continue; 2184 } 2185 2186 if (fw_load_skip_check(psp, ucode)) 2187 continue; 2188 2189 if (psp->autoload_supported && 2190 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2191 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2192 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2193 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2194 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2195 /* PSP only receive one SDMA fw for sienna_cichlid, 2196 * as all four sdma fw are same */ 2197 continue; 2198 2199 psp_print_fw_hdr(psp, ucode); 2200 2201 ret = psp_execute_np_fw_load(psp, ucode); 2202 if (ret) 2203 return ret; 2204 2205 /* Start rlc autoload after psp recieved all the gfx firmware */ 2206 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2207 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2208 ret = psp_rlc_autoload_start(psp); 2209 if (ret) { 2210 DRM_ERROR("Failed to start rlc autoload\n"); 2211 return ret; 2212 } 2213 } 2214 } 2215 2216 return 0; 2217 } 2218 2219 static int psp_load_fw(struct amdgpu_device *adev) 2220 { 2221 int ret; 2222 struct psp_context *psp = &adev->psp; 2223 2224 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2225 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2226 goto skip_memalloc; 2227 } 2228 2229 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2230 if (!psp->cmd) 2231 return -ENOMEM; 2232 2233 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2234 AMDGPU_GEM_DOMAIN_GTT, 2235 &psp->fw_pri_bo, 2236 &psp->fw_pri_mc_addr, 2237 &psp->fw_pri_buf); 2238 if (ret) 2239 goto failed; 2240 2241 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2242 AMDGPU_GEM_DOMAIN_VRAM, 2243 &psp->fence_buf_bo, 2244 &psp->fence_buf_mc_addr, 2245 &psp->fence_buf); 2246 if (ret) 2247 goto failed; 2248 2249 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2250 AMDGPU_GEM_DOMAIN_VRAM, 2251 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2252 (void **)&psp->cmd_buf_mem); 2253 if (ret) 2254 goto failed; 2255 2256 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2257 2258 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2259 if (ret) { 2260 DRM_ERROR("PSP ring init failed!\n"); 2261 goto failed; 2262 } 2263 2264 skip_memalloc: 2265 ret = psp_hw_start(psp); 2266 if (ret) 2267 goto failed; 2268 2269 ret = psp_np_fw_load(psp); 2270 if (ret) 2271 goto failed; 2272 2273 ret = psp_asd_load(psp); 2274 if (ret) { 2275 DRM_ERROR("PSP load asd failed!\n"); 2276 return ret; 2277 } 2278 2279 if (psp->adev->psp.ta_fw) { 2280 ret = psp_ras_initialize(psp); 2281 if (ret) 2282 dev_err(psp->adev->dev, 2283 "RAS: Failed to initialize RAS\n"); 2284 2285 ret = psp_hdcp_initialize(psp); 2286 if (ret) 2287 dev_err(psp->adev->dev, 2288 "HDCP: Failed to initialize HDCP\n"); 2289 2290 ret = psp_dtm_initialize(psp); 2291 if (ret) 2292 dev_err(psp->adev->dev, 2293 "DTM: Failed to initialize DTM\n"); 2294 2295 ret = psp_rap_initialize(psp); 2296 if (ret) 2297 dev_err(psp->adev->dev, 2298 "RAP: Failed to initialize RAP\n"); 2299 2300 ret = psp_securedisplay_initialize(psp); 2301 if (ret) 2302 dev_err(psp->adev->dev, 2303 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2304 } 2305 2306 return 0; 2307 2308 failed: 2309 /* 2310 * all cleanup jobs (xgmi terminate, ras terminate, 2311 * ring destroy, cmd/fence/fw buffers destory, 2312 * psp->cmd destory) are delayed to psp_hw_fini 2313 */ 2314 return ret; 2315 } 2316 2317 static int psp_hw_init(void *handle) 2318 { 2319 int ret; 2320 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2321 2322 mutex_lock(&adev->firmware.mutex); 2323 /* 2324 * This sequence is just used on hw_init only once, no need on 2325 * resume. 2326 */ 2327 ret = amdgpu_ucode_init_bo(adev); 2328 if (ret) 2329 goto failed; 2330 2331 ret = psp_load_fw(adev); 2332 if (ret) { 2333 DRM_ERROR("PSP firmware loading failed\n"); 2334 goto failed; 2335 } 2336 2337 mutex_unlock(&adev->firmware.mutex); 2338 return 0; 2339 2340 failed: 2341 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2342 mutex_unlock(&adev->firmware.mutex); 2343 return -EINVAL; 2344 } 2345 2346 static int psp_hw_fini(void *handle) 2347 { 2348 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2349 struct psp_context *psp = &adev->psp; 2350 int ret; 2351 2352 if (psp->adev->psp.ta_fw) { 2353 psp_ras_terminate(psp); 2354 psp_securedisplay_terminate(psp); 2355 psp_rap_terminate(psp); 2356 psp_dtm_terminate(psp); 2357 psp_hdcp_terminate(psp); 2358 } 2359 2360 psp_asd_unload(psp); 2361 ret = psp_clear_vf_fw(psp); 2362 if (ret) { 2363 DRM_ERROR("PSP clear vf fw!\n"); 2364 return ret; 2365 } 2366 2367 psp_tmr_terminate(psp); 2368 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2369 2370 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2371 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2372 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2373 &psp->fence_buf_mc_addr, &psp->fence_buf); 2374 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2375 (void **)&psp->cmd_buf_mem); 2376 2377 kfree(psp->cmd); 2378 psp->cmd = NULL; 2379 2380 return 0; 2381 } 2382 2383 static int psp_suspend(void *handle) 2384 { 2385 int ret; 2386 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2387 struct psp_context *psp = &adev->psp; 2388 2389 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2390 psp->xgmi_context.initialized == 1) { 2391 ret = psp_xgmi_terminate(psp); 2392 if (ret) { 2393 DRM_ERROR("Failed to terminate xgmi ta\n"); 2394 return ret; 2395 } 2396 } 2397 2398 if (psp->adev->psp.ta_fw) { 2399 ret = psp_ras_terminate(psp); 2400 if (ret) { 2401 DRM_ERROR("Failed to terminate ras ta\n"); 2402 return ret; 2403 } 2404 ret = psp_hdcp_terminate(psp); 2405 if (ret) { 2406 DRM_ERROR("Failed to terminate hdcp ta\n"); 2407 return ret; 2408 } 2409 ret = psp_dtm_terminate(psp); 2410 if (ret) { 2411 DRM_ERROR("Failed to terminate dtm ta\n"); 2412 return ret; 2413 } 2414 ret = psp_rap_terminate(psp); 2415 if (ret) { 2416 DRM_ERROR("Failed to terminate rap ta\n"); 2417 return ret; 2418 } 2419 ret = psp_securedisplay_terminate(psp); 2420 if (ret) { 2421 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2422 return ret; 2423 } 2424 } 2425 2426 ret = psp_asd_unload(psp); 2427 if (ret) { 2428 DRM_ERROR("Failed to unload asd\n"); 2429 return ret; 2430 } 2431 2432 ret = psp_tmr_terminate(psp); 2433 if (ret) { 2434 DRM_ERROR("Failed to terminate tmr\n"); 2435 return ret; 2436 } 2437 2438 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2439 if (ret) { 2440 DRM_ERROR("PSP ring stop failed\n"); 2441 return ret; 2442 } 2443 2444 return 0; 2445 } 2446 2447 static int psp_resume(void *handle) 2448 { 2449 int ret; 2450 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2451 struct psp_context *psp = &adev->psp; 2452 2453 DRM_INFO("PSP is resuming...\n"); 2454 2455 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2456 if (ret) { 2457 DRM_ERROR("Failed to process memory training!\n"); 2458 return ret; 2459 } 2460 2461 mutex_lock(&adev->firmware.mutex); 2462 2463 ret = psp_hw_start(psp); 2464 if (ret) 2465 goto failed; 2466 2467 ret = psp_np_fw_load(psp); 2468 if (ret) 2469 goto failed; 2470 2471 ret = psp_asd_load(psp); 2472 if (ret) { 2473 DRM_ERROR("PSP load asd failed!\n"); 2474 goto failed; 2475 } 2476 2477 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2478 ret = psp_xgmi_initialize(psp); 2479 /* Warning the XGMI seesion initialize failure 2480 * Instead of stop driver initialization 2481 */ 2482 if (ret) 2483 dev_err(psp->adev->dev, 2484 "XGMI: Failed to initialize XGMI session\n"); 2485 } 2486 2487 if (psp->adev->psp.ta_fw) { 2488 ret = psp_ras_initialize(psp); 2489 if (ret) 2490 dev_err(psp->adev->dev, 2491 "RAS: Failed to initialize RAS\n"); 2492 2493 ret = psp_hdcp_initialize(psp); 2494 if (ret) 2495 dev_err(psp->adev->dev, 2496 "HDCP: Failed to initialize HDCP\n"); 2497 2498 ret = psp_dtm_initialize(psp); 2499 if (ret) 2500 dev_err(psp->adev->dev, 2501 "DTM: Failed to initialize DTM\n"); 2502 2503 ret = psp_rap_initialize(psp); 2504 if (ret) 2505 dev_err(psp->adev->dev, 2506 "RAP: Failed to initialize RAP\n"); 2507 2508 ret = psp_securedisplay_initialize(psp); 2509 if (ret) 2510 dev_err(psp->adev->dev, 2511 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2512 } 2513 2514 mutex_unlock(&adev->firmware.mutex); 2515 2516 return 0; 2517 2518 failed: 2519 DRM_ERROR("PSP resume failed\n"); 2520 mutex_unlock(&adev->firmware.mutex); 2521 return ret; 2522 } 2523 2524 int psp_gpu_reset(struct amdgpu_device *adev) 2525 { 2526 int ret; 2527 2528 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2529 return 0; 2530 2531 mutex_lock(&adev->psp.mutex); 2532 ret = psp_mode1_reset(&adev->psp); 2533 mutex_unlock(&adev->psp.mutex); 2534 2535 return ret; 2536 } 2537 2538 int psp_rlc_autoload_start(struct psp_context *psp) 2539 { 2540 int ret; 2541 struct psp_gfx_cmd_resp *cmd; 2542 2543 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2544 if (!cmd) 2545 return -ENOMEM; 2546 2547 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2548 2549 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2550 psp->fence_buf_mc_addr); 2551 kfree(cmd); 2552 return ret; 2553 } 2554 2555 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2556 uint64_t cmd_gpu_addr, int cmd_size) 2557 { 2558 struct amdgpu_firmware_info ucode = {0}; 2559 2560 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2561 AMDGPU_UCODE_ID_VCN0_RAM; 2562 ucode.mc_addr = cmd_gpu_addr; 2563 ucode.ucode_size = cmd_size; 2564 2565 return psp_execute_np_fw_load(&adev->psp, &ucode); 2566 } 2567 2568 int psp_ring_cmd_submit(struct psp_context *psp, 2569 uint64_t cmd_buf_mc_addr, 2570 uint64_t fence_mc_addr, 2571 int index) 2572 { 2573 unsigned int psp_write_ptr_reg = 0; 2574 struct psp_gfx_rb_frame *write_frame; 2575 struct psp_ring *ring = &psp->km_ring; 2576 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2577 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2578 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2579 struct amdgpu_device *adev = psp->adev; 2580 uint32_t ring_size_dw = ring->ring_size / 4; 2581 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2582 2583 /* KM (GPCOM) prepare write pointer */ 2584 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2585 2586 /* Update KM RB frame pointer to new frame */ 2587 /* write_frame ptr increments by size of rb_frame in bytes */ 2588 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2589 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2590 write_frame = ring_buffer_start; 2591 else 2592 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2593 /* Check invalid write_frame ptr address */ 2594 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2595 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2596 ring_buffer_start, ring_buffer_end, write_frame); 2597 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2598 return -EINVAL; 2599 } 2600 2601 /* Initialize KM RB frame */ 2602 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2603 2604 /* Update KM RB frame */ 2605 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2606 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2607 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2608 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2609 write_frame->fence_value = index; 2610 amdgpu_asic_flush_hdp(adev, NULL); 2611 2612 /* Update the write Pointer in DWORDs */ 2613 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2614 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2615 return 0; 2616 } 2617 2618 int psp_init_asd_microcode(struct psp_context *psp, 2619 const char *chip_name) 2620 { 2621 struct amdgpu_device *adev = psp->adev; 2622 char fw_name[PSP_FW_NAME_LEN]; 2623 const struct psp_firmware_header_v1_0 *asd_hdr; 2624 int err = 0; 2625 2626 if (!chip_name) { 2627 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2628 return -EINVAL; 2629 } 2630 2631 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2632 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2633 if (err) 2634 goto out; 2635 2636 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2637 if (err) 2638 goto out; 2639 2640 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2641 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2642 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 2643 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2644 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2645 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2646 return 0; 2647 out: 2648 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2649 release_firmware(adev->psp.asd_fw); 2650 adev->psp.asd_fw = NULL; 2651 return err; 2652 } 2653 2654 int psp_init_toc_microcode(struct psp_context *psp, 2655 const char *chip_name) 2656 { 2657 struct amdgpu_device *adev = psp->adev; 2658 char fw_name[30]; 2659 const struct psp_firmware_header_v1_0 *toc_hdr; 2660 int err = 0; 2661 2662 if (!chip_name) { 2663 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2664 return -EINVAL; 2665 } 2666 2667 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2668 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2669 if (err) 2670 goto out; 2671 2672 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2673 if (err) 2674 goto out; 2675 2676 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2677 adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2678 adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version); 2679 adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2680 adev->psp.toc_start_addr = (uint8_t *)toc_hdr + 2681 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2682 return 0; 2683 out: 2684 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2685 release_firmware(adev->psp.toc_fw); 2686 adev->psp.toc_fw = NULL; 2687 return err; 2688 } 2689 2690 int psp_init_sos_microcode(struct psp_context *psp, 2691 const char *chip_name) 2692 { 2693 struct amdgpu_device *adev = psp->adev; 2694 char fw_name[PSP_FW_NAME_LEN]; 2695 const struct psp_firmware_header_v1_0 *sos_hdr; 2696 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 2697 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 2698 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2699 int err = 0; 2700 2701 if (!chip_name) { 2702 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 2703 return -EINVAL; 2704 } 2705 2706 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 2707 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 2708 if (err) 2709 goto out; 2710 2711 err = amdgpu_ucode_validate(adev->psp.sos_fw); 2712 if (err) 2713 goto out; 2714 2715 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2716 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 2717 2718 switch (sos_hdr->header.header_version_major) { 2719 case 1: 2720 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 2721 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 2722 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 2723 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 2724 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 2725 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2726 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2727 le32_to_cpu(sos_hdr->sos_offset_bytes); 2728 if (sos_hdr->header.header_version_minor == 1) { 2729 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 2730 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 2731 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2732 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 2733 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); 2734 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2735 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); 2736 } 2737 if (sos_hdr->header.header_version_minor == 2) { 2738 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 2739 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); 2740 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2741 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); 2742 } 2743 if (sos_hdr->header.header_version_minor == 3) { 2744 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 2745 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes); 2746 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2747 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes); 2748 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes); 2749 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2750 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes); 2751 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes); 2752 adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2753 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes); 2754 } 2755 break; 2756 default: 2757 dev_err(adev->dev, 2758 "unsupported psp sos firmware\n"); 2759 err = -EINVAL; 2760 goto out; 2761 } 2762 2763 return 0; 2764 out: 2765 dev_err(adev->dev, 2766 "failed to init sos firmware\n"); 2767 release_firmware(adev->psp.sos_fw); 2768 adev->psp.sos_fw = NULL; 2769 2770 return err; 2771 } 2772 2773 static int parse_ta_bin_descriptor(struct psp_context *psp, 2774 const struct ta_fw_bin_desc *desc, 2775 const struct ta_firmware_header_v2_0 *ta_hdr) 2776 { 2777 uint8_t *ucode_start_addr = NULL; 2778 2779 if (!psp || !desc || !ta_hdr) 2780 return -EINVAL; 2781 2782 ucode_start_addr = (uint8_t *)ta_hdr + 2783 le32_to_cpu(desc->offset_bytes) + 2784 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 2785 2786 switch (desc->fw_type) { 2787 case TA_FW_TYPE_PSP_ASD: 2788 psp->asd_fw_version = le32_to_cpu(desc->fw_version); 2789 psp->asd_feature_version = le32_to_cpu(desc->fw_version); 2790 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 2791 psp->asd_start_addr = ucode_start_addr; 2792 break; 2793 case TA_FW_TYPE_PSP_XGMI: 2794 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 2795 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 2796 psp->ta_xgmi_start_addr = ucode_start_addr; 2797 break; 2798 case TA_FW_TYPE_PSP_RAS: 2799 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 2800 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 2801 psp->ta_ras_start_addr = ucode_start_addr; 2802 break; 2803 case TA_FW_TYPE_PSP_HDCP: 2804 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 2805 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 2806 psp->ta_hdcp_start_addr = ucode_start_addr; 2807 break; 2808 case TA_FW_TYPE_PSP_DTM: 2809 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 2810 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 2811 psp->ta_dtm_start_addr = ucode_start_addr; 2812 break; 2813 case TA_FW_TYPE_PSP_RAP: 2814 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version); 2815 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes); 2816 psp->ta_rap_start_addr = ucode_start_addr; 2817 break; 2818 case TA_FW_TYPE_PSP_SECUREDISPLAY: 2819 psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version); 2820 psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes); 2821 psp->ta_securedisplay_start_addr = ucode_start_addr; 2822 break; 2823 default: 2824 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 2825 break; 2826 } 2827 2828 return 0; 2829 } 2830 2831 int psp_init_ta_microcode(struct psp_context *psp, 2832 const char *chip_name) 2833 { 2834 struct amdgpu_device *adev = psp->adev; 2835 char fw_name[PSP_FW_NAME_LEN]; 2836 const struct ta_firmware_header_v2_0 *ta_hdr; 2837 int err = 0; 2838 int ta_index = 0; 2839 2840 if (!chip_name) { 2841 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 2842 return -EINVAL; 2843 } 2844 2845 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 2846 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 2847 if (err) 2848 goto out; 2849 2850 err = amdgpu_ucode_validate(adev->psp.ta_fw); 2851 if (err) 2852 goto out; 2853 2854 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 2855 2856 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 2857 dev_err(adev->dev, "unsupported TA header version\n"); 2858 err = -EINVAL; 2859 goto out; 2860 } 2861 2862 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) { 2863 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 2864 err = -EINVAL; 2865 goto out; 2866 } 2867 2868 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 2869 err = parse_ta_bin_descriptor(psp, 2870 &ta_hdr->ta_fw_bin[ta_index], 2871 ta_hdr); 2872 if (err) 2873 goto out; 2874 } 2875 2876 return 0; 2877 out: 2878 dev_err(adev->dev, "fail to initialize ta microcode\n"); 2879 release_firmware(adev->psp.ta_fw); 2880 adev->psp.ta_fw = NULL; 2881 return err; 2882 } 2883 2884 static int psp_set_clockgating_state(void *handle, 2885 enum amd_clockgating_state state) 2886 { 2887 return 0; 2888 } 2889 2890 static int psp_set_powergating_state(void *handle, 2891 enum amd_powergating_state state) 2892 { 2893 return 0; 2894 } 2895 2896 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 2897 struct device_attribute *attr, 2898 char *buf) 2899 { 2900 struct drm_device *ddev = dev_get_drvdata(dev); 2901 struct amdgpu_device *adev = drm_to_adev(ddev); 2902 uint32_t fw_ver; 2903 int ret; 2904 2905 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2906 DRM_INFO("PSP block is not ready yet."); 2907 return -EBUSY; 2908 } 2909 2910 mutex_lock(&adev->psp.mutex); 2911 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 2912 mutex_unlock(&adev->psp.mutex); 2913 2914 if (ret) { 2915 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 2916 return ret; 2917 } 2918 2919 return snprintf(buf, PAGE_SIZE, "%x\n", fw_ver); 2920 } 2921 2922 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 2923 struct device_attribute *attr, 2924 const char *buf, 2925 size_t count) 2926 { 2927 struct drm_device *ddev = dev_get_drvdata(dev); 2928 struct amdgpu_device *adev = drm_to_adev(ddev); 2929 void *cpu_addr; 2930 dma_addr_t dma_addr; 2931 int ret; 2932 char fw_name[100]; 2933 const struct firmware *usbc_pd_fw; 2934 2935 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2936 DRM_INFO("PSP block is not ready yet."); 2937 return -EBUSY; 2938 } 2939 2940 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 2941 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 2942 if (ret) 2943 goto fail; 2944 2945 /* We need contiguous physical mem to place the FW for psp to access */ 2946 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL); 2947 2948 ret = dma_mapping_error(adev->dev, dma_addr); 2949 if (ret) 2950 goto rel_buf; 2951 2952 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 2953 2954 /* 2955 * x86 specific workaround. 2956 * Without it the buffer is invisible in PSP. 2957 * 2958 * TODO Remove once PSP starts snooping CPU cache 2959 */ 2960 #ifdef CONFIG_X86 2961 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1))); 2962 #endif 2963 2964 mutex_lock(&adev->psp.mutex); 2965 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr); 2966 mutex_unlock(&adev->psp.mutex); 2967 2968 rel_buf: 2969 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr); 2970 release_firmware(usbc_pd_fw); 2971 2972 fail: 2973 if (ret) { 2974 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 2975 return ret; 2976 } 2977 2978 return count; 2979 } 2980 2981 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 2982 psp_usbc_pd_fw_sysfs_read, 2983 psp_usbc_pd_fw_sysfs_write); 2984 2985 2986 2987 const struct amd_ip_funcs psp_ip_funcs = { 2988 .name = "psp", 2989 .early_init = psp_early_init, 2990 .late_init = NULL, 2991 .sw_init = psp_sw_init, 2992 .sw_fini = psp_sw_fini, 2993 .hw_init = psp_hw_init, 2994 .hw_fini = psp_hw_fini, 2995 .suspend = psp_suspend, 2996 .resume = psp_resume, 2997 .is_idle = NULL, 2998 .check_soft_reset = NULL, 2999 .wait_for_idle = NULL, 3000 .soft_reset = NULL, 3001 .set_clockgating_state = psp_set_clockgating_state, 3002 .set_powergating_state = psp_set_powergating_state, 3003 }; 3004 3005 static int psp_sysfs_init(struct amdgpu_device *adev) 3006 { 3007 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3008 3009 if (ret) 3010 DRM_ERROR("Failed to create USBC PD FW control file!"); 3011 3012 return ret; 3013 } 3014 3015 static void psp_sysfs_fini(struct amdgpu_device *adev) 3016 { 3017 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3018 } 3019 3020 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3021 { 3022 .type = AMD_IP_BLOCK_TYPE_PSP, 3023 .major = 3, 3024 .minor = 1, 3025 .rev = 0, 3026 .funcs = &psp_ip_funcs, 3027 }; 3028 3029 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3030 { 3031 .type = AMD_IP_BLOCK_TYPE_PSP, 3032 .major = 10, 3033 .minor = 0, 3034 .rev = 0, 3035 .funcs = &psp_ip_funcs, 3036 }; 3037 3038 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3039 { 3040 .type = AMD_IP_BLOCK_TYPE_PSP, 3041 .major = 11, 3042 .minor = 0, 3043 .rev = 0, 3044 .funcs = &psp_ip_funcs, 3045 }; 3046 3047 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3048 { 3049 .type = AMD_IP_BLOCK_TYPE_PSP, 3050 .major = 12, 3051 .minor = 0, 3052 .rev = 0, 3053 .funcs = &psp_ip_funcs, 3054 }; 3055