1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 #include "psp_v10_0.h" 34 35 static void psp_set_funcs(struct amdgpu_device *adev); 36 37 static int psp_early_init(void *handle) 38 { 39 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 40 41 psp_set_funcs(adev); 42 43 return 0; 44 } 45 46 static int psp_sw_init(void *handle) 47 { 48 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 49 struct psp_context *psp = &adev->psp; 50 int ret; 51 52 switch (adev->asic_type) { 53 case CHIP_VEGA10: 54 psp->init_microcode = psp_v3_1_init_microcode; 55 psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv; 56 psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos; 57 psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf; 58 psp->ring_init = psp_v3_1_ring_init; 59 psp->ring_create = psp_v3_1_ring_create; 60 psp->ring_destroy = psp_v3_1_ring_destroy; 61 psp->cmd_submit = psp_v3_1_cmd_submit; 62 psp->compare_sram_data = psp_v3_1_compare_sram_data; 63 psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk; 64 break; 65 case CHIP_RAVEN: 66 psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf; 67 psp->ring_init = psp_v10_0_ring_init; 68 psp->cmd_submit = psp_v10_0_cmd_submit; 69 psp->compare_sram_data = psp_v10_0_compare_sram_data; 70 break; 71 default: 72 return -EINVAL; 73 } 74 75 psp->adev = adev; 76 77 ret = psp_init_microcode(psp); 78 if (ret) { 79 DRM_ERROR("Failed to load psp firmware!\n"); 80 return ret; 81 } 82 83 return 0; 84 } 85 86 static int psp_sw_fini(void *handle) 87 { 88 return 0; 89 } 90 91 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 92 uint32_t reg_val, uint32_t mask, bool check_changed) 93 { 94 uint32_t val; 95 int i; 96 struct amdgpu_device *adev = psp->adev; 97 98 val = RREG32(reg_index); 99 100 for (i = 0; i < adev->usec_timeout; i++) { 101 if (check_changed) { 102 if (val != reg_val) 103 return 0; 104 } else { 105 if ((val & mask) == reg_val) 106 return 0; 107 } 108 udelay(1); 109 } 110 111 return -ETIME; 112 } 113 114 static int 115 psp_cmd_submit_buf(struct psp_context *psp, 116 struct amdgpu_firmware_info *ucode, 117 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr, 118 int index) 119 { 120 int ret; 121 struct amdgpu_bo *cmd_buf_bo; 122 uint64_t cmd_buf_mc_addr; 123 struct psp_gfx_cmd_resp *cmd_buf_mem; 124 struct amdgpu_device *adev = psp->adev; 125 126 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 127 AMDGPU_GEM_DOMAIN_VRAM, 128 &cmd_buf_bo, &cmd_buf_mc_addr, 129 (void **)&cmd_buf_mem); 130 if (ret) 131 return ret; 132 133 memset(cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 134 135 memcpy(cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 136 137 ret = psp_cmd_submit(psp, ucode, cmd_buf_mc_addr, 138 fence_mc_addr, index); 139 140 while (*((unsigned int *)psp->fence_buf) != index) { 141 msleep(1); 142 } 143 144 amdgpu_bo_free_kernel(&cmd_buf_bo, 145 &cmd_buf_mc_addr, 146 (void **)&cmd_buf_mem); 147 148 return ret; 149 } 150 151 static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd, 152 uint64_t tmr_mc, uint32_t size) 153 { 154 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 155 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 156 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 157 cmd->cmd.cmd_setup_tmr.buf_size = size; 158 } 159 160 /* Set up Trusted Memory Region */ 161 static int psp_tmr_init(struct psp_context *psp) 162 { 163 int ret; 164 165 /* 166 * Allocate 3M memory aligned to 1M from Frame Buffer (local 167 * physical). 168 * 169 * Note: this memory need be reserved till the driver 170 * uninitializes. 171 */ 172 ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000, 173 AMDGPU_GEM_DOMAIN_VRAM, 174 &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 175 176 return ret; 177 } 178 179 static int psp_tmr_load(struct psp_context *psp) 180 { 181 int ret; 182 struct psp_gfx_cmd_resp *cmd; 183 184 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 185 if (!cmd) 186 return -ENOMEM; 187 188 psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000); 189 190 ret = psp_cmd_submit_buf(psp, NULL, cmd, 191 psp->fence_buf_mc_addr, 1); 192 if (ret) 193 goto failed; 194 195 kfree(cmd); 196 197 return 0; 198 199 failed: 200 kfree(cmd); 201 return ret; 202 } 203 204 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd, 205 uint64_t asd_mc, uint64_t asd_mc_shared, 206 uint32_t size, uint32_t shared_size) 207 { 208 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 209 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 210 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 211 cmd->cmd.cmd_load_ta.app_len = size; 212 213 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared); 214 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared); 215 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 216 } 217 218 static int psp_asd_init(struct psp_context *psp) 219 { 220 int ret; 221 222 /* 223 * Allocate 16k memory aligned to 4k from Frame Buffer (local 224 * physical) for shared ASD <-> Driver 225 */ 226 ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE, 227 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 228 &psp->asd_shared_bo, 229 &psp->asd_shared_mc_addr, 230 &psp->asd_shared_buf); 231 232 return ret; 233 } 234 235 static int psp_asd_load(struct psp_context *psp) 236 { 237 int ret; 238 struct psp_gfx_cmd_resp *cmd; 239 240 /* If PSP version doesn't match ASD version, asd loading will be failed. 241 * add workaround to bypass it for sriov now. 242 * TODO: add version check to make it common 243 */ 244 if (amdgpu_sriov_vf(psp->adev)) 245 return 0; 246 247 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 248 if (!cmd) 249 return -ENOMEM; 250 251 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 252 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 253 254 psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr, 255 psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE); 256 257 ret = psp_cmd_submit_buf(psp, NULL, cmd, 258 psp->fence_buf_mc_addr, 2); 259 260 kfree(cmd); 261 262 return ret; 263 } 264 265 static int psp_hw_start(struct psp_context *psp) 266 { 267 int ret; 268 269 ret = psp_bootloader_load_sysdrv(psp); 270 if (ret) 271 return ret; 272 273 ret = psp_bootloader_load_sos(psp); 274 if (ret) 275 return ret; 276 277 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 278 if (ret) 279 return ret; 280 281 ret = psp_tmr_load(psp); 282 if (ret) 283 return ret; 284 285 ret = psp_asd_load(psp); 286 if (ret) 287 return ret; 288 289 return 0; 290 } 291 292 static int psp_np_fw_load(struct psp_context *psp) 293 { 294 int i, ret; 295 struct amdgpu_firmware_info *ucode; 296 struct amdgpu_device* adev = psp->adev; 297 298 for (i = 0; i < adev->firmware.max_ucodes; i++) { 299 ucode = &adev->firmware.ucode[i]; 300 if (!ucode->fw) 301 continue; 302 303 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 304 psp_smu_reload_quirk(psp)) 305 continue; 306 if (amdgpu_sriov_vf(adev) && 307 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 308 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 309 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) 310 /*skip ucode loading in SRIOV VF */ 311 continue; 312 313 ret = psp_prep_cmd_buf(ucode, psp->cmd); 314 if (ret) 315 return ret; 316 317 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 318 psp->fence_buf_mc_addr, i + 3); 319 if (ret) 320 return ret; 321 322 #if 0 323 /* check if firmware loaded sucessfully */ 324 if (!amdgpu_psp_check_fw_loading_status(adev, i)) 325 return -EINVAL; 326 #endif 327 } 328 329 return 0; 330 } 331 332 static int psp_load_fw(struct amdgpu_device *adev) 333 { 334 int ret; 335 struct psp_context *psp = &adev->psp; 336 337 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 338 if (!psp->cmd) 339 return -ENOMEM; 340 341 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 342 AMDGPU_GEM_DOMAIN_GTT, 343 &psp->fw_pri_bo, 344 &psp->fw_pri_mc_addr, 345 &psp->fw_pri_buf); 346 if (ret) 347 goto failed; 348 349 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 350 AMDGPU_GEM_DOMAIN_VRAM, 351 &psp->fence_buf_bo, 352 &psp->fence_buf_mc_addr, 353 &psp->fence_buf); 354 if (ret) 355 goto failed_mem1; 356 357 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 358 359 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 360 if (ret) 361 goto failed_mem1; 362 363 ret = psp_tmr_init(psp); 364 if (ret) 365 goto failed_mem; 366 367 ret = psp_asd_init(psp); 368 if (ret) 369 goto failed_mem; 370 371 ret = psp_hw_start(psp); 372 if (ret) 373 goto failed_mem; 374 375 ret = psp_np_fw_load(psp); 376 if (ret) 377 goto failed_mem; 378 379 return 0; 380 381 failed_mem: 382 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 383 &psp->fence_buf_mc_addr, &psp->fence_buf); 384 failed_mem1: 385 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 386 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 387 failed: 388 kfree(psp->cmd); 389 psp->cmd = NULL; 390 return ret; 391 } 392 393 static int psp_hw_init(void *handle) 394 { 395 int ret; 396 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 397 398 399 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 400 return 0; 401 402 mutex_lock(&adev->firmware.mutex); 403 /* 404 * This sequence is just used on hw_init only once, no need on 405 * resume. 406 */ 407 ret = amdgpu_ucode_init_bo(adev); 408 if (ret) 409 goto failed; 410 411 ret = psp_load_fw(adev); 412 if (ret) { 413 DRM_ERROR("PSP firmware loading failed\n"); 414 goto failed; 415 } 416 417 mutex_unlock(&adev->firmware.mutex); 418 return 0; 419 420 failed: 421 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 422 mutex_unlock(&adev->firmware.mutex); 423 return -EINVAL; 424 } 425 426 static int psp_hw_fini(void *handle) 427 { 428 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 429 struct psp_context *psp = &adev->psp; 430 431 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 432 return 0; 433 434 amdgpu_ucode_fini_bo(adev); 435 436 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 437 438 if (psp->tmr_buf) 439 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 440 441 if (psp->fw_pri_buf) 442 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 443 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 444 445 if (psp->fence_buf_bo) 446 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 447 &psp->fence_buf_mc_addr, &psp->fence_buf); 448 449 kfree(psp->cmd); 450 psp->cmd = NULL; 451 452 return 0; 453 } 454 455 static int psp_suspend(void *handle) 456 { 457 return 0; 458 } 459 460 static int psp_resume(void *handle) 461 { 462 int ret; 463 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 464 struct psp_context *psp = &adev->psp; 465 466 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 467 return 0; 468 469 DRM_INFO("PSP is resuming...\n"); 470 471 mutex_lock(&adev->firmware.mutex); 472 473 ret = psp_hw_start(psp); 474 if (ret) 475 goto failed; 476 477 ret = psp_np_fw_load(psp); 478 if (ret) 479 goto failed; 480 481 mutex_unlock(&adev->firmware.mutex); 482 483 return 0; 484 485 failed: 486 DRM_ERROR("PSP resume failed\n"); 487 mutex_unlock(&adev->firmware.mutex); 488 return ret; 489 } 490 491 static bool psp_check_fw_loading_status(struct amdgpu_device *adev, 492 enum AMDGPU_UCODE_ID ucode_type) 493 { 494 struct amdgpu_firmware_info *ucode = NULL; 495 496 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 497 DRM_INFO("firmware is not loaded by PSP\n"); 498 return true; 499 } 500 501 if (!adev->firmware.fw_size) 502 return false; 503 504 ucode = &adev->firmware.ucode[ucode_type]; 505 if (!ucode->fw || !ucode->ucode_size) 506 return false; 507 508 return psp_compare_sram_data(&adev->psp, ucode, ucode_type); 509 } 510 511 static int psp_set_clockgating_state(void *handle, 512 enum amd_clockgating_state state) 513 { 514 return 0; 515 } 516 517 static int psp_set_powergating_state(void *handle, 518 enum amd_powergating_state state) 519 { 520 return 0; 521 } 522 523 const struct amd_ip_funcs psp_ip_funcs = { 524 .name = "psp", 525 .early_init = psp_early_init, 526 .late_init = NULL, 527 .sw_init = psp_sw_init, 528 .sw_fini = psp_sw_fini, 529 .hw_init = psp_hw_init, 530 .hw_fini = psp_hw_fini, 531 .suspend = psp_suspend, 532 .resume = psp_resume, 533 .is_idle = NULL, 534 .wait_for_idle = NULL, 535 .soft_reset = NULL, 536 .set_clockgating_state = psp_set_clockgating_state, 537 .set_powergating_state = psp_set_powergating_state, 538 }; 539 540 static const struct amdgpu_psp_funcs psp_funcs = { 541 .check_fw_loading_status = psp_check_fw_loading_status, 542 }; 543 544 static void psp_set_funcs(struct amdgpu_device *adev) 545 { 546 if (NULL == adev->firmware.funcs) 547 adev->firmware.funcs = &psp_funcs; 548 } 549 550 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 551 { 552 .type = AMD_IP_BLOCK_TYPE_PSP, 553 .major = 3, 554 .minor = 1, 555 .rev = 0, 556 .funcs = &psp_ip_funcs, 557 }; 558 559 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 560 { 561 .type = AMD_IP_BLOCK_TYPE_PSP, 562 .major = 10, 563 .minor = 0, 564 .rev = 0, 565 .funcs = &psp_ip_funcs, 566 }; 567