1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/dma-mapping.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v3_1.h" 34 #include "psp_v10_0.h" 35 #include "psp_v11_0.h" 36 #include "psp_v12_0.h" 37 #include "psp_v13_0.h" 38 39 #include "amdgpu_ras.h" 40 #include "amdgpu_securedisplay.h" 41 42 static int psp_sysfs_init(struct amdgpu_device *adev); 43 static void psp_sysfs_fini(struct amdgpu_device *adev); 44 45 static int psp_load_smu_fw(struct psp_context *psp); 46 47 /* 48 * Due to DF Cstate management centralized to PMFW, the firmware 49 * loading sequence will be updated as below: 50 * - Load KDB 51 * - Load SYS_DRV 52 * - Load tOS 53 * - Load PMFW 54 * - Setup TMR 55 * - Load other non-psp fw 56 * - Load ASD 57 * - Load XGMI/RAS/HDCP/DTM TA if any 58 * 59 * This new sequence is required for 60 * - Arcturus and onwards 61 * - Navi12 and onwards 62 */ 63 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 64 { 65 struct amdgpu_device *adev = psp->adev; 66 67 psp->pmfw_centralized_cstate_management = false; 68 69 if (amdgpu_sriov_vf(adev)) 70 return; 71 72 if (adev->flags & AMD_IS_APU) 73 return; 74 75 if ((adev->asic_type >= CHIP_ARCTURUS) || 76 (adev->asic_type >= CHIP_NAVI12)) 77 psp->pmfw_centralized_cstate_management = true; 78 } 79 80 static int psp_early_init(void *handle) 81 { 82 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 83 struct psp_context *psp = &adev->psp; 84 85 switch (adev->asic_type) { 86 case CHIP_VEGA10: 87 case CHIP_VEGA12: 88 psp_v3_1_set_psp_funcs(psp); 89 psp->autoload_supported = false; 90 break; 91 case CHIP_RAVEN: 92 psp_v10_0_set_psp_funcs(psp); 93 psp->autoload_supported = false; 94 break; 95 case CHIP_VEGA20: 96 case CHIP_ARCTURUS: 97 psp_v11_0_set_psp_funcs(psp); 98 psp->autoload_supported = false; 99 break; 100 case CHIP_NAVI10: 101 case CHIP_NAVI14: 102 case CHIP_NAVI12: 103 case CHIP_SIENNA_CICHLID: 104 case CHIP_NAVY_FLOUNDER: 105 case CHIP_VANGOGH: 106 case CHIP_DIMGREY_CAVEFISH: 107 psp_v11_0_set_psp_funcs(psp); 108 psp->autoload_supported = true; 109 break; 110 case CHIP_RENOIR: 111 psp_v12_0_set_psp_funcs(psp); 112 break; 113 case CHIP_ALDEBARAN: 114 psp_v13_0_set_psp_funcs(psp); 115 break; 116 default: 117 return -EINVAL; 118 } 119 120 psp->adev = adev; 121 122 psp_check_pmfw_centralized_cstate_management(psp); 123 124 return 0; 125 } 126 127 static void psp_memory_training_fini(struct psp_context *psp) 128 { 129 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 130 131 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 132 kfree(ctx->sys_cache); 133 ctx->sys_cache = NULL; 134 } 135 136 static int psp_memory_training_init(struct psp_context *psp) 137 { 138 int ret; 139 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 140 141 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 142 DRM_DEBUG("memory training is not supported!\n"); 143 return 0; 144 } 145 146 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 147 if (ctx->sys_cache == NULL) { 148 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 149 ret = -ENOMEM; 150 goto Err_out; 151 } 152 153 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 154 ctx->train_data_size, 155 ctx->p2c_train_data_offset, 156 ctx->c2p_train_data_offset); 157 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 158 return 0; 159 160 Err_out: 161 psp_memory_training_fini(psp); 162 return ret; 163 } 164 165 static int psp_sw_init(void *handle) 166 { 167 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 168 struct psp_context *psp = &adev->psp; 169 int ret; 170 171 if (!amdgpu_sriov_vf(adev)) { 172 ret = psp_init_microcode(psp); 173 if (ret) { 174 DRM_ERROR("Failed to load psp firmware!\n"); 175 return ret; 176 } 177 } 178 179 ret = psp_memory_training_init(psp); 180 if (ret) { 181 DRM_ERROR("Failed to initialize memory training!\n"); 182 return ret; 183 } 184 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 185 if (ret) { 186 DRM_ERROR("Failed to process memory training!\n"); 187 return ret; 188 } 189 190 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 191 ret= psp_sysfs_init(adev); 192 if (ret) { 193 return ret; 194 } 195 } 196 197 return 0; 198 } 199 200 static int psp_sw_fini(void *handle) 201 { 202 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 203 204 psp_memory_training_fini(&adev->psp); 205 if (adev->psp.sos_fw) { 206 release_firmware(adev->psp.sos_fw); 207 adev->psp.sos_fw = NULL; 208 } 209 if (adev->psp.asd_fw) { 210 release_firmware(adev->psp.asd_fw); 211 adev->psp.asd_fw = NULL; 212 } 213 if (adev->psp.ta_fw) { 214 release_firmware(adev->psp.ta_fw); 215 adev->psp.ta_fw = NULL; 216 } 217 218 if (adev->asic_type == CHIP_NAVI10 || 219 adev->asic_type == CHIP_SIENNA_CICHLID) 220 psp_sysfs_fini(adev); 221 222 return 0; 223 } 224 225 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 226 uint32_t reg_val, uint32_t mask, bool check_changed) 227 { 228 uint32_t val; 229 int i; 230 struct amdgpu_device *adev = psp->adev; 231 232 if (psp->adev->in_pci_err_recovery) 233 return 0; 234 235 for (i = 0; i < adev->usec_timeout; i++) { 236 val = RREG32(reg_index); 237 if (check_changed) { 238 if (val != reg_val) 239 return 0; 240 } else { 241 if ((val & mask) == reg_val) 242 return 0; 243 } 244 udelay(1); 245 } 246 247 return -ETIME; 248 } 249 250 static int 251 psp_cmd_submit_buf(struct psp_context *psp, 252 struct amdgpu_firmware_info *ucode, 253 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 254 { 255 int ret; 256 int index; 257 int timeout = 20000; 258 bool ras_intr = false; 259 bool skip_unsupport = false; 260 261 if (psp->adev->in_pci_err_recovery) 262 return 0; 263 264 mutex_lock(&psp->mutex); 265 266 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 267 268 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 269 270 index = atomic_inc_return(&psp->fence_value); 271 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 272 if (ret) { 273 atomic_dec(&psp->fence_value); 274 mutex_unlock(&psp->mutex); 275 return ret; 276 } 277 278 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 279 while (*((unsigned int *)psp->fence_buf) != index) { 280 if (--timeout == 0) 281 break; 282 /* 283 * Shouldn't wait for timeout when err_event_athub occurs, 284 * because gpu reset thread triggered and lock resource should 285 * be released for psp resume sequence. 286 */ 287 ras_intr = amdgpu_ras_intr_triggered(); 288 if (ras_intr) 289 break; 290 usleep_range(10, 100); 291 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 292 } 293 294 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 295 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 296 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 297 298 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 299 300 /* In some cases, psp response status is not 0 even there is no 301 * problem while the command is submitted. Some version of PSP FW 302 * doesn't write 0 to that field. 303 * So here we would like to only print a warning instead of an error 304 * during psp initialization to avoid breaking hw_init and it doesn't 305 * return -EINVAL. 306 */ 307 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 308 if (ucode) 309 DRM_WARN("failed to load ucode id (%d) ", 310 ucode->ucode_id); 311 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n", 312 psp->cmd_buf_mem->cmd_id, 313 psp->cmd_buf_mem->resp.status); 314 if (!timeout) { 315 mutex_unlock(&psp->mutex); 316 return -EINVAL; 317 } 318 } 319 320 if (ucode) { 321 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 322 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 323 } 324 mutex_unlock(&psp->mutex); 325 326 return ret; 327 } 328 329 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 330 struct psp_gfx_cmd_resp *cmd, 331 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 332 { 333 struct amdgpu_device *adev = psp->adev; 334 uint32_t size = amdgpu_bo_size(tmr_bo); 335 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 336 337 if (amdgpu_sriov_vf(psp->adev)) 338 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 339 else 340 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 341 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 342 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 343 cmd->cmd.cmd_setup_tmr.buf_size = size; 344 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 345 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 346 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 347 } 348 349 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 350 uint64_t pri_buf_mc, uint32_t size) 351 { 352 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 353 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 354 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 355 cmd->cmd.cmd_load_toc.toc_size = size; 356 } 357 358 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 359 static int psp_load_toc(struct psp_context *psp, 360 uint32_t *tmr_size) 361 { 362 int ret; 363 struct psp_gfx_cmd_resp *cmd; 364 365 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 366 if (!cmd) 367 return -ENOMEM; 368 /* Copy toc to psp firmware private buffer */ 369 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 370 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size); 371 372 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 373 374 ret = psp_cmd_submit_buf(psp, NULL, cmd, 375 psp->fence_buf_mc_addr); 376 if (!ret) 377 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 378 kfree(cmd); 379 return ret; 380 } 381 382 /* Set up Trusted Memory Region */ 383 static int psp_tmr_init(struct psp_context *psp) 384 { 385 int ret; 386 int tmr_size; 387 void *tmr_buf; 388 void **pptr; 389 390 /* 391 * According to HW engineer, they prefer the TMR address be "naturally 392 * aligned" , e.g. the start address be an integer divide of TMR size. 393 * 394 * Note: this memory need be reserved till the driver 395 * uninitializes. 396 */ 397 tmr_size = PSP_TMR_SIZE(psp->adev); 398 399 /* For ASICs support RLC autoload, psp will parse the toc 400 * and calculate the total size of TMR needed */ 401 if (!amdgpu_sriov_vf(psp->adev) && 402 psp->toc_start_addr && 403 psp->toc_bin_size && 404 psp->fw_pri_buf) { 405 ret = psp_load_toc(psp, &tmr_size); 406 if (ret) { 407 DRM_ERROR("Failed to load toc\n"); 408 return ret; 409 } 410 } 411 412 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 413 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 414 AMDGPU_GEM_DOMAIN_VRAM, 415 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 416 417 return ret; 418 } 419 420 static bool psp_skip_tmr(struct psp_context *psp) 421 { 422 switch (psp->adev->asic_type) { 423 case CHIP_NAVI12: 424 case CHIP_SIENNA_CICHLID: 425 case CHIP_ALDEBARAN: 426 return true; 427 default: 428 return false; 429 } 430 } 431 432 static int psp_tmr_load(struct psp_context *psp) 433 { 434 int ret; 435 struct psp_gfx_cmd_resp *cmd; 436 437 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 438 * Already set up by host driver. 439 */ 440 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 441 return 0; 442 443 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 444 if (!cmd) 445 return -ENOMEM; 446 447 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 448 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 449 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 450 451 ret = psp_cmd_submit_buf(psp, NULL, cmd, 452 psp->fence_buf_mc_addr); 453 454 kfree(cmd); 455 456 return ret; 457 } 458 459 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 460 struct psp_gfx_cmd_resp *cmd) 461 { 462 if (amdgpu_sriov_vf(psp->adev)) 463 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 464 else 465 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 466 } 467 468 static int psp_tmr_unload(struct psp_context *psp) 469 { 470 int ret; 471 struct psp_gfx_cmd_resp *cmd; 472 473 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 474 if (!cmd) 475 return -ENOMEM; 476 477 psp_prep_tmr_unload_cmd_buf(psp, cmd); 478 DRM_INFO("free PSP TMR buffer\n"); 479 480 ret = psp_cmd_submit_buf(psp, NULL, cmd, 481 psp->fence_buf_mc_addr); 482 483 kfree(cmd); 484 485 return ret; 486 } 487 488 static int psp_tmr_terminate(struct psp_context *psp) 489 { 490 int ret; 491 void *tmr_buf; 492 void **pptr; 493 494 ret = psp_tmr_unload(psp); 495 if (ret) 496 return ret; 497 498 /* free TMR memory buffer */ 499 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 500 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 501 502 return 0; 503 } 504 505 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 506 uint64_t *output_ptr) 507 { 508 int ret; 509 struct psp_gfx_cmd_resp *cmd; 510 511 if (!output_ptr) 512 return -EINVAL; 513 514 if (amdgpu_sriov_vf(psp->adev)) 515 return 0; 516 517 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 518 if (!cmd) 519 return -ENOMEM; 520 521 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 522 523 ret = psp_cmd_submit_buf(psp, NULL, cmd, 524 psp->fence_buf_mc_addr); 525 526 if (!ret) { 527 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 528 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 529 } 530 531 kfree(cmd); 532 533 return ret; 534 } 535 536 static int psp_boot_config_set(struct amdgpu_device *adev) 537 { 538 struct psp_context *psp = &adev->psp; 539 struct psp_gfx_cmd_resp *cmd = psp->cmd; 540 541 if (adev->asic_type != CHIP_SIENNA_CICHLID || amdgpu_sriov_vf(adev)) 542 return 0; 543 544 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 545 546 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 547 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 548 cmd->cmd.boot_cfg.boot_config = BOOT_CONFIG_GECC; 549 cmd->cmd.boot_cfg.boot_config_valid = BOOT_CONFIG_GECC; 550 551 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 552 } 553 554 static int psp_rl_load(struct amdgpu_device *adev) 555 { 556 struct psp_context *psp = &adev->psp; 557 struct psp_gfx_cmd_resp *cmd = psp->cmd; 558 559 if (psp->rl_bin_size == 0) 560 return 0; 561 562 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 563 memcpy(psp->fw_pri_buf, psp->rl_start_addr, psp->rl_bin_size); 564 565 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 566 567 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 568 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 569 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 570 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl_bin_size; 571 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 572 573 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 574 } 575 576 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 577 uint64_t asd_mc, uint32_t size) 578 { 579 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 580 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 581 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 582 cmd->cmd.cmd_load_ta.app_len = size; 583 584 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 585 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 586 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 587 } 588 589 static int psp_asd_load(struct psp_context *psp) 590 { 591 int ret; 592 struct psp_gfx_cmd_resp *cmd; 593 594 /* If PSP version doesn't match ASD version, asd loading will be failed. 595 * add workaround to bypass it for sriov now. 596 * TODO: add version check to make it common 597 */ 598 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size) 599 return 0; 600 601 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 602 if (!cmd) 603 return -ENOMEM; 604 605 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 606 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 607 608 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 609 psp->asd_ucode_size); 610 611 ret = psp_cmd_submit_buf(psp, NULL, cmd, 612 psp->fence_buf_mc_addr); 613 if (!ret) { 614 psp->asd_context.asd_initialized = true; 615 psp->asd_context.session_id = cmd->resp.session_id; 616 } 617 618 kfree(cmd); 619 620 return ret; 621 } 622 623 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 624 uint32_t session_id) 625 { 626 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 627 cmd->cmd.cmd_unload_ta.session_id = session_id; 628 } 629 630 static int psp_asd_unload(struct psp_context *psp) 631 { 632 int ret; 633 struct psp_gfx_cmd_resp *cmd; 634 635 if (amdgpu_sriov_vf(psp->adev)) 636 return 0; 637 638 if (!psp->asd_context.asd_initialized) 639 return 0; 640 641 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 642 if (!cmd) 643 return -ENOMEM; 644 645 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 646 647 ret = psp_cmd_submit_buf(psp, NULL, cmd, 648 psp->fence_buf_mc_addr); 649 if (!ret) 650 psp->asd_context.asd_initialized = false; 651 652 kfree(cmd); 653 654 return ret; 655 } 656 657 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 658 uint32_t id, uint32_t value) 659 { 660 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 661 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 662 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 663 } 664 665 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 666 uint32_t value) 667 { 668 struct psp_gfx_cmd_resp *cmd = NULL; 669 int ret = 0; 670 671 if (reg >= PSP_REG_LAST) 672 return -EINVAL; 673 674 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 675 if (!cmd) 676 return -ENOMEM; 677 678 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 679 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 680 681 kfree(cmd); 682 return ret; 683 } 684 685 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 686 uint64_t ta_bin_mc, 687 uint32_t ta_bin_size, 688 uint64_t ta_shared_mc, 689 uint32_t ta_shared_size) 690 { 691 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 692 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 693 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 694 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 695 696 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 697 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 698 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 699 } 700 701 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 702 { 703 int ret; 704 705 /* 706 * Allocate 16k memory aligned to 4k from Frame Buffer (local 707 * physical) for xgmi ta <-> Driver 708 */ 709 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 710 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 711 &psp->xgmi_context.xgmi_shared_bo, 712 &psp->xgmi_context.xgmi_shared_mc_addr, 713 &psp->xgmi_context.xgmi_shared_buf); 714 715 return ret; 716 } 717 718 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 719 uint32_t ta_cmd_id, 720 uint32_t session_id) 721 { 722 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 723 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 724 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 725 } 726 727 static int psp_ta_invoke(struct psp_context *psp, 728 uint32_t ta_cmd_id, 729 uint32_t session_id) 730 { 731 int ret; 732 struct psp_gfx_cmd_resp *cmd; 733 734 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 735 if (!cmd) 736 return -ENOMEM; 737 738 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 739 740 ret = psp_cmd_submit_buf(psp, NULL, cmd, 741 psp->fence_buf_mc_addr); 742 743 kfree(cmd); 744 745 return ret; 746 } 747 748 static int psp_xgmi_load(struct psp_context *psp) 749 { 750 int ret; 751 struct psp_gfx_cmd_resp *cmd; 752 753 /* 754 * TODO: bypass the loading in sriov for now 755 */ 756 757 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 758 if (!cmd) 759 return -ENOMEM; 760 761 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 762 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 763 764 psp_prep_ta_load_cmd_buf(cmd, 765 psp->fw_pri_mc_addr, 766 psp->ta_xgmi_ucode_size, 767 psp->xgmi_context.xgmi_shared_mc_addr, 768 PSP_XGMI_SHARED_MEM_SIZE); 769 770 ret = psp_cmd_submit_buf(psp, NULL, cmd, 771 psp->fence_buf_mc_addr); 772 773 if (!ret) { 774 psp->xgmi_context.initialized = 1; 775 psp->xgmi_context.session_id = cmd->resp.session_id; 776 } 777 778 kfree(cmd); 779 780 return ret; 781 } 782 783 static int psp_xgmi_unload(struct psp_context *psp) 784 { 785 int ret; 786 struct psp_gfx_cmd_resp *cmd; 787 struct amdgpu_device *adev = psp->adev; 788 789 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 790 if (adev->asic_type == CHIP_ARCTURUS || 791 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu)) 792 return 0; 793 794 /* 795 * TODO: bypass the unloading in sriov for now 796 */ 797 798 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 799 if (!cmd) 800 return -ENOMEM; 801 802 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 803 804 ret = psp_cmd_submit_buf(psp, NULL, cmd, 805 psp->fence_buf_mc_addr); 806 807 kfree(cmd); 808 809 return ret; 810 } 811 812 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 813 { 814 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 815 } 816 817 int psp_xgmi_terminate(struct psp_context *psp) 818 { 819 int ret; 820 821 if (!psp->xgmi_context.initialized) 822 return 0; 823 824 ret = psp_xgmi_unload(psp); 825 if (ret) 826 return ret; 827 828 psp->xgmi_context.initialized = 0; 829 830 /* free xgmi shared memory */ 831 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 832 &psp->xgmi_context.xgmi_shared_mc_addr, 833 &psp->xgmi_context.xgmi_shared_buf); 834 835 return 0; 836 } 837 838 int psp_xgmi_initialize(struct psp_context *psp) 839 { 840 struct ta_xgmi_shared_memory *xgmi_cmd; 841 int ret; 842 843 if (!psp->adev->psp.ta_fw || 844 !psp->adev->psp.ta_xgmi_ucode_size || 845 !psp->adev->psp.ta_xgmi_start_addr) 846 return -ENOENT; 847 848 if (!psp->xgmi_context.initialized) { 849 ret = psp_xgmi_init_shared_buf(psp); 850 if (ret) 851 return ret; 852 } 853 854 /* Load XGMI TA */ 855 ret = psp_xgmi_load(psp); 856 if (ret) 857 return ret; 858 859 /* Initialize XGMI session */ 860 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 861 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 862 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 863 864 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 865 866 return ret; 867 } 868 869 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 870 { 871 struct ta_xgmi_shared_memory *xgmi_cmd; 872 int ret; 873 874 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 875 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 876 877 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 878 879 /* Invoke xgmi ta to get hive id */ 880 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 881 if (ret) 882 return ret; 883 884 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 885 886 return 0; 887 } 888 889 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 890 { 891 struct ta_xgmi_shared_memory *xgmi_cmd; 892 int ret; 893 894 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 895 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 896 897 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 898 899 /* Invoke xgmi ta to get the node id */ 900 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 901 if (ret) 902 return ret; 903 904 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 905 906 return 0; 907 } 908 909 int psp_xgmi_get_topology_info(struct psp_context *psp, 910 int number_devices, 911 struct psp_xgmi_topology_info *topology) 912 { 913 struct ta_xgmi_shared_memory *xgmi_cmd; 914 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 915 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 916 int i; 917 int ret; 918 919 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 920 return -EINVAL; 921 922 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 923 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 924 925 /* Fill in the shared memory with topology information as input */ 926 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 927 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 928 topology_info_input->num_nodes = number_devices; 929 930 for (i = 0; i < topology_info_input->num_nodes; i++) { 931 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 932 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 933 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 934 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 935 } 936 937 /* Invoke xgmi ta to get the topology information */ 938 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 939 if (ret) 940 return ret; 941 942 /* Read the output topology information from the shared memory */ 943 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 944 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 945 for (i = 0; i < topology->num_nodes; i++) { 946 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 947 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 948 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 949 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 950 } 951 952 return 0; 953 } 954 955 int psp_xgmi_set_topology_info(struct psp_context *psp, 956 int number_devices, 957 struct psp_xgmi_topology_info *topology) 958 { 959 struct ta_xgmi_shared_memory *xgmi_cmd; 960 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 961 int i; 962 963 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 964 return -EINVAL; 965 966 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 967 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 968 969 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 970 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 971 topology_info_input->num_nodes = number_devices; 972 973 for (i = 0; i < topology_info_input->num_nodes; i++) { 974 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 975 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 976 topology_info_input->nodes[i].is_sharing_enabled = 1; 977 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 978 } 979 980 /* Invoke xgmi ta to set topology information */ 981 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 982 } 983 984 // ras begin 985 static int psp_ras_init_shared_buf(struct psp_context *psp) 986 { 987 int ret; 988 989 /* 990 * Allocate 16k memory aligned to 4k from Frame Buffer (local 991 * physical) for ras ta <-> Driver 992 */ 993 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 994 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 995 &psp->ras.ras_shared_bo, 996 &psp->ras.ras_shared_mc_addr, 997 &psp->ras.ras_shared_buf); 998 999 return ret; 1000 } 1001 1002 static int psp_ras_load(struct psp_context *psp) 1003 { 1004 int ret; 1005 struct psp_gfx_cmd_resp *cmd; 1006 struct ta_ras_shared_memory *ras_cmd; 1007 1008 /* 1009 * TODO: bypass the loading in sriov for now 1010 */ 1011 if (amdgpu_sriov_vf(psp->adev)) 1012 return 0; 1013 1014 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1015 if (!cmd) 1016 return -ENOMEM; 1017 1018 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1019 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 1020 1021 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1022 1023 if (psp->adev->gmc.xgmi.connected_to_cpu) 1024 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1025 else 1026 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1027 1028 psp_prep_ta_load_cmd_buf(cmd, 1029 psp->fw_pri_mc_addr, 1030 psp->ta_ras_ucode_size, 1031 psp->ras.ras_shared_mc_addr, 1032 PSP_RAS_SHARED_MEM_SIZE); 1033 1034 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1035 psp->fence_buf_mc_addr); 1036 1037 if (!ret) { 1038 psp->ras.session_id = cmd->resp.session_id; 1039 1040 if (!ras_cmd->ras_status) 1041 psp->ras.ras_initialized = true; 1042 else 1043 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1044 } 1045 1046 if (ret || ras_cmd->ras_status) 1047 amdgpu_ras_fini(psp->adev); 1048 1049 kfree(cmd); 1050 1051 return ret; 1052 } 1053 1054 static int psp_ras_unload(struct psp_context *psp) 1055 { 1056 int ret; 1057 struct psp_gfx_cmd_resp *cmd; 1058 1059 /* 1060 * TODO: bypass the unloading in sriov for now 1061 */ 1062 if (amdgpu_sriov_vf(psp->adev)) 1063 return 0; 1064 1065 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1066 if (!cmd) 1067 return -ENOMEM; 1068 1069 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 1070 1071 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1072 psp->fence_buf_mc_addr); 1073 1074 kfree(cmd); 1075 1076 return ret; 1077 } 1078 1079 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1080 { 1081 struct ta_ras_shared_memory *ras_cmd; 1082 int ret; 1083 1084 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1085 1086 /* 1087 * TODO: bypass the loading in sriov for now 1088 */ 1089 if (amdgpu_sriov_vf(psp->adev)) 1090 return 0; 1091 1092 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 1093 1094 if (amdgpu_ras_intr_triggered()) 1095 return ret; 1096 1097 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1098 { 1099 DRM_WARN("RAS: Unsupported Interface"); 1100 return -EINVAL; 1101 } 1102 1103 if (!ret) { 1104 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1105 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1106 1107 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1108 } 1109 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1110 dev_warn(psp->adev->dev, 1111 "RAS internal register access blocked\n"); 1112 } 1113 1114 return ret; 1115 } 1116 1117 static int psp_ras_status_to_errno(struct amdgpu_device *adev, 1118 enum ta_ras_status ras_status) 1119 { 1120 int ret = -EINVAL; 1121 1122 switch (ras_status) { 1123 case TA_RAS_STATUS__SUCCESS: 1124 ret = 0; 1125 break; 1126 case TA_RAS_STATUS__RESET_NEEDED: 1127 ret = -EAGAIN; 1128 break; 1129 case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: 1130 dev_warn(adev->dev, "RAS WARN: ras function unavailable\n"); 1131 break; 1132 case TA_RAS_STATUS__ERROR_ASD_READ_WRITE: 1133 dev_warn(adev->dev, "RAS WARN: asd read or write failed\n"); 1134 break; 1135 default: 1136 dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret); 1137 } 1138 1139 return ret; 1140 } 1141 1142 int psp_ras_enable_features(struct psp_context *psp, 1143 union ta_ras_cmd_input *info, bool enable) 1144 { 1145 struct ta_ras_shared_memory *ras_cmd; 1146 int ret; 1147 1148 if (!psp->ras.ras_initialized) 1149 return -EINVAL; 1150 1151 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1152 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1153 1154 if (enable) 1155 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1156 else 1157 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1158 1159 ras_cmd->ras_in_message = *info; 1160 1161 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1162 if (ret) 1163 return -EINVAL; 1164 1165 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1166 } 1167 1168 static int psp_ras_terminate(struct psp_context *psp) 1169 { 1170 int ret; 1171 1172 /* 1173 * TODO: bypass the terminate in sriov for now 1174 */ 1175 if (amdgpu_sriov_vf(psp->adev)) 1176 return 0; 1177 1178 if (!psp->ras.ras_initialized) 1179 return 0; 1180 1181 ret = psp_ras_unload(psp); 1182 if (ret) 1183 return ret; 1184 1185 psp->ras.ras_initialized = false; 1186 1187 /* free ras shared memory */ 1188 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1189 &psp->ras.ras_shared_mc_addr, 1190 &psp->ras.ras_shared_buf); 1191 1192 return 0; 1193 } 1194 1195 static int psp_ras_initialize(struct psp_context *psp) 1196 { 1197 int ret; 1198 1199 /* 1200 * TODO: bypass the initialize in sriov for now 1201 */ 1202 if (amdgpu_sriov_vf(psp->adev)) 1203 return 0; 1204 1205 if (!psp->adev->psp.ta_ras_ucode_size || 1206 !psp->adev->psp.ta_ras_start_addr) { 1207 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n"); 1208 return 0; 1209 } 1210 1211 if (!psp->ras.ras_initialized) { 1212 ret = psp_ras_init_shared_buf(psp); 1213 if (ret) 1214 return ret; 1215 } 1216 1217 ret = psp_ras_load(psp); 1218 if (ret) 1219 return ret; 1220 1221 return 0; 1222 } 1223 1224 int psp_ras_trigger_error(struct psp_context *psp, 1225 struct ta_ras_trigger_error_input *info) 1226 { 1227 struct ta_ras_shared_memory *ras_cmd; 1228 int ret; 1229 1230 if (!psp->ras.ras_initialized) 1231 return -EINVAL; 1232 1233 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1234 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1235 1236 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1237 ras_cmd->ras_in_message.trigger_error = *info; 1238 1239 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1240 if (ret) 1241 return -EINVAL; 1242 1243 /* If err_event_athub occurs error inject was successful, however 1244 return status from TA is no long reliable */ 1245 if (amdgpu_ras_intr_triggered()) 1246 return 0; 1247 1248 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1249 } 1250 // ras end 1251 1252 // HDCP start 1253 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1254 { 1255 int ret; 1256 1257 /* 1258 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1259 * physical) for hdcp ta <-> Driver 1260 */ 1261 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1262 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1263 &psp->hdcp_context.hdcp_shared_bo, 1264 &psp->hdcp_context.hdcp_shared_mc_addr, 1265 &psp->hdcp_context.hdcp_shared_buf); 1266 1267 return ret; 1268 } 1269 1270 static int psp_hdcp_load(struct psp_context *psp) 1271 { 1272 int ret; 1273 struct psp_gfx_cmd_resp *cmd; 1274 1275 /* 1276 * TODO: bypass the loading in sriov for now 1277 */ 1278 if (amdgpu_sriov_vf(psp->adev)) 1279 return 0; 1280 1281 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1282 if (!cmd) 1283 return -ENOMEM; 1284 1285 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1286 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr, 1287 psp->ta_hdcp_ucode_size); 1288 1289 psp_prep_ta_load_cmd_buf(cmd, 1290 psp->fw_pri_mc_addr, 1291 psp->ta_hdcp_ucode_size, 1292 psp->hdcp_context.hdcp_shared_mc_addr, 1293 PSP_HDCP_SHARED_MEM_SIZE); 1294 1295 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1296 1297 if (!ret) { 1298 psp->hdcp_context.hdcp_initialized = true; 1299 psp->hdcp_context.session_id = cmd->resp.session_id; 1300 mutex_init(&psp->hdcp_context.mutex); 1301 } 1302 1303 kfree(cmd); 1304 1305 return ret; 1306 } 1307 static int psp_hdcp_initialize(struct psp_context *psp) 1308 { 1309 int ret; 1310 1311 /* 1312 * TODO: bypass the initialize in sriov for now 1313 */ 1314 if (amdgpu_sriov_vf(psp->adev)) 1315 return 0; 1316 1317 if (!psp->adev->psp.ta_hdcp_ucode_size || 1318 !psp->adev->psp.ta_hdcp_start_addr) { 1319 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1320 return 0; 1321 } 1322 1323 if (!psp->hdcp_context.hdcp_initialized) { 1324 ret = psp_hdcp_init_shared_buf(psp); 1325 if (ret) 1326 return ret; 1327 } 1328 1329 ret = psp_hdcp_load(psp); 1330 if (ret) 1331 return ret; 1332 1333 return 0; 1334 } 1335 1336 static int psp_hdcp_unload(struct psp_context *psp) 1337 { 1338 int ret; 1339 struct psp_gfx_cmd_resp *cmd; 1340 1341 /* 1342 * TODO: bypass the unloading in sriov for now 1343 */ 1344 if (amdgpu_sriov_vf(psp->adev)) 1345 return 0; 1346 1347 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1348 if (!cmd) 1349 return -ENOMEM; 1350 1351 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1352 1353 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1354 1355 kfree(cmd); 1356 1357 return ret; 1358 } 1359 1360 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1361 { 1362 /* 1363 * TODO: bypass the loading in sriov for now 1364 */ 1365 if (amdgpu_sriov_vf(psp->adev)) 1366 return 0; 1367 1368 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1369 } 1370 1371 static int psp_hdcp_terminate(struct psp_context *psp) 1372 { 1373 int ret; 1374 1375 /* 1376 * TODO: bypass the terminate in sriov for now 1377 */ 1378 if (amdgpu_sriov_vf(psp->adev)) 1379 return 0; 1380 1381 if (!psp->hdcp_context.hdcp_initialized) { 1382 if (psp->hdcp_context.hdcp_shared_buf) 1383 goto out; 1384 else 1385 return 0; 1386 } 1387 1388 ret = psp_hdcp_unload(psp); 1389 if (ret) 1390 return ret; 1391 1392 psp->hdcp_context.hdcp_initialized = false; 1393 1394 out: 1395 /* free hdcp shared memory */ 1396 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1397 &psp->hdcp_context.hdcp_shared_mc_addr, 1398 &psp->hdcp_context.hdcp_shared_buf); 1399 1400 return 0; 1401 } 1402 // HDCP end 1403 1404 // DTM start 1405 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1406 { 1407 int ret; 1408 1409 /* 1410 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1411 * physical) for dtm ta <-> Driver 1412 */ 1413 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1414 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1415 &psp->dtm_context.dtm_shared_bo, 1416 &psp->dtm_context.dtm_shared_mc_addr, 1417 &psp->dtm_context.dtm_shared_buf); 1418 1419 return ret; 1420 } 1421 1422 static int psp_dtm_load(struct psp_context *psp) 1423 { 1424 int ret; 1425 struct psp_gfx_cmd_resp *cmd; 1426 1427 /* 1428 * TODO: bypass the loading in sriov for now 1429 */ 1430 if (amdgpu_sriov_vf(psp->adev)) 1431 return 0; 1432 1433 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1434 if (!cmd) 1435 return -ENOMEM; 1436 1437 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1438 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1439 1440 psp_prep_ta_load_cmd_buf(cmd, 1441 psp->fw_pri_mc_addr, 1442 psp->ta_dtm_ucode_size, 1443 psp->dtm_context.dtm_shared_mc_addr, 1444 PSP_DTM_SHARED_MEM_SIZE); 1445 1446 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1447 1448 if (!ret) { 1449 psp->dtm_context.dtm_initialized = true; 1450 psp->dtm_context.session_id = cmd->resp.session_id; 1451 mutex_init(&psp->dtm_context.mutex); 1452 } 1453 1454 kfree(cmd); 1455 1456 return ret; 1457 } 1458 1459 static int psp_dtm_initialize(struct psp_context *psp) 1460 { 1461 int ret; 1462 1463 /* 1464 * TODO: bypass the initialize in sriov for now 1465 */ 1466 if (amdgpu_sriov_vf(psp->adev)) 1467 return 0; 1468 1469 if (!psp->adev->psp.ta_dtm_ucode_size || 1470 !psp->adev->psp.ta_dtm_start_addr) { 1471 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1472 return 0; 1473 } 1474 1475 if (!psp->dtm_context.dtm_initialized) { 1476 ret = psp_dtm_init_shared_buf(psp); 1477 if (ret) 1478 return ret; 1479 } 1480 1481 ret = psp_dtm_load(psp); 1482 if (ret) 1483 return ret; 1484 1485 return 0; 1486 } 1487 1488 static int psp_dtm_unload(struct psp_context *psp) 1489 { 1490 int ret; 1491 struct psp_gfx_cmd_resp *cmd; 1492 1493 /* 1494 * TODO: bypass the unloading in sriov for now 1495 */ 1496 if (amdgpu_sriov_vf(psp->adev)) 1497 return 0; 1498 1499 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1500 if (!cmd) 1501 return -ENOMEM; 1502 1503 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1504 1505 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1506 1507 kfree(cmd); 1508 1509 return ret; 1510 } 1511 1512 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1513 { 1514 /* 1515 * TODO: bypass the loading in sriov for now 1516 */ 1517 if (amdgpu_sriov_vf(psp->adev)) 1518 return 0; 1519 1520 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1521 } 1522 1523 static int psp_dtm_terminate(struct psp_context *psp) 1524 { 1525 int ret; 1526 1527 /* 1528 * TODO: bypass the terminate in sriov for now 1529 */ 1530 if (amdgpu_sriov_vf(psp->adev)) 1531 return 0; 1532 1533 if (!psp->dtm_context.dtm_initialized) { 1534 if (psp->dtm_context.dtm_shared_buf) 1535 goto out; 1536 else 1537 return 0; 1538 } 1539 1540 ret = psp_dtm_unload(psp); 1541 if (ret) 1542 return ret; 1543 1544 psp->dtm_context.dtm_initialized = false; 1545 1546 out: 1547 /* free hdcp shared memory */ 1548 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1549 &psp->dtm_context.dtm_shared_mc_addr, 1550 &psp->dtm_context.dtm_shared_buf); 1551 1552 return 0; 1553 } 1554 // DTM end 1555 1556 // RAP start 1557 static int psp_rap_init_shared_buf(struct psp_context *psp) 1558 { 1559 int ret; 1560 1561 /* 1562 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1563 * physical) for rap ta <-> Driver 1564 */ 1565 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE, 1566 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1567 &psp->rap_context.rap_shared_bo, 1568 &psp->rap_context.rap_shared_mc_addr, 1569 &psp->rap_context.rap_shared_buf); 1570 1571 return ret; 1572 } 1573 1574 static int psp_rap_load(struct psp_context *psp) 1575 { 1576 int ret; 1577 struct psp_gfx_cmd_resp *cmd; 1578 1579 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1580 if (!cmd) 1581 return -ENOMEM; 1582 1583 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1584 memcpy(psp->fw_pri_buf, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); 1585 1586 psp_prep_ta_load_cmd_buf(cmd, 1587 psp->fw_pri_mc_addr, 1588 psp->ta_rap_ucode_size, 1589 psp->rap_context.rap_shared_mc_addr, 1590 PSP_RAP_SHARED_MEM_SIZE); 1591 1592 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1593 1594 if (!ret) { 1595 psp->rap_context.rap_initialized = true; 1596 psp->rap_context.session_id = cmd->resp.session_id; 1597 mutex_init(&psp->rap_context.mutex); 1598 } 1599 1600 kfree(cmd); 1601 1602 return ret; 1603 } 1604 1605 static int psp_rap_unload(struct psp_context *psp) 1606 { 1607 int ret; 1608 struct psp_gfx_cmd_resp *cmd; 1609 1610 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1611 if (!cmd) 1612 return -ENOMEM; 1613 1614 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id); 1615 1616 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1617 1618 kfree(cmd); 1619 1620 return ret; 1621 } 1622 1623 static int psp_rap_initialize(struct psp_context *psp) 1624 { 1625 int ret; 1626 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1627 1628 /* 1629 * TODO: bypass the initialize in sriov for now 1630 */ 1631 if (amdgpu_sriov_vf(psp->adev)) 1632 return 0; 1633 1634 if (!psp->adev->psp.ta_rap_ucode_size || 1635 !psp->adev->psp.ta_rap_start_addr) { 1636 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1637 return 0; 1638 } 1639 1640 if (!psp->rap_context.rap_initialized) { 1641 ret = psp_rap_init_shared_buf(psp); 1642 if (ret) 1643 return ret; 1644 } 1645 1646 ret = psp_rap_load(psp); 1647 if (ret) 1648 return ret; 1649 1650 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1651 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1652 psp_rap_unload(psp); 1653 1654 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1655 &psp->rap_context.rap_shared_mc_addr, 1656 &psp->rap_context.rap_shared_buf); 1657 1658 psp->rap_context.rap_initialized = false; 1659 1660 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1661 ret, status); 1662 1663 return ret; 1664 } 1665 1666 return 0; 1667 } 1668 1669 static int psp_rap_terminate(struct psp_context *psp) 1670 { 1671 int ret; 1672 1673 if (!psp->rap_context.rap_initialized) 1674 return 0; 1675 1676 ret = psp_rap_unload(psp); 1677 1678 psp->rap_context.rap_initialized = false; 1679 1680 /* free rap shared memory */ 1681 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1682 &psp->rap_context.rap_shared_mc_addr, 1683 &psp->rap_context.rap_shared_buf); 1684 1685 return ret; 1686 } 1687 1688 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1689 { 1690 struct ta_rap_shared_memory *rap_cmd; 1691 int ret = 0; 1692 1693 if (!psp->rap_context.rap_initialized) 1694 return 0; 1695 1696 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1697 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1698 return -EINVAL; 1699 1700 mutex_lock(&psp->rap_context.mutex); 1701 1702 rap_cmd = (struct ta_rap_shared_memory *) 1703 psp->rap_context.rap_shared_buf; 1704 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1705 1706 rap_cmd->cmd_id = ta_cmd_id; 1707 rap_cmd->validation_method_id = METHOD_A; 1708 1709 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id); 1710 if (ret) 1711 goto out_unlock; 1712 1713 if (status) 1714 *status = rap_cmd->rap_status; 1715 1716 out_unlock: 1717 mutex_unlock(&psp->rap_context.mutex); 1718 1719 return ret; 1720 } 1721 // RAP end 1722 1723 /* securedisplay start */ 1724 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1725 { 1726 int ret; 1727 1728 /* 1729 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1730 * physical) for sa ta <-> Driver 1731 */ 1732 ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE, 1733 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1734 &psp->securedisplay_context.securedisplay_shared_bo, 1735 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1736 &psp->securedisplay_context.securedisplay_shared_buf); 1737 1738 return ret; 1739 } 1740 1741 static int psp_securedisplay_load(struct psp_context *psp) 1742 { 1743 int ret; 1744 struct psp_gfx_cmd_resp *cmd; 1745 1746 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1747 if (!cmd) 1748 return -ENOMEM; 1749 1750 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1751 memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size); 1752 1753 psp_prep_ta_load_cmd_buf(cmd, 1754 psp->fw_pri_mc_addr, 1755 psp->ta_securedisplay_ucode_size, 1756 psp->securedisplay_context.securedisplay_shared_mc_addr, 1757 PSP_SECUREDISPLAY_SHARED_MEM_SIZE); 1758 1759 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1760 1761 if (ret) 1762 goto failed; 1763 1764 psp->securedisplay_context.securedisplay_initialized = true; 1765 psp->securedisplay_context.session_id = cmd->resp.session_id; 1766 mutex_init(&psp->securedisplay_context.mutex); 1767 1768 failed: 1769 kfree(cmd); 1770 return ret; 1771 } 1772 1773 static int psp_securedisplay_unload(struct psp_context *psp) 1774 { 1775 int ret; 1776 struct psp_gfx_cmd_resp *cmd; 1777 1778 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1779 if (!cmd) 1780 return -ENOMEM; 1781 1782 psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id); 1783 1784 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1785 1786 kfree(cmd); 1787 1788 return ret; 1789 } 1790 1791 static int psp_securedisplay_initialize(struct psp_context *psp) 1792 { 1793 int ret; 1794 struct securedisplay_cmd *securedisplay_cmd; 1795 1796 /* 1797 * TODO: bypass the initialize in sriov for now 1798 */ 1799 if (amdgpu_sriov_vf(psp->adev)) 1800 return 0; 1801 1802 if (!psp->adev->psp.ta_securedisplay_ucode_size || 1803 !psp->adev->psp.ta_securedisplay_start_addr) { 1804 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1805 return 0; 1806 } 1807 1808 if (!psp->securedisplay_context.securedisplay_initialized) { 1809 ret = psp_securedisplay_init_shared_buf(psp); 1810 if (ret) 1811 return ret; 1812 } 1813 1814 ret = psp_securedisplay_load(psp); 1815 if (ret) 1816 return ret; 1817 1818 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1819 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1820 1821 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1822 if (ret) { 1823 psp_securedisplay_unload(psp); 1824 1825 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 1826 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1827 &psp->securedisplay_context.securedisplay_shared_buf); 1828 1829 psp->securedisplay_context.securedisplay_initialized = false; 1830 1831 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1832 return -EINVAL; 1833 } 1834 1835 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1836 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1837 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1838 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1839 } 1840 1841 return 0; 1842 } 1843 1844 static int psp_securedisplay_terminate(struct psp_context *psp) 1845 { 1846 int ret; 1847 1848 /* 1849 * TODO:bypass the terminate in sriov for now 1850 */ 1851 if (amdgpu_sriov_vf(psp->adev)) 1852 return 0; 1853 1854 if (!psp->securedisplay_context.securedisplay_initialized) 1855 return 0; 1856 1857 ret = psp_securedisplay_unload(psp); 1858 if (ret) 1859 return ret; 1860 1861 psp->securedisplay_context.securedisplay_initialized = false; 1862 1863 /* free securedisplay shared memory */ 1864 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 1865 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1866 &psp->securedisplay_context.securedisplay_shared_buf); 1867 1868 return ret; 1869 } 1870 1871 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1872 { 1873 int ret; 1874 1875 if (!psp->securedisplay_context.securedisplay_initialized) 1876 return -EINVAL; 1877 1878 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1879 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1880 return -EINVAL; 1881 1882 mutex_lock(&psp->securedisplay_context.mutex); 1883 1884 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id); 1885 1886 mutex_unlock(&psp->securedisplay_context.mutex); 1887 1888 return ret; 1889 } 1890 /* SECUREDISPLAY end */ 1891 1892 static int psp_hw_start(struct psp_context *psp) 1893 { 1894 struct amdgpu_device *adev = psp->adev; 1895 int ret; 1896 1897 if (!amdgpu_sriov_vf(adev)) { 1898 if (psp->kdb_bin_size && 1899 (psp->funcs->bootloader_load_kdb != NULL)) { 1900 ret = psp_bootloader_load_kdb(psp); 1901 if (ret) { 1902 DRM_ERROR("PSP load kdb failed!\n"); 1903 return ret; 1904 } 1905 } 1906 1907 if (psp->spl_bin_size) { 1908 ret = psp_bootloader_load_spl(psp); 1909 if (ret) { 1910 DRM_ERROR("PSP load spl failed!\n"); 1911 return ret; 1912 } 1913 } 1914 1915 ret = psp_bootloader_load_sysdrv(psp); 1916 if (ret) { 1917 DRM_ERROR("PSP load sysdrv failed!\n"); 1918 return ret; 1919 } 1920 1921 ret = psp_bootloader_load_sos(psp); 1922 if (ret) { 1923 DRM_ERROR("PSP load sos failed!\n"); 1924 return ret; 1925 } 1926 } 1927 1928 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1929 if (ret) { 1930 DRM_ERROR("PSP create ring failed!\n"); 1931 return ret; 1932 } 1933 1934 ret = psp_boot_config_set(adev); 1935 if (ret) { 1936 DRM_WARN("PSP set boot config@\n"); 1937 } 1938 1939 ret = psp_tmr_init(psp); 1940 if (ret) { 1941 DRM_ERROR("PSP tmr init failed!\n"); 1942 return ret; 1943 } 1944 1945 /* 1946 * For ASICs with DF Cstate management centralized 1947 * to PMFW, TMR setup should be performed after PMFW 1948 * loaded and before other non-psp firmware loaded. 1949 */ 1950 if (psp->pmfw_centralized_cstate_management) { 1951 ret = psp_load_smu_fw(psp); 1952 if (ret) 1953 return ret; 1954 } 1955 1956 ret = psp_tmr_load(psp); 1957 if (ret) { 1958 DRM_ERROR("PSP load tmr failed!\n"); 1959 return ret; 1960 } 1961 1962 return 0; 1963 } 1964 1965 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 1966 enum psp_gfx_fw_type *type) 1967 { 1968 switch (ucode->ucode_id) { 1969 case AMDGPU_UCODE_ID_SDMA0: 1970 *type = GFX_FW_TYPE_SDMA0; 1971 break; 1972 case AMDGPU_UCODE_ID_SDMA1: 1973 *type = GFX_FW_TYPE_SDMA1; 1974 break; 1975 case AMDGPU_UCODE_ID_SDMA2: 1976 *type = GFX_FW_TYPE_SDMA2; 1977 break; 1978 case AMDGPU_UCODE_ID_SDMA3: 1979 *type = GFX_FW_TYPE_SDMA3; 1980 break; 1981 case AMDGPU_UCODE_ID_SDMA4: 1982 *type = GFX_FW_TYPE_SDMA4; 1983 break; 1984 case AMDGPU_UCODE_ID_SDMA5: 1985 *type = GFX_FW_TYPE_SDMA5; 1986 break; 1987 case AMDGPU_UCODE_ID_SDMA6: 1988 *type = GFX_FW_TYPE_SDMA6; 1989 break; 1990 case AMDGPU_UCODE_ID_SDMA7: 1991 *type = GFX_FW_TYPE_SDMA7; 1992 break; 1993 case AMDGPU_UCODE_ID_CP_MES: 1994 *type = GFX_FW_TYPE_CP_MES; 1995 break; 1996 case AMDGPU_UCODE_ID_CP_MES_DATA: 1997 *type = GFX_FW_TYPE_MES_STACK; 1998 break; 1999 case AMDGPU_UCODE_ID_CP_CE: 2000 *type = GFX_FW_TYPE_CP_CE; 2001 break; 2002 case AMDGPU_UCODE_ID_CP_PFP: 2003 *type = GFX_FW_TYPE_CP_PFP; 2004 break; 2005 case AMDGPU_UCODE_ID_CP_ME: 2006 *type = GFX_FW_TYPE_CP_ME; 2007 break; 2008 case AMDGPU_UCODE_ID_CP_MEC1: 2009 *type = GFX_FW_TYPE_CP_MEC; 2010 break; 2011 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2012 *type = GFX_FW_TYPE_CP_MEC_ME1; 2013 break; 2014 case AMDGPU_UCODE_ID_CP_MEC2: 2015 *type = GFX_FW_TYPE_CP_MEC; 2016 break; 2017 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2018 *type = GFX_FW_TYPE_CP_MEC_ME2; 2019 break; 2020 case AMDGPU_UCODE_ID_RLC_G: 2021 *type = GFX_FW_TYPE_RLC_G; 2022 break; 2023 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2024 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2025 break; 2026 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2027 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2028 break; 2029 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2030 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2031 break; 2032 case AMDGPU_UCODE_ID_RLC_IRAM: 2033 *type = GFX_FW_TYPE_RLC_IRAM; 2034 break; 2035 case AMDGPU_UCODE_ID_RLC_DRAM: 2036 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2037 break; 2038 case AMDGPU_UCODE_ID_SMC: 2039 *type = GFX_FW_TYPE_SMU; 2040 break; 2041 case AMDGPU_UCODE_ID_UVD: 2042 *type = GFX_FW_TYPE_UVD; 2043 break; 2044 case AMDGPU_UCODE_ID_UVD1: 2045 *type = GFX_FW_TYPE_UVD1; 2046 break; 2047 case AMDGPU_UCODE_ID_VCE: 2048 *type = GFX_FW_TYPE_VCE; 2049 break; 2050 case AMDGPU_UCODE_ID_VCN: 2051 *type = GFX_FW_TYPE_VCN; 2052 break; 2053 case AMDGPU_UCODE_ID_VCN1: 2054 *type = GFX_FW_TYPE_VCN1; 2055 break; 2056 case AMDGPU_UCODE_ID_DMCU_ERAM: 2057 *type = GFX_FW_TYPE_DMCU_ERAM; 2058 break; 2059 case AMDGPU_UCODE_ID_DMCU_INTV: 2060 *type = GFX_FW_TYPE_DMCU_ISR; 2061 break; 2062 case AMDGPU_UCODE_ID_VCN0_RAM: 2063 *type = GFX_FW_TYPE_VCN0_RAM; 2064 break; 2065 case AMDGPU_UCODE_ID_VCN1_RAM: 2066 *type = GFX_FW_TYPE_VCN1_RAM; 2067 break; 2068 case AMDGPU_UCODE_ID_DMCUB: 2069 *type = GFX_FW_TYPE_DMUB; 2070 break; 2071 case AMDGPU_UCODE_ID_MAXIMUM: 2072 default: 2073 return -EINVAL; 2074 } 2075 2076 return 0; 2077 } 2078 2079 static void psp_print_fw_hdr(struct psp_context *psp, 2080 struct amdgpu_firmware_info *ucode) 2081 { 2082 struct amdgpu_device *adev = psp->adev; 2083 struct common_firmware_header *hdr; 2084 2085 switch (ucode->ucode_id) { 2086 case AMDGPU_UCODE_ID_SDMA0: 2087 case AMDGPU_UCODE_ID_SDMA1: 2088 case AMDGPU_UCODE_ID_SDMA2: 2089 case AMDGPU_UCODE_ID_SDMA3: 2090 case AMDGPU_UCODE_ID_SDMA4: 2091 case AMDGPU_UCODE_ID_SDMA5: 2092 case AMDGPU_UCODE_ID_SDMA6: 2093 case AMDGPU_UCODE_ID_SDMA7: 2094 hdr = (struct common_firmware_header *) 2095 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2096 amdgpu_ucode_print_sdma_hdr(hdr); 2097 break; 2098 case AMDGPU_UCODE_ID_CP_CE: 2099 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2100 amdgpu_ucode_print_gfx_hdr(hdr); 2101 break; 2102 case AMDGPU_UCODE_ID_CP_PFP: 2103 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2104 amdgpu_ucode_print_gfx_hdr(hdr); 2105 break; 2106 case AMDGPU_UCODE_ID_CP_ME: 2107 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2108 amdgpu_ucode_print_gfx_hdr(hdr); 2109 break; 2110 case AMDGPU_UCODE_ID_CP_MEC1: 2111 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2112 amdgpu_ucode_print_gfx_hdr(hdr); 2113 break; 2114 case AMDGPU_UCODE_ID_RLC_G: 2115 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2116 amdgpu_ucode_print_rlc_hdr(hdr); 2117 break; 2118 case AMDGPU_UCODE_ID_SMC: 2119 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2120 amdgpu_ucode_print_smc_hdr(hdr); 2121 break; 2122 default: 2123 break; 2124 } 2125 } 2126 2127 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2128 struct psp_gfx_cmd_resp *cmd) 2129 { 2130 int ret; 2131 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2132 2133 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 2134 2135 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2136 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2137 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2138 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2139 2140 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2141 if (ret) 2142 DRM_ERROR("Unknown firmware type\n"); 2143 2144 return ret; 2145 } 2146 2147 static int psp_execute_np_fw_load(struct psp_context *psp, 2148 struct amdgpu_firmware_info *ucode) 2149 { 2150 int ret = 0; 2151 2152 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 2153 if (ret) 2154 return ret; 2155 2156 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 2157 psp->fence_buf_mc_addr); 2158 2159 return ret; 2160 } 2161 2162 static int psp_load_smu_fw(struct psp_context *psp) 2163 { 2164 int ret; 2165 struct amdgpu_device *adev = psp->adev; 2166 struct amdgpu_firmware_info *ucode = 2167 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2168 struct amdgpu_ras *ras = psp->ras.ras; 2169 2170 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2171 return 0; 2172 2173 if ((amdgpu_in_reset(adev) && 2174 ras && adev->ras_enabled && 2175 (adev->asic_type == CHIP_ARCTURUS || 2176 adev->asic_type == CHIP_VEGA20)) || 2177 (adev->in_runpm && 2178 adev->asic_type >= CHIP_NAVI10 && 2179 adev->asic_type <= CHIP_NAVI12)) { 2180 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2181 if (ret) { 2182 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2183 } 2184 } 2185 2186 ret = psp_execute_np_fw_load(psp, ucode); 2187 2188 if (ret) 2189 DRM_ERROR("PSP load smu failed!\n"); 2190 2191 return ret; 2192 } 2193 2194 static bool fw_load_skip_check(struct psp_context *psp, 2195 struct amdgpu_firmware_info *ucode) 2196 { 2197 if (!ucode->fw) 2198 return true; 2199 2200 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2201 (psp_smu_reload_quirk(psp) || 2202 psp->autoload_supported || 2203 psp->pmfw_centralized_cstate_management)) 2204 return true; 2205 2206 if (amdgpu_sriov_vf(psp->adev) && 2207 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2208 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2209 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2210 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2211 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2212 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2213 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2214 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2215 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2216 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2217 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2218 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2219 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2220 /*skip ucode loading in SRIOV VF */ 2221 return true; 2222 2223 if (psp->autoload_supported && 2224 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2225 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2226 /* skip mec JT when autoload is enabled */ 2227 return true; 2228 2229 return false; 2230 } 2231 2232 int psp_load_fw_list(struct psp_context *psp, 2233 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2234 { 2235 int ret = 0, i; 2236 struct amdgpu_firmware_info *ucode; 2237 2238 for (i = 0; i < ucode_count; ++i) { 2239 ucode = ucode_list[i]; 2240 psp_print_fw_hdr(psp, ucode); 2241 ret = psp_execute_np_fw_load(psp, ucode); 2242 if (ret) 2243 return ret; 2244 } 2245 return ret; 2246 } 2247 2248 static int psp_np_fw_load(struct psp_context *psp) 2249 { 2250 int i, ret; 2251 struct amdgpu_firmware_info *ucode; 2252 struct amdgpu_device *adev = psp->adev; 2253 2254 if (psp->autoload_supported && 2255 !psp->pmfw_centralized_cstate_management) { 2256 ret = psp_load_smu_fw(psp); 2257 if (ret) 2258 return ret; 2259 } 2260 2261 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2262 ucode = &adev->firmware.ucode[i]; 2263 2264 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2265 !fw_load_skip_check(psp, ucode)) { 2266 ret = psp_load_smu_fw(psp); 2267 if (ret) 2268 return ret; 2269 continue; 2270 } 2271 2272 if (fw_load_skip_check(psp, ucode)) 2273 continue; 2274 2275 if (psp->autoload_supported && 2276 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2277 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2278 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2279 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2280 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2281 /* PSP only receive one SDMA fw for sienna_cichlid, 2282 * as all four sdma fw are same */ 2283 continue; 2284 2285 psp_print_fw_hdr(psp, ucode); 2286 2287 ret = psp_execute_np_fw_load(psp, ucode); 2288 if (ret) 2289 return ret; 2290 2291 /* Start rlc autoload after psp recieved all the gfx firmware */ 2292 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2293 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2294 ret = psp_rlc_autoload_start(psp); 2295 if (ret) { 2296 DRM_ERROR("Failed to start rlc autoload\n"); 2297 return ret; 2298 } 2299 } 2300 } 2301 2302 return 0; 2303 } 2304 2305 static int psp_load_fw(struct amdgpu_device *adev) 2306 { 2307 int ret; 2308 struct psp_context *psp = &adev->psp; 2309 2310 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2311 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2312 goto skip_memalloc; 2313 } 2314 2315 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2316 if (!psp->cmd) 2317 return -ENOMEM; 2318 2319 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2320 AMDGPU_GEM_DOMAIN_GTT, 2321 &psp->fw_pri_bo, 2322 &psp->fw_pri_mc_addr, 2323 &psp->fw_pri_buf); 2324 if (ret) 2325 goto failed; 2326 2327 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2328 AMDGPU_GEM_DOMAIN_VRAM, 2329 &psp->fence_buf_bo, 2330 &psp->fence_buf_mc_addr, 2331 &psp->fence_buf); 2332 if (ret) 2333 goto failed; 2334 2335 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2336 AMDGPU_GEM_DOMAIN_VRAM, 2337 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2338 (void **)&psp->cmd_buf_mem); 2339 if (ret) 2340 goto failed; 2341 2342 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2343 2344 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2345 if (ret) { 2346 DRM_ERROR("PSP ring init failed!\n"); 2347 goto failed; 2348 } 2349 2350 skip_memalloc: 2351 ret = psp_hw_start(psp); 2352 if (ret) 2353 goto failed; 2354 2355 ret = psp_np_fw_load(psp); 2356 if (ret) 2357 goto failed; 2358 2359 ret = psp_asd_load(psp); 2360 if (ret) { 2361 DRM_ERROR("PSP load asd failed!\n"); 2362 return ret; 2363 } 2364 2365 ret = psp_rl_load(adev); 2366 if (ret) { 2367 DRM_ERROR("PSP load RL failed!\n"); 2368 return ret; 2369 } 2370 2371 if (psp->adev->psp.ta_fw) { 2372 ret = psp_ras_initialize(psp); 2373 if (ret) 2374 dev_err(psp->adev->dev, 2375 "RAS: Failed to initialize RAS\n"); 2376 2377 ret = psp_hdcp_initialize(psp); 2378 if (ret) 2379 dev_err(psp->adev->dev, 2380 "HDCP: Failed to initialize HDCP\n"); 2381 2382 ret = psp_dtm_initialize(psp); 2383 if (ret) 2384 dev_err(psp->adev->dev, 2385 "DTM: Failed to initialize DTM\n"); 2386 2387 ret = psp_rap_initialize(psp); 2388 if (ret) 2389 dev_err(psp->adev->dev, 2390 "RAP: Failed to initialize RAP\n"); 2391 2392 ret = psp_securedisplay_initialize(psp); 2393 if (ret) 2394 dev_err(psp->adev->dev, 2395 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2396 } 2397 2398 return 0; 2399 2400 failed: 2401 /* 2402 * all cleanup jobs (xgmi terminate, ras terminate, 2403 * ring destroy, cmd/fence/fw buffers destory, 2404 * psp->cmd destory) are delayed to psp_hw_fini 2405 */ 2406 return ret; 2407 } 2408 2409 static int psp_hw_init(void *handle) 2410 { 2411 int ret; 2412 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2413 2414 mutex_lock(&adev->firmware.mutex); 2415 /* 2416 * This sequence is just used on hw_init only once, no need on 2417 * resume. 2418 */ 2419 ret = amdgpu_ucode_init_bo(adev); 2420 if (ret) 2421 goto failed; 2422 2423 ret = psp_load_fw(adev); 2424 if (ret) { 2425 DRM_ERROR("PSP firmware loading failed\n"); 2426 goto failed; 2427 } 2428 2429 mutex_unlock(&adev->firmware.mutex); 2430 return 0; 2431 2432 failed: 2433 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2434 mutex_unlock(&adev->firmware.mutex); 2435 return -EINVAL; 2436 } 2437 2438 static int psp_hw_fini(void *handle) 2439 { 2440 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2441 struct psp_context *psp = &adev->psp; 2442 2443 if (psp->adev->psp.ta_fw) { 2444 psp_ras_terminate(psp); 2445 psp_securedisplay_terminate(psp); 2446 psp_rap_terminate(psp); 2447 psp_dtm_terminate(psp); 2448 psp_hdcp_terminate(psp); 2449 } 2450 2451 psp_asd_unload(psp); 2452 2453 psp_tmr_terminate(psp); 2454 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2455 2456 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2457 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2458 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2459 &psp->fence_buf_mc_addr, &psp->fence_buf); 2460 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2461 (void **)&psp->cmd_buf_mem); 2462 2463 kfree(psp->cmd); 2464 psp->cmd = NULL; 2465 2466 return 0; 2467 } 2468 2469 static int psp_suspend(void *handle) 2470 { 2471 int ret; 2472 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2473 struct psp_context *psp = &adev->psp; 2474 2475 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2476 psp->xgmi_context.initialized == 1) { 2477 ret = psp_xgmi_terminate(psp); 2478 if (ret) { 2479 DRM_ERROR("Failed to terminate xgmi ta\n"); 2480 return ret; 2481 } 2482 } 2483 2484 if (psp->adev->psp.ta_fw) { 2485 ret = psp_ras_terminate(psp); 2486 if (ret) { 2487 DRM_ERROR("Failed to terminate ras ta\n"); 2488 return ret; 2489 } 2490 ret = psp_hdcp_terminate(psp); 2491 if (ret) { 2492 DRM_ERROR("Failed to terminate hdcp ta\n"); 2493 return ret; 2494 } 2495 ret = psp_dtm_terminate(psp); 2496 if (ret) { 2497 DRM_ERROR("Failed to terminate dtm ta\n"); 2498 return ret; 2499 } 2500 ret = psp_rap_terminate(psp); 2501 if (ret) { 2502 DRM_ERROR("Failed to terminate rap ta\n"); 2503 return ret; 2504 } 2505 ret = psp_securedisplay_terminate(psp); 2506 if (ret) { 2507 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2508 return ret; 2509 } 2510 } 2511 2512 ret = psp_asd_unload(psp); 2513 if (ret) { 2514 DRM_ERROR("Failed to unload asd\n"); 2515 return ret; 2516 } 2517 2518 ret = psp_tmr_terminate(psp); 2519 if (ret) { 2520 DRM_ERROR("Failed to terminate tmr\n"); 2521 return ret; 2522 } 2523 2524 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2525 if (ret) { 2526 DRM_ERROR("PSP ring stop failed\n"); 2527 return ret; 2528 } 2529 2530 return 0; 2531 } 2532 2533 static int psp_resume(void *handle) 2534 { 2535 int ret; 2536 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2537 struct psp_context *psp = &adev->psp; 2538 2539 DRM_INFO("PSP is resuming...\n"); 2540 2541 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2542 if (ret) { 2543 DRM_ERROR("Failed to process memory training!\n"); 2544 return ret; 2545 } 2546 2547 mutex_lock(&adev->firmware.mutex); 2548 2549 ret = psp_hw_start(psp); 2550 if (ret) 2551 goto failed; 2552 2553 ret = psp_np_fw_load(psp); 2554 if (ret) 2555 goto failed; 2556 2557 ret = psp_asd_load(psp); 2558 if (ret) { 2559 DRM_ERROR("PSP load asd failed!\n"); 2560 goto failed; 2561 } 2562 2563 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2564 ret = psp_xgmi_initialize(psp); 2565 /* Warning the XGMI seesion initialize failure 2566 * Instead of stop driver initialization 2567 */ 2568 if (ret) 2569 dev_err(psp->adev->dev, 2570 "XGMI: Failed to initialize XGMI session\n"); 2571 } 2572 2573 if (psp->adev->psp.ta_fw) { 2574 ret = psp_ras_initialize(psp); 2575 if (ret) 2576 dev_err(psp->adev->dev, 2577 "RAS: Failed to initialize RAS\n"); 2578 2579 ret = psp_hdcp_initialize(psp); 2580 if (ret) 2581 dev_err(psp->adev->dev, 2582 "HDCP: Failed to initialize HDCP\n"); 2583 2584 ret = psp_dtm_initialize(psp); 2585 if (ret) 2586 dev_err(psp->adev->dev, 2587 "DTM: Failed to initialize DTM\n"); 2588 2589 ret = psp_rap_initialize(psp); 2590 if (ret) 2591 dev_err(psp->adev->dev, 2592 "RAP: Failed to initialize RAP\n"); 2593 2594 ret = psp_securedisplay_initialize(psp); 2595 if (ret) 2596 dev_err(psp->adev->dev, 2597 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2598 } 2599 2600 mutex_unlock(&adev->firmware.mutex); 2601 2602 return 0; 2603 2604 failed: 2605 DRM_ERROR("PSP resume failed\n"); 2606 mutex_unlock(&adev->firmware.mutex); 2607 return ret; 2608 } 2609 2610 int psp_gpu_reset(struct amdgpu_device *adev) 2611 { 2612 int ret; 2613 2614 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2615 return 0; 2616 2617 mutex_lock(&adev->psp.mutex); 2618 ret = psp_mode1_reset(&adev->psp); 2619 mutex_unlock(&adev->psp.mutex); 2620 2621 return ret; 2622 } 2623 2624 int psp_rlc_autoload_start(struct psp_context *psp) 2625 { 2626 int ret; 2627 struct psp_gfx_cmd_resp *cmd; 2628 2629 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2630 if (!cmd) 2631 return -ENOMEM; 2632 2633 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2634 2635 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2636 psp->fence_buf_mc_addr); 2637 kfree(cmd); 2638 return ret; 2639 } 2640 2641 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2642 uint64_t cmd_gpu_addr, int cmd_size) 2643 { 2644 struct amdgpu_firmware_info ucode = {0}; 2645 2646 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2647 AMDGPU_UCODE_ID_VCN0_RAM; 2648 ucode.mc_addr = cmd_gpu_addr; 2649 ucode.ucode_size = cmd_size; 2650 2651 return psp_execute_np_fw_load(&adev->psp, &ucode); 2652 } 2653 2654 int psp_ring_cmd_submit(struct psp_context *psp, 2655 uint64_t cmd_buf_mc_addr, 2656 uint64_t fence_mc_addr, 2657 int index) 2658 { 2659 unsigned int psp_write_ptr_reg = 0; 2660 struct psp_gfx_rb_frame *write_frame; 2661 struct psp_ring *ring = &psp->km_ring; 2662 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2663 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2664 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2665 struct amdgpu_device *adev = psp->adev; 2666 uint32_t ring_size_dw = ring->ring_size / 4; 2667 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2668 2669 /* KM (GPCOM) prepare write pointer */ 2670 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2671 2672 /* Update KM RB frame pointer to new frame */ 2673 /* write_frame ptr increments by size of rb_frame in bytes */ 2674 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2675 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2676 write_frame = ring_buffer_start; 2677 else 2678 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2679 /* Check invalid write_frame ptr address */ 2680 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2681 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2682 ring_buffer_start, ring_buffer_end, write_frame); 2683 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2684 return -EINVAL; 2685 } 2686 2687 /* Initialize KM RB frame */ 2688 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2689 2690 /* Update KM RB frame */ 2691 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2692 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2693 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2694 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2695 write_frame->fence_value = index; 2696 amdgpu_asic_flush_hdp(adev, NULL); 2697 2698 /* Update the write Pointer in DWORDs */ 2699 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2700 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2701 return 0; 2702 } 2703 2704 int psp_init_asd_microcode(struct psp_context *psp, 2705 const char *chip_name) 2706 { 2707 struct amdgpu_device *adev = psp->adev; 2708 char fw_name[PSP_FW_NAME_LEN]; 2709 const struct psp_firmware_header_v1_0 *asd_hdr; 2710 int err = 0; 2711 2712 if (!chip_name) { 2713 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2714 return -EINVAL; 2715 } 2716 2717 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2718 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2719 if (err) 2720 goto out; 2721 2722 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2723 if (err) 2724 goto out; 2725 2726 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2727 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2728 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 2729 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2730 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2731 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2732 return 0; 2733 out: 2734 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2735 release_firmware(adev->psp.asd_fw); 2736 adev->psp.asd_fw = NULL; 2737 return err; 2738 } 2739 2740 int psp_init_toc_microcode(struct psp_context *psp, 2741 const char *chip_name) 2742 { 2743 struct amdgpu_device *adev = psp->adev; 2744 char fw_name[30]; 2745 const struct psp_firmware_header_v1_0 *toc_hdr; 2746 int err = 0; 2747 2748 if (!chip_name) { 2749 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2750 return -EINVAL; 2751 } 2752 2753 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2754 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2755 if (err) 2756 goto out; 2757 2758 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2759 if (err) 2760 goto out; 2761 2762 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2763 adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2764 adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version); 2765 adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2766 adev->psp.toc_start_addr = (uint8_t *)toc_hdr + 2767 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2768 return 0; 2769 out: 2770 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2771 release_firmware(adev->psp.toc_fw); 2772 adev->psp.toc_fw = NULL; 2773 return err; 2774 } 2775 2776 int psp_init_sos_microcode(struct psp_context *psp, 2777 const char *chip_name) 2778 { 2779 struct amdgpu_device *adev = psp->adev; 2780 char fw_name[PSP_FW_NAME_LEN]; 2781 const struct psp_firmware_header_v1_0 *sos_hdr; 2782 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 2783 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 2784 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2785 int err = 0; 2786 2787 if (!chip_name) { 2788 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 2789 return -EINVAL; 2790 } 2791 2792 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 2793 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 2794 if (err) 2795 goto out; 2796 2797 err = amdgpu_ucode_validate(adev->psp.sos_fw); 2798 if (err) 2799 goto out; 2800 2801 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2802 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 2803 2804 switch (sos_hdr->header.header_version_major) { 2805 case 1: 2806 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 2807 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 2808 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 2809 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 2810 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 2811 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2812 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2813 le32_to_cpu(sos_hdr->sos_offset_bytes); 2814 if (sos_hdr->header.header_version_minor == 1) { 2815 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 2816 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 2817 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2818 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 2819 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); 2820 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2821 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); 2822 } 2823 if (sos_hdr->header.header_version_minor == 2) { 2824 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 2825 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); 2826 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2827 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); 2828 } 2829 if (sos_hdr->header.header_version_minor == 3) { 2830 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 2831 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes); 2832 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2833 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes); 2834 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes); 2835 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2836 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes); 2837 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes); 2838 adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2839 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes); 2840 adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl_size_bytes); 2841 adev->psp.rl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2842 le32_to_cpu(sos_hdr_v1_3->rl_offset_bytes); 2843 } 2844 break; 2845 default: 2846 dev_err(adev->dev, 2847 "unsupported psp sos firmware\n"); 2848 err = -EINVAL; 2849 goto out; 2850 } 2851 2852 return 0; 2853 out: 2854 dev_err(adev->dev, 2855 "failed to init sos firmware\n"); 2856 release_firmware(adev->psp.sos_fw); 2857 adev->psp.sos_fw = NULL; 2858 2859 return err; 2860 } 2861 2862 static int parse_ta_bin_descriptor(struct psp_context *psp, 2863 const struct ta_fw_bin_desc *desc, 2864 const struct ta_firmware_header_v2_0 *ta_hdr) 2865 { 2866 uint8_t *ucode_start_addr = NULL; 2867 2868 if (!psp || !desc || !ta_hdr) 2869 return -EINVAL; 2870 2871 ucode_start_addr = (uint8_t *)ta_hdr + 2872 le32_to_cpu(desc->offset_bytes) + 2873 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 2874 2875 switch (desc->fw_type) { 2876 case TA_FW_TYPE_PSP_ASD: 2877 psp->asd_fw_version = le32_to_cpu(desc->fw_version); 2878 psp->asd_feature_version = le32_to_cpu(desc->fw_version); 2879 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 2880 psp->asd_start_addr = ucode_start_addr; 2881 break; 2882 case TA_FW_TYPE_PSP_XGMI: 2883 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 2884 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 2885 psp->ta_xgmi_start_addr = ucode_start_addr; 2886 break; 2887 case TA_FW_TYPE_PSP_RAS: 2888 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 2889 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 2890 psp->ta_ras_start_addr = ucode_start_addr; 2891 break; 2892 case TA_FW_TYPE_PSP_HDCP: 2893 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 2894 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 2895 psp->ta_hdcp_start_addr = ucode_start_addr; 2896 break; 2897 case TA_FW_TYPE_PSP_DTM: 2898 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 2899 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 2900 psp->ta_dtm_start_addr = ucode_start_addr; 2901 break; 2902 case TA_FW_TYPE_PSP_RAP: 2903 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version); 2904 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes); 2905 psp->ta_rap_start_addr = ucode_start_addr; 2906 break; 2907 case TA_FW_TYPE_PSP_SECUREDISPLAY: 2908 psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version); 2909 psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes); 2910 psp->ta_securedisplay_start_addr = ucode_start_addr; 2911 break; 2912 default: 2913 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 2914 break; 2915 } 2916 2917 return 0; 2918 } 2919 2920 int psp_init_ta_microcode(struct psp_context *psp, 2921 const char *chip_name) 2922 { 2923 struct amdgpu_device *adev = psp->adev; 2924 char fw_name[PSP_FW_NAME_LEN]; 2925 const struct ta_firmware_header_v2_0 *ta_hdr; 2926 int err = 0; 2927 int ta_index = 0; 2928 2929 if (!chip_name) { 2930 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 2931 return -EINVAL; 2932 } 2933 2934 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 2935 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 2936 if (err) 2937 goto out; 2938 2939 err = amdgpu_ucode_validate(adev->psp.ta_fw); 2940 if (err) 2941 goto out; 2942 2943 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 2944 2945 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 2946 dev_err(adev->dev, "unsupported TA header version\n"); 2947 err = -EINVAL; 2948 goto out; 2949 } 2950 2951 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) { 2952 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 2953 err = -EINVAL; 2954 goto out; 2955 } 2956 2957 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 2958 err = parse_ta_bin_descriptor(psp, 2959 &ta_hdr->ta_fw_bin[ta_index], 2960 ta_hdr); 2961 if (err) 2962 goto out; 2963 } 2964 2965 return 0; 2966 out: 2967 dev_err(adev->dev, "fail to initialize ta microcode\n"); 2968 release_firmware(adev->psp.ta_fw); 2969 adev->psp.ta_fw = NULL; 2970 return err; 2971 } 2972 2973 static int psp_set_clockgating_state(void *handle, 2974 enum amd_clockgating_state state) 2975 { 2976 return 0; 2977 } 2978 2979 static int psp_set_powergating_state(void *handle, 2980 enum amd_powergating_state state) 2981 { 2982 return 0; 2983 } 2984 2985 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 2986 struct device_attribute *attr, 2987 char *buf) 2988 { 2989 struct drm_device *ddev = dev_get_drvdata(dev); 2990 struct amdgpu_device *adev = drm_to_adev(ddev); 2991 uint32_t fw_ver; 2992 int ret; 2993 2994 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2995 DRM_INFO("PSP block is not ready yet."); 2996 return -EBUSY; 2997 } 2998 2999 mutex_lock(&adev->psp.mutex); 3000 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3001 mutex_unlock(&adev->psp.mutex); 3002 3003 if (ret) { 3004 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3005 return ret; 3006 } 3007 3008 return sysfs_emit(buf, "%x\n", fw_ver); 3009 } 3010 3011 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3012 struct device_attribute *attr, 3013 const char *buf, 3014 size_t count) 3015 { 3016 struct drm_device *ddev = dev_get_drvdata(dev); 3017 struct amdgpu_device *adev = drm_to_adev(ddev); 3018 void *cpu_addr; 3019 dma_addr_t dma_addr; 3020 int ret; 3021 char fw_name[100]; 3022 const struct firmware *usbc_pd_fw; 3023 3024 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3025 DRM_INFO("PSP block is not ready yet."); 3026 return -EBUSY; 3027 } 3028 3029 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3030 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3031 if (ret) 3032 goto fail; 3033 3034 /* We need contiguous physical mem to place the FW for psp to access */ 3035 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL); 3036 3037 ret = dma_mapping_error(adev->dev, dma_addr); 3038 if (ret) 3039 goto rel_buf; 3040 3041 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3042 3043 /* 3044 * x86 specific workaround. 3045 * Without it the buffer is invisible in PSP. 3046 * 3047 * TODO Remove once PSP starts snooping CPU cache 3048 */ 3049 #ifdef CONFIG_X86 3050 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1))); 3051 #endif 3052 3053 mutex_lock(&adev->psp.mutex); 3054 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr); 3055 mutex_unlock(&adev->psp.mutex); 3056 3057 rel_buf: 3058 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr); 3059 release_firmware(usbc_pd_fw); 3060 3061 fail: 3062 if (ret) { 3063 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3064 return ret; 3065 } 3066 3067 return count; 3068 } 3069 3070 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3071 psp_usbc_pd_fw_sysfs_read, 3072 psp_usbc_pd_fw_sysfs_write); 3073 3074 3075 3076 const struct amd_ip_funcs psp_ip_funcs = { 3077 .name = "psp", 3078 .early_init = psp_early_init, 3079 .late_init = NULL, 3080 .sw_init = psp_sw_init, 3081 .sw_fini = psp_sw_fini, 3082 .hw_init = psp_hw_init, 3083 .hw_fini = psp_hw_fini, 3084 .suspend = psp_suspend, 3085 .resume = psp_resume, 3086 .is_idle = NULL, 3087 .check_soft_reset = NULL, 3088 .wait_for_idle = NULL, 3089 .soft_reset = NULL, 3090 .set_clockgating_state = psp_set_clockgating_state, 3091 .set_powergating_state = psp_set_powergating_state, 3092 }; 3093 3094 static int psp_sysfs_init(struct amdgpu_device *adev) 3095 { 3096 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3097 3098 if (ret) 3099 DRM_ERROR("Failed to create USBC PD FW control file!"); 3100 3101 return ret; 3102 } 3103 3104 static void psp_sysfs_fini(struct amdgpu_device *adev) 3105 { 3106 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3107 } 3108 3109 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3110 { 3111 .type = AMD_IP_BLOCK_TYPE_PSP, 3112 .major = 3, 3113 .minor = 1, 3114 .rev = 0, 3115 .funcs = &psp_ip_funcs, 3116 }; 3117 3118 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3119 { 3120 .type = AMD_IP_BLOCK_TYPE_PSP, 3121 .major = 10, 3122 .minor = 0, 3123 .rev = 0, 3124 .funcs = &psp_ip_funcs, 3125 }; 3126 3127 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3128 { 3129 .type = AMD_IP_BLOCK_TYPE_PSP, 3130 .major = 11, 3131 .minor = 0, 3132 .rev = 0, 3133 .funcs = &psp_ip_funcs, 3134 }; 3135 3136 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3137 { 3138 .type = AMD_IP_BLOCK_TYPE_PSP, 3139 .major = 12, 3140 .minor = 0, 3141 .rev = 0, 3142 .funcs = &psp_ip_funcs, 3143 }; 3144 3145 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3146 .type = AMD_IP_BLOCK_TYPE_PSP, 3147 .major = 13, 3148 .minor = 0, 3149 .rev = 0, 3150 .funcs = &psp_ip_funcs, 3151 }; 3152