1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/dma-mapping.h> 28 #include <drm/drm_drv.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_ucode.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v12_0.h" 38 #include "psp_v13_0.h" 39 40 #include "amdgpu_ras.h" 41 #include "amdgpu_securedisplay.h" 42 #include "amdgpu_atomfirmware.h" 43 44 #include <drm/drm_drv.h> 45 46 static int psp_sysfs_init(struct amdgpu_device *adev); 47 static void psp_sysfs_fini(struct amdgpu_device *adev); 48 49 static int psp_load_smu_fw(struct psp_context *psp); 50 51 /* 52 * Due to DF Cstate management centralized to PMFW, the firmware 53 * loading sequence will be updated as below: 54 * - Load KDB 55 * - Load SYS_DRV 56 * - Load tOS 57 * - Load PMFW 58 * - Setup TMR 59 * - Load other non-psp fw 60 * - Load ASD 61 * - Load XGMI/RAS/HDCP/DTM TA if any 62 * 63 * This new sequence is required for 64 * - Arcturus and onwards 65 * - Navi12 and onwards 66 */ 67 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 68 { 69 struct amdgpu_device *adev = psp->adev; 70 71 psp->pmfw_centralized_cstate_management = false; 72 73 if (amdgpu_sriov_vf(adev)) 74 return; 75 76 if (adev->flags & AMD_IS_APU) 77 return; 78 79 if ((adev->asic_type >= CHIP_ARCTURUS) || 80 (adev->asic_type >= CHIP_NAVI12)) 81 psp->pmfw_centralized_cstate_management = true; 82 } 83 84 static int psp_early_init(void *handle) 85 { 86 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 87 struct psp_context *psp = &adev->psp; 88 89 switch (adev->asic_type) { 90 case CHIP_VEGA10: 91 case CHIP_VEGA12: 92 psp_v3_1_set_psp_funcs(psp); 93 psp->autoload_supported = false; 94 break; 95 case CHIP_RAVEN: 96 psp_v10_0_set_psp_funcs(psp); 97 psp->autoload_supported = false; 98 break; 99 case CHIP_VEGA20: 100 case CHIP_ARCTURUS: 101 psp_v11_0_set_psp_funcs(psp); 102 psp->autoload_supported = false; 103 break; 104 case CHIP_NAVI10: 105 case CHIP_NAVI14: 106 case CHIP_NAVI12: 107 case CHIP_SIENNA_CICHLID: 108 case CHIP_NAVY_FLOUNDER: 109 case CHIP_VANGOGH: 110 case CHIP_DIMGREY_CAVEFISH: 111 case CHIP_BEIGE_GOBY: 112 psp_v11_0_set_psp_funcs(psp); 113 psp->autoload_supported = true; 114 break; 115 case CHIP_RENOIR: 116 psp_v12_0_set_psp_funcs(psp); 117 break; 118 case CHIP_ALDEBARAN: 119 psp_v13_0_set_psp_funcs(psp); 120 break; 121 case CHIP_YELLOW_CARP: 122 psp_v13_0_set_psp_funcs(psp); 123 psp->autoload_supported = true; 124 break; 125 default: 126 return -EINVAL; 127 } 128 129 psp->adev = adev; 130 131 psp_check_pmfw_centralized_cstate_management(psp); 132 133 return 0; 134 } 135 136 static void psp_memory_training_fini(struct psp_context *psp) 137 { 138 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 139 140 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 141 kfree(ctx->sys_cache); 142 ctx->sys_cache = NULL; 143 } 144 145 static int psp_memory_training_init(struct psp_context *psp) 146 { 147 int ret; 148 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 149 150 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 151 DRM_DEBUG("memory training is not supported!\n"); 152 return 0; 153 } 154 155 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 156 if (ctx->sys_cache == NULL) { 157 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 158 ret = -ENOMEM; 159 goto Err_out; 160 } 161 162 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 163 ctx->train_data_size, 164 ctx->p2c_train_data_offset, 165 ctx->c2p_train_data_offset); 166 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 167 return 0; 168 169 Err_out: 170 psp_memory_training_fini(psp); 171 return ret; 172 } 173 174 /* 175 * Helper funciton to query psp runtime database entry 176 * 177 * @adev: amdgpu_device pointer 178 * @entry_type: the type of psp runtime database entry 179 * @db_entry: runtime database entry pointer 180 * 181 * Return false if runtime database doesn't exit or entry is invalid 182 * or true if the specific database entry is found, and copy to @db_entry 183 */ 184 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 185 enum psp_runtime_entry_type entry_type, 186 void *db_entry) 187 { 188 uint64_t db_header_pos, db_dir_pos; 189 struct psp_runtime_data_header db_header = {0}; 190 struct psp_runtime_data_directory db_dir = {0}; 191 bool ret = false; 192 int i; 193 194 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 195 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 196 197 /* read runtime db header from vram */ 198 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 199 sizeof(struct psp_runtime_data_header), false); 200 201 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 202 /* runtime db doesn't exist, exit */ 203 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 204 return false; 205 } 206 207 /* read runtime database entry from vram */ 208 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 209 sizeof(struct psp_runtime_data_directory), false); 210 211 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 212 /* invalid db entry count, exit */ 213 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 214 return false; 215 } 216 217 /* look up for requested entry type */ 218 for (i = 0; i < db_dir.entry_count && !ret; i++) { 219 if (db_dir.entry_list[i].entry_type == entry_type) { 220 switch (entry_type) { 221 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 222 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 223 /* invalid db entry size */ 224 dev_warn(adev->dev, "Invalid PSP runtime database entry size\n"); 225 return false; 226 } 227 /* read runtime database entry */ 228 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 229 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 230 ret = true; 231 break; 232 default: 233 ret = false; 234 break; 235 } 236 } 237 } 238 239 return ret; 240 } 241 242 static int psp_sw_init(void *handle) 243 { 244 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 245 struct psp_context *psp = &adev->psp; 246 int ret; 247 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 248 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 249 250 if (!amdgpu_sriov_vf(adev)) { 251 ret = psp_init_microcode(psp); 252 if (ret) { 253 DRM_ERROR("Failed to load psp firmware!\n"); 254 return ret; 255 } 256 } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) { 257 ret = psp_init_ta_microcode(psp, "aldebaran"); 258 if (ret) { 259 DRM_ERROR("Failed to initialize ta microcode!\n"); 260 return ret; 261 } 262 } 263 264 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 265 if (psp_get_runtime_db_entry(adev, 266 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 267 &boot_cfg_entry)) { 268 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 269 if ((psp->boot_cfg_bitmask) & 270 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 271 /* If psp runtime database exists, then 272 * only enable two stage memory training 273 * when TWO_STAGE_DRAM_TRAINING bit is set 274 * in runtime database */ 275 mem_training_ctx->enable_mem_training = true; 276 } 277 278 } else { 279 /* If psp runtime database doesn't exist or 280 * is invalid, force enable two stage memory 281 * training */ 282 mem_training_ctx->enable_mem_training = true; 283 } 284 285 if (mem_training_ctx->enable_mem_training) { 286 ret = psp_memory_training_init(psp); 287 if (ret) { 288 DRM_ERROR("Failed to initialize memory training!\n"); 289 return ret; 290 } 291 292 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 293 if (ret) { 294 DRM_ERROR("Failed to process memory training!\n"); 295 return ret; 296 } 297 } 298 299 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 300 ret= psp_sysfs_init(adev); 301 if (ret) { 302 return ret; 303 } 304 } 305 306 return 0; 307 } 308 309 static int psp_sw_fini(void *handle) 310 { 311 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 312 313 psp_memory_training_fini(&adev->psp); 314 if (adev->psp.sos_fw) { 315 release_firmware(adev->psp.sos_fw); 316 adev->psp.sos_fw = NULL; 317 } 318 if (adev->psp.asd_fw) { 319 release_firmware(adev->psp.asd_fw); 320 adev->psp.asd_fw = NULL; 321 } 322 if (adev->psp.ta_fw) { 323 release_firmware(adev->psp.ta_fw); 324 adev->psp.ta_fw = NULL; 325 } 326 327 if (adev->asic_type == CHIP_NAVI10 || 328 adev->asic_type == CHIP_SIENNA_CICHLID) 329 psp_sysfs_fini(adev); 330 331 return 0; 332 } 333 334 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 335 uint32_t reg_val, uint32_t mask, bool check_changed) 336 { 337 uint32_t val; 338 int i; 339 struct amdgpu_device *adev = psp->adev; 340 341 if (psp->adev->no_hw_access) 342 return 0; 343 344 for (i = 0; i < adev->usec_timeout; i++) { 345 val = RREG32(reg_index); 346 if (check_changed) { 347 if (val != reg_val) 348 return 0; 349 } else { 350 if ((val & mask) == reg_val) 351 return 0; 352 } 353 udelay(1); 354 } 355 356 return -ETIME; 357 } 358 359 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 360 { 361 switch (cmd_id) { 362 case GFX_CMD_ID_LOAD_TA: 363 return "LOAD_TA"; 364 case GFX_CMD_ID_UNLOAD_TA: 365 return "UNLOAD_TA"; 366 case GFX_CMD_ID_INVOKE_CMD: 367 return "INVOKE_CMD"; 368 case GFX_CMD_ID_LOAD_ASD: 369 return "LOAD_ASD"; 370 case GFX_CMD_ID_SETUP_TMR: 371 return "SETUP_TMR"; 372 case GFX_CMD_ID_LOAD_IP_FW: 373 return "LOAD_IP_FW"; 374 case GFX_CMD_ID_DESTROY_TMR: 375 return "DESTROY_TMR"; 376 case GFX_CMD_ID_SAVE_RESTORE: 377 return "SAVE_RESTORE_IP_FW"; 378 case GFX_CMD_ID_SETUP_VMR: 379 return "SETUP_VMR"; 380 case GFX_CMD_ID_DESTROY_VMR: 381 return "DESTROY_VMR"; 382 case GFX_CMD_ID_PROG_REG: 383 return "PROG_REG"; 384 case GFX_CMD_ID_GET_FW_ATTESTATION: 385 return "GET_FW_ATTESTATION"; 386 case GFX_CMD_ID_LOAD_TOC: 387 return "ID_LOAD_TOC"; 388 case GFX_CMD_ID_AUTOLOAD_RLC: 389 return "AUTOLOAD_RLC"; 390 case GFX_CMD_ID_BOOT_CFG: 391 return "BOOT_CFG"; 392 default: 393 return "UNKNOWN CMD"; 394 } 395 } 396 397 static int 398 psp_cmd_submit_buf(struct psp_context *psp, 399 struct amdgpu_firmware_info *ucode, 400 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 401 { 402 int ret; 403 int index, idx; 404 int timeout = 20000; 405 bool ras_intr = false; 406 bool skip_unsupport = false; 407 408 if (psp->adev->no_hw_access) 409 return 0; 410 411 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 412 return 0; 413 414 mutex_lock(&psp->mutex); 415 416 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 417 418 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 419 420 index = atomic_inc_return(&psp->fence_value); 421 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 422 if (ret) { 423 atomic_dec(&psp->fence_value); 424 goto exit; 425 } 426 427 amdgpu_device_invalidate_hdp(psp->adev, NULL); 428 while (*((unsigned int *)psp->fence_buf) != index) { 429 if (--timeout == 0) 430 break; 431 /* 432 * Shouldn't wait for timeout when err_event_athub occurs, 433 * because gpu reset thread triggered and lock resource should 434 * be released for psp resume sequence. 435 */ 436 ras_intr = amdgpu_ras_intr_triggered(); 437 if (ras_intr) 438 break; 439 usleep_range(10, 100); 440 amdgpu_device_invalidate_hdp(psp->adev, NULL); 441 } 442 443 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 444 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 445 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 446 447 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 448 449 /* In some cases, psp response status is not 0 even there is no 450 * problem while the command is submitted. Some version of PSP FW 451 * doesn't write 0 to that field. 452 * So here we would like to only print a warning instead of an error 453 * during psp initialization to avoid breaking hw_init and it doesn't 454 * return -EINVAL. 455 */ 456 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 457 if (ucode) 458 DRM_WARN("failed to load ucode (%s) ", 459 amdgpu_ucode_name(ucode->ucode_id)); 460 DRM_WARN("psp gfx command (%s) failed and response status is (0x%X)\n", 461 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 462 psp->cmd_buf_mem->resp.status); 463 if (!timeout) { 464 ret = -EINVAL; 465 goto exit; 466 } 467 } 468 469 if (ucode) { 470 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 471 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 472 } 473 474 exit: 475 mutex_unlock(&psp->mutex); 476 drm_dev_exit(idx); 477 return ret; 478 } 479 480 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 481 struct psp_gfx_cmd_resp *cmd, 482 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 483 { 484 struct amdgpu_device *adev = psp->adev; 485 uint32_t size = amdgpu_bo_size(tmr_bo); 486 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 487 488 if (amdgpu_sriov_vf(psp->adev)) 489 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 490 else 491 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 492 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 493 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 494 cmd->cmd.cmd_setup_tmr.buf_size = size; 495 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 496 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 497 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 498 } 499 500 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 501 uint64_t pri_buf_mc, uint32_t size) 502 { 503 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 504 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 505 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 506 cmd->cmd.cmd_load_toc.toc_size = size; 507 } 508 509 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 510 static int psp_load_toc(struct psp_context *psp, 511 uint32_t *tmr_size) 512 { 513 int ret; 514 struct psp_gfx_cmd_resp *cmd; 515 516 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 517 if (!cmd) 518 return -ENOMEM; 519 /* Copy toc to psp firmware private buffer */ 520 psp_copy_fw(psp, psp->toc_start_addr, psp->toc_bin_size); 521 522 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 523 524 ret = psp_cmd_submit_buf(psp, NULL, cmd, 525 psp->fence_buf_mc_addr); 526 if (!ret) 527 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 528 kfree(cmd); 529 return ret; 530 } 531 532 /* Set up Trusted Memory Region */ 533 static int psp_tmr_init(struct psp_context *psp) 534 { 535 int ret; 536 int tmr_size; 537 void *tmr_buf; 538 void **pptr; 539 540 /* 541 * According to HW engineer, they prefer the TMR address be "naturally 542 * aligned" , e.g. the start address be an integer divide of TMR size. 543 * 544 * Note: this memory need be reserved till the driver 545 * uninitializes. 546 */ 547 tmr_size = PSP_TMR_SIZE(psp->adev); 548 549 /* For ASICs support RLC autoload, psp will parse the toc 550 * and calculate the total size of TMR needed */ 551 if (!amdgpu_sriov_vf(psp->adev) && 552 psp->toc_start_addr && 553 psp->toc_bin_size && 554 psp->fw_pri_buf) { 555 ret = psp_load_toc(psp, &tmr_size); 556 if (ret) { 557 DRM_ERROR("Failed to load toc\n"); 558 return ret; 559 } 560 } 561 562 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 563 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 564 AMDGPU_GEM_DOMAIN_VRAM, 565 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 566 567 return ret; 568 } 569 570 static bool psp_skip_tmr(struct psp_context *psp) 571 { 572 switch (psp->adev->asic_type) { 573 case CHIP_NAVI12: 574 case CHIP_SIENNA_CICHLID: 575 case CHIP_ALDEBARAN: 576 return true; 577 default: 578 return false; 579 } 580 } 581 582 static int psp_tmr_load(struct psp_context *psp) 583 { 584 int ret; 585 struct psp_gfx_cmd_resp *cmd; 586 587 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 588 * Already set up by host driver. 589 */ 590 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 591 return 0; 592 593 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 594 if (!cmd) 595 return -ENOMEM; 596 597 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 598 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 599 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 600 601 ret = psp_cmd_submit_buf(psp, NULL, cmd, 602 psp->fence_buf_mc_addr); 603 604 kfree(cmd); 605 606 return ret; 607 } 608 609 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 610 struct psp_gfx_cmd_resp *cmd) 611 { 612 if (amdgpu_sriov_vf(psp->adev)) 613 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 614 else 615 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 616 } 617 618 static int psp_tmr_unload(struct psp_context *psp) 619 { 620 int ret; 621 struct psp_gfx_cmd_resp *cmd; 622 623 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 624 if (!cmd) 625 return -ENOMEM; 626 627 psp_prep_tmr_unload_cmd_buf(psp, cmd); 628 DRM_INFO("free PSP TMR buffer\n"); 629 630 ret = psp_cmd_submit_buf(psp, NULL, cmd, 631 psp->fence_buf_mc_addr); 632 633 kfree(cmd); 634 635 return ret; 636 } 637 638 static int psp_tmr_terminate(struct psp_context *psp) 639 { 640 int ret; 641 void *tmr_buf; 642 void **pptr; 643 644 ret = psp_tmr_unload(psp); 645 if (ret) 646 return ret; 647 648 /* free TMR memory buffer */ 649 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 650 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 651 652 return 0; 653 } 654 655 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 656 uint64_t *output_ptr) 657 { 658 int ret; 659 struct psp_gfx_cmd_resp *cmd; 660 661 if (!output_ptr) 662 return -EINVAL; 663 664 if (amdgpu_sriov_vf(psp->adev)) 665 return 0; 666 667 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 668 if (!cmd) 669 return -ENOMEM; 670 671 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 672 673 ret = psp_cmd_submit_buf(psp, NULL, cmd, 674 psp->fence_buf_mc_addr); 675 676 if (!ret) { 677 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 678 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 679 } 680 681 kfree(cmd); 682 683 return ret; 684 } 685 686 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 687 { 688 struct psp_context *psp = &adev->psp; 689 struct psp_gfx_cmd_resp *cmd = psp->cmd; 690 int ret; 691 692 if (amdgpu_sriov_vf(adev)) 693 return 0; 694 695 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 696 697 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 698 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 699 700 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 701 if (!ret) { 702 *boot_cfg = 703 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 704 } 705 706 return ret; 707 } 708 709 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 710 { 711 struct psp_context *psp = &adev->psp; 712 struct psp_gfx_cmd_resp *cmd = psp->cmd; 713 714 if (amdgpu_sriov_vf(adev)) 715 return 0; 716 717 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 718 719 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 720 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 721 cmd->cmd.boot_cfg.boot_config = boot_cfg; 722 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 723 724 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 725 } 726 727 static int psp_rl_load(struct amdgpu_device *adev) 728 { 729 struct psp_context *psp = &adev->psp; 730 struct psp_gfx_cmd_resp *cmd = psp->cmd; 731 732 if (psp->rl_bin_size == 0) 733 return 0; 734 735 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 736 memcpy(psp->fw_pri_buf, psp->rl_start_addr, psp->rl_bin_size); 737 738 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 739 740 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 741 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 742 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 743 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl_bin_size; 744 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 745 746 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 747 } 748 749 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 750 uint64_t asd_mc, uint32_t size) 751 { 752 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 753 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 754 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 755 cmd->cmd.cmd_load_ta.app_len = size; 756 757 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 758 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 759 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 760 } 761 762 static int psp_asd_load(struct psp_context *psp) 763 { 764 int ret; 765 struct psp_gfx_cmd_resp *cmd; 766 767 /* If PSP version doesn't match ASD version, asd loading will be failed. 768 * add workaround to bypass it for sriov now. 769 * TODO: add version check to make it common 770 */ 771 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size) 772 return 0; 773 774 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 775 if (!cmd) 776 return -ENOMEM; 777 778 psp_copy_fw(psp, psp->asd_start_addr, psp->asd_ucode_size); 779 780 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 781 psp->asd_ucode_size); 782 783 ret = psp_cmd_submit_buf(psp, NULL, cmd, 784 psp->fence_buf_mc_addr); 785 if (!ret) { 786 psp->asd_context.asd_initialized = true; 787 psp->asd_context.session_id = cmd->resp.session_id; 788 } 789 790 kfree(cmd); 791 792 return ret; 793 } 794 795 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 796 uint32_t session_id) 797 { 798 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 799 cmd->cmd.cmd_unload_ta.session_id = session_id; 800 } 801 802 static int psp_asd_unload(struct psp_context *psp) 803 { 804 int ret; 805 struct psp_gfx_cmd_resp *cmd; 806 807 if (amdgpu_sriov_vf(psp->adev)) 808 return 0; 809 810 if (!psp->asd_context.asd_initialized) 811 return 0; 812 813 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 814 if (!cmd) 815 return -ENOMEM; 816 817 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 818 819 ret = psp_cmd_submit_buf(psp, NULL, cmd, 820 psp->fence_buf_mc_addr); 821 if (!ret) 822 psp->asd_context.asd_initialized = false; 823 824 kfree(cmd); 825 826 return ret; 827 } 828 829 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 830 uint32_t id, uint32_t value) 831 { 832 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 833 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 834 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 835 } 836 837 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 838 uint32_t value) 839 { 840 struct psp_gfx_cmd_resp *cmd = NULL; 841 int ret = 0; 842 843 if (reg >= PSP_REG_LAST) 844 return -EINVAL; 845 846 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 847 if (!cmd) 848 return -ENOMEM; 849 850 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 851 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 852 if (ret) 853 DRM_ERROR("PSP failed to program reg id %d", reg); 854 855 kfree(cmd); 856 return ret; 857 } 858 859 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 860 uint64_t ta_bin_mc, 861 uint32_t ta_bin_size, 862 uint64_t ta_shared_mc, 863 uint32_t ta_shared_size) 864 { 865 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 866 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 867 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 868 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 869 870 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 871 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 872 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 873 } 874 875 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 876 { 877 int ret; 878 879 /* 880 * Allocate 16k memory aligned to 4k from Frame Buffer (local 881 * physical) for xgmi ta <-> Driver 882 */ 883 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 884 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 885 &psp->xgmi_context.xgmi_shared_bo, 886 &psp->xgmi_context.xgmi_shared_mc_addr, 887 &psp->xgmi_context.xgmi_shared_buf); 888 889 return ret; 890 } 891 892 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 893 uint32_t ta_cmd_id, 894 uint32_t session_id) 895 { 896 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 897 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 898 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 899 } 900 901 static int psp_ta_invoke(struct psp_context *psp, 902 uint32_t ta_cmd_id, 903 uint32_t session_id) 904 { 905 int ret; 906 struct psp_gfx_cmd_resp *cmd; 907 908 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 909 if (!cmd) 910 return -ENOMEM; 911 912 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 913 914 ret = psp_cmd_submit_buf(psp, NULL, cmd, 915 psp->fence_buf_mc_addr); 916 917 kfree(cmd); 918 919 return ret; 920 } 921 922 static int psp_xgmi_load(struct psp_context *psp) 923 { 924 int ret; 925 struct psp_gfx_cmd_resp *cmd; 926 927 /* 928 * TODO: bypass the loading in sriov for now 929 */ 930 931 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 932 if (!cmd) 933 return -ENOMEM; 934 935 psp_copy_fw(psp, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 936 937 psp_prep_ta_load_cmd_buf(cmd, 938 psp->fw_pri_mc_addr, 939 psp->ta_xgmi_ucode_size, 940 psp->xgmi_context.xgmi_shared_mc_addr, 941 PSP_XGMI_SHARED_MEM_SIZE); 942 943 ret = psp_cmd_submit_buf(psp, NULL, cmd, 944 psp->fence_buf_mc_addr); 945 946 if (!ret) { 947 psp->xgmi_context.initialized = 1; 948 psp->xgmi_context.session_id = cmd->resp.session_id; 949 } 950 951 kfree(cmd); 952 953 return ret; 954 } 955 956 static int psp_xgmi_unload(struct psp_context *psp) 957 { 958 int ret; 959 struct psp_gfx_cmd_resp *cmd; 960 struct amdgpu_device *adev = psp->adev; 961 962 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 963 if (adev->asic_type == CHIP_ARCTURUS || 964 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu)) 965 return 0; 966 967 /* 968 * TODO: bypass the unloading in sriov for now 969 */ 970 971 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 972 if (!cmd) 973 return -ENOMEM; 974 975 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 976 977 ret = psp_cmd_submit_buf(psp, NULL, cmd, 978 psp->fence_buf_mc_addr); 979 980 kfree(cmd); 981 982 return ret; 983 } 984 985 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 986 { 987 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 988 } 989 990 int psp_xgmi_terminate(struct psp_context *psp) 991 { 992 int ret; 993 994 if (!psp->xgmi_context.initialized) 995 return 0; 996 997 ret = psp_xgmi_unload(psp); 998 if (ret) 999 return ret; 1000 1001 psp->xgmi_context.initialized = 0; 1002 1003 /* free xgmi shared memory */ 1004 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 1005 &psp->xgmi_context.xgmi_shared_mc_addr, 1006 &psp->xgmi_context.xgmi_shared_buf); 1007 1008 return 0; 1009 } 1010 1011 int psp_xgmi_initialize(struct psp_context *psp) 1012 { 1013 struct ta_xgmi_shared_memory *xgmi_cmd; 1014 int ret; 1015 1016 if (!psp->adev->psp.ta_fw || 1017 !psp->adev->psp.ta_xgmi_ucode_size || 1018 !psp->adev->psp.ta_xgmi_start_addr) 1019 return -ENOENT; 1020 1021 if (!psp->xgmi_context.initialized) { 1022 ret = psp_xgmi_init_shared_buf(psp); 1023 if (ret) 1024 return ret; 1025 } 1026 1027 /* Load XGMI TA */ 1028 ret = psp_xgmi_load(psp); 1029 if (ret) 1030 return ret; 1031 1032 /* Initialize XGMI session */ 1033 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 1034 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1035 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1036 1037 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1038 1039 return ret; 1040 } 1041 1042 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1043 { 1044 struct ta_xgmi_shared_memory *xgmi_cmd; 1045 int ret; 1046 1047 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1048 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1049 1050 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1051 1052 /* Invoke xgmi ta to get hive id */ 1053 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1054 if (ret) 1055 return ret; 1056 1057 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1058 1059 return 0; 1060 } 1061 1062 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1063 { 1064 struct ta_xgmi_shared_memory *xgmi_cmd; 1065 int ret; 1066 1067 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1068 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1069 1070 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1071 1072 /* Invoke xgmi ta to get the node id */ 1073 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1074 if (ret) 1075 return ret; 1076 1077 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1078 1079 return 0; 1080 } 1081 1082 int psp_xgmi_get_topology_info(struct psp_context *psp, 1083 int number_devices, 1084 struct psp_xgmi_topology_info *topology) 1085 { 1086 struct ta_xgmi_shared_memory *xgmi_cmd; 1087 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1088 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1089 int i; 1090 int ret; 1091 1092 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1093 return -EINVAL; 1094 1095 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1096 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1097 1098 /* Fill in the shared memory with topology information as input */ 1099 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1100 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1101 topology_info_input->num_nodes = number_devices; 1102 1103 for (i = 0; i < topology_info_input->num_nodes; i++) { 1104 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1105 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1106 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1107 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1108 } 1109 1110 /* Invoke xgmi ta to get the topology information */ 1111 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1112 if (ret) 1113 return ret; 1114 1115 /* Read the output topology information from the shared memory */ 1116 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1117 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1118 for (i = 0; i < topology->num_nodes; i++) { 1119 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1120 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1121 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 1122 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 1123 } 1124 1125 return 0; 1126 } 1127 1128 int psp_xgmi_set_topology_info(struct psp_context *psp, 1129 int number_devices, 1130 struct psp_xgmi_topology_info *topology) 1131 { 1132 struct ta_xgmi_shared_memory *xgmi_cmd; 1133 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1134 int i; 1135 1136 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1137 return -EINVAL; 1138 1139 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1140 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1141 1142 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1143 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1144 topology_info_input->num_nodes = number_devices; 1145 1146 for (i = 0; i < topology_info_input->num_nodes; i++) { 1147 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1148 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1149 topology_info_input->nodes[i].is_sharing_enabled = 1; 1150 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1151 } 1152 1153 /* Invoke xgmi ta to set topology information */ 1154 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1155 } 1156 1157 // ras begin 1158 static int psp_ras_init_shared_buf(struct psp_context *psp) 1159 { 1160 int ret; 1161 1162 /* 1163 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1164 * physical) for ras ta <-> Driver 1165 */ 1166 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 1167 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1168 &psp->ras.ras_shared_bo, 1169 &psp->ras.ras_shared_mc_addr, 1170 &psp->ras.ras_shared_buf); 1171 1172 return ret; 1173 } 1174 1175 static int psp_ras_load(struct psp_context *psp) 1176 { 1177 int ret; 1178 struct psp_gfx_cmd_resp *cmd; 1179 struct ta_ras_shared_memory *ras_cmd; 1180 1181 /* 1182 * TODO: bypass the loading in sriov for now 1183 */ 1184 if (amdgpu_sriov_vf(psp->adev)) 1185 return 0; 1186 1187 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1188 if (!cmd) 1189 return -ENOMEM; 1190 1191 psp_copy_fw(psp, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 1192 1193 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1194 1195 if (psp->adev->gmc.xgmi.connected_to_cpu) 1196 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1197 else 1198 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1199 1200 psp_prep_ta_load_cmd_buf(cmd, 1201 psp->fw_pri_mc_addr, 1202 psp->ta_ras_ucode_size, 1203 psp->ras.ras_shared_mc_addr, 1204 PSP_RAS_SHARED_MEM_SIZE); 1205 1206 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1207 psp->fence_buf_mc_addr); 1208 1209 if (!ret) { 1210 psp->ras.session_id = cmd->resp.session_id; 1211 1212 if (!ras_cmd->ras_status) 1213 psp->ras.ras_initialized = true; 1214 else 1215 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1216 } 1217 1218 if (ret || ras_cmd->ras_status) 1219 amdgpu_ras_fini(psp->adev); 1220 1221 kfree(cmd); 1222 1223 return ret; 1224 } 1225 1226 static int psp_ras_unload(struct psp_context *psp) 1227 { 1228 int ret; 1229 struct psp_gfx_cmd_resp *cmd; 1230 1231 /* 1232 * TODO: bypass the unloading in sriov for now 1233 */ 1234 if (amdgpu_sriov_vf(psp->adev)) 1235 return 0; 1236 1237 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1238 if (!cmd) 1239 return -ENOMEM; 1240 1241 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 1242 1243 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1244 psp->fence_buf_mc_addr); 1245 1246 kfree(cmd); 1247 1248 return ret; 1249 } 1250 1251 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1252 { 1253 struct ta_ras_shared_memory *ras_cmd; 1254 int ret; 1255 1256 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1257 1258 /* 1259 * TODO: bypass the loading in sriov for now 1260 */ 1261 if (amdgpu_sriov_vf(psp->adev)) 1262 return 0; 1263 1264 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 1265 1266 if (amdgpu_ras_intr_triggered()) 1267 return ret; 1268 1269 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1270 { 1271 DRM_WARN("RAS: Unsupported Interface"); 1272 return -EINVAL; 1273 } 1274 1275 if (!ret) { 1276 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1277 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1278 1279 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1280 } 1281 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1282 dev_warn(psp->adev->dev, 1283 "RAS internal register access blocked\n"); 1284 } 1285 1286 return ret; 1287 } 1288 1289 static int psp_ras_status_to_errno(struct amdgpu_device *adev, 1290 enum ta_ras_status ras_status) 1291 { 1292 int ret = -EINVAL; 1293 1294 switch (ras_status) { 1295 case TA_RAS_STATUS__SUCCESS: 1296 ret = 0; 1297 break; 1298 case TA_RAS_STATUS__RESET_NEEDED: 1299 ret = -EAGAIN; 1300 break; 1301 case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: 1302 dev_warn(adev->dev, "RAS WARN: ras function unavailable\n"); 1303 break; 1304 case TA_RAS_STATUS__ERROR_ASD_READ_WRITE: 1305 dev_warn(adev->dev, "RAS WARN: asd read or write failed\n"); 1306 break; 1307 default: 1308 dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret); 1309 } 1310 1311 return ret; 1312 } 1313 1314 int psp_ras_enable_features(struct psp_context *psp, 1315 union ta_ras_cmd_input *info, bool enable) 1316 { 1317 struct ta_ras_shared_memory *ras_cmd; 1318 int ret; 1319 1320 if (!psp->ras.ras_initialized) 1321 return -EINVAL; 1322 1323 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1324 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1325 1326 if (enable) 1327 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1328 else 1329 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1330 1331 ras_cmd->ras_in_message = *info; 1332 1333 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1334 if (ret) 1335 return -EINVAL; 1336 1337 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1338 } 1339 1340 static int psp_ras_terminate(struct psp_context *psp) 1341 { 1342 int ret; 1343 1344 /* 1345 * TODO: bypass the terminate in sriov for now 1346 */ 1347 if (amdgpu_sriov_vf(psp->adev)) 1348 return 0; 1349 1350 if (!psp->ras.ras_initialized) 1351 return 0; 1352 1353 ret = psp_ras_unload(psp); 1354 if (ret) 1355 return ret; 1356 1357 psp->ras.ras_initialized = false; 1358 1359 /* free ras shared memory */ 1360 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1361 &psp->ras.ras_shared_mc_addr, 1362 &psp->ras.ras_shared_buf); 1363 1364 return 0; 1365 } 1366 1367 static int psp_ras_initialize(struct psp_context *psp) 1368 { 1369 int ret; 1370 uint32_t boot_cfg = 0xFF; 1371 struct amdgpu_device *adev = psp->adev; 1372 1373 /* 1374 * TODO: bypass the initialize in sriov for now 1375 */ 1376 if (amdgpu_sriov_vf(adev)) 1377 return 0; 1378 1379 if (!adev->psp.ta_ras_ucode_size || 1380 !adev->psp.ta_ras_start_addr) { 1381 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1382 return 0; 1383 } 1384 1385 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1386 /* query GECC enablement status from boot config 1387 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1388 */ 1389 ret = psp_boot_config_get(adev, &boot_cfg); 1390 if (ret) 1391 dev_warn(adev->dev, "PSP get boot config failed\n"); 1392 1393 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1394 if (!boot_cfg) { 1395 dev_info(adev->dev, "GECC is disabled\n"); 1396 } else { 1397 /* disable GECC in next boot cycle if ras is 1398 * disabled by module parameter amdgpu_ras_enable 1399 * and/or amdgpu_ras_mask, or boot_config_get call 1400 * is failed 1401 */ 1402 ret = psp_boot_config_set(adev, 0); 1403 if (ret) 1404 dev_warn(adev->dev, "PSP set boot config failed\n"); 1405 else 1406 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1407 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1408 } 1409 } else { 1410 if (1 == boot_cfg) { 1411 dev_info(adev->dev, "GECC is enabled\n"); 1412 } else { 1413 /* enable GECC in next boot cycle if it is disabled 1414 * in boot config, or force enable GECC if failed to 1415 * get boot configuration 1416 */ 1417 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1418 if (ret) 1419 dev_warn(adev->dev, "PSP set boot config failed\n"); 1420 else 1421 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1422 } 1423 } 1424 } 1425 1426 if (!psp->ras.ras_initialized) { 1427 ret = psp_ras_init_shared_buf(psp); 1428 if (ret) 1429 return ret; 1430 } 1431 1432 ret = psp_ras_load(psp); 1433 if (ret) 1434 return ret; 1435 1436 return 0; 1437 } 1438 1439 int psp_ras_trigger_error(struct psp_context *psp, 1440 struct ta_ras_trigger_error_input *info) 1441 { 1442 struct ta_ras_shared_memory *ras_cmd; 1443 int ret; 1444 1445 if (!psp->ras.ras_initialized) 1446 return -EINVAL; 1447 1448 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1449 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1450 1451 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1452 ras_cmd->ras_in_message.trigger_error = *info; 1453 1454 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1455 if (ret) 1456 return -EINVAL; 1457 1458 /* If err_event_athub occurs error inject was successful, however 1459 return status from TA is no long reliable */ 1460 if (amdgpu_ras_intr_triggered()) 1461 return 0; 1462 1463 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1464 } 1465 // ras end 1466 1467 // HDCP start 1468 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1469 { 1470 int ret; 1471 1472 /* 1473 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1474 * physical) for hdcp ta <-> Driver 1475 */ 1476 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1477 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1478 &psp->hdcp_context.hdcp_shared_bo, 1479 &psp->hdcp_context.hdcp_shared_mc_addr, 1480 &psp->hdcp_context.hdcp_shared_buf); 1481 1482 return ret; 1483 } 1484 1485 static int psp_hdcp_load(struct psp_context *psp) 1486 { 1487 int ret; 1488 struct psp_gfx_cmd_resp *cmd; 1489 1490 /* 1491 * TODO: bypass the loading in sriov for now 1492 */ 1493 if (amdgpu_sriov_vf(psp->adev)) 1494 return 0; 1495 1496 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1497 if (!cmd) 1498 return -ENOMEM; 1499 1500 psp_copy_fw(psp, psp->ta_hdcp_start_addr, 1501 psp->ta_hdcp_ucode_size); 1502 1503 psp_prep_ta_load_cmd_buf(cmd, 1504 psp->fw_pri_mc_addr, 1505 psp->ta_hdcp_ucode_size, 1506 psp->hdcp_context.hdcp_shared_mc_addr, 1507 PSP_HDCP_SHARED_MEM_SIZE); 1508 1509 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1510 1511 if (!ret) { 1512 psp->hdcp_context.hdcp_initialized = true; 1513 psp->hdcp_context.session_id = cmd->resp.session_id; 1514 mutex_init(&psp->hdcp_context.mutex); 1515 } 1516 1517 kfree(cmd); 1518 1519 return ret; 1520 } 1521 static int psp_hdcp_initialize(struct psp_context *psp) 1522 { 1523 int ret; 1524 1525 /* 1526 * TODO: bypass the initialize in sriov for now 1527 */ 1528 if (amdgpu_sriov_vf(psp->adev)) 1529 return 0; 1530 1531 if (!psp->adev->psp.ta_hdcp_ucode_size || 1532 !psp->adev->psp.ta_hdcp_start_addr) { 1533 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1534 return 0; 1535 } 1536 1537 if (!psp->hdcp_context.hdcp_initialized) { 1538 ret = psp_hdcp_init_shared_buf(psp); 1539 if (ret) 1540 return ret; 1541 } 1542 1543 ret = psp_hdcp_load(psp); 1544 if (ret) 1545 return ret; 1546 1547 return 0; 1548 } 1549 1550 static int psp_hdcp_unload(struct psp_context *psp) 1551 { 1552 int ret; 1553 struct psp_gfx_cmd_resp *cmd; 1554 1555 /* 1556 * TODO: bypass the unloading in sriov for now 1557 */ 1558 if (amdgpu_sriov_vf(psp->adev)) 1559 return 0; 1560 1561 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1562 if (!cmd) 1563 return -ENOMEM; 1564 1565 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1566 1567 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1568 1569 kfree(cmd); 1570 1571 return ret; 1572 } 1573 1574 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1575 { 1576 /* 1577 * TODO: bypass the loading in sriov for now 1578 */ 1579 if (amdgpu_sriov_vf(psp->adev)) 1580 return 0; 1581 1582 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1583 } 1584 1585 static int psp_hdcp_terminate(struct psp_context *psp) 1586 { 1587 int ret; 1588 1589 /* 1590 * TODO: bypass the terminate in sriov for now 1591 */ 1592 if (amdgpu_sriov_vf(psp->adev)) 1593 return 0; 1594 1595 if (!psp->hdcp_context.hdcp_initialized) { 1596 if (psp->hdcp_context.hdcp_shared_buf) 1597 goto out; 1598 else 1599 return 0; 1600 } 1601 1602 ret = psp_hdcp_unload(psp); 1603 if (ret) 1604 return ret; 1605 1606 psp->hdcp_context.hdcp_initialized = false; 1607 1608 out: 1609 /* free hdcp shared memory */ 1610 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1611 &psp->hdcp_context.hdcp_shared_mc_addr, 1612 &psp->hdcp_context.hdcp_shared_buf); 1613 1614 return 0; 1615 } 1616 // HDCP end 1617 1618 // DTM start 1619 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1620 { 1621 int ret; 1622 1623 /* 1624 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1625 * physical) for dtm ta <-> Driver 1626 */ 1627 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1628 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1629 &psp->dtm_context.dtm_shared_bo, 1630 &psp->dtm_context.dtm_shared_mc_addr, 1631 &psp->dtm_context.dtm_shared_buf); 1632 1633 return ret; 1634 } 1635 1636 static int psp_dtm_load(struct psp_context *psp) 1637 { 1638 int ret; 1639 struct psp_gfx_cmd_resp *cmd; 1640 1641 /* 1642 * TODO: bypass the loading in sriov for now 1643 */ 1644 if (amdgpu_sriov_vf(psp->adev)) 1645 return 0; 1646 1647 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1648 if (!cmd) 1649 return -ENOMEM; 1650 1651 psp_copy_fw(psp, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1652 1653 psp_prep_ta_load_cmd_buf(cmd, 1654 psp->fw_pri_mc_addr, 1655 psp->ta_dtm_ucode_size, 1656 psp->dtm_context.dtm_shared_mc_addr, 1657 PSP_DTM_SHARED_MEM_SIZE); 1658 1659 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1660 1661 if (!ret) { 1662 psp->dtm_context.dtm_initialized = true; 1663 psp->dtm_context.session_id = cmd->resp.session_id; 1664 mutex_init(&psp->dtm_context.mutex); 1665 } 1666 1667 kfree(cmd); 1668 1669 return ret; 1670 } 1671 1672 static int psp_dtm_initialize(struct psp_context *psp) 1673 { 1674 int ret; 1675 1676 /* 1677 * TODO: bypass the initialize in sriov for now 1678 */ 1679 if (amdgpu_sriov_vf(psp->adev)) 1680 return 0; 1681 1682 if (!psp->adev->psp.ta_dtm_ucode_size || 1683 !psp->adev->psp.ta_dtm_start_addr) { 1684 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1685 return 0; 1686 } 1687 1688 if (!psp->dtm_context.dtm_initialized) { 1689 ret = psp_dtm_init_shared_buf(psp); 1690 if (ret) 1691 return ret; 1692 } 1693 1694 ret = psp_dtm_load(psp); 1695 if (ret) 1696 return ret; 1697 1698 return 0; 1699 } 1700 1701 static int psp_dtm_unload(struct psp_context *psp) 1702 { 1703 int ret; 1704 struct psp_gfx_cmd_resp *cmd; 1705 1706 /* 1707 * TODO: bypass the unloading in sriov for now 1708 */ 1709 if (amdgpu_sriov_vf(psp->adev)) 1710 return 0; 1711 1712 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1713 if (!cmd) 1714 return -ENOMEM; 1715 1716 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1717 1718 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1719 1720 kfree(cmd); 1721 1722 return ret; 1723 } 1724 1725 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1726 { 1727 /* 1728 * TODO: bypass the loading in sriov for now 1729 */ 1730 if (amdgpu_sriov_vf(psp->adev)) 1731 return 0; 1732 1733 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1734 } 1735 1736 static int psp_dtm_terminate(struct psp_context *psp) 1737 { 1738 int ret; 1739 1740 /* 1741 * TODO: bypass the terminate in sriov for now 1742 */ 1743 if (amdgpu_sriov_vf(psp->adev)) 1744 return 0; 1745 1746 if (!psp->dtm_context.dtm_initialized) { 1747 if (psp->dtm_context.dtm_shared_buf) 1748 goto out; 1749 else 1750 return 0; 1751 } 1752 1753 ret = psp_dtm_unload(psp); 1754 if (ret) 1755 return ret; 1756 1757 psp->dtm_context.dtm_initialized = false; 1758 1759 out: 1760 /* free hdcp shared memory */ 1761 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1762 &psp->dtm_context.dtm_shared_mc_addr, 1763 &psp->dtm_context.dtm_shared_buf); 1764 1765 return 0; 1766 } 1767 // DTM end 1768 1769 // RAP start 1770 static int psp_rap_init_shared_buf(struct psp_context *psp) 1771 { 1772 int ret; 1773 1774 /* 1775 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1776 * physical) for rap ta <-> Driver 1777 */ 1778 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE, 1779 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1780 &psp->rap_context.rap_shared_bo, 1781 &psp->rap_context.rap_shared_mc_addr, 1782 &psp->rap_context.rap_shared_buf); 1783 1784 return ret; 1785 } 1786 1787 static int psp_rap_load(struct psp_context *psp) 1788 { 1789 int ret; 1790 struct psp_gfx_cmd_resp *cmd; 1791 1792 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1793 if (!cmd) 1794 return -ENOMEM; 1795 1796 psp_copy_fw(psp, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); 1797 1798 psp_prep_ta_load_cmd_buf(cmd, 1799 psp->fw_pri_mc_addr, 1800 psp->ta_rap_ucode_size, 1801 psp->rap_context.rap_shared_mc_addr, 1802 PSP_RAP_SHARED_MEM_SIZE); 1803 1804 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1805 1806 if (!ret) { 1807 psp->rap_context.rap_initialized = true; 1808 psp->rap_context.session_id = cmd->resp.session_id; 1809 mutex_init(&psp->rap_context.mutex); 1810 } 1811 1812 kfree(cmd); 1813 1814 return ret; 1815 } 1816 1817 static int psp_rap_unload(struct psp_context *psp) 1818 { 1819 int ret; 1820 struct psp_gfx_cmd_resp *cmd; 1821 1822 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1823 if (!cmd) 1824 return -ENOMEM; 1825 1826 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id); 1827 1828 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1829 1830 kfree(cmd); 1831 1832 return ret; 1833 } 1834 1835 static int psp_rap_initialize(struct psp_context *psp) 1836 { 1837 int ret; 1838 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1839 1840 /* 1841 * TODO: bypass the initialize in sriov for now 1842 */ 1843 if (amdgpu_sriov_vf(psp->adev)) 1844 return 0; 1845 1846 if (!psp->adev->psp.ta_rap_ucode_size || 1847 !psp->adev->psp.ta_rap_start_addr) { 1848 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1849 return 0; 1850 } 1851 1852 if (!psp->rap_context.rap_initialized) { 1853 ret = psp_rap_init_shared_buf(psp); 1854 if (ret) 1855 return ret; 1856 } 1857 1858 ret = psp_rap_load(psp); 1859 if (ret) 1860 return ret; 1861 1862 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1863 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1864 psp_rap_unload(psp); 1865 1866 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1867 &psp->rap_context.rap_shared_mc_addr, 1868 &psp->rap_context.rap_shared_buf); 1869 1870 psp->rap_context.rap_initialized = false; 1871 1872 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1873 ret, status); 1874 1875 return ret; 1876 } 1877 1878 return 0; 1879 } 1880 1881 static int psp_rap_terminate(struct psp_context *psp) 1882 { 1883 int ret; 1884 1885 if (!psp->rap_context.rap_initialized) 1886 return 0; 1887 1888 ret = psp_rap_unload(psp); 1889 1890 psp->rap_context.rap_initialized = false; 1891 1892 /* free rap shared memory */ 1893 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1894 &psp->rap_context.rap_shared_mc_addr, 1895 &psp->rap_context.rap_shared_buf); 1896 1897 return ret; 1898 } 1899 1900 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1901 { 1902 struct ta_rap_shared_memory *rap_cmd; 1903 int ret = 0; 1904 1905 if (!psp->rap_context.rap_initialized) 1906 return 0; 1907 1908 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1909 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1910 return -EINVAL; 1911 1912 mutex_lock(&psp->rap_context.mutex); 1913 1914 rap_cmd = (struct ta_rap_shared_memory *) 1915 psp->rap_context.rap_shared_buf; 1916 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1917 1918 rap_cmd->cmd_id = ta_cmd_id; 1919 rap_cmd->validation_method_id = METHOD_A; 1920 1921 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id); 1922 if (ret) 1923 goto out_unlock; 1924 1925 if (status) 1926 *status = rap_cmd->rap_status; 1927 1928 out_unlock: 1929 mutex_unlock(&psp->rap_context.mutex); 1930 1931 return ret; 1932 } 1933 // RAP end 1934 1935 /* securedisplay start */ 1936 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1937 { 1938 int ret; 1939 1940 /* 1941 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1942 * physical) for sa ta <-> Driver 1943 */ 1944 ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE, 1945 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1946 &psp->securedisplay_context.securedisplay_shared_bo, 1947 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1948 &psp->securedisplay_context.securedisplay_shared_buf); 1949 1950 return ret; 1951 } 1952 1953 static int psp_securedisplay_load(struct psp_context *psp) 1954 { 1955 int ret; 1956 struct psp_gfx_cmd_resp *cmd; 1957 1958 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1959 if (!cmd) 1960 return -ENOMEM; 1961 1962 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1963 memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size); 1964 1965 psp_prep_ta_load_cmd_buf(cmd, 1966 psp->fw_pri_mc_addr, 1967 psp->ta_securedisplay_ucode_size, 1968 psp->securedisplay_context.securedisplay_shared_mc_addr, 1969 PSP_SECUREDISPLAY_SHARED_MEM_SIZE); 1970 1971 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1972 1973 if (ret) 1974 goto failed; 1975 1976 psp->securedisplay_context.securedisplay_initialized = true; 1977 psp->securedisplay_context.session_id = cmd->resp.session_id; 1978 mutex_init(&psp->securedisplay_context.mutex); 1979 1980 failed: 1981 kfree(cmd); 1982 return ret; 1983 } 1984 1985 static int psp_securedisplay_unload(struct psp_context *psp) 1986 { 1987 int ret; 1988 struct psp_gfx_cmd_resp *cmd; 1989 1990 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1991 if (!cmd) 1992 return -ENOMEM; 1993 1994 psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id); 1995 1996 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1997 1998 kfree(cmd); 1999 2000 return ret; 2001 } 2002 2003 static int psp_securedisplay_initialize(struct psp_context *psp) 2004 { 2005 int ret; 2006 struct securedisplay_cmd *securedisplay_cmd; 2007 2008 /* 2009 * TODO: bypass the initialize in sriov for now 2010 */ 2011 if (amdgpu_sriov_vf(psp->adev)) 2012 return 0; 2013 2014 if (!psp->adev->psp.ta_securedisplay_ucode_size || 2015 !psp->adev->psp.ta_securedisplay_start_addr) { 2016 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 2017 return 0; 2018 } 2019 2020 if (!psp->securedisplay_context.securedisplay_initialized) { 2021 ret = psp_securedisplay_init_shared_buf(psp); 2022 if (ret) 2023 return ret; 2024 } 2025 2026 ret = psp_securedisplay_load(psp); 2027 if (ret) 2028 return ret; 2029 2030 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2031 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2032 2033 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2034 if (ret) { 2035 psp_securedisplay_unload(psp); 2036 2037 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 2038 &psp->securedisplay_context.securedisplay_shared_mc_addr, 2039 &psp->securedisplay_context.securedisplay_shared_buf); 2040 2041 psp->securedisplay_context.securedisplay_initialized = false; 2042 2043 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2044 return -EINVAL; 2045 } 2046 2047 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2048 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2049 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2050 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2051 } 2052 2053 return 0; 2054 } 2055 2056 static int psp_securedisplay_terminate(struct psp_context *psp) 2057 { 2058 int ret; 2059 2060 /* 2061 * TODO:bypass the terminate in sriov for now 2062 */ 2063 if (amdgpu_sriov_vf(psp->adev)) 2064 return 0; 2065 2066 if (!psp->securedisplay_context.securedisplay_initialized) 2067 return 0; 2068 2069 ret = psp_securedisplay_unload(psp); 2070 if (ret) 2071 return ret; 2072 2073 psp->securedisplay_context.securedisplay_initialized = false; 2074 2075 /* free securedisplay shared memory */ 2076 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 2077 &psp->securedisplay_context.securedisplay_shared_mc_addr, 2078 &psp->securedisplay_context.securedisplay_shared_buf); 2079 2080 return ret; 2081 } 2082 2083 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2084 { 2085 int ret; 2086 2087 if (!psp->securedisplay_context.securedisplay_initialized) 2088 return -EINVAL; 2089 2090 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2091 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2092 return -EINVAL; 2093 2094 mutex_lock(&psp->securedisplay_context.mutex); 2095 2096 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id); 2097 2098 mutex_unlock(&psp->securedisplay_context.mutex); 2099 2100 return ret; 2101 } 2102 /* SECUREDISPLAY end */ 2103 2104 static int psp_hw_start(struct psp_context *psp) 2105 { 2106 struct amdgpu_device *adev = psp->adev; 2107 int ret; 2108 2109 if (!amdgpu_sriov_vf(adev)) { 2110 if (psp->kdb_bin_size && 2111 (psp->funcs->bootloader_load_kdb != NULL)) { 2112 ret = psp_bootloader_load_kdb(psp); 2113 if (ret) { 2114 DRM_ERROR("PSP load kdb failed!\n"); 2115 return ret; 2116 } 2117 } 2118 2119 if (psp->spl_bin_size) { 2120 ret = psp_bootloader_load_spl(psp); 2121 if (ret) { 2122 DRM_ERROR("PSP load spl failed!\n"); 2123 return ret; 2124 } 2125 } 2126 2127 ret = psp_bootloader_load_sysdrv(psp); 2128 if (ret) { 2129 DRM_ERROR("PSP load sysdrv failed!\n"); 2130 return ret; 2131 } 2132 2133 ret = psp_bootloader_load_sos(psp); 2134 if (ret) { 2135 DRM_ERROR("PSP load sos failed!\n"); 2136 return ret; 2137 } 2138 } 2139 2140 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2141 if (ret) { 2142 DRM_ERROR("PSP create ring failed!\n"); 2143 return ret; 2144 } 2145 2146 ret = psp_tmr_init(psp); 2147 if (ret) { 2148 DRM_ERROR("PSP tmr init failed!\n"); 2149 return ret; 2150 } 2151 2152 /* 2153 * For ASICs with DF Cstate management centralized 2154 * to PMFW, TMR setup should be performed after PMFW 2155 * loaded and before other non-psp firmware loaded. 2156 */ 2157 if (psp->pmfw_centralized_cstate_management) { 2158 ret = psp_load_smu_fw(psp); 2159 if (ret) 2160 return ret; 2161 } 2162 2163 ret = psp_tmr_load(psp); 2164 if (ret) { 2165 DRM_ERROR("PSP load tmr failed!\n"); 2166 return ret; 2167 } 2168 2169 return 0; 2170 } 2171 2172 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2173 enum psp_gfx_fw_type *type) 2174 { 2175 switch (ucode->ucode_id) { 2176 case AMDGPU_UCODE_ID_SDMA0: 2177 *type = GFX_FW_TYPE_SDMA0; 2178 break; 2179 case AMDGPU_UCODE_ID_SDMA1: 2180 *type = GFX_FW_TYPE_SDMA1; 2181 break; 2182 case AMDGPU_UCODE_ID_SDMA2: 2183 *type = GFX_FW_TYPE_SDMA2; 2184 break; 2185 case AMDGPU_UCODE_ID_SDMA3: 2186 *type = GFX_FW_TYPE_SDMA3; 2187 break; 2188 case AMDGPU_UCODE_ID_SDMA4: 2189 *type = GFX_FW_TYPE_SDMA4; 2190 break; 2191 case AMDGPU_UCODE_ID_SDMA5: 2192 *type = GFX_FW_TYPE_SDMA5; 2193 break; 2194 case AMDGPU_UCODE_ID_SDMA6: 2195 *type = GFX_FW_TYPE_SDMA6; 2196 break; 2197 case AMDGPU_UCODE_ID_SDMA7: 2198 *type = GFX_FW_TYPE_SDMA7; 2199 break; 2200 case AMDGPU_UCODE_ID_CP_MES: 2201 *type = GFX_FW_TYPE_CP_MES; 2202 break; 2203 case AMDGPU_UCODE_ID_CP_MES_DATA: 2204 *type = GFX_FW_TYPE_MES_STACK; 2205 break; 2206 case AMDGPU_UCODE_ID_CP_CE: 2207 *type = GFX_FW_TYPE_CP_CE; 2208 break; 2209 case AMDGPU_UCODE_ID_CP_PFP: 2210 *type = GFX_FW_TYPE_CP_PFP; 2211 break; 2212 case AMDGPU_UCODE_ID_CP_ME: 2213 *type = GFX_FW_TYPE_CP_ME; 2214 break; 2215 case AMDGPU_UCODE_ID_CP_MEC1: 2216 *type = GFX_FW_TYPE_CP_MEC; 2217 break; 2218 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2219 *type = GFX_FW_TYPE_CP_MEC_ME1; 2220 break; 2221 case AMDGPU_UCODE_ID_CP_MEC2: 2222 *type = GFX_FW_TYPE_CP_MEC; 2223 break; 2224 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2225 *type = GFX_FW_TYPE_CP_MEC_ME2; 2226 break; 2227 case AMDGPU_UCODE_ID_RLC_G: 2228 *type = GFX_FW_TYPE_RLC_G; 2229 break; 2230 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2231 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2232 break; 2233 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2234 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2235 break; 2236 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2237 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2238 break; 2239 case AMDGPU_UCODE_ID_RLC_IRAM: 2240 *type = GFX_FW_TYPE_RLC_IRAM; 2241 break; 2242 case AMDGPU_UCODE_ID_RLC_DRAM: 2243 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2244 break; 2245 case AMDGPU_UCODE_ID_SMC: 2246 *type = GFX_FW_TYPE_SMU; 2247 break; 2248 case AMDGPU_UCODE_ID_UVD: 2249 *type = GFX_FW_TYPE_UVD; 2250 break; 2251 case AMDGPU_UCODE_ID_UVD1: 2252 *type = GFX_FW_TYPE_UVD1; 2253 break; 2254 case AMDGPU_UCODE_ID_VCE: 2255 *type = GFX_FW_TYPE_VCE; 2256 break; 2257 case AMDGPU_UCODE_ID_VCN: 2258 *type = GFX_FW_TYPE_VCN; 2259 break; 2260 case AMDGPU_UCODE_ID_VCN1: 2261 *type = GFX_FW_TYPE_VCN1; 2262 break; 2263 case AMDGPU_UCODE_ID_DMCU_ERAM: 2264 *type = GFX_FW_TYPE_DMCU_ERAM; 2265 break; 2266 case AMDGPU_UCODE_ID_DMCU_INTV: 2267 *type = GFX_FW_TYPE_DMCU_ISR; 2268 break; 2269 case AMDGPU_UCODE_ID_VCN0_RAM: 2270 *type = GFX_FW_TYPE_VCN0_RAM; 2271 break; 2272 case AMDGPU_UCODE_ID_VCN1_RAM: 2273 *type = GFX_FW_TYPE_VCN1_RAM; 2274 break; 2275 case AMDGPU_UCODE_ID_DMCUB: 2276 *type = GFX_FW_TYPE_DMUB; 2277 break; 2278 case AMDGPU_UCODE_ID_MAXIMUM: 2279 default: 2280 return -EINVAL; 2281 } 2282 2283 return 0; 2284 } 2285 2286 static void psp_print_fw_hdr(struct psp_context *psp, 2287 struct amdgpu_firmware_info *ucode) 2288 { 2289 struct amdgpu_device *adev = psp->adev; 2290 struct common_firmware_header *hdr; 2291 2292 switch (ucode->ucode_id) { 2293 case AMDGPU_UCODE_ID_SDMA0: 2294 case AMDGPU_UCODE_ID_SDMA1: 2295 case AMDGPU_UCODE_ID_SDMA2: 2296 case AMDGPU_UCODE_ID_SDMA3: 2297 case AMDGPU_UCODE_ID_SDMA4: 2298 case AMDGPU_UCODE_ID_SDMA5: 2299 case AMDGPU_UCODE_ID_SDMA6: 2300 case AMDGPU_UCODE_ID_SDMA7: 2301 hdr = (struct common_firmware_header *) 2302 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2303 amdgpu_ucode_print_sdma_hdr(hdr); 2304 break; 2305 case AMDGPU_UCODE_ID_CP_CE: 2306 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2307 amdgpu_ucode_print_gfx_hdr(hdr); 2308 break; 2309 case AMDGPU_UCODE_ID_CP_PFP: 2310 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2311 amdgpu_ucode_print_gfx_hdr(hdr); 2312 break; 2313 case AMDGPU_UCODE_ID_CP_ME: 2314 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2315 amdgpu_ucode_print_gfx_hdr(hdr); 2316 break; 2317 case AMDGPU_UCODE_ID_CP_MEC1: 2318 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2319 amdgpu_ucode_print_gfx_hdr(hdr); 2320 break; 2321 case AMDGPU_UCODE_ID_RLC_G: 2322 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2323 amdgpu_ucode_print_rlc_hdr(hdr); 2324 break; 2325 case AMDGPU_UCODE_ID_SMC: 2326 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2327 amdgpu_ucode_print_smc_hdr(hdr); 2328 break; 2329 default: 2330 break; 2331 } 2332 } 2333 2334 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2335 struct psp_gfx_cmd_resp *cmd) 2336 { 2337 int ret; 2338 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2339 2340 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 2341 2342 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2343 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2344 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2345 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2346 2347 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2348 if (ret) 2349 DRM_ERROR("Unknown firmware type\n"); 2350 2351 return ret; 2352 } 2353 2354 static int psp_execute_np_fw_load(struct psp_context *psp, 2355 struct amdgpu_firmware_info *ucode) 2356 { 2357 int ret = 0; 2358 2359 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 2360 if (ret) 2361 return ret; 2362 2363 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 2364 psp->fence_buf_mc_addr); 2365 2366 return ret; 2367 } 2368 2369 static int psp_load_smu_fw(struct psp_context *psp) 2370 { 2371 int ret; 2372 struct amdgpu_device *adev = psp->adev; 2373 struct amdgpu_firmware_info *ucode = 2374 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2375 struct amdgpu_ras *ras = psp->ras.ras; 2376 2377 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2378 return 0; 2379 2380 if ((amdgpu_in_reset(adev) && 2381 ras && adev->ras_enabled && 2382 (adev->asic_type == CHIP_ARCTURUS || 2383 adev->asic_type == CHIP_VEGA20))) { 2384 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2385 if (ret) { 2386 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2387 } 2388 } 2389 2390 ret = psp_execute_np_fw_load(psp, ucode); 2391 2392 if (ret) 2393 DRM_ERROR("PSP load smu failed!\n"); 2394 2395 return ret; 2396 } 2397 2398 static bool fw_load_skip_check(struct psp_context *psp, 2399 struct amdgpu_firmware_info *ucode) 2400 { 2401 if (!ucode->fw) 2402 return true; 2403 2404 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2405 (psp_smu_reload_quirk(psp) || 2406 psp->autoload_supported || 2407 psp->pmfw_centralized_cstate_management)) 2408 return true; 2409 2410 if (amdgpu_sriov_vf(psp->adev) && 2411 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2412 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2413 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2414 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2415 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2416 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2417 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2418 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2419 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2420 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2421 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2422 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2423 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2424 /*skip ucode loading in SRIOV VF */ 2425 return true; 2426 2427 if (psp->autoload_supported && 2428 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2429 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2430 /* skip mec JT when autoload is enabled */ 2431 return true; 2432 2433 return false; 2434 } 2435 2436 int psp_load_fw_list(struct psp_context *psp, 2437 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2438 { 2439 int ret = 0, i; 2440 struct amdgpu_firmware_info *ucode; 2441 2442 for (i = 0; i < ucode_count; ++i) { 2443 ucode = ucode_list[i]; 2444 psp_print_fw_hdr(psp, ucode); 2445 ret = psp_execute_np_fw_load(psp, ucode); 2446 if (ret) 2447 return ret; 2448 } 2449 return ret; 2450 } 2451 2452 static int psp_np_fw_load(struct psp_context *psp) 2453 { 2454 int i, ret; 2455 struct amdgpu_firmware_info *ucode; 2456 struct amdgpu_device *adev = psp->adev; 2457 2458 if (psp->autoload_supported && 2459 !psp->pmfw_centralized_cstate_management) { 2460 ret = psp_load_smu_fw(psp); 2461 if (ret) 2462 return ret; 2463 } 2464 2465 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2466 ucode = &adev->firmware.ucode[i]; 2467 2468 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2469 !fw_load_skip_check(psp, ucode)) { 2470 ret = psp_load_smu_fw(psp); 2471 if (ret) 2472 return ret; 2473 continue; 2474 } 2475 2476 if (fw_load_skip_check(psp, ucode)) 2477 continue; 2478 2479 if (psp->autoload_supported && 2480 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2481 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2482 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2483 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2484 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2485 /* PSP only receive one SDMA fw for sienna_cichlid, 2486 * as all four sdma fw are same */ 2487 continue; 2488 2489 psp_print_fw_hdr(psp, ucode); 2490 2491 ret = psp_execute_np_fw_load(psp, ucode); 2492 if (ret) 2493 return ret; 2494 2495 /* Start rlc autoload after psp recieved all the gfx firmware */ 2496 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2497 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2498 ret = psp_rlc_autoload_start(psp); 2499 if (ret) { 2500 DRM_ERROR("Failed to start rlc autoload\n"); 2501 return ret; 2502 } 2503 } 2504 } 2505 2506 return 0; 2507 } 2508 2509 static int psp_load_fw(struct amdgpu_device *adev) 2510 { 2511 int ret; 2512 struct psp_context *psp = &adev->psp; 2513 2514 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2515 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2516 goto skip_memalloc; 2517 } 2518 2519 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2520 if (!psp->cmd) 2521 return -ENOMEM; 2522 2523 if (amdgpu_sriov_vf(adev)) { 2524 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2525 AMDGPU_GEM_DOMAIN_VRAM, 2526 &psp->fw_pri_bo, 2527 &psp->fw_pri_mc_addr, 2528 &psp->fw_pri_buf); 2529 } else { 2530 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2531 AMDGPU_GEM_DOMAIN_GTT, 2532 &psp->fw_pri_bo, 2533 &psp->fw_pri_mc_addr, 2534 &psp->fw_pri_buf); 2535 } 2536 2537 if (ret) 2538 goto failed; 2539 2540 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2541 AMDGPU_GEM_DOMAIN_VRAM, 2542 &psp->fence_buf_bo, 2543 &psp->fence_buf_mc_addr, 2544 &psp->fence_buf); 2545 if (ret) 2546 goto failed; 2547 2548 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2549 AMDGPU_GEM_DOMAIN_VRAM, 2550 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2551 (void **)&psp->cmd_buf_mem); 2552 if (ret) 2553 goto failed; 2554 2555 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2556 2557 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2558 if (ret) { 2559 DRM_ERROR("PSP ring init failed!\n"); 2560 goto failed; 2561 } 2562 2563 skip_memalloc: 2564 ret = psp_hw_start(psp); 2565 if (ret) 2566 goto failed; 2567 2568 ret = psp_np_fw_load(psp); 2569 if (ret) 2570 goto failed; 2571 2572 ret = psp_asd_load(psp); 2573 if (ret) { 2574 DRM_ERROR("PSP load asd failed!\n"); 2575 return ret; 2576 } 2577 2578 ret = psp_rl_load(adev); 2579 if (ret) { 2580 DRM_ERROR("PSP load RL failed!\n"); 2581 return ret; 2582 } 2583 2584 if (psp->adev->psp.ta_fw) { 2585 ret = psp_ras_initialize(psp); 2586 if (ret) 2587 dev_err(psp->adev->dev, 2588 "RAS: Failed to initialize RAS\n"); 2589 2590 ret = psp_hdcp_initialize(psp); 2591 if (ret) 2592 dev_err(psp->adev->dev, 2593 "HDCP: Failed to initialize HDCP\n"); 2594 2595 ret = psp_dtm_initialize(psp); 2596 if (ret) 2597 dev_err(psp->adev->dev, 2598 "DTM: Failed to initialize DTM\n"); 2599 2600 ret = psp_rap_initialize(psp); 2601 if (ret) 2602 dev_err(psp->adev->dev, 2603 "RAP: Failed to initialize RAP\n"); 2604 2605 ret = psp_securedisplay_initialize(psp); 2606 if (ret) 2607 dev_err(psp->adev->dev, 2608 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2609 } 2610 2611 return 0; 2612 2613 failed: 2614 /* 2615 * all cleanup jobs (xgmi terminate, ras terminate, 2616 * ring destroy, cmd/fence/fw buffers destory, 2617 * psp->cmd destory) are delayed to psp_hw_fini 2618 */ 2619 return ret; 2620 } 2621 2622 static int psp_hw_init(void *handle) 2623 { 2624 int ret; 2625 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2626 2627 mutex_lock(&adev->firmware.mutex); 2628 /* 2629 * This sequence is just used on hw_init only once, no need on 2630 * resume. 2631 */ 2632 ret = amdgpu_ucode_init_bo(adev); 2633 if (ret) 2634 goto failed; 2635 2636 ret = psp_load_fw(adev); 2637 if (ret) { 2638 DRM_ERROR("PSP firmware loading failed\n"); 2639 goto failed; 2640 } 2641 2642 mutex_unlock(&adev->firmware.mutex); 2643 return 0; 2644 2645 failed: 2646 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2647 mutex_unlock(&adev->firmware.mutex); 2648 return -EINVAL; 2649 } 2650 2651 static int psp_hw_fini(void *handle) 2652 { 2653 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2654 struct psp_context *psp = &adev->psp; 2655 2656 if (psp->adev->psp.ta_fw) { 2657 psp_ras_terminate(psp); 2658 psp_securedisplay_terminate(psp); 2659 psp_rap_terminate(psp); 2660 psp_dtm_terminate(psp); 2661 psp_hdcp_terminate(psp); 2662 } 2663 2664 psp_asd_unload(psp); 2665 2666 psp_tmr_terminate(psp); 2667 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2668 2669 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2670 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2671 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2672 &psp->fence_buf_mc_addr, &psp->fence_buf); 2673 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2674 (void **)&psp->cmd_buf_mem); 2675 2676 kfree(psp->cmd); 2677 psp->cmd = NULL; 2678 2679 return 0; 2680 } 2681 2682 static int psp_suspend(void *handle) 2683 { 2684 int ret; 2685 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2686 struct psp_context *psp = &adev->psp; 2687 2688 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2689 psp->xgmi_context.initialized == 1) { 2690 ret = psp_xgmi_terminate(psp); 2691 if (ret) { 2692 DRM_ERROR("Failed to terminate xgmi ta\n"); 2693 return ret; 2694 } 2695 } 2696 2697 if (psp->adev->psp.ta_fw) { 2698 ret = psp_ras_terminate(psp); 2699 if (ret) { 2700 DRM_ERROR("Failed to terminate ras ta\n"); 2701 return ret; 2702 } 2703 ret = psp_hdcp_terminate(psp); 2704 if (ret) { 2705 DRM_ERROR("Failed to terminate hdcp ta\n"); 2706 return ret; 2707 } 2708 ret = psp_dtm_terminate(psp); 2709 if (ret) { 2710 DRM_ERROR("Failed to terminate dtm ta\n"); 2711 return ret; 2712 } 2713 ret = psp_rap_terminate(psp); 2714 if (ret) { 2715 DRM_ERROR("Failed to terminate rap ta\n"); 2716 return ret; 2717 } 2718 ret = psp_securedisplay_terminate(psp); 2719 if (ret) { 2720 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2721 return ret; 2722 } 2723 } 2724 2725 ret = psp_asd_unload(psp); 2726 if (ret) { 2727 DRM_ERROR("Failed to unload asd\n"); 2728 return ret; 2729 } 2730 2731 ret = psp_tmr_terminate(psp); 2732 if (ret) { 2733 DRM_ERROR("Failed to terminate tmr\n"); 2734 return ret; 2735 } 2736 2737 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2738 if (ret) { 2739 DRM_ERROR("PSP ring stop failed\n"); 2740 return ret; 2741 } 2742 2743 return 0; 2744 } 2745 2746 static int psp_resume(void *handle) 2747 { 2748 int ret; 2749 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2750 struct psp_context *psp = &adev->psp; 2751 2752 DRM_INFO("PSP is resuming...\n"); 2753 2754 if (psp->mem_train_ctx.enable_mem_training) { 2755 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2756 if (ret) { 2757 DRM_ERROR("Failed to process memory training!\n"); 2758 return ret; 2759 } 2760 } 2761 2762 mutex_lock(&adev->firmware.mutex); 2763 2764 ret = psp_hw_start(psp); 2765 if (ret) 2766 goto failed; 2767 2768 ret = psp_np_fw_load(psp); 2769 if (ret) 2770 goto failed; 2771 2772 ret = psp_asd_load(psp); 2773 if (ret) { 2774 DRM_ERROR("PSP load asd failed!\n"); 2775 goto failed; 2776 } 2777 2778 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2779 ret = psp_xgmi_initialize(psp); 2780 /* Warning the XGMI seesion initialize failure 2781 * Instead of stop driver initialization 2782 */ 2783 if (ret) 2784 dev_err(psp->adev->dev, 2785 "XGMI: Failed to initialize XGMI session\n"); 2786 } 2787 2788 if (psp->adev->psp.ta_fw) { 2789 ret = psp_ras_initialize(psp); 2790 if (ret) 2791 dev_err(psp->adev->dev, 2792 "RAS: Failed to initialize RAS\n"); 2793 2794 ret = psp_hdcp_initialize(psp); 2795 if (ret) 2796 dev_err(psp->adev->dev, 2797 "HDCP: Failed to initialize HDCP\n"); 2798 2799 ret = psp_dtm_initialize(psp); 2800 if (ret) 2801 dev_err(psp->adev->dev, 2802 "DTM: Failed to initialize DTM\n"); 2803 2804 ret = psp_rap_initialize(psp); 2805 if (ret) 2806 dev_err(psp->adev->dev, 2807 "RAP: Failed to initialize RAP\n"); 2808 2809 ret = psp_securedisplay_initialize(psp); 2810 if (ret) 2811 dev_err(psp->adev->dev, 2812 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2813 } 2814 2815 mutex_unlock(&adev->firmware.mutex); 2816 2817 return 0; 2818 2819 failed: 2820 DRM_ERROR("PSP resume failed\n"); 2821 mutex_unlock(&adev->firmware.mutex); 2822 return ret; 2823 } 2824 2825 int psp_gpu_reset(struct amdgpu_device *adev) 2826 { 2827 int ret; 2828 2829 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2830 return 0; 2831 2832 mutex_lock(&adev->psp.mutex); 2833 ret = psp_mode1_reset(&adev->psp); 2834 mutex_unlock(&adev->psp.mutex); 2835 2836 return ret; 2837 } 2838 2839 int psp_rlc_autoload_start(struct psp_context *psp) 2840 { 2841 int ret; 2842 struct psp_gfx_cmd_resp *cmd; 2843 2844 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2845 if (!cmd) 2846 return -ENOMEM; 2847 2848 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2849 2850 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2851 psp->fence_buf_mc_addr); 2852 kfree(cmd); 2853 return ret; 2854 } 2855 2856 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2857 uint64_t cmd_gpu_addr, int cmd_size) 2858 { 2859 struct amdgpu_firmware_info ucode = {0}; 2860 2861 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2862 AMDGPU_UCODE_ID_VCN0_RAM; 2863 ucode.mc_addr = cmd_gpu_addr; 2864 ucode.ucode_size = cmd_size; 2865 2866 return psp_execute_np_fw_load(&adev->psp, &ucode); 2867 } 2868 2869 int psp_ring_cmd_submit(struct psp_context *psp, 2870 uint64_t cmd_buf_mc_addr, 2871 uint64_t fence_mc_addr, 2872 int index) 2873 { 2874 unsigned int psp_write_ptr_reg = 0; 2875 struct psp_gfx_rb_frame *write_frame; 2876 struct psp_ring *ring = &psp->km_ring; 2877 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2878 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2879 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2880 struct amdgpu_device *adev = psp->adev; 2881 uint32_t ring_size_dw = ring->ring_size / 4; 2882 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2883 2884 /* KM (GPCOM) prepare write pointer */ 2885 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2886 2887 /* Update KM RB frame pointer to new frame */ 2888 /* write_frame ptr increments by size of rb_frame in bytes */ 2889 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2890 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2891 write_frame = ring_buffer_start; 2892 else 2893 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2894 /* Check invalid write_frame ptr address */ 2895 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2896 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2897 ring_buffer_start, ring_buffer_end, write_frame); 2898 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2899 return -EINVAL; 2900 } 2901 2902 /* Initialize KM RB frame */ 2903 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2904 2905 /* Update KM RB frame */ 2906 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2907 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2908 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2909 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2910 write_frame->fence_value = index; 2911 amdgpu_device_flush_hdp(adev, NULL); 2912 2913 /* Update the write Pointer in DWORDs */ 2914 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2915 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2916 return 0; 2917 } 2918 2919 int psp_init_asd_microcode(struct psp_context *psp, 2920 const char *chip_name) 2921 { 2922 struct amdgpu_device *adev = psp->adev; 2923 char fw_name[PSP_FW_NAME_LEN]; 2924 const struct psp_firmware_header_v1_0 *asd_hdr; 2925 int err = 0; 2926 2927 if (!chip_name) { 2928 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2929 return -EINVAL; 2930 } 2931 2932 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2933 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2934 if (err) 2935 goto out; 2936 2937 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2938 if (err) 2939 goto out; 2940 2941 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2942 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2943 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2944 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2945 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2946 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2947 return 0; 2948 out: 2949 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2950 release_firmware(adev->psp.asd_fw); 2951 adev->psp.asd_fw = NULL; 2952 return err; 2953 } 2954 2955 int psp_init_toc_microcode(struct psp_context *psp, 2956 const char *chip_name) 2957 { 2958 struct amdgpu_device *adev = psp->adev; 2959 char fw_name[30]; 2960 const struct psp_firmware_header_v1_0 *toc_hdr; 2961 int err = 0; 2962 2963 if (!chip_name) { 2964 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2965 return -EINVAL; 2966 } 2967 2968 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2969 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2970 if (err) 2971 goto out; 2972 2973 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2974 if (err) 2975 goto out; 2976 2977 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2978 adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2979 adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2980 adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2981 adev->psp.toc_start_addr = (uint8_t *)toc_hdr + 2982 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2983 return 0; 2984 out: 2985 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2986 release_firmware(adev->psp.toc_fw); 2987 adev->psp.toc_fw = NULL; 2988 return err; 2989 } 2990 2991 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 2992 { 2993 const struct psp_firmware_header_v1_0 *sos_hdr; 2994 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2995 uint8_t *ucode_array_start_addr; 2996 2997 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2998 ucode_array_start_addr = (uint8_t *)sos_hdr + 2999 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3000 3001 if (adev->gmc.xgmi.connected_to_cpu || (adev->asic_type != CHIP_ALDEBARAN)) { 3002 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3003 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3004 3005 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos.offset_bytes); 3006 adev->psp.sys_start_addr = ucode_array_start_addr; 3007 3008 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos.size_bytes); 3009 adev->psp.sos_start_addr = ucode_array_start_addr + 3010 le32_to_cpu(sos_hdr->sos.offset_bytes); 3011 } else { 3012 /* Load alternate PSP SOS FW */ 3013 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3014 3015 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3016 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3017 3018 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3019 adev->psp.sys_start_addr = ucode_array_start_addr + 3020 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3021 3022 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3023 adev->psp.sos_start_addr = ucode_array_start_addr + 3024 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3025 } 3026 3027 if ((adev->psp.sys_bin_size == 0) || (adev->psp.sos_bin_size == 0)) { 3028 dev_warn(adev->dev, "PSP SOS FW not available"); 3029 return -EINVAL; 3030 } 3031 3032 return 0; 3033 } 3034 3035 int psp_init_sos_microcode(struct psp_context *psp, 3036 const char *chip_name) 3037 { 3038 struct amdgpu_device *adev = psp->adev; 3039 char fw_name[PSP_FW_NAME_LEN]; 3040 const struct psp_firmware_header_v1_0 *sos_hdr; 3041 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3042 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3043 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3044 int err = 0; 3045 uint8_t *ucode_array_start_addr; 3046 3047 if (!chip_name) { 3048 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3049 return -EINVAL; 3050 } 3051 3052 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3053 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3054 if (err) 3055 goto out; 3056 3057 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3058 if (err) 3059 goto out; 3060 3061 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3062 ucode_array_start_addr = (uint8_t *)sos_hdr + 3063 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3064 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3065 3066 switch (sos_hdr->header.header_version_major) { 3067 case 1: 3068 err = psp_init_sos_base_fw(adev); 3069 if (err) 3070 goto out; 3071 3072 if (sos_hdr->header.header_version_minor == 1) { 3073 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3074 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3075 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 3076 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3077 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3078 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 3079 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3080 } 3081 if (sos_hdr->header.header_version_minor == 2) { 3082 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3083 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3084 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 3085 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3086 } 3087 if (sos_hdr->header.header_version_minor == 3) { 3088 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3089 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3090 adev->psp.toc_start_addr = ucode_array_start_addr + 3091 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3092 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3093 adev->psp.kdb_start_addr = ucode_array_start_addr + 3094 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3095 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3096 adev->psp.spl_start_addr = ucode_array_start_addr + 3097 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3098 adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3099 adev->psp.rl_start_addr = ucode_array_start_addr + 3100 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3101 } 3102 break; 3103 default: 3104 dev_err(adev->dev, 3105 "unsupported psp sos firmware\n"); 3106 err = -EINVAL; 3107 goto out; 3108 } 3109 3110 return 0; 3111 out: 3112 dev_err(adev->dev, 3113 "failed to init sos firmware\n"); 3114 release_firmware(adev->psp.sos_fw); 3115 adev->psp.sos_fw = NULL; 3116 3117 return err; 3118 } 3119 3120 static int parse_ta_bin_descriptor(struct psp_context *psp, 3121 const struct ta_fw_bin_desc *desc, 3122 const struct ta_firmware_header_v2_0 *ta_hdr) 3123 { 3124 uint8_t *ucode_start_addr = NULL; 3125 3126 if (!psp || !desc || !ta_hdr) 3127 return -EINVAL; 3128 3129 ucode_start_addr = (uint8_t *)ta_hdr + 3130 le32_to_cpu(desc->offset_bytes) + 3131 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3132 3133 switch (desc->fw_type) { 3134 case TA_FW_TYPE_PSP_ASD: 3135 psp->asd_fw_version = le32_to_cpu(desc->fw_version); 3136 psp->asd_feature_version = le32_to_cpu(desc->fw_version); 3137 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 3138 psp->asd_start_addr = ucode_start_addr; 3139 break; 3140 case TA_FW_TYPE_PSP_XGMI: 3141 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 3142 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 3143 psp->ta_xgmi_start_addr = ucode_start_addr; 3144 break; 3145 case TA_FW_TYPE_PSP_RAS: 3146 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 3147 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 3148 psp->ta_ras_start_addr = ucode_start_addr; 3149 break; 3150 case TA_FW_TYPE_PSP_HDCP: 3151 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 3152 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 3153 psp->ta_hdcp_start_addr = ucode_start_addr; 3154 break; 3155 case TA_FW_TYPE_PSP_DTM: 3156 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 3157 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 3158 psp->ta_dtm_start_addr = ucode_start_addr; 3159 break; 3160 case TA_FW_TYPE_PSP_RAP: 3161 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version); 3162 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes); 3163 psp->ta_rap_start_addr = ucode_start_addr; 3164 break; 3165 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3166 psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version); 3167 psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes); 3168 psp->ta_securedisplay_start_addr = ucode_start_addr; 3169 break; 3170 default: 3171 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3172 break; 3173 } 3174 3175 return 0; 3176 } 3177 3178 int psp_init_ta_microcode(struct psp_context *psp, 3179 const char *chip_name) 3180 { 3181 struct amdgpu_device *adev = psp->adev; 3182 char fw_name[PSP_FW_NAME_LEN]; 3183 const struct ta_firmware_header_v2_0 *ta_hdr; 3184 int err = 0; 3185 int ta_index = 0; 3186 3187 if (!chip_name) { 3188 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3189 return -EINVAL; 3190 } 3191 3192 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3193 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3194 if (err) 3195 goto out; 3196 3197 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3198 if (err) 3199 goto out; 3200 3201 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3202 3203 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3204 dev_err(adev->dev, "unsupported TA header version\n"); 3205 err = -EINVAL; 3206 goto out; 3207 } 3208 3209 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) { 3210 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3211 err = -EINVAL; 3212 goto out; 3213 } 3214 3215 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3216 err = parse_ta_bin_descriptor(psp, 3217 &ta_hdr->ta_fw_bin[ta_index], 3218 ta_hdr); 3219 if (err) 3220 goto out; 3221 } 3222 3223 return 0; 3224 out: 3225 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3226 release_firmware(adev->psp.ta_fw); 3227 adev->psp.ta_fw = NULL; 3228 return err; 3229 } 3230 3231 static int psp_set_clockgating_state(void *handle, 3232 enum amd_clockgating_state state) 3233 { 3234 return 0; 3235 } 3236 3237 static int psp_set_powergating_state(void *handle, 3238 enum amd_powergating_state state) 3239 { 3240 return 0; 3241 } 3242 3243 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3244 struct device_attribute *attr, 3245 char *buf) 3246 { 3247 struct drm_device *ddev = dev_get_drvdata(dev); 3248 struct amdgpu_device *adev = drm_to_adev(ddev); 3249 uint32_t fw_ver; 3250 int ret; 3251 3252 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3253 DRM_INFO("PSP block is not ready yet."); 3254 return -EBUSY; 3255 } 3256 3257 mutex_lock(&adev->psp.mutex); 3258 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3259 mutex_unlock(&adev->psp.mutex); 3260 3261 if (ret) { 3262 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3263 return ret; 3264 } 3265 3266 return sysfs_emit(buf, "%x\n", fw_ver); 3267 } 3268 3269 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3270 struct device_attribute *attr, 3271 const char *buf, 3272 size_t count) 3273 { 3274 struct drm_device *ddev = dev_get_drvdata(dev); 3275 struct amdgpu_device *adev = drm_to_adev(ddev); 3276 void *cpu_addr; 3277 dma_addr_t dma_addr; 3278 int ret, idx; 3279 char fw_name[100]; 3280 const struct firmware *usbc_pd_fw; 3281 3282 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3283 DRM_INFO("PSP block is not ready yet."); 3284 return -EBUSY; 3285 } 3286 3287 if (!drm_dev_enter(ddev, &idx)) 3288 return -ENODEV; 3289 3290 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3291 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3292 if (ret) 3293 goto fail; 3294 3295 /* We need contiguous physical mem to place the FW for psp to access */ 3296 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL); 3297 3298 ret = dma_mapping_error(adev->dev, dma_addr); 3299 if (ret) 3300 goto rel_buf; 3301 3302 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3303 3304 /* 3305 * x86 specific workaround. 3306 * Without it the buffer is invisible in PSP. 3307 * 3308 * TODO Remove once PSP starts snooping CPU cache 3309 */ 3310 #ifdef CONFIG_X86 3311 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1))); 3312 #endif 3313 3314 mutex_lock(&adev->psp.mutex); 3315 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr); 3316 mutex_unlock(&adev->psp.mutex); 3317 3318 rel_buf: 3319 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr); 3320 release_firmware(usbc_pd_fw); 3321 fail: 3322 if (ret) { 3323 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3324 count = ret; 3325 } 3326 3327 drm_dev_exit(idx); 3328 return count; 3329 } 3330 3331 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3332 { 3333 int idx; 3334 3335 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 3336 return; 3337 3338 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3339 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3340 3341 drm_dev_exit(idx); 3342 } 3343 3344 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3345 psp_usbc_pd_fw_sysfs_read, 3346 psp_usbc_pd_fw_sysfs_write); 3347 3348 3349 3350 const struct amd_ip_funcs psp_ip_funcs = { 3351 .name = "psp", 3352 .early_init = psp_early_init, 3353 .late_init = NULL, 3354 .sw_init = psp_sw_init, 3355 .sw_fini = psp_sw_fini, 3356 .hw_init = psp_hw_init, 3357 .hw_fini = psp_hw_fini, 3358 .suspend = psp_suspend, 3359 .resume = psp_resume, 3360 .is_idle = NULL, 3361 .check_soft_reset = NULL, 3362 .wait_for_idle = NULL, 3363 .soft_reset = NULL, 3364 .set_clockgating_state = psp_set_clockgating_state, 3365 .set_powergating_state = psp_set_powergating_state, 3366 }; 3367 3368 static int psp_sysfs_init(struct amdgpu_device *adev) 3369 { 3370 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3371 3372 if (ret) 3373 DRM_ERROR("Failed to create USBC PD FW control file!"); 3374 3375 return ret; 3376 } 3377 3378 static void psp_sysfs_fini(struct amdgpu_device *adev) 3379 { 3380 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3381 } 3382 3383 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3384 { 3385 .type = AMD_IP_BLOCK_TYPE_PSP, 3386 .major = 3, 3387 .minor = 1, 3388 .rev = 0, 3389 .funcs = &psp_ip_funcs, 3390 }; 3391 3392 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3393 { 3394 .type = AMD_IP_BLOCK_TYPE_PSP, 3395 .major = 10, 3396 .minor = 0, 3397 .rev = 0, 3398 .funcs = &psp_ip_funcs, 3399 }; 3400 3401 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3402 { 3403 .type = AMD_IP_BLOCK_TYPE_PSP, 3404 .major = 11, 3405 .minor = 0, 3406 .rev = 0, 3407 .funcs = &psp_ip_funcs, 3408 }; 3409 3410 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3411 { 3412 .type = AMD_IP_BLOCK_TYPE_PSP, 3413 .major = 12, 3414 .minor = 0, 3415 .rev = 0, 3416 .funcs = &psp_ip_funcs, 3417 }; 3418 3419 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3420 .type = AMD_IP_BLOCK_TYPE_PSP, 3421 .major = 13, 3422 .minor = 0, 3423 .rev = 0, 3424 .funcs = &psp_ip_funcs, 3425 }; 3426