1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v3_1.h" 34 #include "psp_v10_0.h" 35 #include "psp_v11_0.h" 36 #include "psp_v12_0.h" 37 #include "psp_v13_0.h" 38 39 #include "amdgpu_ras.h" 40 #include "amdgpu_securedisplay.h" 41 #include "amdgpu_atomfirmware.h" 42 43 #include <drm/drm_drv.h> 44 45 static int psp_sysfs_init(struct amdgpu_device *adev); 46 static void psp_sysfs_fini(struct amdgpu_device *adev); 47 48 static int psp_load_smu_fw(struct psp_context *psp); 49 50 /* 51 * Due to DF Cstate management centralized to PMFW, the firmware 52 * loading sequence will be updated as below: 53 * - Load KDB 54 * - Load SYS_DRV 55 * - Load tOS 56 * - Load PMFW 57 * - Setup TMR 58 * - Load other non-psp fw 59 * - Load ASD 60 * - Load XGMI/RAS/HDCP/DTM TA if any 61 * 62 * This new sequence is required for 63 * - Arcturus and onwards 64 * - Navi12 and onwards 65 */ 66 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 67 { 68 struct amdgpu_device *adev = psp->adev; 69 70 psp->pmfw_centralized_cstate_management = false; 71 72 if (amdgpu_sriov_vf(adev)) 73 return; 74 75 if (adev->flags & AMD_IS_APU) 76 return; 77 78 if ((adev->asic_type >= CHIP_ARCTURUS) || 79 (adev->asic_type >= CHIP_NAVI12)) 80 psp->pmfw_centralized_cstate_management = true; 81 } 82 83 static int psp_early_init(void *handle) 84 { 85 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 86 struct psp_context *psp = &adev->psp; 87 88 switch (adev->asic_type) { 89 case CHIP_VEGA10: 90 case CHIP_VEGA12: 91 psp_v3_1_set_psp_funcs(psp); 92 psp->autoload_supported = false; 93 break; 94 case CHIP_RAVEN: 95 psp_v10_0_set_psp_funcs(psp); 96 psp->autoload_supported = false; 97 break; 98 case CHIP_VEGA20: 99 case CHIP_ARCTURUS: 100 psp_v11_0_set_psp_funcs(psp); 101 psp->autoload_supported = false; 102 break; 103 case CHIP_NAVI10: 104 case CHIP_NAVI14: 105 case CHIP_NAVI12: 106 case CHIP_SIENNA_CICHLID: 107 case CHIP_NAVY_FLOUNDER: 108 case CHIP_VANGOGH: 109 case CHIP_DIMGREY_CAVEFISH: 110 case CHIP_BEIGE_GOBY: 111 psp_v11_0_set_psp_funcs(psp); 112 psp->autoload_supported = true; 113 break; 114 case CHIP_RENOIR: 115 psp_v12_0_set_psp_funcs(psp); 116 break; 117 case CHIP_ALDEBARAN: 118 psp_v13_0_set_psp_funcs(psp); 119 break; 120 case CHIP_YELLOW_CARP: 121 psp_v13_0_set_psp_funcs(psp); 122 psp->autoload_supported = true; 123 break; 124 default: 125 return -EINVAL; 126 } 127 128 psp->adev = adev; 129 130 psp_check_pmfw_centralized_cstate_management(psp); 131 132 return 0; 133 } 134 135 static void psp_memory_training_fini(struct psp_context *psp) 136 { 137 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 138 139 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 140 kfree(ctx->sys_cache); 141 ctx->sys_cache = NULL; 142 } 143 144 static int psp_memory_training_init(struct psp_context *psp) 145 { 146 int ret; 147 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 148 149 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 150 DRM_DEBUG("memory training is not supported!\n"); 151 return 0; 152 } 153 154 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 155 if (ctx->sys_cache == NULL) { 156 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 157 ret = -ENOMEM; 158 goto Err_out; 159 } 160 161 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 162 ctx->train_data_size, 163 ctx->p2c_train_data_offset, 164 ctx->c2p_train_data_offset); 165 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 166 return 0; 167 168 Err_out: 169 psp_memory_training_fini(psp); 170 return ret; 171 } 172 173 /* 174 * Helper funciton to query psp runtime database entry 175 * 176 * @adev: amdgpu_device pointer 177 * @entry_type: the type of psp runtime database entry 178 * @db_entry: runtime database entry pointer 179 * 180 * Return false if runtime database doesn't exit or entry is invalid 181 * or true if the specific database entry is found, and copy to @db_entry 182 */ 183 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 184 enum psp_runtime_entry_type entry_type, 185 void *db_entry) 186 { 187 uint64_t db_header_pos, db_dir_pos; 188 struct psp_runtime_data_header db_header = {0}; 189 struct psp_runtime_data_directory db_dir = {0}; 190 bool ret = false; 191 int i; 192 193 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 194 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 195 196 /* read runtime db header from vram */ 197 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 198 sizeof(struct psp_runtime_data_header), false); 199 200 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 201 /* runtime db doesn't exist, exit */ 202 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 203 return false; 204 } 205 206 /* read runtime database entry from vram */ 207 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 208 sizeof(struct psp_runtime_data_directory), false); 209 210 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 211 /* invalid db entry count, exit */ 212 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 213 return false; 214 } 215 216 /* look up for requested entry type */ 217 for (i = 0; i < db_dir.entry_count && !ret; i++) { 218 if (db_dir.entry_list[i].entry_type == entry_type) { 219 switch (entry_type) { 220 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 221 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 222 /* invalid db entry size */ 223 dev_warn(adev->dev, "Invalid PSP runtime database entry size\n"); 224 return false; 225 } 226 /* read runtime database entry */ 227 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 228 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 229 ret = true; 230 break; 231 default: 232 ret = false; 233 break; 234 } 235 } 236 } 237 238 return ret; 239 } 240 241 static int psp_sw_init(void *handle) 242 { 243 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 244 struct psp_context *psp = &adev->psp; 245 int ret; 246 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 247 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 248 249 if (!amdgpu_sriov_vf(adev)) { 250 ret = psp_init_microcode(psp); 251 if (ret) { 252 DRM_ERROR("Failed to load psp firmware!\n"); 253 return ret; 254 } 255 } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) { 256 ret = psp_init_ta_microcode(psp, "aldebaran"); 257 if (ret) { 258 DRM_ERROR("Failed to initialize ta microcode!\n"); 259 return ret; 260 } 261 } 262 263 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 264 if (psp_get_runtime_db_entry(adev, 265 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 266 &boot_cfg_entry)) { 267 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 268 if ((psp->boot_cfg_bitmask) & 269 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 270 /* If psp runtime database exists, then 271 * only enable two stage memory training 272 * when TWO_STAGE_DRAM_TRAINING bit is set 273 * in runtime database */ 274 mem_training_ctx->enable_mem_training = true; 275 } 276 277 } else { 278 /* If psp runtime database doesn't exist or 279 * is invalid, force enable two stage memory 280 * training */ 281 mem_training_ctx->enable_mem_training = true; 282 } 283 284 if (mem_training_ctx->enable_mem_training) { 285 ret = psp_memory_training_init(psp); 286 if (ret) { 287 DRM_ERROR("Failed to initialize memory training!\n"); 288 return ret; 289 } 290 291 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 292 if (ret) { 293 DRM_ERROR("Failed to process memory training!\n"); 294 return ret; 295 } 296 } 297 298 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 299 ret= psp_sysfs_init(adev); 300 if (ret) { 301 return ret; 302 } 303 } 304 305 return 0; 306 } 307 308 static int psp_sw_fini(void *handle) 309 { 310 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 311 312 psp_memory_training_fini(&adev->psp); 313 if (adev->psp.sos_fw) { 314 release_firmware(adev->psp.sos_fw); 315 adev->psp.sos_fw = NULL; 316 } 317 if (adev->psp.asd_fw) { 318 release_firmware(adev->psp.asd_fw); 319 adev->psp.asd_fw = NULL; 320 } 321 if (adev->psp.ta_fw) { 322 release_firmware(adev->psp.ta_fw); 323 adev->psp.ta_fw = NULL; 324 } 325 326 if (adev->asic_type == CHIP_NAVI10 || 327 adev->asic_type == CHIP_SIENNA_CICHLID) 328 psp_sysfs_fini(adev); 329 330 return 0; 331 } 332 333 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 334 uint32_t reg_val, uint32_t mask, bool check_changed) 335 { 336 uint32_t val; 337 int i; 338 struct amdgpu_device *adev = psp->adev; 339 340 if (psp->adev->no_hw_access) 341 return 0; 342 343 for (i = 0; i < adev->usec_timeout; i++) { 344 val = RREG32(reg_index); 345 if (check_changed) { 346 if (val != reg_val) 347 return 0; 348 } else { 349 if ((val & mask) == reg_val) 350 return 0; 351 } 352 udelay(1); 353 } 354 355 return -ETIME; 356 } 357 358 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 359 { 360 switch (cmd_id) { 361 case GFX_CMD_ID_LOAD_TA: 362 return "LOAD_TA"; 363 case GFX_CMD_ID_UNLOAD_TA: 364 return "UNLOAD_TA"; 365 case GFX_CMD_ID_INVOKE_CMD: 366 return "INVOKE_CMD"; 367 case GFX_CMD_ID_LOAD_ASD: 368 return "LOAD_ASD"; 369 case GFX_CMD_ID_SETUP_TMR: 370 return "SETUP_TMR"; 371 case GFX_CMD_ID_LOAD_IP_FW: 372 return "LOAD_IP_FW"; 373 case GFX_CMD_ID_DESTROY_TMR: 374 return "DESTROY_TMR"; 375 case GFX_CMD_ID_SAVE_RESTORE: 376 return "SAVE_RESTORE_IP_FW"; 377 case GFX_CMD_ID_SETUP_VMR: 378 return "SETUP_VMR"; 379 case GFX_CMD_ID_DESTROY_VMR: 380 return "DESTROY_VMR"; 381 case GFX_CMD_ID_PROG_REG: 382 return "PROG_REG"; 383 case GFX_CMD_ID_GET_FW_ATTESTATION: 384 return "GET_FW_ATTESTATION"; 385 case GFX_CMD_ID_LOAD_TOC: 386 return "ID_LOAD_TOC"; 387 case GFX_CMD_ID_AUTOLOAD_RLC: 388 return "AUTOLOAD_RLC"; 389 case GFX_CMD_ID_BOOT_CFG: 390 return "BOOT_CFG"; 391 default: 392 return "UNKNOWN CMD"; 393 } 394 } 395 396 static int 397 psp_cmd_submit_buf(struct psp_context *psp, 398 struct amdgpu_firmware_info *ucode, 399 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 400 { 401 int ret; 402 int index, idx; 403 int timeout = 20000; 404 bool ras_intr = false; 405 bool skip_unsupport = false; 406 407 if (psp->adev->no_hw_access) 408 return 0; 409 410 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 411 return 0; 412 413 mutex_lock(&psp->mutex); 414 415 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 416 417 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 418 419 index = atomic_inc_return(&psp->fence_value); 420 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 421 if (ret) { 422 atomic_dec(&psp->fence_value); 423 goto exit; 424 } 425 426 amdgpu_device_invalidate_hdp(psp->adev, NULL); 427 while (*((unsigned int *)psp->fence_buf) != index) { 428 if (--timeout == 0) 429 break; 430 /* 431 * Shouldn't wait for timeout when err_event_athub occurs, 432 * because gpu reset thread triggered and lock resource should 433 * be released for psp resume sequence. 434 */ 435 ras_intr = amdgpu_ras_intr_triggered(); 436 if (ras_intr) 437 break; 438 usleep_range(10, 100); 439 amdgpu_device_invalidate_hdp(psp->adev, NULL); 440 } 441 442 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 443 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 444 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 445 446 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 447 448 /* In some cases, psp response status is not 0 even there is no 449 * problem while the command is submitted. Some version of PSP FW 450 * doesn't write 0 to that field. 451 * So here we would like to only print a warning instead of an error 452 * during psp initialization to avoid breaking hw_init and it doesn't 453 * return -EINVAL. 454 */ 455 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 456 if (ucode) 457 DRM_WARN("failed to load ucode (%s) ", 458 amdgpu_ucode_name(ucode->ucode_id)); 459 DRM_WARN("psp gfx command (%s) failed and response status is (0x%X)\n", 460 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 461 psp->cmd_buf_mem->resp.status); 462 if (!timeout) { 463 ret = -EINVAL; 464 goto exit; 465 } 466 } 467 468 if (ucode) { 469 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 470 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 471 } 472 473 exit: 474 mutex_unlock(&psp->mutex); 475 drm_dev_exit(idx); 476 return ret; 477 } 478 479 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 480 struct psp_gfx_cmd_resp *cmd, 481 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 482 { 483 struct amdgpu_device *adev = psp->adev; 484 uint32_t size = amdgpu_bo_size(tmr_bo); 485 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 486 487 if (amdgpu_sriov_vf(psp->adev)) 488 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 489 else 490 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 491 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 492 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 493 cmd->cmd.cmd_setup_tmr.buf_size = size; 494 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 495 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 496 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 497 } 498 499 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 500 uint64_t pri_buf_mc, uint32_t size) 501 { 502 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 503 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 504 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 505 cmd->cmd.cmd_load_toc.toc_size = size; 506 } 507 508 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 509 static int psp_load_toc(struct psp_context *psp, 510 uint32_t *tmr_size) 511 { 512 int ret; 513 struct psp_gfx_cmd_resp *cmd; 514 515 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 516 if (!cmd) 517 return -ENOMEM; 518 /* Copy toc to psp firmware private buffer */ 519 psp_copy_fw(psp, psp->toc_start_addr, psp->toc_bin_size); 520 521 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 522 523 ret = psp_cmd_submit_buf(psp, NULL, cmd, 524 psp->fence_buf_mc_addr); 525 if (!ret) 526 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 527 kfree(cmd); 528 return ret; 529 } 530 531 /* Set up Trusted Memory Region */ 532 static int psp_tmr_init(struct psp_context *psp) 533 { 534 int ret; 535 int tmr_size; 536 void *tmr_buf; 537 void **pptr; 538 539 /* 540 * According to HW engineer, they prefer the TMR address be "naturally 541 * aligned" , e.g. the start address be an integer divide of TMR size. 542 * 543 * Note: this memory need be reserved till the driver 544 * uninitializes. 545 */ 546 tmr_size = PSP_TMR_SIZE(psp->adev); 547 548 /* For ASICs support RLC autoload, psp will parse the toc 549 * and calculate the total size of TMR needed */ 550 if (!amdgpu_sriov_vf(psp->adev) && 551 psp->toc_start_addr && 552 psp->toc_bin_size && 553 psp->fw_pri_buf) { 554 ret = psp_load_toc(psp, &tmr_size); 555 if (ret) { 556 DRM_ERROR("Failed to load toc\n"); 557 return ret; 558 } 559 } 560 561 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 562 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 563 AMDGPU_GEM_DOMAIN_VRAM, 564 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 565 566 return ret; 567 } 568 569 static bool psp_skip_tmr(struct psp_context *psp) 570 { 571 switch (psp->adev->asic_type) { 572 case CHIP_NAVI12: 573 case CHIP_SIENNA_CICHLID: 574 case CHIP_ALDEBARAN: 575 return true; 576 default: 577 return false; 578 } 579 } 580 581 static int psp_tmr_load(struct psp_context *psp) 582 { 583 int ret; 584 struct psp_gfx_cmd_resp *cmd; 585 586 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 587 * Already set up by host driver. 588 */ 589 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 590 return 0; 591 592 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 593 if (!cmd) 594 return -ENOMEM; 595 596 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 597 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 598 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 599 600 ret = psp_cmd_submit_buf(psp, NULL, cmd, 601 psp->fence_buf_mc_addr); 602 603 kfree(cmd); 604 605 return ret; 606 } 607 608 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 609 struct psp_gfx_cmd_resp *cmd) 610 { 611 if (amdgpu_sriov_vf(psp->adev)) 612 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 613 else 614 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 615 } 616 617 static int psp_tmr_unload(struct psp_context *psp) 618 { 619 int ret; 620 struct psp_gfx_cmd_resp *cmd; 621 622 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 623 if (!cmd) 624 return -ENOMEM; 625 626 psp_prep_tmr_unload_cmd_buf(psp, cmd); 627 DRM_INFO("free PSP TMR buffer\n"); 628 629 ret = psp_cmd_submit_buf(psp, NULL, cmd, 630 psp->fence_buf_mc_addr); 631 632 kfree(cmd); 633 634 return ret; 635 } 636 637 static int psp_tmr_terminate(struct psp_context *psp) 638 { 639 int ret; 640 void *tmr_buf; 641 void **pptr; 642 643 ret = psp_tmr_unload(psp); 644 if (ret) 645 return ret; 646 647 /* free TMR memory buffer */ 648 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 649 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 650 651 return 0; 652 } 653 654 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 655 uint64_t *output_ptr) 656 { 657 int ret; 658 struct psp_gfx_cmd_resp *cmd; 659 660 if (!output_ptr) 661 return -EINVAL; 662 663 if (amdgpu_sriov_vf(psp->adev)) 664 return 0; 665 666 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 667 if (!cmd) 668 return -ENOMEM; 669 670 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 671 672 ret = psp_cmd_submit_buf(psp, NULL, cmd, 673 psp->fence_buf_mc_addr); 674 675 if (!ret) { 676 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 677 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 678 } 679 680 kfree(cmd); 681 682 return ret; 683 } 684 685 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 686 { 687 struct psp_context *psp = &adev->psp; 688 struct psp_gfx_cmd_resp *cmd = psp->cmd; 689 int ret; 690 691 if (amdgpu_sriov_vf(adev)) 692 return 0; 693 694 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 695 696 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 697 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 698 699 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 700 if (!ret) { 701 *boot_cfg = 702 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 703 } 704 705 return ret; 706 } 707 708 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 709 { 710 struct psp_context *psp = &adev->psp; 711 struct psp_gfx_cmd_resp *cmd = psp->cmd; 712 713 if (amdgpu_sriov_vf(adev)) 714 return 0; 715 716 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 717 718 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 719 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 720 cmd->cmd.boot_cfg.boot_config = boot_cfg; 721 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 722 723 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 724 } 725 726 static int psp_rl_load(struct amdgpu_device *adev) 727 { 728 struct psp_context *psp = &adev->psp; 729 struct psp_gfx_cmd_resp *cmd = psp->cmd; 730 731 if (psp->rl_bin_size == 0) 732 return 0; 733 734 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 735 memcpy(psp->fw_pri_buf, psp->rl_start_addr, psp->rl_bin_size); 736 737 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 738 739 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 740 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 741 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 742 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl_bin_size; 743 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 744 745 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 746 } 747 748 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 749 uint64_t asd_mc, uint32_t size) 750 { 751 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 752 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 753 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 754 cmd->cmd.cmd_load_ta.app_len = size; 755 756 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 757 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 758 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 759 } 760 761 static int psp_asd_load(struct psp_context *psp) 762 { 763 int ret; 764 struct psp_gfx_cmd_resp *cmd; 765 766 /* If PSP version doesn't match ASD version, asd loading will be failed. 767 * add workaround to bypass it for sriov now. 768 * TODO: add version check to make it common 769 */ 770 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size) 771 return 0; 772 773 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 774 if (!cmd) 775 return -ENOMEM; 776 777 psp_copy_fw(psp, psp->asd_start_addr, psp->asd_ucode_size); 778 779 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 780 psp->asd_ucode_size); 781 782 ret = psp_cmd_submit_buf(psp, NULL, cmd, 783 psp->fence_buf_mc_addr); 784 if (!ret) { 785 psp->asd_context.asd_initialized = true; 786 psp->asd_context.session_id = cmd->resp.session_id; 787 } 788 789 kfree(cmd); 790 791 return ret; 792 } 793 794 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 795 uint32_t session_id) 796 { 797 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 798 cmd->cmd.cmd_unload_ta.session_id = session_id; 799 } 800 801 static int psp_asd_unload(struct psp_context *psp) 802 { 803 int ret; 804 struct psp_gfx_cmd_resp *cmd; 805 806 if (amdgpu_sriov_vf(psp->adev)) 807 return 0; 808 809 if (!psp->asd_context.asd_initialized) 810 return 0; 811 812 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 813 if (!cmd) 814 return -ENOMEM; 815 816 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 817 818 ret = psp_cmd_submit_buf(psp, NULL, cmd, 819 psp->fence_buf_mc_addr); 820 if (!ret) 821 psp->asd_context.asd_initialized = false; 822 823 kfree(cmd); 824 825 return ret; 826 } 827 828 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 829 uint32_t id, uint32_t value) 830 { 831 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 832 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 833 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 834 } 835 836 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 837 uint32_t value) 838 { 839 struct psp_gfx_cmd_resp *cmd = NULL; 840 int ret = 0; 841 842 if (reg >= PSP_REG_LAST) 843 return -EINVAL; 844 845 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 846 if (!cmd) 847 return -ENOMEM; 848 849 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 850 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 851 if (ret) 852 DRM_ERROR("PSP failed to program reg id %d", reg); 853 854 kfree(cmd); 855 return ret; 856 } 857 858 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 859 uint64_t ta_bin_mc, 860 uint32_t ta_bin_size, 861 uint64_t ta_shared_mc, 862 uint32_t ta_shared_size) 863 { 864 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 865 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 866 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 867 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 868 869 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 870 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 871 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 872 } 873 874 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 875 { 876 int ret; 877 878 /* 879 * Allocate 16k memory aligned to 4k from Frame Buffer (local 880 * physical) for xgmi ta <-> Driver 881 */ 882 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 883 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 884 &psp->xgmi_context.xgmi_shared_bo, 885 &psp->xgmi_context.xgmi_shared_mc_addr, 886 &psp->xgmi_context.xgmi_shared_buf); 887 888 return ret; 889 } 890 891 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 892 uint32_t ta_cmd_id, 893 uint32_t session_id) 894 { 895 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 896 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 897 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 898 } 899 900 static int psp_ta_invoke(struct psp_context *psp, 901 uint32_t ta_cmd_id, 902 uint32_t session_id) 903 { 904 int ret; 905 struct psp_gfx_cmd_resp *cmd; 906 907 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 908 if (!cmd) 909 return -ENOMEM; 910 911 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 912 913 ret = psp_cmd_submit_buf(psp, NULL, cmd, 914 psp->fence_buf_mc_addr); 915 916 kfree(cmd); 917 918 return ret; 919 } 920 921 static int psp_xgmi_load(struct psp_context *psp) 922 { 923 int ret; 924 struct psp_gfx_cmd_resp *cmd; 925 926 /* 927 * TODO: bypass the loading in sriov for now 928 */ 929 930 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 931 if (!cmd) 932 return -ENOMEM; 933 934 psp_copy_fw(psp, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 935 936 psp_prep_ta_load_cmd_buf(cmd, 937 psp->fw_pri_mc_addr, 938 psp->ta_xgmi_ucode_size, 939 psp->xgmi_context.xgmi_shared_mc_addr, 940 PSP_XGMI_SHARED_MEM_SIZE); 941 942 ret = psp_cmd_submit_buf(psp, NULL, cmd, 943 psp->fence_buf_mc_addr); 944 945 if (!ret) { 946 psp->xgmi_context.initialized = 1; 947 psp->xgmi_context.session_id = cmd->resp.session_id; 948 } 949 950 kfree(cmd); 951 952 return ret; 953 } 954 955 static int psp_xgmi_unload(struct psp_context *psp) 956 { 957 int ret; 958 struct psp_gfx_cmd_resp *cmd; 959 struct amdgpu_device *adev = psp->adev; 960 961 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 962 if (adev->asic_type == CHIP_ARCTURUS || 963 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu)) 964 return 0; 965 966 /* 967 * TODO: bypass the unloading in sriov for now 968 */ 969 970 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 971 if (!cmd) 972 return -ENOMEM; 973 974 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 975 976 ret = psp_cmd_submit_buf(psp, NULL, cmd, 977 psp->fence_buf_mc_addr); 978 979 kfree(cmd); 980 981 return ret; 982 } 983 984 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 985 { 986 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 987 } 988 989 int psp_xgmi_terminate(struct psp_context *psp) 990 { 991 int ret; 992 993 if (!psp->xgmi_context.initialized) 994 return 0; 995 996 ret = psp_xgmi_unload(psp); 997 if (ret) 998 return ret; 999 1000 psp->xgmi_context.initialized = 0; 1001 1002 /* free xgmi shared memory */ 1003 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 1004 &psp->xgmi_context.xgmi_shared_mc_addr, 1005 &psp->xgmi_context.xgmi_shared_buf); 1006 1007 return 0; 1008 } 1009 1010 int psp_xgmi_initialize(struct psp_context *psp) 1011 { 1012 struct ta_xgmi_shared_memory *xgmi_cmd; 1013 int ret; 1014 1015 if (!psp->adev->psp.ta_fw || 1016 !psp->adev->psp.ta_xgmi_ucode_size || 1017 !psp->adev->psp.ta_xgmi_start_addr) 1018 return -ENOENT; 1019 1020 if (!psp->xgmi_context.initialized) { 1021 ret = psp_xgmi_init_shared_buf(psp); 1022 if (ret) 1023 return ret; 1024 } 1025 1026 /* Load XGMI TA */ 1027 ret = psp_xgmi_load(psp); 1028 if (ret) 1029 return ret; 1030 1031 /* Initialize XGMI session */ 1032 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 1033 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1034 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1035 1036 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1037 1038 return ret; 1039 } 1040 1041 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1042 { 1043 struct ta_xgmi_shared_memory *xgmi_cmd; 1044 int ret; 1045 1046 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1047 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1048 1049 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1050 1051 /* Invoke xgmi ta to get hive id */ 1052 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1053 if (ret) 1054 return ret; 1055 1056 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1057 1058 return 0; 1059 } 1060 1061 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1062 { 1063 struct ta_xgmi_shared_memory *xgmi_cmd; 1064 int ret; 1065 1066 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1067 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1068 1069 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1070 1071 /* Invoke xgmi ta to get the node id */ 1072 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1073 if (ret) 1074 return ret; 1075 1076 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1077 1078 return 0; 1079 } 1080 1081 int psp_xgmi_get_topology_info(struct psp_context *psp, 1082 int number_devices, 1083 struct psp_xgmi_topology_info *topology) 1084 { 1085 struct ta_xgmi_shared_memory *xgmi_cmd; 1086 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1087 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1088 int i; 1089 int ret; 1090 1091 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1092 return -EINVAL; 1093 1094 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1095 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1096 1097 /* Fill in the shared memory with topology information as input */ 1098 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1099 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1100 topology_info_input->num_nodes = number_devices; 1101 1102 for (i = 0; i < topology_info_input->num_nodes; i++) { 1103 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1104 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1105 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1106 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1107 } 1108 1109 /* Invoke xgmi ta to get the topology information */ 1110 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1111 if (ret) 1112 return ret; 1113 1114 /* Read the output topology information from the shared memory */ 1115 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1116 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1117 for (i = 0; i < topology->num_nodes; i++) { 1118 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1119 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1120 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 1121 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 1122 } 1123 1124 return 0; 1125 } 1126 1127 int psp_xgmi_set_topology_info(struct psp_context *psp, 1128 int number_devices, 1129 struct psp_xgmi_topology_info *topology) 1130 { 1131 struct ta_xgmi_shared_memory *xgmi_cmd; 1132 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1133 int i; 1134 1135 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1136 return -EINVAL; 1137 1138 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1139 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1140 1141 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1142 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1143 topology_info_input->num_nodes = number_devices; 1144 1145 for (i = 0; i < topology_info_input->num_nodes; i++) { 1146 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1147 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1148 topology_info_input->nodes[i].is_sharing_enabled = 1; 1149 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1150 } 1151 1152 /* Invoke xgmi ta to set topology information */ 1153 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1154 } 1155 1156 // ras begin 1157 static int psp_ras_init_shared_buf(struct psp_context *psp) 1158 { 1159 int ret; 1160 1161 /* 1162 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1163 * physical) for ras ta <-> Driver 1164 */ 1165 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 1166 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1167 &psp->ras.ras_shared_bo, 1168 &psp->ras.ras_shared_mc_addr, 1169 &psp->ras.ras_shared_buf); 1170 1171 return ret; 1172 } 1173 1174 static int psp_ras_load(struct psp_context *psp) 1175 { 1176 int ret; 1177 struct psp_gfx_cmd_resp *cmd; 1178 struct ta_ras_shared_memory *ras_cmd; 1179 1180 /* 1181 * TODO: bypass the loading in sriov for now 1182 */ 1183 if (amdgpu_sriov_vf(psp->adev)) 1184 return 0; 1185 1186 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1187 if (!cmd) 1188 return -ENOMEM; 1189 1190 psp_copy_fw(psp, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 1191 1192 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1193 1194 if (psp->adev->gmc.xgmi.connected_to_cpu) 1195 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1196 else 1197 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1198 1199 psp_prep_ta_load_cmd_buf(cmd, 1200 psp->fw_pri_mc_addr, 1201 psp->ta_ras_ucode_size, 1202 psp->ras.ras_shared_mc_addr, 1203 PSP_RAS_SHARED_MEM_SIZE); 1204 1205 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1206 psp->fence_buf_mc_addr); 1207 1208 if (!ret) { 1209 psp->ras.session_id = cmd->resp.session_id; 1210 1211 if (!ras_cmd->ras_status) 1212 psp->ras.ras_initialized = true; 1213 else 1214 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1215 } 1216 1217 if (ret || ras_cmd->ras_status) 1218 amdgpu_ras_fini(psp->adev); 1219 1220 kfree(cmd); 1221 1222 return ret; 1223 } 1224 1225 static int psp_ras_unload(struct psp_context *psp) 1226 { 1227 int ret; 1228 struct psp_gfx_cmd_resp *cmd; 1229 1230 /* 1231 * TODO: bypass the unloading in sriov for now 1232 */ 1233 if (amdgpu_sriov_vf(psp->adev)) 1234 return 0; 1235 1236 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1237 if (!cmd) 1238 return -ENOMEM; 1239 1240 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 1241 1242 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1243 psp->fence_buf_mc_addr); 1244 1245 kfree(cmd); 1246 1247 return ret; 1248 } 1249 1250 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1251 { 1252 struct ta_ras_shared_memory *ras_cmd; 1253 int ret; 1254 1255 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1256 1257 /* 1258 * TODO: bypass the loading in sriov for now 1259 */ 1260 if (amdgpu_sriov_vf(psp->adev)) 1261 return 0; 1262 1263 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 1264 1265 if (amdgpu_ras_intr_triggered()) 1266 return ret; 1267 1268 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1269 { 1270 DRM_WARN("RAS: Unsupported Interface"); 1271 return -EINVAL; 1272 } 1273 1274 if (!ret) { 1275 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1276 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1277 1278 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1279 } 1280 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1281 dev_warn(psp->adev->dev, 1282 "RAS internal register access blocked\n"); 1283 } 1284 1285 return ret; 1286 } 1287 1288 static int psp_ras_status_to_errno(struct amdgpu_device *adev, 1289 enum ta_ras_status ras_status) 1290 { 1291 int ret = -EINVAL; 1292 1293 switch (ras_status) { 1294 case TA_RAS_STATUS__SUCCESS: 1295 ret = 0; 1296 break; 1297 case TA_RAS_STATUS__RESET_NEEDED: 1298 ret = -EAGAIN; 1299 break; 1300 case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: 1301 dev_warn(adev->dev, "RAS WARN: ras function unavailable\n"); 1302 break; 1303 case TA_RAS_STATUS__ERROR_ASD_READ_WRITE: 1304 dev_warn(adev->dev, "RAS WARN: asd read or write failed\n"); 1305 break; 1306 default: 1307 dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret); 1308 } 1309 1310 return ret; 1311 } 1312 1313 int psp_ras_enable_features(struct psp_context *psp, 1314 union ta_ras_cmd_input *info, bool enable) 1315 { 1316 struct ta_ras_shared_memory *ras_cmd; 1317 int ret; 1318 1319 if (!psp->ras.ras_initialized) 1320 return -EINVAL; 1321 1322 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1323 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1324 1325 if (enable) 1326 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1327 else 1328 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1329 1330 ras_cmd->ras_in_message = *info; 1331 1332 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1333 if (ret) 1334 return -EINVAL; 1335 1336 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1337 } 1338 1339 static int psp_ras_terminate(struct psp_context *psp) 1340 { 1341 int ret; 1342 1343 /* 1344 * TODO: bypass the terminate in sriov for now 1345 */ 1346 if (amdgpu_sriov_vf(psp->adev)) 1347 return 0; 1348 1349 if (!psp->ras.ras_initialized) 1350 return 0; 1351 1352 ret = psp_ras_unload(psp); 1353 if (ret) 1354 return ret; 1355 1356 psp->ras.ras_initialized = false; 1357 1358 /* free ras shared memory */ 1359 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1360 &psp->ras.ras_shared_mc_addr, 1361 &psp->ras.ras_shared_buf); 1362 1363 return 0; 1364 } 1365 1366 static int psp_ras_initialize(struct psp_context *psp) 1367 { 1368 int ret; 1369 uint32_t boot_cfg = 0xFF; 1370 struct amdgpu_device *adev = psp->adev; 1371 1372 /* 1373 * TODO: bypass the initialize in sriov for now 1374 */ 1375 if (amdgpu_sriov_vf(adev)) 1376 return 0; 1377 1378 if (!adev->psp.ta_ras_ucode_size || 1379 !adev->psp.ta_ras_start_addr) { 1380 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1381 return 0; 1382 } 1383 1384 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1385 /* query GECC enablement status from boot config 1386 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1387 */ 1388 ret = psp_boot_config_get(adev, &boot_cfg); 1389 if (ret) 1390 dev_warn(adev->dev, "PSP get boot config failed\n"); 1391 1392 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1393 if (!boot_cfg) { 1394 dev_info(adev->dev, "GECC is disabled\n"); 1395 } else { 1396 /* disable GECC in next boot cycle if ras is 1397 * disabled by module parameter amdgpu_ras_enable 1398 * and/or amdgpu_ras_mask, or boot_config_get call 1399 * is failed 1400 */ 1401 ret = psp_boot_config_set(adev, 0); 1402 if (ret) 1403 dev_warn(adev->dev, "PSP set boot config failed\n"); 1404 else 1405 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1406 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1407 } 1408 } else { 1409 if (1 == boot_cfg) { 1410 dev_info(adev->dev, "GECC is enabled\n"); 1411 } else { 1412 /* enable GECC in next boot cycle if it is disabled 1413 * in boot config, or force enable GECC if failed to 1414 * get boot configuration 1415 */ 1416 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1417 if (ret) 1418 dev_warn(adev->dev, "PSP set boot config failed\n"); 1419 else 1420 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1421 } 1422 } 1423 } 1424 1425 if (!psp->ras.ras_initialized) { 1426 ret = psp_ras_init_shared_buf(psp); 1427 if (ret) 1428 return ret; 1429 } 1430 1431 ret = psp_ras_load(psp); 1432 if (ret) 1433 return ret; 1434 1435 return 0; 1436 } 1437 1438 int psp_ras_trigger_error(struct psp_context *psp, 1439 struct ta_ras_trigger_error_input *info) 1440 { 1441 struct ta_ras_shared_memory *ras_cmd; 1442 int ret; 1443 1444 if (!psp->ras.ras_initialized) 1445 return -EINVAL; 1446 1447 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1448 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1449 1450 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1451 ras_cmd->ras_in_message.trigger_error = *info; 1452 1453 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1454 if (ret) 1455 return -EINVAL; 1456 1457 /* If err_event_athub occurs error inject was successful, however 1458 return status from TA is no long reliable */ 1459 if (amdgpu_ras_intr_triggered()) 1460 return 0; 1461 1462 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1463 } 1464 // ras end 1465 1466 // HDCP start 1467 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1468 { 1469 int ret; 1470 1471 /* 1472 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1473 * physical) for hdcp ta <-> Driver 1474 */ 1475 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1476 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1477 &psp->hdcp_context.hdcp_shared_bo, 1478 &psp->hdcp_context.hdcp_shared_mc_addr, 1479 &psp->hdcp_context.hdcp_shared_buf); 1480 1481 return ret; 1482 } 1483 1484 static int psp_hdcp_load(struct psp_context *psp) 1485 { 1486 int ret; 1487 struct psp_gfx_cmd_resp *cmd; 1488 1489 /* 1490 * TODO: bypass the loading in sriov for now 1491 */ 1492 if (amdgpu_sriov_vf(psp->adev)) 1493 return 0; 1494 1495 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1496 if (!cmd) 1497 return -ENOMEM; 1498 1499 psp_copy_fw(psp, psp->ta_hdcp_start_addr, 1500 psp->ta_hdcp_ucode_size); 1501 1502 psp_prep_ta_load_cmd_buf(cmd, 1503 psp->fw_pri_mc_addr, 1504 psp->ta_hdcp_ucode_size, 1505 psp->hdcp_context.hdcp_shared_mc_addr, 1506 PSP_HDCP_SHARED_MEM_SIZE); 1507 1508 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1509 1510 if (!ret) { 1511 psp->hdcp_context.hdcp_initialized = true; 1512 psp->hdcp_context.session_id = cmd->resp.session_id; 1513 mutex_init(&psp->hdcp_context.mutex); 1514 } 1515 1516 kfree(cmd); 1517 1518 return ret; 1519 } 1520 static int psp_hdcp_initialize(struct psp_context *psp) 1521 { 1522 int ret; 1523 1524 /* 1525 * TODO: bypass the initialize in sriov for now 1526 */ 1527 if (amdgpu_sriov_vf(psp->adev)) 1528 return 0; 1529 1530 if (!psp->adev->psp.ta_hdcp_ucode_size || 1531 !psp->adev->psp.ta_hdcp_start_addr) { 1532 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1533 return 0; 1534 } 1535 1536 if (!psp->hdcp_context.hdcp_initialized) { 1537 ret = psp_hdcp_init_shared_buf(psp); 1538 if (ret) 1539 return ret; 1540 } 1541 1542 ret = psp_hdcp_load(psp); 1543 if (ret) 1544 return ret; 1545 1546 return 0; 1547 } 1548 1549 static int psp_hdcp_unload(struct psp_context *psp) 1550 { 1551 int ret; 1552 struct psp_gfx_cmd_resp *cmd; 1553 1554 /* 1555 * TODO: bypass the unloading in sriov for now 1556 */ 1557 if (amdgpu_sriov_vf(psp->adev)) 1558 return 0; 1559 1560 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1561 if (!cmd) 1562 return -ENOMEM; 1563 1564 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1565 1566 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1567 1568 kfree(cmd); 1569 1570 return ret; 1571 } 1572 1573 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1574 { 1575 /* 1576 * TODO: bypass the loading in sriov for now 1577 */ 1578 if (amdgpu_sriov_vf(psp->adev)) 1579 return 0; 1580 1581 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1582 } 1583 1584 static int psp_hdcp_terminate(struct psp_context *psp) 1585 { 1586 int ret; 1587 1588 /* 1589 * TODO: bypass the terminate in sriov for now 1590 */ 1591 if (amdgpu_sriov_vf(psp->adev)) 1592 return 0; 1593 1594 if (!psp->hdcp_context.hdcp_initialized) { 1595 if (psp->hdcp_context.hdcp_shared_buf) 1596 goto out; 1597 else 1598 return 0; 1599 } 1600 1601 ret = psp_hdcp_unload(psp); 1602 if (ret) 1603 return ret; 1604 1605 psp->hdcp_context.hdcp_initialized = false; 1606 1607 out: 1608 /* free hdcp shared memory */ 1609 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1610 &psp->hdcp_context.hdcp_shared_mc_addr, 1611 &psp->hdcp_context.hdcp_shared_buf); 1612 1613 return 0; 1614 } 1615 // HDCP end 1616 1617 // DTM start 1618 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1619 { 1620 int ret; 1621 1622 /* 1623 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1624 * physical) for dtm ta <-> Driver 1625 */ 1626 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1627 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1628 &psp->dtm_context.dtm_shared_bo, 1629 &psp->dtm_context.dtm_shared_mc_addr, 1630 &psp->dtm_context.dtm_shared_buf); 1631 1632 return ret; 1633 } 1634 1635 static int psp_dtm_load(struct psp_context *psp) 1636 { 1637 int ret; 1638 struct psp_gfx_cmd_resp *cmd; 1639 1640 /* 1641 * TODO: bypass the loading in sriov for now 1642 */ 1643 if (amdgpu_sriov_vf(psp->adev)) 1644 return 0; 1645 1646 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1647 if (!cmd) 1648 return -ENOMEM; 1649 1650 psp_copy_fw(psp, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1651 1652 psp_prep_ta_load_cmd_buf(cmd, 1653 psp->fw_pri_mc_addr, 1654 psp->ta_dtm_ucode_size, 1655 psp->dtm_context.dtm_shared_mc_addr, 1656 PSP_DTM_SHARED_MEM_SIZE); 1657 1658 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1659 1660 if (!ret) { 1661 psp->dtm_context.dtm_initialized = true; 1662 psp->dtm_context.session_id = cmd->resp.session_id; 1663 mutex_init(&psp->dtm_context.mutex); 1664 } 1665 1666 kfree(cmd); 1667 1668 return ret; 1669 } 1670 1671 static int psp_dtm_initialize(struct psp_context *psp) 1672 { 1673 int ret; 1674 1675 /* 1676 * TODO: bypass the initialize in sriov for now 1677 */ 1678 if (amdgpu_sriov_vf(psp->adev)) 1679 return 0; 1680 1681 if (!psp->adev->psp.ta_dtm_ucode_size || 1682 !psp->adev->psp.ta_dtm_start_addr) { 1683 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1684 return 0; 1685 } 1686 1687 if (!psp->dtm_context.dtm_initialized) { 1688 ret = psp_dtm_init_shared_buf(psp); 1689 if (ret) 1690 return ret; 1691 } 1692 1693 ret = psp_dtm_load(psp); 1694 if (ret) 1695 return ret; 1696 1697 return 0; 1698 } 1699 1700 static int psp_dtm_unload(struct psp_context *psp) 1701 { 1702 int ret; 1703 struct psp_gfx_cmd_resp *cmd; 1704 1705 /* 1706 * TODO: bypass the unloading in sriov for now 1707 */ 1708 if (amdgpu_sriov_vf(psp->adev)) 1709 return 0; 1710 1711 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1712 if (!cmd) 1713 return -ENOMEM; 1714 1715 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1716 1717 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1718 1719 kfree(cmd); 1720 1721 return ret; 1722 } 1723 1724 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1725 { 1726 /* 1727 * TODO: bypass the loading in sriov for now 1728 */ 1729 if (amdgpu_sriov_vf(psp->adev)) 1730 return 0; 1731 1732 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1733 } 1734 1735 static int psp_dtm_terminate(struct psp_context *psp) 1736 { 1737 int ret; 1738 1739 /* 1740 * TODO: bypass the terminate in sriov for now 1741 */ 1742 if (amdgpu_sriov_vf(psp->adev)) 1743 return 0; 1744 1745 if (!psp->dtm_context.dtm_initialized) { 1746 if (psp->dtm_context.dtm_shared_buf) 1747 goto out; 1748 else 1749 return 0; 1750 } 1751 1752 ret = psp_dtm_unload(psp); 1753 if (ret) 1754 return ret; 1755 1756 psp->dtm_context.dtm_initialized = false; 1757 1758 out: 1759 /* free hdcp shared memory */ 1760 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1761 &psp->dtm_context.dtm_shared_mc_addr, 1762 &psp->dtm_context.dtm_shared_buf); 1763 1764 return 0; 1765 } 1766 // DTM end 1767 1768 // RAP start 1769 static int psp_rap_init_shared_buf(struct psp_context *psp) 1770 { 1771 int ret; 1772 1773 /* 1774 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1775 * physical) for rap ta <-> Driver 1776 */ 1777 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE, 1778 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1779 &psp->rap_context.rap_shared_bo, 1780 &psp->rap_context.rap_shared_mc_addr, 1781 &psp->rap_context.rap_shared_buf); 1782 1783 return ret; 1784 } 1785 1786 static int psp_rap_load(struct psp_context *psp) 1787 { 1788 int ret; 1789 struct psp_gfx_cmd_resp *cmd; 1790 1791 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1792 if (!cmd) 1793 return -ENOMEM; 1794 1795 psp_copy_fw(psp, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); 1796 1797 psp_prep_ta_load_cmd_buf(cmd, 1798 psp->fw_pri_mc_addr, 1799 psp->ta_rap_ucode_size, 1800 psp->rap_context.rap_shared_mc_addr, 1801 PSP_RAP_SHARED_MEM_SIZE); 1802 1803 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1804 1805 if (!ret) { 1806 psp->rap_context.rap_initialized = true; 1807 psp->rap_context.session_id = cmd->resp.session_id; 1808 mutex_init(&psp->rap_context.mutex); 1809 } 1810 1811 kfree(cmd); 1812 1813 return ret; 1814 } 1815 1816 static int psp_rap_unload(struct psp_context *psp) 1817 { 1818 int ret; 1819 struct psp_gfx_cmd_resp *cmd; 1820 1821 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1822 if (!cmd) 1823 return -ENOMEM; 1824 1825 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id); 1826 1827 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1828 1829 kfree(cmd); 1830 1831 return ret; 1832 } 1833 1834 static int psp_rap_initialize(struct psp_context *psp) 1835 { 1836 int ret; 1837 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1838 1839 /* 1840 * TODO: bypass the initialize in sriov for now 1841 */ 1842 if (amdgpu_sriov_vf(psp->adev)) 1843 return 0; 1844 1845 if (!psp->adev->psp.ta_rap_ucode_size || 1846 !psp->adev->psp.ta_rap_start_addr) { 1847 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1848 return 0; 1849 } 1850 1851 if (!psp->rap_context.rap_initialized) { 1852 ret = psp_rap_init_shared_buf(psp); 1853 if (ret) 1854 return ret; 1855 } 1856 1857 ret = psp_rap_load(psp); 1858 if (ret) 1859 return ret; 1860 1861 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1862 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1863 psp_rap_unload(psp); 1864 1865 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1866 &psp->rap_context.rap_shared_mc_addr, 1867 &psp->rap_context.rap_shared_buf); 1868 1869 psp->rap_context.rap_initialized = false; 1870 1871 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1872 ret, status); 1873 1874 return ret; 1875 } 1876 1877 return 0; 1878 } 1879 1880 static int psp_rap_terminate(struct psp_context *psp) 1881 { 1882 int ret; 1883 1884 if (!psp->rap_context.rap_initialized) 1885 return 0; 1886 1887 ret = psp_rap_unload(psp); 1888 1889 psp->rap_context.rap_initialized = false; 1890 1891 /* free rap shared memory */ 1892 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1893 &psp->rap_context.rap_shared_mc_addr, 1894 &psp->rap_context.rap_shared_buf); 1895 1896 return ret; 1897 } 1898 1899 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1900 { 1901 struct ta_rap_shared_memory *rap_cmd; 1902 int ret = 0; 1903 1904 if (!psp->rap_context.rap_initialized) 1905 return 0; 1906 1907 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1908 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1909 return -EINVAL; 1910 1911 mutex_lock(&psp->rap_context.mutex); 1912 1913 rap_cmd = (struct ta_rap_shared_memory *) 1914 psp->rap_context.rap_shared_buf; 1915 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1916 1917 rap_cmd->cmd_id = ta_cmd_id; 1918 rap_cmd->validation_method_id = METHOD_A; 1919 1920 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id); 1921 if (ret) 1922 goto out_unlock; 1923 1924 if (status) 1925 *status = rap_cmd->rap_status; 1926 1927 out_unlock: 1928 mutex_unlock(&psp->rap_context.mutex); 1929 1930 return ret; 1931 } 1932 // RAP end 1933 1934 /* securedisplay start */ 1935 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1936 { 1937 int ret; 1938 1939 /* 1940 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1941 * physical) for sa ta <-> Driver 1942 */ 1943 ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE, 1944 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1945 &psp->securedisplay_context.securedisplay_shared_bo, 1946 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1947 &psp->securedisplay_context.securedisplay_shared_buf); 1948 1949 return ret; 1950 } 1951 1952 static int psp_securedisplay_load(struct psp_context *psp) 1953 { 1954 int ret; 1955 struct psp_gfx_cmd_resp *cmd; 1956 1957 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1958 if (!cmd) 1959 return -ENOMEM; 1960 1961 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1962 memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size); 1963 1964 psp_prep_ta_load_cmd_buf(cmd, 1965 psp->fw_pri_mc_addr, 1966 psp->ta_securedisplay_ucode_size, 1967 psp->securedisplay_context.securedisplay_shared_mc_addr, 1968 PSP_SECUREDISPLAY_SHARED_MEM_SIZE); 1969 1970 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1971 1972 if (ret) 1973 goto failed; 1974 1975 psp->securedisplay_context.securedisplay_initialized = true; 1976 psp->securedisplay_context.session_id = cmd->resp.session_id; 1977 mutex_init(&psp->securedisplay_context.mutex); 1978 1979 failed: 1980 kfree(cmd); 1981 return ret; 1982 } 1983 1984 static int psp_securedisplay_unload(struct psp_context *psp) 1985 { 1986 int ret; 1987 struct psp_gfx_cmd_resp *cmd; 1988 1989 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1990 if (!cmd) 1991 return -ENOMEM; 1992 1993 psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id); 1994 1995 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1996 1997 kfree(cmd); 1998 1999 return ret; 2000 } 2001 2002 static int psp_securedisplay_initialize(struct psp_context *psp) 2003 { 2004 int ret; 2005 struct securedisplay_cmd *securedisplay_cmd; 2006 2007 /* 2008 * TODO: bypass the initialize in sriov for now 2009 */ 2010 if (amdgpu_sriov_vf(psp->adev)) 2011 return 0; 2012 2013 if (!psp->adev->psp.ta_securedisplay_ucode_size || 2014 !psp->adev->psp.ta_securedisplay_start_addr) { 2015 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 2016 return 0; 2017 } 2018 2019 if (!psp->securedisplay_context.securedisplay_initialized) { 2020 ret = psp_securedisplay_init_shared_buf(psp); 2021 if (ret) 2022 return ret; 2023 } 2024 2025 ret = psp_securedisplay_load(psp); 2026 if (ret) 2027 return ret; 2028 2029 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2030 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2031 2032 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2033 if (ret) { 2034 psp_securedisplay_unload(psp); 2035 2036 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 2037 &psp->securedisplay_context.securedisplay_shared_mc_addr, 2038 &psp->securedisplay_context.securedisplay_shared_buf); 2039 2040 psp->securedisplay_context.securedisplay_initialized = false; 2041 2042 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2043 return -EINVAL; 2044 } 2045 2046 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2047 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2048 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2049 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2050 } 2051 2052 return 0; 2053 } 2054 2055 static int psp_securedisplay_terminate(struct psp_context *psp) 2056 { 2057 int ret; 2058 2059 /* 2060 * TODO:bypass the terminate in sriov for now 2061 */ 2062 if (amdgpu_sriov_vf(psp->adev)) 2063 return 0; 2064 2065 if (!psp->securedisplay_context.securedisplay_initialized) 2066 return 0; 2067 2068 ret = psp_securedisplay_unload(psp); 2069 if (ret) 2070 return ret; 2071 2072 psp->securedisplay_context.securedisplay_initialized = false; 2073 2074 /* free securedisplay shared memory */ 2075 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 2076 &psp->securedisplay_context.securedisplay_shared_mc_addr, 2077 &psp->securedisplay_context.securedisplay_shared_buf); 2078 2079 return ret; 2080 } 2081 2082 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2083 { 2084 int ret; 2085 2086 if (!psp->securedisplay_context.securedisplay_initialized) 2087 return -EINVAL; 2088 2089 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2090 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2091 return -EINVAL; 2092 2093 mutex_lock(&psp->securedisplay_context.mutex); 2094 2095 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id); 2096 2097 mutex_unlock(&psp->securedisplay_context.mutex); 2098 2099 return ret; 2100 } 2101 /* SECUREDISPLAY end */ 2102 2103 static int psp_hw_start(struct psp_context *psp) 2104 { 2105 struct amdgpu_device *adev = psp->adev; 2106 int ret; 2107 2108 if (!amdgpu_sriov_vf(adev)) { 2109 if (psp->kdb_bin_size && 2110 (psp->funcs->bootloader_load_kdb != NULL)) { 2111 ret = psp_bootloader_load_kdb(psp); 2112 if (ret) { 2113 DRM_ERROR("PSP load kdb failed!\n"); 2114 return ret; 2115 } 2116 } 2117 2118 if (psp->spl_bin_size) { 2119 ret = psp_bootloader_load_spl(psp); 2120 if (ret) { 2121 DRM_ERROR("PSP load spl failed!\n"); 2122 return ret; 2123 } 2124 } 2125 2126 ret = psp_bootloader_load_sysdrv(psp); 2127 if (ret) { 2128 DRM_ERROR("PSP load sysdrv failed!\n"); 2129 return ret; 2130 } 2131 2132 ret = psp_bootloader_load_sos(psp); 2133 if (ret) { 2134 DRM_ERROR("PSP load sos failed!\n"); 2135 return ret; 2136 } 2137 } 2138 2139 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2140 if (ret) { 2141 DRM_ERROR("PSP create ring failed!\n"); 2142 return ret; 2143 } 2144 2145 ret = psp_tmr_init(psp); 2146 if (ret) { 2147 DRM_ERROR("PSP tmr init failed!\n"); 2148 return ret; 2149 } 2150 2151 /* 2152 * For ASICs with DF Cstate management centralized 2153 * to PMFW, TMR setup should be performed after PMFW 2154 * loaded and before other non-psp firmware loaded. 2155 */ 2156 if (psp->pmfw_centralized_cstate_management) { 2157 ret = psp_load_smu_fw(psp); 2158 if (ret) 2159 return ret; 2160 } 2161 2162 ret = psp_tmr_load(psp); 2163 if (ret) { 2164 DRM_ERROR("PSP load tmr failed!\n"); 2165 return ret; 2166 } 2167 2168 return 0; 2169 } 2170 2171 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2172 enum psp_gfx_fw_type *type) 2173 { 2174 switch (ucode->ucode_id) { 2175 case AMDGPU_UCODE_ID_SDMA0: 2176 *type = GFX_FW_TYPE_SDMA0; 2177 break; 2178 case AMDGPU_UCODE_ID_SDMA1: 2179 *type = GFX_FW_TYPE_SDMA1; 2180 break; 2181 case AMDGPU_UCODE_ID_SDMA2: 2182 *type = GFX_FW_TYPE_SDMA2; 2183 break; 2184 case AMDGPU_UCODE_ID_SDMA3: 2185 *type = GFX_FW_TYPE_SDMA3; 2186 break; 2187 case AMDGPU_UCODE_ID_SDMA4: 2188 *type = GFX_FW_TYPE_SDMA4; 2189 break; 2190 case AMDGPU_UCODE_ID_SDMA5: 2191 *type = GFX_FW_TYPE_SDMA5; 2192 break; 2193 case AMDGPU_UCODE_ID_SDMA6: 2194 *type = GFX_FW_TYPE_SDMA6; 2195 break; 2196 case AMDGPU_UCODE_ID_SDMA7: 2197 *type = GFX_FW_TYPE_SDMA7; 2198 break; 2199 case AMDGPU_UCODE_ID_CP_MES: 2200 *type = GFX_FW_TYPE_CP_MES; 2201 break; 2202 case AMDGPU_UCODE_ID_CP_MES_DATA: 2203 *type = GFX_FW_TYPE_MES_STACK; 2204 break; 2205 case AMDGPU_UCODE_ID_CP_CE: 2206 *type = GFX_FW_TYPE_CP_CE; 2207 break; 2208 case AMDGPU_UCODE_ID_CP_PFP: 2209 *type = GFX_FW_TYPE_CP_PFP; 2210 break; 2211 case AMDGPU_UCODE_ID_CP_ME: 2212 *type = GFX_FW_TYPE_CP_ME; 2213 break; 2214 case AMDGPU_UCODE_ID_CP_MEC1: 2215 *type = GFX_FW_TYPE_CP_MEC; 2216 break; 2217 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2218 *type = GFX_FW_TYPE_CP_MEC_ME1; 2219 break; 2220 case AMDGPU_UCODE_ID_CP_MEC2: 2221 *type = GFX_FW_TYPE_CP_MEC; 2222 break; 2223 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2224 *type = GFX_FW_TYPE_CP_MEC_ME2; 2225 break; 2226 case AMDGPU_UCODE_ID_RLC_G: 2227 *type = GFX_FW_TYPE_RLC_G; 2228 break; 2229 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2230 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2231 break; 2232 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2233 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2234 break; 2235 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2236 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2237 break; 2238 case AMDGPU_UCODE_ID_RLC_IRAM: 2239 *type = GFX_FW_TYPE_RLC_IRAM; 2240 break; 2241 case AMDGPU_UCODE_ID_RLC_DRAM: 2242 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2243 break; 2244 case AMDGPU_UCODE_ID_SMC: 2245 *type = GFX_FW_TYPE_SMU; 2246 break; 2247 case AMDGPU_UCODE_ID_UVD: 2248 *type = GFX_FW_TYPE_UVD; 2249 break; 2250 case AMDGPU_UCODE_ID_UVD1: 2251 *type = GFX_FW_TYPE_UVD1; 2252 break; 2253 case AMDGPU_UCODE_ID_VCE: 2254 *type = GFX_FW_TYPE_VCE; 2255 break; 2256 case AMDGPU_UCODE_ID_VCN: 2257 *type = GFX_FW_TYPE_VCN; 2258 break; 2259 case AMDGPU_UCODE_ID_VCN1: 2260 *type = GFX_FW_TYPE_VCN1; 2261 break; 2262 case AMDGPU_UCODE_ID_DMCU_ERAM: 2263 *type = GFX_FW_TYPE_DMCU_ERAM; 2264 break; 2265 case AMDGPU_UCODE_ID_DMCU_INTV: 2266 *type = GFX_FW_TYPE_DMCU_ISR; 2267 break; 2268 case AMDGPU_UCODE_ID_VCN0_RAM: 2269 *type = GFX_FW_TYPE_VCN0_RAM; 2270 break; 2271 case AMDGPU_UCODE_ID_VCN1_RAM: 2272 *type = GFX_FW_TYPE_VCN1_RAM; 2273 break; 2274 case AMDGPU_UCODE_ID_DMCUB: 2275 *type = GFX_FW_TYPE_DMUB; 2276 break; 2277 case AMDGPU_UCODE_ID_MAXIMUM: 2278 default: 2279 return -EINVAL; 2280 } 2281 2282 return 0; 2283 } 2284 2285 static void psp_print_fw_hdr(struct psp_context *psp, 2286 struct amdgpu_firmware_info *ucode) 2287 { 2288 struct amdgpu_device *adev = psp->adev; 2289 struct common_firmware_header *hdr; 2290 2291 switch (ucode->ucode_id) { 2292 case AMDGPU_UCODE_ID_SDMA0: 2293 case AMDGPU_UCODE_ID_SDMA1: 2294 case AMDGPU_UCODE_ID_SDMA2: 2295 case AMDGPU_UCODE_ID_SDMA3: 2296 case AMDGPU_UCODE_ID_SDMA4: 2297 case AMDGPU_UCODE_ID_SDMA5: 2298 case AMDGPU_UCODE_ID_SDMA6: 2299 case AMDGPU_UCODE_ID_SDMA7: 2300 hdr = (struct common_firmware_header *) 2301 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2302 amdgpu_ucode_print_sdma_hdr(hdr); 2303 break; 2304 case AMDGPU_UCODE_ID_CP_CE: 2305 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2306 amdgpu_ucode_print_gfx_hdr(hdr); 2307 break; 2308 case AMDGPU_UCODE_ID_CP_PFP: 2309 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2310 amdgpu_ucode_print_gfx_hdr(hdr); 2311 break; 2312 case AMDGPU_UCODE_ID_CP_ME: 2313 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2314 amdgpu_ucode_print_gfx_hdr(hdr); 2315 break; 2316 case AMDGPU_UCODE_ID_CP_MEC1: 2317 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2318 amdgpu_ucode_print_gfx_hdr(hdr); 2319 break; 2320 case AMDGPU_UCODE_ID_RLC_G: 2321 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2322 amdgpu_ucode_print_rlc_hdr(hdr); 2323 break; 2324 case AMDGPU_UCODE_ID_SMC: 2325 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2326 amdgpu_ucode_print_smc_hdr(hdr); 2327 break; 2328 default: 2329 break; 2330 } 2331 } 2332 2333 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2334 struct psp_gfx_cmd_resp *cmd) 2335 { 2336 int ret; 2337 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2338 2339 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 2340 2341 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2342 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2343 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2344 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2345 2346 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2347 if (ret) 2348 DRM_ERROR("Unknown firmware type\n"); 2349 2350 return ret; 2351 } 2352 2353 static int psp_execute_np_fw_load(struct psp_context *psp, 2354 struct amdgpu_firmware_info *ucode) 2355 { 2356 int ret = 0; 2357 2358 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 2359 if (ret) 2360 return ret; 2361 2362 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 2363 psp->fence_buf_mc_addr); 2364 2365 return ret; 2366 } 2367 2368 static int psp_load_smu_fw(struct psp_context *psp) 2369 { 2370 int ret; 2371 struct amdgpu_device *adev = psp->adev; 2372 struct amdgpu_firmware_info *ucode = 2373 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2374 struct amdgpu_ras *ras = psp->ras.ras; 2375 2376 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2377 return 0; 2378 2379 if ((amdgpu_in_reset(adev) && 2380 ras && adev->ras_enabled && 2381 (adev->asic_type == CHIP_ARCTURUS || 2382 adev->asic_type == CHIP_VEGA20))) { 2383 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2384 if (ret) { 2385 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2386 } 2387 } 2388 2389 ret = psp_execute_np_fw_load(psp, ucode); 2390 2391 if (ret) 2392 DRM_ERROR("PSP load smu failed!\n"); 2393 2394 return ret; 2395 } 2396 2397 static bool fw_load_skip_check(struct psp_context *psp, 2398 struct amdgpu_firmware_info *ucode) 2399 { 2400 if (!ucode->fw) 2401 return true; 2402 2403 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2404 (psp_smu_reload_quirk(psp) || 2405 psp->autoload_supported || 2406 psp->pmfw_centralized_cstate_management)) 2407 return true; 2408 2409 if (amdgpu_sriov_vf(psp->adev) && 2410 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2411 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2412 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2413 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2414 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2415 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2416 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2417 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2418 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2419 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2420 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2421 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2422 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2423 /*skip ucode loading in SRIOV VF */ 2424 return true; 2425 2426 if (psp->autoload_supported && 2427 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2428 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2429 /* skip mec JT when autoload is enabled */ 2430 return true; 2431 2432 return false; 2433 } 2434 2435 int psp_load_fw_list(struct psp_context *psp, 2436 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2437 { 2438 int ret = 0, i; 2439 struct amdgpu_firmware_info *ucode; 2440 2441 for (i = 0; i < ucode_count; ++i) { 2442 ucode = ucode_list[i]; 2443 psp_print_fw_hdr(psp, ucode); 2444 ret = psp_execute_np_fw_load(psp, ucode); 2445 if (ret) 2446 return ret; 2447 } 2448 return ret; 2449 } 2450 2451 static int psp_np_fw_load(struct psp_context *psp) 2452 { 2453 int i, ret; 2454 struct amdgpu_firmware_info *ucode; 2455 struct amdgpu_device *adev = psp->adev; 2456 2457 if (psp->autoload_supported && 2458 !psp->pmfw_centralized_cstate_management) { 2459 ret = psp_load_smu_fw(psp); 2460 if (ret) 2461 return ret; 2462 } 2463 2464 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2465 ucode = &adev->firmware.ucode[i]; 2466 2467 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2468 !fw_load_skip_check(psp, ucode)) { 2469 ret = psp_load_smu_fw(psp); 2470 if (ret) 2471 return ret; 2472 continue; 2473 } 2474 2475 if (fw_load_skip_check(psp, ucode)) 2476 continue; 2477 2478 if (psp->autoload_supported && 2479 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2480 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2481 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2482 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2483 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2484 /* PSP only receive one SDMA fw for sienna_cichlid, 2485 * as all four sdma fw are same */ 2486 continue; 2487 2488 psp_print_fw_hdr(psp, ucode); 2489 2490 ret = psp_execute_np_fw_load(psp, ucode); 2491 if (ret) 2492 return ret; 2493 2494 /* Start rlc autoload after psp recieved all the gfx firmware */ 2495 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2496 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2497 ret = psp_rlc_autoload_start(psp); 2498 if (ret) { 2499 DRM_ERROR("Failed to start rlc autoload\n"); 2500 return ret; 2501 } 2502 } 2503 } 2504 2505 return 0; 2506 } 2507 2508 static int psp_load_fw(struct amdgpu_device *adev) 2509 { 2510 int ret; 2511 struct psp_context *psp = &adev->psp; 2512 2513 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2514 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2515 goto skip_memalloc; 2516 } 2517 2518 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2519 if (!psp->cmd) 2520 return -ENOMEM; 2521 2522 if (amdgpu_sriov_vf(adev)) { 2523 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2524 AMDGPU_GEM_DOMAIN_VRAM, 2525 &psp->fw_pri_bo, 2526 &psp->fw_pri_mc_addr, 2527 &psp->fw_pri_buf); 2528 } else { 2529 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2530 AMDGPU_GEM_DOMAIN_GTT, 2531 &psp->fw_pri_bo, 2532 &psp->fw_pri_mc_addr, 2533 &psp->fw_pri_buf); 2534 } 2535 2536 if (ret) 2537 goto failed; 2538 2539 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2540 AMDGPU_GEM_DOMAIN_VRAM, 2541 &psp->fence_buf_bo, 2542 &psp->fence_buf_mc_addr, 2543 &psp->fence_buf); 2544 if (ret) 2545 goto failed; 2546 2547 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2548 AMDGPU_GEM_DOMAIN_VRAM, 2549 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2550 (void **)&psp->cmd_buf_mem); 2551 if (ret) 2552 goto failed; 2553 2554 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2555 2556 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2557 if (ret) { 2558 DRM_ERROR("PSP ring init failed!\n"); 2559 goto failed; 2560 } 2561 2562 skip_memalloc: 2563 ret = psp_hw_start(psp); 2564 if (ret) 2565 goto failed; 2566 2567 ret = psp_np_fw_load(psp); 2568 if (ret) 2569 goto failed; 2570 2571 ret = psp_asd_load(psp); 2572 if (ret) { 2573 DRM_ERROR("PSP load asd failed!\n"); 2574 return ret; 2575 } 2576 2577 ret = psp_rl_load(adev); 2578 if (ret) { 2579 DRM_ERROR("PSP load RL failed!\n"); 2580 return ret; 2581 } 2582 2583 if (psp->adev->psp.ta_fw) { 2584 ret = psp_ras_initialize(psp); 2585 if (ret) 2586 dev_err(psp->adev->dev, 2587 "RAS: Failed to initialize RAS\n"); 2588 2589 ret = psp_hdcp_initialize(psp); 2590 if (ret) 2591 dev_err(psp->adev->dev, 2592 "HDCP: Failed to initialize HDCP\n"); 2593 2594 ret = psp_dtm_initialize(psp); 2595 if (ret) 2596 dev_err(psp->adev->dev, 2597 "DTM: Failed to initialize DTM\n"); 2598 2599 ret = psp_rap_initialize(psp); 2600 if (ret) 2601 dev_err(psp->adev->dev, 2602 "RAP: Failed to initialize RAP\n"); 2603 2604 ret = psp_securedisplay_initialize(psp); 2605 if (ret) 2606 dev_err(psp->adev->dev, 2607 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2608 } 2609 2610 return 0; 2611 2612 failed: 2613 /* 2614 * all cleanup jobs (xgmi terminate, ras terminate, 2615 * ring destroy, cmd/fence/fw buffers destory, 2616 * psp->cmd destory) are delayed to psp_hw_fini 2617 */ 2618 return ret; 2619 } 2620 2621 static int psp_hw_init(void *handle) 2622 { 2623 int ret; 2624 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2625 2626 mutex_lock(&adev->firmware.mutex); 2627 /* 2628 * This sequence is just used on hw_init only once, no need on 2629 * resume. 2630 */ 2631 ret = amdgpu_ucode_init_bo(adev); 2632 if (ret) 2633 goto failed; 2634 2635 ret = psp_load_fw(adev); 2636 if (ret) { 2637 DRM_ERROR("PSP firmware loading failed\n"); 2638 goto failed; 2639 } 2640 2641 mutex_unlock(&adev->firmware.mutex); 2642 return 0; 2643 2644 failed: 2645 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2646 mutex_unlock(&adev->firmware.mutex); 2647 return -EINVAL; 2648 } 2649 2650 static int psp_hw_fini(void *handle) 2651 { 2652 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2653 struct psp_context *psp = &adev->psp; 2654 2655 if (psp->adev->psp.ta_fw) { 2656 psp_ras_terminate(psp); 2657 psp_securedisplay_terminate(psp); 2658 psp_rap_terminate(psp); 2659 psp_dtm_terminate(psp); 2660 psp_hdcp_terminate(psp); 2661 } 2662 2663 psp_asd_unload(psp); 2664 2665 psp_tmr_terminate(psp); 2666 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2667 2668 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2669 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2670 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2671 &psp->fence_buf_mc_addr, &psp->fence_buf); 2672 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2673 (void **)&psp->cmd_buf_mem); 2674 2675 kfree(psp->cmd); 2676 psp->cmd = NULL; 2677 2678 return 0; 2679 } 2680 2681 static int psp_suspend(void *handle) 2682 { 2683 int ret; 2684 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2685 struct psp_context *psp = &adev->psp; 2686 2687 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2688 psp->xgmi_context.initialized == 1) { 2689 ret = psp_xgmi_terminate(psp); 2690 if (ret) { 2691 DRM_ERROR("Failed to terminate xgmi ta\n"); 2692 return ret; 2693 } 2694 } 2695 2696 if (psp->adev->psp.ta_fw) { 2697 ret = psp_ras_terminate(psp); 2698 if (ret) { 2699 DRM_ERROR("Failed to terminate ras ta\n"); 2700 return ret; 2701 } 2702 ret = psp_hdcp_terminate(psp); 2703 if (ret) { 2704 DRM_ERROR("Failed to terminate hdcp ta\n"); 2705 return ret; 2706 } 2707 ret = psp_dtm_terminate(psp); 2708 if (ret) { 2709 DRM_ERROR("Failed to terminate dtm ta\n"); 2710 return ret; 2711 } 2712 ret = psp_rap_terminate(psp); 2713 if (ret) { 2714 DRM_ERROR("Failed to terminate rap ta\n"); 2715 return ret; 2716 } 2717 ret = psp_securedisplay_terminate(psp); 2718 if (ret) { 2719 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2720 return ret; 2721 } 2722 } 2723 2724 ret = psp_asd_unload(psp); 2725 if (ret) { 2726 DRM_ERROR("Failed to unload asd\n"); 2727 return ret; 2728 } 2729 2730 ret = psp_tmr_terminate(psp); 2731 if (ret) { 2732 DRM_ERROR("Failed to terminate tmr\n"); 2733 return ret; 2734 } 2735 2736 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2737 if (ret) { 2738 DRM_ERROR("PSP ring stop failed\n"); 2739 return ret; 2740 } 2741 2742 return 0; 2743 } 2744 2745 static int psp_resume(void *handle) 2746 { 2747 int ret; 2748 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2749 struct psp_context *psp = &adev->psp; 2750 2751 DRM_INFO("PSP is resuming...\n"); 2752 2753 if (psp->mem_train_ctx.enable_mem_training) { 2754 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2755 if (ret) { 2756 DRM_ERROR("Failed to process memory training!\n"); 2757 return ret; 2758 } 2759 } 2760 2761 mutex_lock(&adev->firmware.mutex); 2762 2763 ret = psp_hw_start(psp); 2764 if (ret) 2765 goto failed; 2766 2767 ret = psp_np_fw_load(psp); 2768 if (ret) 2769 goto failed; 2770 2771 ret = psp_asd_load(psp); 2772 if (ret) { 2773 DRM_ERROR("PSP load asd failed!\n"); 2774 goto failed; 2775 } 2776 2777 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2778 ret = psp_xgmi_initialize(psp); 2779 /* Warning the XGMI seesion initialize failure 2780 * Instead of stop driver initialization 2781 */ 2782 if (ret) 2783 dev_err(psp->adev->dev, 2784 "XGMI: Failed to initialize XGMI session\n"); 2785 } 2786 2787 if (psp->adev->psp.ta_fw) { 2788 ret = psp_ras_initialize(psp); 2789 if (ret) 2790 dev_err(psp->adev->dev, 2791 "RAS: Failed to initialize RAS\n"); 2792 2793 ret = psp_hdcp_initialize(psp); 2794 if (ret) 2795 dev_err(psp->adev->dev, 2796 "HDCP: Failed to initialize HDCP\n"); 2797 2798 ret = psp_dtm_initialize(psp); 2799 if (ret) 2800 dev_err(psp->adev->dev, 2801 "DTM: Failed to initialize DTM\n"); 2802 2803 ret = psp_rap_initialize(psp); 2804 if (ret) 2805 dev_err(psp->adev->dev, 2806 "RAP: Failed to initialize RAP\n"); 2807 2808 ret = psp_securedisplay_initialize(psp); 2809 if (ret) 2810 dev_err(psp->adev->dev, 2811 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2812 } 2813 2814 mutex_unlock(&adev->firmware.mutex); 2815 2816 return 0; 2817 2818 failed: 2819 DRM_ERROR("PSP resume failed\n"); 2820 mutex_unlock(&adev->firmware.mutex); 2821 return ret; 2822 } 2823 2824 int psp_gpu_reset(struct amdgpu_device *adev) 2825 { 2826 int ret; 2827 2828 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2829 return 0; 2830 2831 mutex_lock(&adev->psp.mutex); 2832 ret = psp_mode1_reset(&adev->psp); 2833 mutex_unlock(&adev->psp.mutex); 2834 2835 return ret; 2836 } 2837 2838 int psp_rlc_autoload_start(struct psp_context *psp) 2839 { 2840 int ret; 2841 struct psp_gfx_cmd_resp *cmd; 2842 2843 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2844 if (!cmd) 2845 return -ENOMEM; 2846 2847 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2848 2849 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2850 psp->fence_buf_mc_addr); 2851 kfree(cmd); 2852 return ret; 2853 } 2854 2855 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2856 uint64_t cmd_gpu_addr, int cmd_size) 2857 { 2858 struct amdgpu_firmware_info ucode = {0}; 2859 2860 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2861 AMDGPU_UCODE_ID_VCN0_RAM; 2862 ucode.mc_addr = cmd_gpu_addr; 2863 ucode.ucode_size = cmd_size; 2864 2865 return psp_execute_np_fw_load(&adev->psp, &ucode); 2866 } 2867 2868 int psp_ring_cmd_submit(struct psp_context *psp, 2869 uint64_t cmd_buf_mc_addr, 2870 uint64_t fence_mc_addr, 2871 int index) 2872 { 2873 unsigned int psp_write_ptr_reg = 0; 2874 struct psp_gfx_rb_frame *write_frame; 2875 struct psp_ring *ring = &psp->km_ring; 2876 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2877 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2878 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2879 struct amdgpu_device *adev = psp->adev; 2880 uint32_t ring_size_dw = ring->ring_size / 4; 2881 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2882 2883 /* KM (GPCOM) prepare write pointer */ 2884 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2885 2886 /* Update KM RB frame pointer to new frame */ 2887 /* write_frame ptr increments by size of rb_frame in bytes */ 2888 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2889 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2890 write_frame = ring_buffer_start; 2891 else 2892 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2893 /* Check invalid write_frame ptr address */ 2894 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2895 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2896 ring_buffer_start, ring_buffer_end, write_frame); 2897 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2898 return -EINVAL; 2899 } 2900 2901 /* Initialize KM RB frame */ 2902 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2903 2904 /* Update KM RB frame */ 2905 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2906 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2907 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2908 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2909 write_frame->fence_value = index; 2910 amdgpu_device_flush_hdp(adev, NULL); 2911 2912 /* Update the write Pointer in DWORDs */ 2913 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2914 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2915 return 0; 2916 } 2917 2918 int psp_init_asd_microcode(struct psp_context *psp, 2919 const char *chip_name) 2920 { 2921 struct amdgpu_device *adev = psp->adev; 2922 char fw_name[PSP_FW_NAME_LEN]; 2923 const struct psp_firmware_header_v1_0 *asd_hdr; 2924 int err = 0; 2925 2926 if (!chip_name) { 2927 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2928 return -EINVAL; 2929 } 2930 2931 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2932 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2933 if (err) 2934 goto out; 2935 2936 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2937 if (err) 2938 goto out; 2939 2940 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2941 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2942 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2943 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2944 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2945 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2946 return 0; 2947 out: 2948 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2949 release_firmware(adev->psp.asd_fw); 2950 adev->psp.asd_fw = NULL; 2951 return err; 2952 } 2953 2954 int psp_init_toc_microcode(struct psp_context *psp, 2955 const char *chip_name) 2956 { 2957 struct amdgpu_device *adev = psp->adev; 2958 char fw_name[30]; 2959 const struct psp_firmware_header_v1_0 *toc_hdr; 2960 int err = 0; 2961 2962 if (!chip_name) { 2963 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2964 return -EINVAL; 2965 } 2966 2967 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2968 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2969 if (err) 2970 goto out; 2971 2972 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2973 if (err) 2974 goto out; 2975 2976 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2977 adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2978 adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2979 adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2980 adev->psp.toc_start_addr = (uint8_t *)toc_hdr + 2981 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2982 return 0; 2983 out: 2984 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2985 release_firmware(adev->psp.toc_fw); 2986 adev->psp.toc_fw = NULL; 2987 return err; 2988 } 2989 2990 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 2991 { 2992 const struct psp_firmware_header_v1_0 *sos_hdr; 2993 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2994 uint8_t *ucode_array_start_addr; 2995 2996 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2997 ucode_array_start_addr = (uint8_t *)sos_hdr + 2998 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2999 3000 if (adev->gmc.xgmi.connected_to_cpu || (adev->asic_type != CHIP_ALDEBARAN)) { 3001 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3002 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3003 3004 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos.offset_bytes); 3005 adev->psp.sys_start_addr = ucode_array_start_addr; 3006 3007 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos.size_bytes); 3008 adev->psp.sos_start_addr = ucode_array_start_addr + 3009 le32_to_cpu(sos_hdr->sos.offset_bytes); 3010 } else { 3011 /* Load alternate PSP SOS FW */ 3012 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3013 3014 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3015 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3016 3017 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3018 adev->psp.sys_start_addr = ucode_array_start_addr + 3019 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3020 3021 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3022 adev->psp.sos_start_addr = ucode_array_start_addr + 3023 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3024 } 3025 3026 if ((adev->psp.sys_bin_size == 0) || (adev->psp.sos_bin_size == 0)) { 3027 dev_warn(adev->dev, "PSP SOS FW not available"); 3028 return -EINVAL; 3029 } 3030 3031 return 0; 3032 } 3033 3034 int psp_init_sos_microcode(struct psp_context *psp, 3035 const char *chip_name) 3036 { 3037 struct amdgpu_device *adev = psp->adev; 3038 char fw_name[PSP_FW_NAME_LEN]; 3039 const struct psp_firmware_header_v1_0 *sos_hdr; 3040 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3041 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3042 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3043 int err = 0; 3044 uint8_t *ucode_array_start_addr; 3045 3046 if (!chip_name) { 3047 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3048 return -EINVAL; 3049 } 3050 3051 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3052 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3053 if (err) 3054 goto out; 3055 3056 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3057 if (err) 3058 goto out; 3059 3060 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3061 ucode_array_start_addr = (uint8_t *)sos_hdr + 3062 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3063 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3064 3065 switch (sos_hdr->header.header_version_major) { 3066 case 1: 3067 err = psp_init_sos_base_fw(adev); 3068 if (err) 3069 goto out; 3070 3071 if (sos_hdr->header.header_version_minor == 1) { 3072 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3073 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3074 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 3075 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3076 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3077 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 3078 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3079 } 3080 if (sos_hdr->header.header_version_minor == 2) { 3081 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3082 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3083 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 3084 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3085 } 3086 if (sos_hdr->header.header_version_minor == 3) { 3087 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3088 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3089 adev->psp.toc_start_addr = ucode_array_start_addr + 3090 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3091 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3092 adev->psp.kdb_start_addr = ucode_array_start_addr + 3093 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3094 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3095 adev->psp.spl_start_addr = ucode_array_start_addr + 3096 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3097 adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3098 adev->psp.rl_start_addr = ucode_array_start_addr + 3099 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3100 } 3101 break; 3102 default: 3103 dev_err(adev->dev, 3104 "unsupported psp sos firmware\n"); 3105 err = -EINVAL; 3106 goto out; 3107 } 3108 3109 return 0; 3110 out: 3111 dev_err(adev->dev, 3112 "failed to init sos firmware\n"); 3113 release_firmware(adev->psp.sos_fw); 3114 adev->psp.sos_fw = NULL; 3115 3116 return err; 3117 } 3118 3119 static int parse_ta_bin_descriptor(struct psp_context *psp, 3120 const struct ta_fw_bin_desc *desc, 3121 const struct ta_firmware_header_v2_0 *ta_hdr) 3122 { 3123 uint8_t *ucode_start_addr = NULL; 3124 3125 if (!psp || !desc || !ta_hdr) 3126 return -EINVAL; 3127 3128 ucode_start_addr = (uint8_t *)ta_hdr + 3129 le32_to_cpu(desc->offset_bytes) + 3130 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3131 3132 switch (desc->fw_type) { 3133 case TA_FW_TYPE_PSP_ASD: 3134 psp->asd_fw_version = le32_to_cpu(desc->fw_version); 3135 psp->asd_feature_version = le32_to_cpu(desc->fw_version); 3136 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 3137 psp->asd_start_addr = ucode_start_addr; 3138 break; 3139 case TA_FW_TYPE_PSP_XGMI: 3140 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 3141 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 3142 psp->ta_xgmi_start_addr = ucode_start_addr; 3143 break; 3144 case TA_FW_TYPE_PSP_RAS: 3145 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 3146 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 3147 psp->ta_ras_start_addr = ucode_start_addr; 3148 break; 3149 case TA_FW_TYPE_PSP_HDCP: 3150 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 3151 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 3152 psp->ta_hdcp_start_addr = ucode_start_addr; 3153 break; 3154 case TA_FW_TYPE_PSP_DTM: 3155 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 3156 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 3157 psp->ta_dtm_start_addr = ucode_start_addr; 3158 break; 3159 case TA_FW_TYPE_PSP_RAP: 3160 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version); 3161 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes); 3162 psp->ta_rap_start_addr = ucode_start_addr; 3163 break; 3164 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3165 psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version); 3166 psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes); 3167 psp->ta_securedisplay_start_addr = ucode_start_addr; 3168 break; 3169 default: 3170 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3171 break; 3172 } 3173 3174 return 0; 3175 } 3176 3177 int psp_init_ta_microcode(struct psp_context *psp, 3178 const char *chip_name) 3179 { 3180 struct amdgpu_device *adev = psp->adev; 3181 char fw_name[PSP_FW_NAME_LEN]; 3182 const struct ta_firmware_header_v2_0 *ta_hdr; 3183 int err = 0; 3184 int ta_index = 0; 3185 3186 if (!chip_name) { 3187 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3188 return -EINVAL; 3189 } 3190 3191 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3192 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3193 if (err) 3194 goto out; 3195 3196 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3197 if (err) 3198 goto out; 3199 3200 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3201 3202 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3203 dev_err(adev->dev, "unsupported TA header version\n"); 3204 err = -EINVAL; 3205 goto out; 3206 } 3207 3208 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) { 3209 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3210 err = -EINVAL; 3211 goto out; 3212 } 3213 3214 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3215 err = parse_ta_bin_descriptor(psp, 3216 &ta_hdr->ta_fw_bin[ta_index], 3217 ta_hdr); 3218 if (err) 3219 goto out; 3220 } 3221 3222 return 0; 3223 out: 3224 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3225 release_firmware(adev->psp.ta_fw); 3226 adev->psp.ta_fw = NULL; 3227 return err; 3228 } 3229 3230 static int psp_set_clockgating_state(void *handle, 3231 enum amd_clockgating_state state) 3232 { 3233 return 0; 3234 } 3235 3236 static int psp_set_powergating_state(void *handle, 3237 enum amd_powergating_state state) 3238 { 3239 return 0; 3240 } 3241 3242 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3243 struct device_attribute *attr, 3244 char *buf) 3245 { 3246 struct drm_device *ddev = dev_get_drvdata(dev); 3247 struct amdgpu_device *adev = drm_to_adev(ddev); 3248 uint32_t fw_ver; 3249 int ret; 3250 3251 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3252 DRM_INFO("PSP block is not ready yet."); 3253 return -EBUSY; 3254 } 3255 3256 mutex_lock(&adev->psp.mutex); 3257 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3258 mutex_unlock(&adev->psp.mutex); 3259 3260 if (ret) { 3261 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3262 return ret; 3263 } 3264 3265 return sysfs_emit(buf, "%x\n", fw_ver); 3266 } 3267 3268 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3269 struct device_attribute *attr, 3270 const char *buf, 3271 size_t count) 3272 { 3273 struct drm_device *ddev = dev_get_drvdata(dev); 3274 struct amdgpu_device *adev = drm_to_adev(ddev); 3275 int ret, idx; 3276 char fw_name[100]; 3277 const struct firmware *usbc_pd_fw; 3278 struct amdgpu_bo *fw_buf_bo = NULL; 3279 uint64_t fw_pri_mc_addr; 3280 void *fw_pri_cpu_addr; 3281 3282 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3283 DRM_INFO("PSP block is not ready yet."); 3284 return -EBUSY; 3285 } 3286 3287 if (!drm_dev_enter(ddev, &idx)) 3288 return -ENODEV; 3289 3290 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3291 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3292 if (ret) 3293 goto fail; 3294 3295 /* LFB address which is aligned to 1MB boundary per PSP request */ 3296 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3297 AMDGPU_GEM_DOMAIN_VRAM, 3298 &fw_buf_bo, 3299 &fw_pri_mc_addr, 3300 &fw_pri_cpu_addr); 3301 if (ret) 3302 goto rel_buf; 3303 3304 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3305 3306 mutex_lock(&adev->psp.mutex); 3307 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3308 mutex_unlock(&adev->psp.mutex); 3309 3310 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3311 3312 rel_buf: 3313 release_firmware(usbc_pd_fw); 3314 fail: 3315 if (ret) { 3316 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3317 count = ret; 3318 } 3319 3320 drm_dev_exit(idx); 3321 return count; 3322 } 3323 3324 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3325 { 3326 int idx; 3327 3328 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 3329 return; 3330 3331 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3332 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3333 3334 drm_dev_exit(idx); 3335 } 3336 3337 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3338 psp_usbc_pd_fw_sysfs_read, 3339 psp_usbc_pd_fw_sysfs_write); 3340 3341 3342 3343 const struct amd_ip_funcs psp_ip_funcs = { 3344 .name = "psp", 3345 .early_init = psp_early_init, 3346 .late_init = NULL, 3347 .sw_init = psp_sw_init, 3348 .sw_fini = psp_sw_fini, 3349 .hw_init = psp_hw_init, 3350 .hw_fini = psp_hw_fini, 3351 .suspend = psp_suspend, 3352 .resume = psp_resume, 3353 .is_idle = NULL, 3354 .check_soft_reset = NULL, 3355 .wait_for_idle = NULL, 3356 .soft_reset = NULL, 3357 .set_clockgating_state = psp_set_clockgating_state, 3358 .set_powergating_state = psp_set_powergating_state, 3359 }; 3360 3361 static int psp_sysfs_init(struct amdgpu_device *adev) 3362 { 3363 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3364 3365 if (ret) 3366 DRM_ERROR("Failed to create USBC PD FW control file!"); 3367 3368 return ret; 3369 } 3370 3371 static void psp_sysfs_fini(struct amdgpu_device *adev) 3372 { 3373 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3374 } 3375 3376 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3377 { 3378 .type = AMD_IP_BLOCK_TYPE_PSP, 3379 .major = 3, 3380 .minor = 1, 3381 .rev = 0, 3382 .funcs = &psp_ip_funcs, 3383 }; 3384 3385 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3386 { 3387 .type = AMD_IP_BLOCK_TYPE_PSP, 3388 .major = 10, 3389 .minor = 0, 3390 .rev = 0, 3391 .funcs = &psp_ip_funcs, 3392 }; 3393 3394 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3395 { 3396 .type = AMD_IP_BLOCK_TYPE_PSP, 3397 .major = 11, 3398 .minor = 0, 3399 .rev = 0, 3400 .funcs = &psp_ip_funcs, 3401 }; 3402 3403 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3404 { 3405 .type = AMD_IP_BLOCK_TYPE_PSP, 3406 .major = 12, 3407 .minor = 0, 3408 .rev = 0, 3409 .funcs = &psp_ip_funcs, 3410 }; 3411 3412 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3413 .type = AMD_IP_BLOCK_TYPE_PSP, 3414 .major = 13, 3415 .minor = 0, 3416 .rev = 0, 3417 .funcs = &psp_ip_funcs, 3418 }; 3419