1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 42 #include "amdgpu_ras.h" 43 #include "amdgpu_securedisplay.h" 44 #include "amdgpu_atomfirmware.h" 45 46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 47 48 static int psp_sysfs_init(struct amdgpu_device *adev); 49 static void psp_sysfs_fini(struct amdgpu_device *adev); 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 static int psp_ring_init(struct psp_context *psp, 56 enum psp_ring_type ring_type) 57 { 58 int ret = 0; 59 struct psp_ring *ring; 60 struct amdgpu_device *adev = psp->adev; 61 62 ring = &psp->km_ring; 63 64 ring->ring_type = ring_type; 65 66 /* allocate 4k Page of Local Frame Buffer memory for ring */ 67 ring->ring_size = 0x1000; 68 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 69 AMDGPU_GEM_DOMAIN_VRAM | 70 AMDGPU_GEM_DOMAIN_GTT, 71 &adev->firmware.rbuf, 72 &ring->ring_mem_mc_addr, 73 (void **)&ring->ring_mem); 74 if (ret) { 75 ring->ring_size = 0; 76 return ret; 77 } 78 79 return 0; 80 } 81 82 /* 83 * Due to DF Cstate management centralized to PMFW, the firmware 84 * loading sequence will be updated as below: 85 * - Load KDB 86 * - Load SYS_DRV 87 * - Load tOS 88 * - Load PMFW 89 * - Setup TMR 90 * - Load other non-psp fw 91 * - Load ASD 92 * - Load XGMI/RAS/HDCP/DTM TA if any 93 * 94 * This new sequence is required for 95 * - Arcturus and onwards 96 */ 97 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 98 { 99 struct amdgpu_device *adev = psp->adev; 100 101 if (amdgpu_sriov_vf(adev)) { 102 psp->pmfw_centralized_cstate_management = false; 103 return; 104 } 105 106 switch (adev->ip_versions[MP0_HWIP][0]) { 107 case IP_VERSION(11, 0, 0): 108 case IP_VERSION(11, 0, 4): 109 case IP_VERSION(11, 0, 5): 110 case IP_VERSION(11, 0, 7): 111 case IP_VERSION(11, 0, 9): 112 case IP_VERSION(11, 0, 11): 113 case IP_VERSION(11, 0, 12): 114 case IP_VERSION(11, 0, 13): 115 case IP_VERSION(13, 0, 0): 116 case IP_VERSION(13, 0, 2): 117 case IP_VERSION(13, 0, 7): 118 psp->pmfw_centralized_cstate_management = true; 119 break; 120 default: 121 psp->pmfw_centralized_cstate_management = false; 122 break; 123 } 124 } 125 126 static int psp_init_sriov_microcode(struct psp_context *psp) 127 { 128 struct amdgpu_device *adev = psp->adev; 129 char ucode_prefix[30]; 130 int ret = 0; 131 132 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 133 134 switch (adev->ip_versions[MP0_HWIP][0]) { 135 case IP_VERSION(9, 0, 0): 136 case IP_VERSION(11, 0, 7): 137 case IP_VERSION(11, 0, 9): 138 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 139 ret = psp_init_cap_microcode(psp, ucode_prefix); 140 break; 141 case IP_VERSION(13, 0, 2): 142 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 143 ret = psp_init_cap_microcode(psp, ucode_prefix); 144 ret &= psp_init_ta_microcode(psp, ucode_prefix); 145 break; 146 case IP_VERSION(13, 0, 0): 147 adev->virt.autoload_ucode_id = 0; 148 break; 149 case IP_VERSION(13, 0, 10): 150 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 151 ret = psp_init_cap_microcode(psp, ucode_prefix); 152 break; 153 default: 154 return -EINVAL; 155 } 156 return ret; 157 } 158 159 static int psp_early_init(void *handle) 160 { 161 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 162 struct psp_context *psp = &adev->psp; 163 164 switch (adev->ip_versions[MP0_HWIP][0]) { 165 case IP_VERSION(9, 0, 0): 166 psp_v3_1_set_psp_funcs(psp); 167 psp->autoload_supported = false; 168 break; 169 case IP_VERSION(10, 0, 0): 170 case IP_VERSION(10, 0, 1): 171 psp_v10_0_set_psp_funcs(psp); 172 psp->autoload_supported = false; 173 break; 174 case IP_VERSION(11, 0, 2): 175 case IP_VERSION(11, 0, 4): 176 psp_v11_0_set_psp_funcs(psp); 177 psp->autoload_supported = false; 178 break; 179 case IP_VERSION(11, 0, 0): 180 case IP_VERSION(11, 0, 5): 181 case IP_VERSION(11, 0, 9): 182 case IP_VERSION(11, 0, 7): 183 case IP_VERSION(11, 0, 11): 184 case IP_VERSION(11, 5, 0): 185 case IP_VERSION(11, 0, 12): 186 case IP_VERSION(11, 0, 13): 187 psp_v11_0_set_psp_funcs(psp); 188 psp->autoload_supported = true; 189 break; 190 case IP_VERSION(11, 0, 3): 191 case IP_VERSION(12, 0, 1): 192 psp_v12_0_set_psp_funcs(psp); 193 break; 194 case IP_VERSION(13, 0, 2): 195 case IP_VERSION(13, 0, 6): 196 psp_v13_0_set_psp_funcs(psp); 197 break; 198 case IP_VERSION(13, 0, 1): 199 case IP_VERSION(13, 0, 3): 200 case IP_VERSION(13, 0, 5): 201 case IP_VERSION(13, 0, 8): 202 case IP_VERSION(13, 0, 10): 203 case IP_VERSION(13, 0, 11): 204 psp_v13_0_set_psp_funcs(psp); 205 psp->autoload_supported = true; 206 break; 207 case IP_VERSION(11, 0, 8): 208 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 209 psp_v11_0_8_set_psp_funcs(psp); 210 psp->autoload_supported = false; 211 } 212 break; 213 case IP_VERSION(13, 0, 0): 214 case IP_VERSION(13, 0, 7): 215 psp_v13_0_set_psp_funcs(psp); 216 psp->autoload_supported = true; 217 break; 218 case IP_VERSION(13, 0, 4): 219 psp_v13_0_4_set_psp_funcs(psp); 220 psp->autoload_supported = true; 221 break; 222 default: 223 return -EINVAL; 224 } 225 226 psp->adev = adev; 227 228 psp_check_pmfw_centralized_cstate_management(psp); 229 230 if (amdgpu_sriov_vf(adev)) 231 return psp_init_sriov_microcode(psp); 232 else 233 return psp_init_microcode(psp); 234 } 235 236 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 237 { 238 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 239 &mem_ctx->shared_buf); 240 mem_ctx->shared_bo = NULL; 241 } 242 243 static void psp_free_shared_bufs(struct psp_context *psp) 244 { 245 void *tmr_buf; 246 void **pptr; 247 248 /* free TMR memory buffer */ 249 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 250 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 251 psp->tmr_bo = NULL; 252 253 /* free xgmi shared memory */ 254 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 255 256 /* free ras shared memory */ 257 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 258 259 /* free hdcp shared memory */ 260 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 261 262 /* free dtm shared memory */ 263 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 264 265 /* free rap shared memory */ 266 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 267 268 /* free securedisplay shared memory */ 269 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 270 271 272 } 273 274 static void psp_memory_training_fini(struct psp_context *psp) 275 { 276 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 277 278 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 279 kfree(ctx->sys_cache); 280 ctx->sys_cache = NULL; 281 } 282 283 static int psp_memory_training_init(struct psp_context *psp) 284 { 285 int ret; 286 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 287 288 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 289 DRM_DEBUG("memory training is not supported!\n"); 290 return 0; 291 } 292 293 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 294 if (ctx->sys_cache == NULL) { 295 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 296 ret = -ENOMEM; 297 goto Err_out; 298 } 299 300 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 301 ctx->train_data_size, 302 ctx->p2c_train_data_offset, 303 ctx->c2p_train_data_offset); 304 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 305 return 0; 306 307 Err_out: 308 psp_memory_training_fini(psp); 309 return ret; 310 } 311 312 /* 313 * Helper funciton to query psp runtime database entry 314 * 315 * @adev: amdgpu_device pointer 316 * @entry_type: the type of psp runtime database entry 317 * @db_entry: runtime database entry pointer 318 * 319 * Return false if runtime database doesn't exit or entry is invalid 320 * or true if the specific database entry is found, and copy to @db_entry 321 */ 322 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 323 enum psp_runtime_entry_type entry_type, 324 void *db_entry) 325 { 326 uint64_t db_header_pos, db_dir_pos; 327 struct psp_runtime_data_header db_header = {0}; 328 struct psp_runtime_data_directory db_dir = {0}; 329 bool ret = false; 330 int i; 331 332 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) 333 return false; 334 335 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 336 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 337 338 /* read runtime db header from vram */ 339 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 340 sizeof(struct psp_runtime_data_header), false); 341 342 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 343 /* runtime db doesn't exist, exit */ 344 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 345 return false; 346 } 347 348 /* read runtime database entry from vram */ 349 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 350 sizeof(struct psp_runtime_data_directory), false); 351 352 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 353 /* invalid db entry count, exit */ 354 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 355 return false; 356 } 357 358 /* look up for requested entry type */ 359 for (i = 0; i < db_dir.entry_count && !ret; i++) { 360 if (db_dir.entry_list[i].entry_type == entry_type) { 361 switch (entry_type) { 362 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 363 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 364 /* invalid db entry size */ 365 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 366 return false; 367 } 368 /* read runtime database entry */ 369 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 370 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 371 ret = true; 372 break; 373 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 374 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 375 /* invalid db entry size */ 376 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 377 return false; 378 } 379 /* read runtime database entry */ 380 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 381 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 382 ret = true; 383 break; 384 default: 385 ret = false; 386 break; 387 } 388 } 389 } 390 391 return ret; 392 } 393 394 static int psp_sw_init(void *handle) 395 { 396 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 397 struct psp_context *psp = &adev->psp; 398 int ret; 399 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 400 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 401 struct psp_runtime_scpm_entry scpm_entry; 402 403 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 404 if (!psp->cmd) { 405 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 406 ret = -ENOMEM; 407 } 408 409 adev->psp.xgmi_context.supports_extended_data = 410 !adev->gmc.xgmi.connected_to_cpu && 411 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 412 413 memset(&scpm_entry, 0, sizeof(scpm_entry)); 414 if ((psp_get_runtime_db_entry(adev, 415 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 416 &scpm_entry)) && 417 (scpm_entry.scpm_status != SCPM_DISABLE)) { 418 adev->scpm_enabled = true; 419 adev->scpm_status = scpm_entry.scpm_status; 420 } else { 421 adev->scpm_enabled = false; 422 adev->scpm_status = SCPM_DISABLE; 423 } 424 425 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 426 427 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 428 if (psp_get_runtime_db_entry(adev, 429 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 430 &boot_cfg_entry)) { 431 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 432 if ((psp->boot_cfg_bitmask) & 433 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 434 /* If psp runtime database exists, then 435 * only enable two stage memory training 436 * when TWO_STAGE_DRAM_TRAINING bit is set 437 * in runtime database */ 438 mem_training_ctx->enable_mem_training = true; 439 } 440 441 } else { 442 /* If psp runtime database doesn't exist or 443 * is invalid, force enable two stage memory 444 * training */ 445 mem_training_ctx->enable_mem_training = true; 446 } 447 448 if (mem_training_ctx->enable_mem_training) { 449 ret = psp_memory_training_init(psp); 450 if (ret) { 451 DRM_ERROR("Failed to initialize memory training!\n"); 452 return ret; 453 } 454 455 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 456 if (ret) { 457 DRM_ERROR("Failed to process memory training!\n"); 458 return ret; 459 } 460 } 461 462 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 463 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 464 ret = psp_sysfs_init(adev); 465 if (ret) 466 return ret; 467 } 468 469 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 470 amdgpu_sriov_vf(adev) ? 471 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 472 &psp->fw_pri_bo, 473 &psp->fw_pri_mc_addr, 474 &psp->fw_pri_buf); 475 if (ret) 476 return ret; 477 478 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 479 AMDGPU_GEM_DOMAIN_VRAM, 480 &psp->fence_buf_bo, 481 &psp->fence_buf_mc_addr, 482 &psp->fence_buf); 483 if (ret) 484 goto failed1; 485 486 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 487 AMDGPU_GEM_DOMAIN_VRAM, 488 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 489 (void **)&psp->cmd_buf_mem); 490 if (ret) 491 goto failed2; 492 493 return 0; 494 495 failed2: 496 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 497 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 498 failed1: 499 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 500 &psp->fence_buf_mc_addr, &psp->fence_buf); 501 return ret; 502 } 503 504 static int psp_sw_fini(void *handle) 505 { 506 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 507 struct psp_context *psp = &adev->psp; 508 struct psp_gfx_cmd_resp *cmd = psp->cmd; 509 510 psp_memory_training_fini(psp); 511 512 amdgpu_ucode_release(&psp->sos_fw); 513 amdgpu_ucode_release(&psp->asd_fw); 514 amdgpu_ucode_release(&psp->ta_fw); 515 amdgpu_ucode_release(&psp->cap_fw); 516 amdgpu_ucode_release(&psp->toc_fw); 517 518 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 519 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 520 psp_sysfs_fini(adev); 521 522 kfree(cmd); 523 cmd = NULL; 524 525 psp_free_shared_bufs(psp); 526 527 if (psp->km_ring.ring_mem) 528 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 529 &psp->km_ring.ring_mem_mc_addr, 530 (void **)&psp->km_ring.ring_mem); 531 532 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 533 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 534 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 535 &psp->fence_buf_mc_addr, &psp->fence_buf); 536 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 537 (void **)&psp->cmd_buf_mem); 538 539 return 0; 540 } 541 542 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 543 uint32_t reg_val, uint32_t mask, bool check_changed) 544 { 545 uint32_t val; 546 int i; 547 struct amdgpu_device *adev = psp->adev; 548 549 if (psp->adev->no_hw_access) 550 return 0; 551 552 for (i = 0; i < adev->usec_timeout; i++) { 553 val = RREG32(reg_index); 554 if (check_changed) { 555 if (val != reg_val) 556 return 0; 557 } else { 558 if ((val & mask) == reg_val) 559 return 0; 560 } 561 udelay(1); 562 } 563 564 return -ETIME; 565 } 566 567 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 568 { 569 switch (cmd_id) { 570 case GFX_CMD_ID_LOAD_TA: 571 return "LOAD_TA"; 572 case GFX_CMD_ID_UNLOAD_TA: 573 return "UNLOAD_TA"; 574 case GFX_CMD_ID_INVOKE_CMD: 575 return "INVOKE_CMD"; 576 case GFX_CMD_ID_LOAD_ASD: 577 return "LOAD_ASD"; 578 case GFX_CMD_ID_SETUP_TMR: 579 return "SETUP_TMR"; 580 case GFX_CMD_ID_LOAD_IP_FW: 581 return "LOAD_IP_FW"; 582 case GFX_CMD_ID_DESTROY_TMR: 583 return "DESTROY_TMR"; 584 case GFX_CMD_ID_SAVE_RESTORE: 585 return "SAVE_RESTORE_IP_FW"; 586 case GFX_CMD_ID_SETUP_VMR: 587 return "SETUP_VMR"; 588 case GFX_CMD_ID_DESTROY_VMR: 589 return "DESTROY_VMR"; 590 case GFX_CMD_ID_PROG_REG: 591 return "PROG_REG"; 592 case GFX_CMD_ID_GET_FW_ATTESTATION: 593 return "GET_FW_ATTESTATION"; 594 case GFX_CMD_ID_LOAD_TOC: 595 return "ID_LOAD_TOC"; 596 case GFX_CMD_ID_AUTOLOAD_RLC: 597 return "AUTOLOAD_RLC"; 598 case GFX_CMD_ID_BOOT_CFG: 599 return "BOOT_CFG"; 600 default: 601 return "UNKNOWN CMD"; 602 } 603 } 604 605 static int 606 psp_cmd_submit_buf(struct psp_context *psp, 607 struct amdgpu_firmware_info *ucode, 608 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 609 { 610 int ret; 611 int index; 612 int timeout = 20000; 613 bool ras_intr = false; 614 bool skip_unsupport = false; 615 616 if (psp->adev->no_hw_access) 617 return 0; 618 619 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 620 621 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 622 623 index = atomic_inc_return(&psp->fence_value); 624 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 625 if (ret) { 626 atomic_dec(&psp->fence_value); 627 goto exit; 628 } 629 630 amdgpu_device_invalidate_hdp(psp->adev, NULL); 631 while (*((unsigned int *)psp->fence_buf) != index) { 632 if (--timeout == 0) 633 break; 634 /* 635 * Shouldn't wait for timeout when err_event_athub occurs, 636 * because gpu reset thread triggered and lock resource should 637 * be released for psp resume sequence. 638 */ 639 ras_intr = amdgpu_ras_intr_triggered(); 640 if (ras_intr) 641 break; 642 usleep_range(10, 100); 643 amdgpu_device_invalidate_hdp(psp->adev, NULL); 644 } 645 646 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 647 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 648 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 649 650 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 651 652 /* In some cases, psp response status is not 0 even there is no 653 * problem while the command is submitted. Some version of PSP FW 654 * doesn't write 0 to that field. 655 * So here we would like to only print a warning instead of an error 656 * during psp initialization to avoid breaking hw_init and it doesn't 657 * return -EINVAL. 658 */ 659 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 660 if (ucode) 661 DRM_WARN("failed to load ucode %s(0x%X) ", 662 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 663 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 664 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 665 psp->cmd_buf_mem->resp.status); 666 /* If any firmware (including CAP) load fails under SRIOV, it should 667 * return failure to stop the VF from initializing. 668 * Also return failure in case of timeout 669 */ 670 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 671 ret = -EINVAL; 672 goto exit; 673 } 674 } 675 676 if (ucode) { 677 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 678 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 679 } 680 681 exit: 682 return ret; 683 } 684 685 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 686 { 687 struct psp_gfx_cmd_resp *cmd = psp->cmd; 688 689 mutex_lock(&psp->mutex); 690 691 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 692 693 return cmd; 694 } 695 696 static void release_psp_cmd_buf(struct psp_context *psp) 697 { 698 mutex_unlock(&psp->mutex); 699 } 700 701 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 702 struct psp_gfx_cmd_resp *cmd, 703 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 704 { 705 struct amdgpu_device *adev = psp->adev; 706 uint32_t size = 0; 707 uint64_t tmr_pa = 0; 708 709 if (tmr_bo) { 710 size = amdgpu_bo_size(tmr_bo); 711 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 712 } 713 714 if (amdgpu_sriov_vf(psp->adev)) 715 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 716 else 717 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 718 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 719 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 720 cmd->cmd.cmd_setup_tmr.buf_size = size; 721 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 722 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 723 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 724 } 725 726 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 727 uint64_t pri_buf_mc, uint32_t size) 728 { 729 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 730 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 731 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 732 cmd->cmd.cmd_load_toc.toc_size = size; 733 } 734 735 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 736 static int psp_load_toc(struct psp_context *psp, 737 uint32_t *tmr_size) 738 { 739 int ret; 740 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 741 742 /* Copy toc to psp firmware private buffer */ 743 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 744 745 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 746 747 ret = psp_cmd_submit_buf(psp, NULL, cmd, 748 psp->fence_buf_mc_addr); 749 if (!ret) 750 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 751 752 release_psp_cmd_buf(psp); 753 754 return ret; 755 } 756 757 static bool psp_boottime_tmr(struct psp_context *psp) 758 { 759 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 760 case IP_VERSION(13, 0, 6): 761 return true; 762 default: 763 return false; 764 } 765 } 766 767 /* Set up Trusted Memory Region */ 768 static int psp_tmr_init(struct psp_context *psp) 769 { 770 int ret = 0; 771 int tmr_size; 772 void *tmr_buf; 773 void **pptr; 774 775 /* 776 * According to HW engineer, they prefer the TMR address be "naturally 777 * aligned" , e.g. the start address be an integer divide of TMR size. 778 * 779 * Note: this memory need be reserved till the driver 780 * uninitializes. 781 */ 782 tmr_size = PSP_TMR_SIZE(psp->adev); 783 784 /* For ASICs support RLC autoload, psp will parse the toc 785 * and calculate the total size of TMR needed */ 786 if (!amdgpu_sriov_vf(psp->adev) && 787 psp->toc.start_addr && 788 psp->toc.size_bytes && 789 psp->fw_pri_buf) { 790 ret = psp_load_toc(psp, &tmr_size); 791 if (ret) { 792 DRM_ERROR("Failed to load toc\n"); 793 return ret; 794 } 795 } 796 797 if (!psp->tmr_bo) { 798 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 799 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 800 PSP_TMR_ALIGNMENT, 801 AMDGPU_HAS_VRAM(psp->adev) ? 802 AMDGPU_GEM_DOMAIN_VRAM : 803 AMDGPU_GEM_DOMAIN_GTT, 804 &psp->tmr_bo, &psp->tmr_mc_addr, 805 pptr); 806 } 807 808 return ret; 809 } 810 811 static bool psp_skip_tmr(struct psp_context *psp) 812 { 813 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 814 case IP_VERSION(11, 0, 9): 815 case IP_VERSION(11, 0, 7): 816 case IP_VERSION(13, 0, 2): 817 case IP_VERSION(13, 0, 10): 818 return true; 819 default: 820 return false; 821 } 822 } 823 824 static int psp_tmr_load(struct psp_context *psp) 825 { 826 int ret; 827 struct psp_gfx_cmd_resp *cmd; 828 829 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 830 * Already set up by host driver. 831 */ 832 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 833 return 0; 834 835 cmd = acquire_psp_cmd_buf(psp); 836 837 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 838 if (psp->tmr_bo) 839 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 840 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 841 842 ret = psp_cmd_submit_buf(psp, NULL, cmd, 843 psp->fence_buf_mc_addr); 844 845 release_psp_cmd_buf(psp); 846 847 return ret; 848 } 849 850 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 851 struct psp_gfx_cmd_resp *cmd) 852 { 853 if (amdgpu_sriov_vf(psp->adev)) 854 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 855 else 856 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 857 } 858 859 static int psp_tmr_unload(struct psp_context *psp) 860 { 861 int ret; 862 struct psp_gfx_cmd_resp *cmd; 863 864 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV, 865 * as TMR is not loaded at all 866 */ 867 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 868 return 0; 869 870 cmd = acquire_psp_cmd_buf(psp); 871 872 psp_prep_tmr_unload_cmd_buf(psp, cmd); 873 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 874 875 ret = psp_cmd_submit_buf(psp, NULL, cmd, 876 psp->fence_buf_mc_addr); 877 878 release_psp_cmd_buf(psp); 879 880 return ret; 881 } 882 883 static int psp_tmr_terminate(struct psp_context *psp) 884 { 885 return psp_tmr_unload(psp); 886 } 887 888 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 889 uint64_t *output_ptr) 890 { 891 int ret; 892 struct psp_gfx_cmd_resp *cmd; 893 894 if (!output_ptr) 895 return -EINVAL; 896 897 if (amdgpu_sriov_vf(psp->adev)) 898 return 0; 899 900 cmd = acquire_psp_cmd_buf(psp); 901 902 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 903 904 ret = psp_cmd_submit_buf(psp, NULL, cmd, 905 psp->fence_buf_mc_addr); 906 907 if (!ret) { 908 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 909 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 910 } 911 912 release_psp_cmd_buf(psp); 913 914 return ret; 915 } 916 917 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 918 { 919 struct psp_context *psp = &adev->psp; 920 struct psp_gfx_cmd_resp *cmd; 921 int ret; 922 923 if (amdgpu_sriov_vf(adev)) 924 return 0; 925 926 cmd = acquire_psp_cmd_buf(psp); 927 928 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 929 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 930 931 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 932 if (!ret) { 933 *boot_cfg = 934 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 935 } 936 937 release_psp_cmd_buf(psp); 938 939 return ret; 940 } 941 942 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 943 { 944 int ret; 945 struct psp_context *psp = &adev->psp; 946 struct psp_gfx_cmd_resp *cmd; 947 948 if (amdgpu_sriov_vf(adev)) 949 return 0; 950 951 cmd = acquire_psp_cmd_buf(psp); 952 953 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 954 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 955 cmd->cmd.boot_cfg.boot_config = boot_cfg; 956 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 957 958 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 959 960 release_psp_cmd_buf(psp); 961 962 return ret; 963 } 964 965 static int psp_rl_load(struct amdgpu_device *adev) 966 { 967 int ret; 968 struct psp_context *psp = &adev->psp; 969 struct psp_gfx_cmd_resp *cmd; 970 971 if (!is_psp_fw_valid(psp->rl)) 972 return 0; 973 974 cmd = acquire_psp_cmd_buf(psp); 975 976 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 977 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 978 979 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 980 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 981 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 982 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 983 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 984 985 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 986 987 release_psp_cmd_buf(psp); 988 989 return ret; 990 } 991 992 static int psp_asd_initialize(struct psp_context *psp) 993 { 994 int ret; 995 996 /* If PSP version doesn't match ASD version, asd loading will be failed. 997 * add workaround to bypass it for sriov now. 998 * TODO: add version check to make it common 999 */ 1000 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1001 return 0; 1002 1003 psp->asd_context.mem_context.shared_mc_addr = 0; 1004 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1005 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1006 1007 ret = psp_ta_load(psp, &psp->asd_context); 1008 if (!ret) 1009 psp->asd_context.initialized = true; 1010 1011 return ret; 1012 } 1013 1014 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1015 uint32_t session_id) 1016 { 1017 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1018 cmd->cmd.cmd_unload_ta.session_id = session_id; 1019 } 1020 1021 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1022 { 1023 int ret; 1024 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1025 1026 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1027 1028 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1029 1030 context->resp_status = cmd->resp.status; 1031 1032 release_psp_cmd_buf(psp); 1033 1034 return ret; 1035 } 1036 1037 static int psp_asd_terminate(struct psp_context *psp) 1038 { 1039 int ret; 1040 1041 if (amdgpu_sriov_vf(psp->adev)) 1042 return 0; 1043 1044 if (!psp->asd_context.initialized) 1045 return 0; 1046 1047 ret = psp_ta_unload(psp, &psp->asd_context); 1048 if (!ret) 1049 psp->asd_context.initialized = false; 1050 1051 return ret; 1052 } 1053 1054 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1055 uint32_t id, uint32_t value) 1056 { 1057 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1058 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1059 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1060 } 1061 1062 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1063 uint32_t value) 1064 { 1065 struct psp_gfx_cmd_resp *cmd; 1066 int ret = 0; 1067 1068 if (reg >= PSP_REG_LAST) 1069 return -EINVAL; 1070 1071 cmd = acquire_psp_cmd_buf(psp); 1072 1073 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1074 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1075 if (ret) 1076 DRM_ERROR("PSP failed to program reg id %d", reg); 1077 1078 release_psp_cmd_buf(psp); 1079 1080 return ret; 1081 } 1082 1083 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1084 uint64_t ta_bin_mc, 1085 struct ta_context *context) 1086 { 1087 cmd->cmd_id = context->ta_load_type; 1088 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1089 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1090 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1091 1092 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1093 lower_32_bits(context->mem_context.shared_mc_addr); 1094 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1095 upper_32_bits(context->mem_context.shared_mc_addr); 1096 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1097 } 1098 1099 int psp_ta_init_shared_buf(struct psp_context *psp, 1100 struct ta_mem_context *mem_ctx) 1101 { 1102 /* 1103 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1104 * physical) for ta to host memory 1105 */ 1106 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1107 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1108 AMDGPU_GEM_DOMAIN_GTT, 1109 &mem_ctx->shared_bo, 1110 &mem_ctx->shared_mc_addr, 1111 &mem_ctx->shared_buf); 1112 } 1113 1114 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1115 uint32_t ta_cmd_id, 1116 uint32_t session_id) 1117 { 1118 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1119 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1120 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1121 } 1122 1123 int psp_ta_invoke(struct psp_context *psp, 1124 uint32_t ta_cmd_id, 1125 struct ta_context *context) 1126 { 1127 int ret; 1128 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1129 1130 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1131 1132 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1133 psp->fence_buf_mc_addr); 1134 1135 context->resp_status = cmd->resp.status; 1136 1137 release_psp_cmd_buf(psp); 1138 1139 return ret; 1140 } 1141 1142 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1143 { 1144 int ret; 1145 struct psp_gfx_cmd_resp *cmd; 1146 1147 cmd = acquire_psp_cmd_buf(psp); 1148 1149 psp_copy_fw(psp, context->bin_desc.start_addr, 1150 context->bin_desc.size_bytes); 1151 1152 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1153 1154 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1155 psp->fence_buf_mc_addr); 1156 1157 context->resp_status = cmd->resp.status; 1158 1159 if (!ret) 1160 context->session_id = cmd->resp.session_id; 1161 1162 release_psp_cmd_buf(psp); 1163 1164 return ret; 1165 } 1166 1167 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1168 { 1169 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1170 } 1171 1172 int psp_xgmi_terminate(struct psp_context *psp) 1173 { 1174 int ret; 1175 struct amdgpu_device *adev = psp->adev; 1176 1177 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1178 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1179 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1180 adev->gmc.xgmi.connected_to_cpu)) 1181 return 0; 1182 1183 if (!psp->xgmi_context.context.initialized) 1184 return 0; 1185 1186 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1187 1188 psp->xgmi_context.context.initialized = false; 1189 1190 return ret; 1191 } 1192 1193 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1194 { 1195 struct ta_xgmi_shared_memory *xgmi_cmd; 1196 int ret; 1197 1198 if (!psp->ta_fw || 1199 !psp->xgmi_context.context.bin_desc.size_bytes || 1200 !psp->xgmi_context.context.bin_desc.start_addr) 1201 return -ENOENT; 1202 1203 if (!load_ta) 1204 goto invoke; 1205 1206 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1207 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1208 1209 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1210 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1211 if (ret) 1212 return ret; 1213 } 1214 1215 /* Load XGMI TA */ 1216 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1217 if (!ret) 1218 psp->xgmi_context.context.initialized = true; 1219 else 1220 return ret; 1221 1222 invoke: 1223 /* Initialize XGMI session */ 1224 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1225 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1226 xgmi_cmd->flag_extend_link_record = set_extended_data; 1227 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1228 1229 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1230 1231 return ret; 1232 } 1233 1234 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1235 { 1236 struct ta_xgmi_shared_memory *xgmi_cmd; 1237 int ret; 1238 1239 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1240 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1241 1242 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1243 1244 /* Invoke xgmi ta to get hive id */ 1245 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1246 if (ret) 1247 return ret; 1248 1249 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1250 1251 return 0; 1252 } 1253 1254 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1255 { 1256 struct ta_xgmi_shared_memory *xgmi_cmd; 1257 int ret; 1258 1259 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1260 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1261 1262 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1263 1264 /* Invoke xgmi ta to get the node id */ 1265 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1266 if (ret) 1267 return ret; 1268 1269 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1270 1271 return 0; 1272 } 1273 1274 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1275 { 1276 return (psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1277 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1278 psp->adev->ip_versions[MP0_HWIP][0] >= IP_VERSION(13, 0, 6); 1279 } 1280 1281 /* 1282 * Chips that support extended topology information require the driver to 1283 * reflect topology information in the opposite direction. This is 1284 * because the TA has already exceeded its link record limit and if the 1285 * TA holds bi-directional information, the driver would have to do 1286 * multiple fetches instead of just two. 1287 */ 1288 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1289 struct psp_xgmi_node_info node_info) 1290 { 1291 struct amdgpu_device *mirror_adev; 1292 struct amdgpu_hive_info *hive; 1293 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1294 uint64_t dst_node_id = node_info.node_id; 1295 uint8_t dst_num_hops = node_info.num_hops; 1296 uint8_t dst_num_links = node_info.num_links; 1297 1298 hive = amdgpu_get_xgmi_hive(psp->adev); 1299 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1300 struct psp_xgmi_topology_info *mirror_top_info; 1301 int j; 1302 1303 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1304 continue; 1305 1306 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1307 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1308 if (mirror_top_info->nodes[j].node_id != src_node_id) 1309 continue; 1310 1311 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1312 /* 1313 * prevent 0 num_links value re-reflection since reflection 1314 * criteria is based on num_hops (direct or indirect). 1315 * 1316 */ 1317 if (dst_num_links) 1318 mirror_top_info->nodes[j].num_links = dst_num_links; 1319 1320 break; 1321 } 1322 1323 break; 1324 } 1325 1326 amdgpu_put_xgmi_hive(hive); 1327 } 1328 1329 int psp_xgmi_get_topology_info(struct psp_context *psp, 1330 int number_devices, 1331 struct psp_xgmi_topology_info *topology, 1332 bool get_extended_data) 1333 { 1334 struct ta_xgmi_shared_memory *xgmi_cmd; 1335 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1336 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1337 int i; 1338 int ret; 1339 1340 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1341 return -EINVAL; 1342 1343 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1344 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1345 xgmi_cmd->flag_extend_link_record = get_extended_data; 1346 1347 /* Fill in the shared memory with topology information as input */ 1348 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1349 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1350 topology_info_input->num_nodes = number_devices; 1351 1352 for (i = 0; i < topology_info_input->num_nodes; i++) { 1353 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1354 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1355 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1356 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1357 } 1358 1359 /* Invoke xgmi ta to get the topology information */ 1360 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1361 if (ret) 1362 return ret; 1363 1364 /* Read the output topology information from the shared memory */ 1365 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1366 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1367 for (i = 0; i < topology->num_nodes; i++) { 1368 /* extended data will either be 0 or equal to non-extended data */ 1369 if (topology_info_output->nodes[i].num_hops) 1370 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1371 1372 /* non-extended data gets everything here so no need to update */ 1373 if (!get_extended_data) { 1374 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1375 topology->nodes[i].is_sharing_enabled = 1376 topology_info_output->nodes[i].is_sharing_enabled; 1377 topology->nodes[i].sdma_engine = 1378 topology_info_output->nodes[i].sdma_engine; 1379 } 1380 1381 } 1382 1383 /* Invoke xgmi ta again to get the link information */ 1384 if (psp_xgmi_peer_link_info_supported(psp)) { 1385 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1386 bool requires_reflection = 1387 (psp->xgmi_context.supports_extended_data && get_extended_data) || 1388 psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6); 1389 1390 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1391 1392 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1393 1394 if (ret) 1395 return ret; 1396 1397 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1398 for (i = 0; i < topology->num_nodes; i++) { 1399 /* accumulate num_links on extended data */ 1400 topology->nodes[i].num_links = get_extended_data ? 1401 topology->nodes[i].num_links + 1402 link_info_output->nodes[i].num_links : 1403 link_info_output->nodes[i].num_links; 1404 1405 /* reflect the topology information for bi-directionality */ 1406 if (requires_reflection && topology->nodes[i].num_hops) 1407 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1408 } 1409 } 1410 1411 return 0; 1412 } 1413 1414 int psp_xgmi_set_topology_info(struct psp_context *psp, 1415 int number_devices, 1416 struct psp_xgmi_topology_info *topology) 1417 { 1418 struct ta_xgmi_shared_memory *xgmi_cmd; 1419 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1420 int i; 1421 1422 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1423 return -EINVAL; 1424 1425 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1426 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1427 1428 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1429 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1430 topology_info_input->num_nodes = number_devices; 1431 1432 for (i = 0; i < topology_info_input->num_nodes; i++) { 1433 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1434 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1435 topology_info_input->nodes[i].is_sharing_enabled = 1; 1436 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1437 } 1438 1439 /* Invoke xgmi ta to set topology information */ 1440 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1441 } 1442 1443 // ras begin 1444 static void psp_ras_ta_check_status(struct psp_context *psp) 1445 { 1446 struct ta_ras_shared_memory *ras_cmd = 1447 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1448 1449 switch (ras_cmd->ras_status) { 1450 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1451 dev_warn(psp->adev->dev, 1452 "RAS WARNING: cmd failed due to unsupported ip\n"); 1453 break; 1454 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1455 dev_warn(psp->adev->dev, 1456 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1457 break; 1458 case TA_RAS_STATUS__SUCCESS: 1459 break; 1460 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1461 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1462 dev_warn(psp->adev->dev, 1463 "RAS WARNING: Inject error to critical region is not allowed\n"); 1464 break; 1465 default: 1466 dev_warn(psp->adev->dev, 1467 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1468 break; 1469 } 1470 } 1471 1472 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1473 { 1474 struct ta_ras_shared_memory *ras_cmd; 1475 int ret; 1476 1477 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1478 1479 /* 1480 * TODO: bypass the loading in sriov for now 1481 */ 1482 if (amdgpu_sriov_vf(psp->adev)) 1483 return 0; 1484 1485 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1486 1487 if (amdgpu_ras_intr_triggered()) 1488 return ret; 1489 1490 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 1491 DRM_WARN("RAS: Unsupported Interface"); 1492 return -EINVAL; 1493 } 1494 1495 if (!ret) { 1496 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1497 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1498 1499 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1500 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1501 dev_warn(psp->adev->dev, 1502 "RAS internal register access blocked\n"); 1503 1504 psp_ras_ta_check_status(psp); 1505 } 1506 1507 return ret; 1508 } 1509 1510 int psp_ras_enable_features(struct psp_context *psp, 1511 union ta_ras_cmd_input *info, bool enable) 1512 { 1513 struct ta_ras_shared_memory *ras_cmd; 1514 int ret; 1515 1516 if (!psp->ras_context.context.initialized) 1517 return -EINVAL; 1518 1519 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1520 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1521 1522 if (enable) 1523 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1524 else 1525 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1526 1527 ras_cmd->ras_in_message = *info; 1528 1529 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1530 if (ret) 1531 return -EINVAL; 1532 1533 return 0; 1534 } 1535 1536 int psp_ras_terminate(struct psp_context *psp) 1537 { 1538 int ret; 1539 1540 /* 1541 * TODO: bypass the terminate in sriov for now 1542 */ 1543 if (amdgpu_sriov_vf(psp->adev)) 1544 return 0; 1545 1546 if (!psp->ras_context.context.initialized) 1547 return 0; 1548 1549 ret = psp_ta_unload(psp, &psp->ras_context.context); 1550 1551 psp->ras_context.context.initialized = false; 1552 1553 return ret; 1554 } 1555 1556 int psp_ras_initialize(struct psp_context *psp) 1557 { 1558 int ret; 1559 uint32_t boot_cfg = 0xFF; 1560 struct amdgpu_device *adev = psp->adev; 1561 struct ta_ras_shared_memory *ras_cmd; 1562 1563 /* 1564 * TODO: bypass the initialize in sriov for now 1565 */ 1566 if (amdgpu_sriov_vf(adev)) 1567 return 0; 1568 1569 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1570 !adev->psp.ras_context.context.bin_desc.start_addr) { 1571 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1572 return 0; 1573 } 1574 1575 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1576 /* query GECC enablement status from boot config 1577 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1578 */ 1579 ret = psp_boot_config_get(adev, &boot_cfg); 1580 if (ret) 1581 dev_warn(adev->dev, "PSP get boot config failed\n"); 1582 1583 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1584 if (!boot_cfg) { 1585 dev_info(adev->dev, "GECC is disabled\n"); 1586 } else { 1587 /* disable GECC in next boot cycle if ras is 1588 * disabled by module parameter amdgpu_ras_enable 1589 * and/or amdgpu_ras_mask, or boot_config_get call 1590 * is failed 1591 */ 1592 ret = psp_boot_config_set(adev, 0); 1593 if (ret) 1594 dev_warn(adev->dev, "PSP set boot config failed\n"); 1595 else 1596 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1597 } 1598 } else { 1599 if (boot_cfg == 1) { 1600 dev_info(adev->dev, "GECC is enabled\n"); 1601 } else { 1602 /* enable GECC in next boot cycle if it is disabled 1603 * in boot config, or force enable GECC if failed to 1604 * get boot configuration 1605 */ 1606 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1607 if (ret) 1608 dev_warn(adev->dev, "PSP set boot config failed\n"); 1609 else 1610 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1611 } 1612 } 1613 } 1614 1615 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1616 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1617 1618 if (!psp->ras_context.context.mem_context.shared_buf) { 1619 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1620 if (ret) 1621 return ret; 1622 } 1623 1624 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1625 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1626 1627 if (amdgpu_ras_is_poison_mode_supported(adev)) 1628 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1629 if (!adev->gmc.xgmi.connected_to_cpu) 1630 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1631 1632 ret = psp_ta_load(psp, &psp->ras_context.context); 1633 1634 if (!ret && !ras_cmd->ras_status) 1635 psp->ras_context.context.initialized = true; 1636 else { 1637 if (ras_cmd->ras_status) 1638 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1639 1640 /* fail to load RAS TA */ 1641 psp->ras_context.context.initialized = false; 1642 } 1643 1644 return ret; 1645 } 1646 1647 int psp_ras_trigger_error(struct psp_context *psp, 1648 struct ta_ras_trigger_error_input *info) 1649 { 1650 struct ta_ras_shared_memory *ras_cmd; 1651 int ret; 1652 1653 if (!psp->ras_context.context.initialized) 1654 return -EINVAL; 1655 1656 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1657 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1658 1659 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1660 ras_cmd->ras_in_message.trigger_error = *info; 1661 1662 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1663 if (ret) 1664 return -EINVAL; 1665 1666 /* If err_event_athub occurs error inject was successful, however 1667 return status from TA is no long reliable */ 1668 if (amdgpu_ras_intr_triggered()) 1669 return 0; 1670 1671 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1672 return -EACCES; 1673 else if (ras_cmd->ras_status) 1674 return -EINVAL; 1675 1676 return 0; 1677 } 1678 // ras end 1679 1680 // HDCP start 1681 static int psp_hdcp_initialize(struct psp_context *psp) 1682 { 1683 int ret; 1684 1685 /* 1686 * TODO: bypass the initialize in sriov for now 1687 */ 1688 if (amdgpu_sriov_vf(psp->adev)) 1689 return 0; 1690 1691 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1692 !psp->hdcp_context.context.bin_desc.start_addr) { 1693 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1694 return 0; 1695 } 1696 1697 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1698 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1699 1700 if (!psp->hdcp_context.context.mem_context.shared_buf) { 1701 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1702 if (ret) 1703 return ret; 1704 } 1705 1706 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1707 if (!ret) { 1708 psp->hdcp_context.context.initialized = true; 1709 mutex_init(&psp->hdcp_context.mutex); 1710 } 1711 1712 return ret; 1713 } 1714 1715 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1716 { 1717 /* 1718 * TODO: bypass the loading in sriov for now 1719 */ 1720 if (amdgpu_sriov_vf(psp->adev)) 1721 return 0; 1722 1723 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1724 } 1725 1726 static int psp_hdcp_terminate(struct psp_context *psp) 1727 { 1728 int ret; 1729 1730 /* 1731 * TODO: bypass the terminate in sriov for now 1732 */ 1733 if (amdgpu_sriov_vf(psp->adev)) 1734 return 0; 1735 1736 if (!psp->hdcp_context.context.initialized) 1737 return 0; 1738 1739 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1740 1741 psp->hdcp_context.context.initialized = false; 1742 1743 return ret; 1744 } 1745 // HDCP end 1746 1747 // DTM start 1748 static int psp_dtm_initialize(struct psp_context *psp) 1749 { 1750 int ret; 1751 1752 /* 1753 * TODO: bypass the initialize in sriov for now 1754 */ 1755 if (amdgpu_sriov_vf(psp->adev)) 1756 return 0; 1757 1758 if (!psp->dtm_context.context.bin_desc.size_bytes || 1759 !psp->dtm_context.context.bin_desc.start_addr) { 1760 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1761 return 0; 1762 } 1763 1764 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1765 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1766 1767 if (!psp->dtm_context.context.mem_context.shared_buf) { 1768 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1769 if (ret) 1770 return ret; 1771 } 1772 1773 ret = psp_ta_load(psp, &psp->dtm_context.context); 1774 if (!ret) { 1775 psp->dtm_context.context.initialized = true; 1776 mutex_init(&psp->dtm_context.mutex); 1777 } 1778 1779 return ret; 1780 } 1781 1782 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1783 { 1784 /* 1785 * TODO: bypass the loading in sriov for now 1786 */ 1787 if (amdgpu_sriov_vf(psp->adev)) 1788 return 0; 1789 1790 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1791 } 1792 1793 static int psp_dtm_terminate(struct psp_context *psp) 1794 { 1795 int ret; 1796 1797 /* 1798 * TODO: bypass the terminate in sriov for now 1799 */ 1800 if (amdgpu_sriov_vf(psp->adev)) 1801 return 0; 1802 1803 if (!psp->dtm_context.context.initialized) 1804 return 0; 1805 1806 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1807 1808 psp->dtm_context.context.initialized = false; 1809 1810 return ret; 1811 } 1812 // DTM end 1813 1814 // RAP start 1815 static int psp_rap_initialize(struct psp_context *psp) 1816 { 1817 int ret; 1818 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1819 1820 /* 1821 * TODO: bypass the initialize in sriov for now 1822 */ 1823 if (amdgpu_sriov_vf(psp->adev)) 1824 return 0; 1825 1826 if (!psp->rap_context.context.bin_desc.size_bytes || 1827 !psp->rap_context.context.bin_desc.start_addr) { 1828 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1829 return 0; 1830 } 1831 1832 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1833 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1834 1835 if (!psp->rap_context.context.mem_context.shared_buf) { 1836 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1837 if (ret) 1838 return ret; 1839 } 1840 1841 ret = psp_ta_load(psp, &psp->rap_context.context); 1842 if (!ret) { 1843 psp->rap_context.context.initialized = true; 1844 mutex_init(&psp->rap_context.mutex); 1845 } else 1846 return ret; 1847 1848 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1849 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1850 psp_rap_terminate(psp); 1851 /* free rap shared memory */ 1852 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1853 1854 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1855 ret, status); 1856 1857 return ret; 1858 } 1859 1860 return 0; 1861 } 1862 1863 static int psp_rap_terminate(struct psp_context *psp) 1864 { 1865 int ret; 1866 1867 if (!psp->rap_context.context.initialized) 1868 return 0; 1869 1870 ret = psp_ta_unload(psp, &psp->rap_context.context); 1871 1872 psp->rap_context.context.initialized = false; 1873 1874 return ret; 1875 } 1876 1877 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1878 { 1879 struct ta_rap_shared_memory *rap_cmd; 1880 int ret = 0; 1881 1882 if (!psp->rap_context.context.initialized) 1883 return 0; 1884 1885 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1886 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1887 return -EINVAL; 1888 1889 mutex_lock(&psp->rap_context.mutex); 1890 1891 rap_cmd = (struct ta_rap_shared_memory *) 1892 psp->rap_context.context.mem_context.shared_buf; 1893 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1894 1895 rap_cmd->cmd_id = ta_cmd_id; 1896 rap_cmd->validation_method_id = METHOD_A; 1897 1898 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1899 if (ret) 1900 goto out_unlock; 1901 1902 if (status) 1903 *status = rap_cmd->rap_status; 1904 1905 out_unlock: 1906 mutex_unlock(&psp->rap_context.mutex); 1907 1908 return ret; 1909 } 1910 // RAP end 1911 1912 /* securedisplay start */ 1913 static int psp_securedisplay_initialize(struct psp_context *psp) 1914 { 1915 int ret; 1916 struct ta_securedisplay_cmd *securedisplay_cmd; 1917 1918 /* 1919 * TODO: bypass the initialize in sriov for now 1920 */ 1921 if (amdgpu_sriov_vf(psp->adev)) 1922 return 0; 1923 1924 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1925 !psp->securedisplay_context.context.bin_desc.start_addr) { 1926 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1927 return 0; 1928 } 1929 1930 psp->securedisplay_context.context.mem_context.shared_mem_size = 1931 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1932 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1933 1934 if (!psp->securedisplay_context.context.initialized) { 1935 ret = psp_ta_init_shared_buf(psp, 1936 &psp->securedisplay_context.context.mem_context); 1937 if (ret) 1938 return ret; 1939 } 1940 1941 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 1942 if (!ret) { 1943 psp->securedisplay_context.context.initialized = true; 1944 mutex_init(&psp->securedisplay_context.mutex); 1945 } else 1946 return ret; 1947 1948 mutex_lock(&psp->securedisplay_context.mutex); 1949 1950 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1951 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1952 1953 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1954 1955 mutex_unlock(&psp->securedisplay_context.mutex); 1956 1957 if (ret) { 1958 psp_securedisplay_terminate(psp); 1959 /* free securedisplay shared memory */ 1960 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1961 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1962 return -EINVAL; 1963 } 1964 1965 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1966 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1967 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1968 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1969 } 1970 1971 return 0; 1972 } 1973 1974 static int psp_securedisplay_terminate(struct psp_context *psp) 1975 { 1976 int ret; 1977 1978 /* 1979 * TODO:bypass the terminate in sriov for now 1980 */ 1981 if (amdgpu_sriov_vf(psp->adev)) 1982 return 0; 1983 1984 if (!psp->securedisplay_context.context.initialized) 1985 return 0; 1986 1987 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 1988 1989 psp->securedisplay_context.context.initialized = false; 1990 1991 return ret; 1992 } 1993 1994 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1995 { 1996 int ret; 1997 1998 if (!psp->securedisplay_context.context.initialized) 1999 return -EINVAL; 2000 2001 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2002 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2003 return -EINVAL; 2004 2005 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2006 2007 return ret; 2008 } 2009 /* SECUREDISPLAY end */ 2010 2011 static int psp_hw_start(struct psp_context *psp) 2012 { 2013 struct amdgpu_device *adev = psp->adev; 2014 int ret; 2015 2016 if (!amdgpu_sriov_vf(adev)) { 2017 if ((is_psp_fw_valid(psp->kdb)) && 2018 (psp->funcs->bootloader_load_kdb != NULL)) { 2019 ret = psp_bootloader_load_kdb(psp); 2020 if (ret) { 2021 DRM_ERROR("PSP load kdb failed!\n"); 2022 return ret; 2023 } 2024 } 2025 2026 if ((is_psp_fw_valid(psp->spl)) && 2027 (psp->funcs->bootloader_load_spl != NULL)) { 2028 ret = psp_bootloader_load_spl(psp); 2029 if (ret) { 2030 DRM_ERROR("PSP load spl failed!\n"); 2031 return ret; 2032 } 2033 } 2034 2035 if ((is_psp_fw_valid(psp->sys)) && 2036 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2037 ret = psp_bootloader_load_sysdrv(psp); 2038 if (ret) { 2039 DRM_ERROR("PSP load sys drv failed!\n"); 2040 return ret; 2041 } 2042 } 2043 2044 if ((is_psp_fw_valid(psp->soc_drv)) && 2045 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2046 ret = psp_bootloader_load_soc_drv(psp); 2047 if (ret) { 2048 DRM_ERROR("PSP load soc drv failed!\n"); 2049 return ret; 2050 } 2051 } 2052 2053 if ((is_psp_fw_valid(psp->intf_drv)) && 2054 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2055 ret = psp_bootloader_load_intf_drv(psp); 2056 if (ret) { 2057 DRM_ERROR("PSP load intf drv failed!\n"); 2058 return ret; 2059 } 2060 } 2061 2062 if ((is_psp_fw_valid(psp->dbg_drv)) && 2063 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2064 ret = psp_bootloader_load_dbg_drv(psp); 2065 if (ret) { 2066 DRM_ERROR("PSP load dbg drv failed!\n"); 2067 return ret; 2068 } 2069 } 2070 2071 if ((is_psp_fw_valid(psp->ras_drv)) && 2072 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2073 ret = psp_bootloader_load_ras_drv(psp); 2074 if (ret) { 2075 DRM_ERROR("PSP load ras_drv failed!\n"); 2076 return ret; 2077 } 2078 } 2079 2080 if ((is_psp_fw_valid(psp->sos)) && 2081 (psp->funcs->bootloader_load_sos != NULL)) { 2082 ret = psp_bootloader_load_sos(psp); 2083 if (ret) { 2084 DRM_ERROR("PSP load sos failed!\n"); 2085 return ret; 2086 } 2087 } 2088 } 2089 2090 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2091 if (ret) { 2092 DRM_ERROR("PSP create ring failed!\n"); 2093 return ret; 2094 } 2095 2096 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2097 goto skip_pin_bo; 2098 2099 if (!psp_boottime_tmr(psp)) { 2100 ret = psp_tmr_init(psp); 2101 if (ret) { 2102 DRM_ERROR("PSP tmr init failed!\n"); 2103 return ret; 2104 } 2105 } 2106 2107 skip_pin_bo: 2108 /* 2109 * For ASICs with DF Cstate management centralized 2110 * to PMFW, TMR setup should be performed after PMFW 2111 * loaded and before other non-psp firmware loaded. 2112 */ 2113 if (psp->pmfw_centralized_cstate_management) { 2114 ret = psp_load_smu_fw(psp); 2115 if (ret) 2116 return ret; 2117 } 2118 2119 ret = psp_tmr_load(psp); 2120 if (ret) { 2121 DRM_ERROR("PSP load tmr failed!\n"); 2122 return ret; 2123 } 2124 2125 return 0; 2126 } 2127 2128 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2129 enum psp_gfx_fw_type *type) 2130 { 2131 switch (ucode->ucode_id) { 2132 case AMDGPU_UCODE_ID_CAP: 2133 *type = GFX_FW_TYPE_CAP; 2134 break; 2135 case AMDGPU_UCODE_ID_SDMA0: 2136 *type = GFX_FW_TYPE_SDMA0; 2137 break; 2138 case AMDGPU_UCODE_ID_SDMA1: 2139 *type = GFX_FW_TYPE_SDMA1; 2140 break; 2141 case AMDGPU_UCODE_ID_SDMA2: 2142 *type = GFX_FW_TYPE_SDMA2; 2143 break; 2144 case AMDGPU_UCODE_ID_SDMA3: 2145 *type = GFX_FW_TYPE_SDMA3; 2146 break; 2147 case AMDGPU_UCODE_ID_SDMA4: 2148 *type = GFX_FW_TYPE_SDMA4; 2149 break; 2150 case AMDGPU_UCODE_ID_SDMA5: 2151 *type = GFX_FW_TYPE_SDMA5; 2152 break; 2153 case AMDGPU_UCODE_ID_SDMA6: 2154 *type = GFX_FW_TYPE_SDMA6; 2155 break; 2156 case AMDGPU_UCODE_ID_SDMA7: 2157 *type = GFX_FW_TYPE_SDMA7; 2158 break; 2159 case AMDGPU_UCODE_ID_CP_MES: 2160 *type = GFX_FW_TYPE_CP_MES; 2161 break; 2162 case AMDGPU_UCODE_ID_CP_MES_DATA: 2163 *type = GFX_FW_TYPE_MES_STACK; 2164 break; 2165 case AMDGPU_UCODE_ID_CP_MES1: 2166 *type = GFX_FW_TYPE_CP_MES_KIQ; 2167 break; 2168 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2169 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2170 break; 2171 case AMDGPU_UCODE_ID_CP_CE: 2172 *type = GFX_FW_TYPE_CP_CE; 2173 break; 2174 case AMDGPU_UCODE_ID_CP_PFP: 2175 *type = GFX_FW_TYPE_CP_PFP; 2176 break; 2177 case AMDGPU_UCODE_ID_CP_ME: 2178 *type = GFX_FW_TYPE_CP_ME; 2179 break; 2180 case AMDGPU_UCODE_ID_CP_MEC1: 2181 *type = GFX_FW_TYPE_CP_MEC; 2182 break; 2183 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2184 *type = GFX_FW_TYPE_CP_MEC_ME1; 2185 break; 2186 case AMDGPU_UCODE_ID_CP_MEC2: 2187 *type = GFX_FW_TYPE_CP_MEC; 2188 break; 2189 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2190 *type = GFX_FW_TYPE_CP_MEC_ME2; 2191 break; 2192 case AMDGPU_UCODE_ID_RLC_P: 2193 *type = GFX_FW_TYPE_RLC_P; 2194 break; 2195 case AMDGPU_UCODE_ID_RLC_V: 2196 *type = GFX_FW_TYPE_RLC_V; 2197 break; 2198 case AMDGPU_UCODE_ID_RLC_G: 2199 *type = GFX_FW_TYPE_RLC_G; 2200 break; 2201 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2202 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2203 break; 2204 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2205 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2206 break; 2207 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2208 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2209 break; 2210 case AMDGPU_UCODE_ID_RLC_IRAM: 2211 *type = GFX_FW_TYPE_RLC_IRAM; 2212 break; 2213 case AMDGPU_UCODE_ID_RLC_DRAM: 2214 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2215 break; 2216 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2217 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2218 break; 2219 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2220 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2221 break; 2222 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2223 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2224 break; 2225 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2226 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2227 break; 2228 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2229 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2230 break; 2231 case AMDGPU_UCODE_ID_SMC: 2232 *type = GFX_FW_TYPE_SMU; 2233 break; 2234 case AMDGPU_UCODE_ID_PPTABLE: 2235 *type = GFX_FW_TYPE_PPTABLE; 2236 break; 2237 case AMDGPU_UCODE_ID_UVD: 2238 *type = GFX_FW_TYPE_UVD; 2239 break; 2240 case AMDGPU_UCODE_ID_UVD1: 2241 *type = GFX_FW_TYPE_UVD1; 2242 break; 2243 case AMDGPU_UCODE_ID_VCE: 2244 *type = GFX_FW_TYPE_VCE; 2245 break; 2246 case AMDGPU_UCODE_ID_VCN: 2247 *type = GFX_FW_TYPE_VCN; 2248 break; 2249 case AMDGPU_UCODE_ID_VCN1: 2250 *type = GFX_FW_TYPE_VCN1; 2251 break; 2252 case AMDGPU_UCODE_ID_DMCU_ERAM: 2253 *type = GFX_FW_TYPE_DMCU_ERAM; 2254 break; 2255 case AMDGPU_UCODE_ID_DMCU_INTV: 2256 *type = GFX_FW_TYPE_DMCU_ISR; 2257 break; 2258 case AMDGPU_UCODE_ID_VCN0_RAM: 2259 *type = GFX_FW_TYPE_VCN0_RAM; 2260 break; 2261 case AMDGPU_UCODE_ID_VCN1_RAM: 2262 *type = GFX_FW_TYPE_VCN1_RAM; 2263 break; 2264 case AMDGPU_UCODE_ID_DMCUB: 2265 *type = GFX_FW_TYPE_DMUB; 2266 break; 2267 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2268 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2269 break; 2270 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2271 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2272 break; 2273 case AMDGPU_UCODE_ID_IMU_I: 2274 *type = GFX_FW_TYPE_IMU_I; 2275 break; 2276 case AMDGPU_UCODE_ID_IMU_D: 2277 *type = GFX_FW_TYPE_IMU_D; 2278 break; 2279 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2280 *type = GFX_FW_TYPE_RS64_PFP; 2281 break; 2282 case AMDGPU_UCODE_ID_CP_RS64_ME: 2283 *type = GFX_FW_TYPE_RS64_ME; 2284 break; 2285 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2286 *type = GFX_FW_TYPE_RS64_MEC; 2287 break; 2288 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2289 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2290 break; 2291 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2292 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2293 break; 2294 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2295 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2296 break; 2297 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2298 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2299 break; 2300 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2301 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2302 break; 2303 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2304 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2305 break; 2306 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2307 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2308 break; 2309 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2310 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2311 break; 2312 case AMDGPU_UCODE_ID_MAXIMUM: 2313 default: 2314 return -EINVAL; 2315 } 2316 2317 return 0; 2318 } 2319 2320 static void psp_print_fw_hdr(struct psp_context *psp, 2321 struct amdgpu_firmware_info *ucode) 2322 { 2323 struct amdgpu_device *adev = psp->adev; 2324 struct common_firmware_header *hdr; 2325 2326 switch (ucode->ucode_id) { 2327 case AMDGPU_UCODE_ID_SDMA0: 2328 case AMDGPU_UCODE_ID_SDMA1: 2329 case AMDGPU_UCODE_ID_SDMA2: 2330 case AMDGPU_UCODE_ID_SDMA3: 2331 case AMDGPU_UCODE_ID_SDMA4: 2332 case AMDGPU_UCODE_ID_SDMA5: 2333 case AMDGPU_UCODE_ID_SDMA6: 2334 case AMDGPU_UCODE_ID_SDMA7: 2335 hdr = (struct common_firmware_header *) 2336 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2337 amdgpu_ucode_print_sdma_hdr(hdr); 2338 break; 2339 case AMDGPU_UCODE_ID_CP_CE: 2340 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2341 amdgpu_ucode_print_gfx_hdr(hdr); 2342 break; 2343 case AMDGPU_UCODE_ID_CP_PFP: 2344 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2345 amdgpu_ucode_print_gfx_hdr(hdr); 2346 break; 2347 case AMDGPU_UCODE_ID_CP_ME: 2348 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2349 amdgpu_ucode_print_gfx_hdr(hdr); 2350 break; 2351 case AMDGPU_UCODE_ID_CP_MEC1: 2352 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2353 amdgpu_ucode_print_gfx_hdr(hdr); 2354 break; 2355 case AMDGPU_UCODE_ID_RLC_G: 2356 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2357 amdgpu_ucode_print_rlc_hdr(hdr); 2358 break; 2359 case AMDGPU_UCODE_ID_SMC: 2360 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2361 amdgpu_ucode_print_smc_hdr(hdr); 2362 break; 2363 default: 2364 break; 2365 } 2366 } 2367 2368 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2369 struct psp_gfx_cmd_resp *cmd) 2370 { 2371 int ret; 2372 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2373 2374 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2375 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2376 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2377 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2378 2379 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2380 if (ret) 2381 DRM_ERROR("Unknown firmware type\n"); 2382 2383 return ret; 2384 } 2385 2386 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2387 struct amdgpu_firmware_info *ucode) 2388 { 2389 int ret = 0; 2390 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2391 2392 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2393 if (!ret) { 2394 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2395 psp->fence_buf_mc_addr); 2396 } 2397 2398 release_psp_cmd_buf(psp); 2399 2400 return ret; 2401 } 2402 2403 static int psp_load_smu_fw(struct psp_context *psp) 2404 { 2405 int ret; 2406 struct amdgpu_device *adev = psp->adev; 2407 struct amdgpu_firmware_info *ucode = 2408 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2409 struct amdgpu_ras *ras = psp->ras_context.ras; 2410 2411 /* 2412 * Skip SMU FW reloading in case of using BACO for runpm only, 2413 * as SMU is always alive. 2414 */ 2415 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2416 return 0; 2417 2418 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2419 return 0; 2420 2421 if ((amdgpu_in_reset(adev) && 2422 ras && adev->ras_enabled && 2423 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2424 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2425 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2426 if (ret) 2427 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2428 } 2429 2430 ret = psp_execute_non_psp_fw_load(psp, ucode); 2431 2432 if (ret) 2433 DRM_ERROR("PSP load smu failed!\n"); 2434 2435 return ret; 2436 } 2437 2438 static bool fw_load_skip_check(struct psp_context *psp, 2439 struct amdgpu_firmware_info *ucode) 2440 { 2441 if (!ucode->fw || !ucode->ucode_size) 2442 return true; 2443 2444 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2445 (psp_smu_reload_quirk(psp) || 2446 psp->autoload_supported || 2447 psp->pmfw_centralized_cstate_management)) 2448 return true; 2449 2450 if (amdgpu_sriov_vf(psp->adev) && 2451 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2452 return true; 2453 2454 if (psp->autoload_supported && 2455 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2456 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2457 /* skip mec JT when autoload is enabled */ 2458 return true; 2459 2460 return false; 2461 } 2462 2463 int psp_load_fw_list(struct psp_context *psp, 2464 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2465 { 2466 int ret = 0, i; 2467 struct amdgpu_firmware_info *ucode; 2468 2469 for (i = 0; i < ucode_count; ++i) { 2470 ucode = ucode_list[i]; 2471 psp_print_fw_hdr(psp, ucode); 2472 ret = psp_execute_non_psp_fw_load(psp, ucode); 2473 if (ret) 2474 return ret; 2475 } 2476 return ret; 2477 } 2478 2479 static int psp_load_non_psp_fw(struct psp_context *psp) 2480 { 2481 int i, ret; 2482 struct amdgpu_firmware_info *ucode; 2483 struct amdgpu_device *adev = psp->adev; 2484 2485 if (psp->autoload_supported && 2486 !psp->pmfw_centralized_cstate_management) { 2487 ret = psp_load_smu_fw(psp); 2488 if (ret) 2489 return ret; 2490 } 2491 2492 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2493 ucode = &adev->firmware.ucode[i]; 2494 2495 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2496 !fw_load_skip_check(psp, ucode)) { 2497 ret = psp_load_smu_fw(psp); 2498 if (ret) 2499 return ret; 2500 continue; 2501 } 2502 2503 if (fw_load_skip_check(psp, ucode)) 2504 continue; 2505 2506 if (psp->autoload_supported && 2507 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2508 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2509 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2510 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2511 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2512 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2513 /* PSP only receive one SDMA fw for sienna_cichlid, 2514 * as all four sdma fw are same */ 2515 continue; 2516 2517 psp_print_fw_hdr(psp, ucode); 2518 2519 ret = psp_execute_non_psp_fw_load(psp, ucode); 2520 if (ret) 2521 return ret; 2522 2523 /* Start rlc autoload after psp recieved all the gfx firmware */ 2524 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2525 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2526 ret = psp_rlc_autoload_start(psp); 2527 if (ret) { 2528 DRM_ERROR("Failed to start rlc autoload\n"); 2529 return ret; 2530 } 2531 } 2532 } 2533 2534 return 0; 2535 } 2536 2537 static int psp_load_fw(struct amdgpu_device *adev) 2538 { 2539 int ret; 2540 struct psp_context *psp = &adev->psp; 2541 2542 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2543 /* should not destroy ring, only stop */ 2544 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2545 } else { 2546 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2547 2548 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2549 if (ret) { 2550 DRM_ERROR("PSP ring init failed!\n"); 2551 goto failed; 2552 } 2553 } 2554 2555 ret = psp_hw_start(psp); 2556 if (ret) 2557 goto failed; 2558 2559 ret = psp_load_non_psp_fw(psp); 2560 if (ret) 2561 goto failed1; 2562 2563 ret = psp_asd_initialize(psp); 2564 if (ret) { 2565 DRM_ERROR("PSP load asd failed!\n"); 2566 goto failed1; 2567 } 2568 2569 ret = psp_rl_load(adev); 2570 if (ret) { 2571 DRM_ERROR("PSP load RL failed!\n"); 2572 goto failed1; 2573 } 2574 2575 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2576 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2577 ret = psp_xgmi_initialize(psp, false, true); 2578 /* Warning the XGMI seesion initialize failure 2579 * Instead of stop driver initialization 2580 */ 2581 if (ret) 2582 dev_err(psp->adev->dev, 2583 "XGMI: Failed to initialize XGMI session\n"); 2584 } 2585 } 2586 2587 if (psp->ta_fw) { 2588 ret = psp_ras_initialize(psp); 2589 if (ret) 2590 dev_err(psp->adev->dev, 2591 "RAS: Failed to initialize RAS\n"); 2592 2593 ret = psp_hdcp_initialize(psp); 2594 if (ret) 2595 dev_err(psp->adev->dev, 2596 "HDCP: Failed to initialize HDCP\n"); 2597 2598 ret = psp_dtm_initialize(psp); 2599 if (ret) 2600 dev_err(psp->adev->dev, 2601 "DTM: Failed to initialize DTM\n"); 2602 2603 ret = psp_rap_initialize(psp); 2604 if (ret) 2605 dev_err(psp->adev->dev, 2606 "RAP: Failed to initialize RAP\n"); 2607 2608 ret = psp_securedisplay_initialize(psp); 2609 if (ret) 2610 dev_err(psp->adev->dev, 2611 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2612 } 2613 2614 return 0; 2615 2616 failed1: 2617 psp_free_shared_bufs(psp); 2618 failed: 2619 /* 2620 * all cleanup jobs (xgmi terminate, ras terminate, 2621 * ring destroy, cmd/fence/fw buffers destory, 2622 * psp->cmd destory) are delayed to psp_hw_fini 2623 */ 2624 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2625 return ret; 2626 } 2627 2628 static int psp_hw_init(void *handle) 2629 { 2630 int ret; 2631 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2632 2633 mutex_lock(&adev->firmware.mutex); 2634 /* 2635 * This sequence is just used on hw_init only once, no need on 2636 * resume. 2637 */ 2638 ret = amdgpu_ucode_init_bo(adev); 2639 if (ret) 2640 goto failed; 2641 2642 ret = psp_load_fw(adev); 2643 if (ret) { 2644 DRM_ERROR("PSP firmware loading failed\n"); 2645 goto failed; 2646 } 2647 2648 mutex_unlock(&adev->firmware.mutex); 2649 return 0; 2650 2651 failed: 2652 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2653 mutex_unlock(&adev->firmware.mutex); 2654 return -EINVAL; 2655 } 2656 2657 static int psp_hw_fini(void *handle) 2658 { 2659 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2660 struct psp_context *psp = &adev->psp; 2661 2662 if (psp->ta_fw) { 2663 psp_ras_terminate(psp); 2664 psp_securedisplay_terminate(psp); 2665 psp_rap_terminate(psp); 2666 psp_dtm_terminate(psp); 2667 psp_hdcp_terminate(psp); 2668 2669 if (adev->gmc.xgmi.num_physical_nodes > 1) 2670 psp_xgmi_terminate(psp); 2671 } 2672 2673 psp_asd_terminate(psp); 2674 psp_tmr_terminate(psp); 2675 2676 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2677 2678 return 0; 2679 } 2680 2681 static int psp_suspend(void *handle) 2682 { 2683 int ret = 0; 2684 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2685 struct psp_context *psp = &adev->psp; 2686 2687 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2688 psp->xgmi_context.context.initialized) { 2689 ret = psp_xgmi_terminate(psp); 2690 if (ret) { 2691 DRM_ERROR("Failed to terminate xgmi ta\n"); 2692 goto out; 2693 } 2694 } 2695 2696 if (psp->ta_fw) { 2697 ret = psp_ras_terminate(psp); 2698 if (ret) { 2699 DRM_ERROR("Failed to terminate ras ta\n"); 2700 goto out; 2701 } 2702 ret = psp_hdcp_terminate(psp); 2703 if (ret) { 2704 DRM_ERROR("Failed to terminate hdcp ta\n"); 2705 goto out; 2706 } 2707 ret = psp_dtm_terminate(psp); 2708 if (ret) { 2709 DRM_ERROR("Failed to terminate dtm ta\n"); 2710 goto out; 2711 } 2712 ret = psp_rap_terminate(psp); 2713 if (ret) { 2714 DRM_ERROR("Failed to terminate rap ta\n"); 2715 goto out; 2716 } 2717 ret = psp_securedisplay_terminate(psp); 2718 if (ret) { 2719 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2720 goto out; 2721 } 2722 } 2723 2724 ret = psp_asd_terminate(psp); 2725 if (ret) { 2726 DRM_ERROR("Failed to terminate asd\n"); 2727 goto out; 2728 } 2729 2730 ret = psp_tmr_terminate(psp); 2731 if (ret) { 2732 DRM_ERROR("Failed to terminate tmr\n"); 2733 goto out; 2734 } 2735 2736 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2737 if (ret) 2738 DRM_ERROR("PSP ring stop failed\n"); 2739 2740 out: 2741 return ret; 2742 } 2743 2744 static int psp_resume(void *handle) 2745 { 2746 int ret; 2747 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2748 struct psp_context *psp = &adev->psp; 2749 2750 DRM_INFO("PSP is resuming...\n"); 2751 2752 if (psp->mem_train_ctx.enable_mem_training) { 2753 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2754 if (ret) { 2755 DRM_ERROR("Failed to process memory training!\n"); 2756 return ret; 2757 } 2758 } 2759 2760 mutex_lock(&adev->firmware.mutex); 2761 2762 ret = psp_hw_start(psp); 2763 if (ret) 2764 goto failed; 2765 2766 ret = psp_load_non_psp_fw(psp); 2767 if (ret) 2768 goto failed; 2769 2770 ret = psp_asd_initialize(psp); 2771 if (ret) { 2772 DRM_ERROR("PSP load asd failed!\n"); 2773 goto failed; 2774 } 2775 2776 ret = psp_rl_load(adev); 2777 if (ret) { 2778 dev_err(adev->dev, "PSP load RL failed!\n"); 2779 goto failed; 2780 } 2781 2782 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2783 ret = psp_xgmi_initialize(psp, false, true); 2784 /* Warning the XGMI seesion initialize failure 2785 * Instead of stop driver initialization 2786 */ 2787 if (ret) 2788 dev_err(psp->adev->dev, 2789 "XGMI: Failed to initialize XGMI session\n"); 2790 } 2791 2792 if (psp->ta_fw) { 2793 ret = psp_ras_initialize(psp); 2794 if (ret) 2795 dev_err(psp->adev->dev, 2796 "RAS: Failed to initialize RAS\n"); 2797 2798 ret = psp_hdcp_initialize(psp); 2799 if (ret) 2800 dev_err(psp->adev->dev, 2801 "HDCP: Failed to initialize HDCP\n"); 2802 2803 ret = psp_dtm_initialize(psp); 2804 if (ret) 2805 dev_err(psp->adev->dev, 2806 "DTM: Failed to initialize DTM\n"); 2807 2808 ret = psp_rap_initialize(psp); 2809 if (ret) 2810 dev_err(psp->adev->dev, 2811 "RAP: Failed to initialize RAP\n"); 2812 2813 ret = psp_securedisplay_initialize(psp); 2814 if (ret) 2815 dev_err(psp->adev->dev, 2816 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2817 } 2818 2819 mutex_unlock(&adev->firmware.mutex); 2820 2821 return 0; 2822 2823 failed: 2824 DRM_ERROR("PSP resume failed\n"); 2825 mutex_unlock(&adev->firmware.mutex); 2826 return ret; 2827 } 2828 2829 int psp_gpu_reset(struct amdgpu_device *adev) 2830 { 2831 int ret; 2832 2833 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2834 return 0; 2835 2836 mutex_lock(&adev->psp.mutex); 2837 ret = psp_mode1_reset(&adev->psp); 2838 mutex_unlock(&adev->psp.mutex); 2839 2840 return ret; 2841 } 2842 2843 int psp_rlc_autoload_start(struct psp_context *psp) 2844 { 2845 int ret; 2846 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2847 2848 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2849 2850 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2851 psp->fence_buf_mc_addr); 2852 2853 release_psp_cmd_buf(psp); 2854 2855 return ret; 2856 } 2857 2858 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2859 uint64_t cmd_gpu_addr, int cmd_size) 2860 { 2861 struct amdgpu_firmware_info ucode = {0}; 2862 2863 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2864 AMDGPU_UCODE_ID_VCN0_RAM; 2865 ucode.mc_addr = cmd_gpu_addr; 2866 ucode.ucode_size = cmd_size; 2867 2868 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2869 } 2870 2871 int psp_ring_cmd_submit(struct psp_context *psp, 2872 uint64_t cmd_buf_mc_addr, 2873 uint64_t fence_mc_addr, 2874 int index) 2875 { 2876 unsigned int psp_write_ptr_reg = 0; 2877 struct psp_gfx_rb_frame *write_frame; 2878 struct psp_ring *ring = &psp->km_ring; 2879 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2880 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2881 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2882 struct amdgpu_device *adev = psp->adev; 2883 uint32_t ring_size_dw = ring->ring_size / 4; 2884 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2885 2886 /* KM (GPCOM) prepare write pointer */ 2887 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2888 2889 /* Update KM RB frame pointer to new frame */ 2890 /* write_frame ptr increments by size of rb_frame in bytes */ 2891 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2892 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2893 write_frame = ring_buffer_start; 2894 else 2895 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2896 /* Check invalid write_frame ptr address */ 2897 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2898 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2899 ring_buffer_start, ring_buffer_end, write_frame); 2900 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2901 return -EINVAL; 2902 } 2903 2904 /* Initialize KM RB frame */ 2905 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2906 2907 /* Update KM RB frame */ 2908 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2909 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2910 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2911 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2912 write_frame->fence_value = index; 2913 amdgpu_device_flush_hdp(adev, NULL); 2914 2915 /* Update the write Pointer in DWORDs */ 2916 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2917 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2918 return 0; 2919 } 2920 2921 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 2922 { 2923 struct amdgpu_device *adev = psp->adev; 2924 char fw_name[PSP_FW_NAME_LEN]; 2925 const struct psp_firmware_header_v1_0 *asd_hdr; 2926 int err = 0; 2927 2928 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2929 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name); 2930 if (err) 2931 goto out; 2932 2933 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2934 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2935 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2936 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2937 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2938 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2939 return 0; 2940 out: 2941 amdgpu_ucode_release(&adev->psp.asd_fw); 2942 return err; 2943 } 2944 2945 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 2946 { 2947 struct amdgpu_device *adev = psp->adev; 2948 char fw_name[PSP_FW_NAME_LEN]; 2949 const struct psp_firmware_header_v1_0 *toc_hdr; 2950 int err = 0; 2951 2952 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2953 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 2954 if (err) 2955 goto out; 2956 2957 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2958 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2959 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2960 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2961 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2962 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2963 return 0; 2964 out: 2965 amdgpu_ucode_release(&adev->psp.toc_fw); 2966 return err; 2967 } 2968 2969 static int parse_sos_bin_descriptor(struct psp_context *psp, 2970 const struct psp_fw_bin_desc *desc, 2971 const struct psp_firmware_header_v2_0 *sos_hdr) 2972 { 2973 uint8_t *ucode_start_addr = NULL; 2974 2975 if (!psp || !desc || !sos_hdr) 2976 return -EINVAL; 2977 2978 ucode_start_addr = (uint8_t *)sos_hdr + 2979 le32_to_cpu(desc->offset_bytes) + 2980 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2981 2982 switch (desc->fw_type) { 2983 case PSP_FW_TYPE_PSP_SOS: 2984 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2985 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2986 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2987 psp->sos.start_addr = ucode_start_addr; 2988 break; 2989 case PSP_FW_TYPE_PSP_SYS_DRV: 2990 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2991 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2992 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2993 psp->sys.start_addr = ucode_start_addr; 2994 break; 2995 case PSP_FW_TYPE_PSP_KDB: 2996 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2997 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2998 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2999 psp->kdb.start_addr = ucode_start_addr; 3000 break; 3001 case PSP_FW_TYPE_PSP_TOC: 3002 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3003 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3004 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3005 psp->toc.start_addr = ucode_start_addr; 3006 break; 3007 case PSP_FW_TYPE_PSP_SPL: 3008 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3009 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3010 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3011 psp->spl.start_addr = ucode_start_addr; 3012 break; 3013 case PSP_FW_TYPE_PSP_RL: 3014 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3015 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3016 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3017 psp->rl.start_addr = ucode_start_addr; 3018 break; 3019 case PSP_FW_TYPE_PSP_SOC_DRV: 3020 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3021 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3022 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3023 psp->soc_drv.start_addr = ucode_start_addr; 3024 break; 3025 case PSP_FW_TYPE_PSP_INTF_DRV: 3026 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3027 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3028 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3029 psp->intf_drv.start_addr = ucode_start_addr; 3030 break; 3031 case PSP_FW_TYPE_PSP_DBG_DRV: 3032 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3033 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3034 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3035 psp->dbg_drv.start_addr = ucode_start_addr; 3036 break; 3037 case PSP_FW_TYPE_PSP_RAS_DRV: 3038 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3039 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3040 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3041 psp->ras_drv.start_addr = ucode_start_addr; 3042 break; 3043 default: 3044 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3045 break; 3046 } 3047 3048 return 0; 3049 } 3050 3051 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3052 { 3053 const struct psp_firmware_header_v1_0 *sos_hdr; 3054 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3055 uint8_t *ucode_array_start_addr; 3056 3057 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3058 ucode_array_start_addr = (uint8_t *)sos_hdr + 3059 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3060 3061 if (adev->gmc.xgmi.connected_to_cpu || 3062 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3063 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3064 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3065 3066 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3067 adev->psp.sys.start_addr = ucode_array_start_addr; 3068 3069 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3070 adev->psp.sos.start_addr = ucode_array_start_addr + 3071 le32_to_cpu(sos_hdr->sos.offset_bytes); 3072 } else { 3073 /* Load alternate PSP SOS FW */ 3074 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3075 3076 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3077 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3078 3079 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3080 adev->psp.sys.start_addr = ucode_array_start_addr + 3081 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3082 3083 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3084 adev->psp.sos.start_addr = ucode_array_start_addr + 3085 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3086 } 3087 3088 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3089 dev_warn(adev->dev, "PSP SOS FW not available"); 3090 return -EINVAL; 3091 } 3092 3093 return 0; 3094 } 3095 3096 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3097 { 3098 struct amdgpu_device *adev = psp->adev; 3099 char fw_name[PSP_FW_NAME_LEN]; 3100 const struct psp_firmware_header_v1_0 *sos_hdr; 3101 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3102 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3103 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3104 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3105 int err = 0; 3106 uint8_t *ucode_array_start_addr; 3107 int fw_index = 0; 3108 3109 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3110 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name); 3111 if (err) 3112 goto out; 3113 3114 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3115 ucode_array_start_addr = (uint8_t *)sos_hdr + 3116 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3117 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3118 3119 switch (sos_hdr->header.header_version_major) { 3120 case 1: 3121 err = psp_init_sos_base_fw(adev); 3122 if (err) 3123 goto out; 3124 3125 if (sos_hdr->header.header_version_minor == 1) { 3126 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3127 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3128 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3129 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3130 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3131 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3132 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3133 } 3134 if (sos_hdr->header.header_version_minor == 2) { 3135 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3136 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3137 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3138 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3139 } 3140 if (sos_hdr->header.header_version_minor == 3) { 3141 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3142 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3143 adev->psp.toc.start_addr = ucode_array_start_addr + 3144 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3145 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3146 adev->psp.kdb.start_addr = ucode_array_start_addr + 3147 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3148 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3149 adev->psp.spl.start_addr = ucode_array_start_addr + 3150 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3151 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3152 adev->psp.rl.start_addr = ucode_array_start_addr + 3153 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3154 } 3155 break; 3156 case 2: 3157 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3158 3159 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3160 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3161 err = -EINVAL; 3162 goto out; 3163 } 3164 3165 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3166 err = parse_sos_bin_descriptor(psp, 3167 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3168 sos_hdr_v2_0); 3169 if (err) 3170 goto out; 3171 } 3172 break; 3173 default: 3174 dev_err(adev->dev, 3175 "unsupported psp sos firmware\n"); 3176 err = -EINVAL; 3177 goto out; 3178 } 3179 3180 return 0; 3181 out: 3182 amdgpu_ucode_release(&adev->psp.sos_fw); 3183 3184 return err; 3185 } 3186 3187 static int parse_ta_bin_descriptor(struct psp_context *psp, 3188 const struct psp_fw_bin_desc *desc, 3189 const struct ta_firmware_header_v2_0 *ta_hdr) 3190 { 3191 uint8_t *ucode_start_addr = NULL; 3192 3193 if (!psp || !desc || !ta_hdr) 3194 return -EINVAL; 3195 3196 ucode_start_addr = (uint8_t *)ta_hdr + 3197 le32_to_cpu(desc->offset_bytes) + 3198 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3199 3200 switch (desc->fw_type) { 3201 case TA_FW_TYPE_PSP_ASD: 3202 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3203 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3204 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3205 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3206 break; 3207 case TA_FW_TYPE_PSP_XGMI: 3208 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3209 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3210 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3211 break; 3212 case TA_FW_TYPE_PSP_RAS: 3213 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3214 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3215 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3216 break; 3217 case TA_FW_TYPE_PSP_HDCP: 3218 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3219 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3220 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3221 break; 3222 case TA_FW_TYPE_PSP_DTM: 3223 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3224 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3225 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3226 break; 3227 case TA_FW_TYPE_PSP_RAP: 3228 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3229 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3230 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3231 break; 3232 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3233 psp->securedisplay_context.context.bin_desc.fw_version = 3234 le32_to_cpu(desc->fw_version); 3235 psp->securedisplay_context.context.bin_desc.size_bytes = 3236 le32_to_cpu(desc->size_bytes); 3237 psp->securedisplay_context.context.bin_desc.start_addr = 3238 ucode_start_addr; 3239 break; 3240 default: 3241 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3242 break; 3243 } 3244 3245 return 0; 3246 } 3247 3248 static int parse_ta_v1_microcode(struct psp_context *psp) 3249 { 3250 const struct ta_firmware_header_v1_0 *ta_hdr; 3251 struct amdgpu_device *adev = psp->adev; 3252 3253 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3254 3255 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3256 return -EINVAL; 3257 3258 adev->psp.xgmi_context.context.bin_desc.fw_version = 3259 le32_to_cpu(ta_hdr->xgmi.fw_version); 3260 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3261 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3262 adev->psp.xgmi_context.context.bin_desc.start_addr = 3263 (uint8_t *)ta_hdr + 3264 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3265 3266 adev->psp.ras_context.context.bin_desc.fw_version = 3267 le32_to_cpu(ta_hdr->ras.fw_version); 3268 adev->psp.ras_context.context.bin_desc.size_bytes = 3269 le32_to_cpu(ta_hdr->ras.size_bytes); 3270 adev->psp.ras_context.context.bin_desc.start_addr = 3271 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3272 le32_to_cpu(ta_hdr->ras.offset_bytes); 3273 3274 adev->psp.hdcp_context.context.bin_desc.fw_version = 3275 le32_to_cpu(ta_hdr->hdcp.fw_version); 3276 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3277 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3278 adev->psp.hdcp_context.context.bin_desc.start_addr = 3279 (uint8_t *)ta_hdr + 3280 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3281 3282 adev->psp.dtm_context.context.bin_desc.fw_version = 3283 le32_to_cpu(ta_hdr->dtm.fw_version); 3284 adev->psp.dtm_context.context.bin_desc.size_bytes = 3285 le32_to_cpu(ta_hdr->dtm.size_bytes); 3286 adev->psp.dtm_context.context.bin_desc.start_addr = 3287 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3288 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3289 3290 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3291 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3292 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3293 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3294 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3295 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3296 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3297 3298 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3299 3300 return 0; 3301 } 3302 3303 static int parse_ta_v2_microcode(struct psp_context *psp) 3304 { 3305 const struct ta_firmware_header_v2_0 *ta_hdr; 3306 struct amdgpu_device *adev = psp->adev; 3307 int err = 0; 3308 int ta_index = 0; 3309 3310 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3311 3312 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3313 return -EINVAL; 3314 3315 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3316 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3317 return -EINVAL; 3318 } 3319 3320 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3321 err = parse_ta_bin_descriptor(psp, 3322 &ta_hdr->ta_fw_bin[ta_index], 3323 ta_hdr); 3324 if (err) 3325 return err; 3326 } 3327 3328 return 0; 3329 } 3330 3331 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3332 { 3333 const struct common_firmware_header *hdr; 3334 struct amdgpu_device *adev = psp->adev; 3335 char fw_name[PSP_FW_NAME_LEN]; 3336 int err; 3337 3338 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3339 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name); 3340 if (err) 3341 return err; 3342 3343 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3344 switch (le16_to_cpu(hdr->header_version_major)) { 3345 case 1: 3346 err = parse_ta_v1_microcode(psp); 3347 break; 3348 case 2: 3349 err = parse_ta_v2_microcode(psp); 3350 break; 3351 default: 3352 dev_err(adev->dev, "unsupported TA header version\n"); 3353 err = -EINVAL; 3354 } 3355 3356 if (err) 3357 amdgpu_ucode_release(&adev->psp.ta_fw); 3358 3359 return err; 3360 } 3361 3362 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 3363 { 3364 struct amdgpu_device *adev = psp->adev; 3365 char fw_name[PSP_FW_NAME_LEN]; 3366 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3367 struct amdgpu_firmware_info *info = NULL; 3368 int err = 0; 3369 3370 if (!amdgpu_sriov_vf(adev)) { 3371 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3372 return -EINVAL; 3373 } 3374 3375 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3376 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name); 3377 if (err) { 3378 if (err == -ENODEV) { 3379 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3380 err = 0; 3381 goto out; 3382 } 3383 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3384 } 3385 3386 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3387 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3388 info->fw = adev->psp.cap_fw; 3389 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3390 adev->psp.cap_fw->data; 3391 adev->firmware.fw_size += ALIGN( 3392 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3393 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3394 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3395 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3396 3397 return 0; 3398 3399 out: 3400 amdgpu_ucode_release(&adev->psp.cap_fw); 3401 return err; 3402 } 3403 3404 static int psp_set_clockgating_state(void *handle, 3405 enum amd_clockgating_state state) 3406 { 3407 return 0; 3408 } 3409 3410 static int psp_set_powergating_state(void *handle, 3411 enum amd_powergating_state state) 3412 { 3413 return 0; 3414 } 3415 3416 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3417 struct device_attribute *attr, 3418 char *buf) 3419 { 3420 struct drm_device *ddev = dev_get_drvdata(dev); 3421 struct amdgpu_device *adev = drm_to_adev(ddev); 3422 uint32_t fw_ver; 3423 int ret; 3424 3425 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3426 DRM_INFO("PSP block is not ready yet."); 3427 return -EBUSY; 3428 } 3429 3430 mutex_lock(&adev->psp.mutex); 3431 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3432 mutex_unlock(&adev->psp.mutex); 3433 3434 if (ret) { 3435 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3436 return ret; 3437 } 3438 3439 return sysfs_emit(buf, "%x\n", fw_ver); 3440 } 3441 3442 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3443 struct device_attribute *attr, 3444 const char *buf, 3445 size_t count) 3446 { 3447 struct drm_device *ddev = dev_get_drvdata(dev); 3448 struct amdgpu_device *adev = drm_to_adev(ddev); 3449 int ret, idx; 3450 char fw_name[100]; 3451 const struct firmware *usbc_pd_fw; 3452 struct amdgpu_bo *fw_buf_bo = NULL; 3453 uint64_t fw_pri_mc_addr; 3454 void *fw_pri_cpu_addr; 3455 3456 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3457 DRM_INFO("PSP block is not ready yet."); 3458 return -EBUSY; 3459 } 3460 3461 if (!drm_dev_enter(ddev, &idx)) 3462 return -ENODEV; 3463 3464 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3465 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3466 if (ret) 3467 goto fail; 3468 3469 /* LFB address which is aligned to 1MB boundary per PSP request */ 3470 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3471 AMDGPU_GEM_DOMAIN_VRAM | 3472 AMDGPU_GEM_DOMAIN_GTT, 3473 &fw_buf_bo, &fw_pri_mc_addr, 3474 &fw_pri_cpu_addr); 3475 if (ret) 3476 goto rel_buf; 3477 3478 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3479 3480 mutex_lock(&adev->psp.mutex); 3481 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3482 mutex_unlock(&adev->psp.mutex); 3483 3484 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3485 3486 rel_buf: 3487 release_firmware(usbc_pd_fw); 3488 fail: 3489 if (ret) { 3490 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3491 count = ret; 3492 } 3493 3494 drm_dev_exit(idx); 3495 return count; 3496 } 3497 3498 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3499 { 3500 int idx; 3501 3502 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3503 return; 3504 3505 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3506 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3507 3508 drm_dev_exit(idx); 3509 } 3510 3511 static DEVICE_ATTR(usbc_pd_fw, 0644, 3512 psp_usbc_pd_fw_sysfs_read, 3513 psp_usbc_pd_fw_sysfs_write); 3514 3515 int is_psp_fw_valid(struct psp_bin_desc bin) 3516 { 3517 return bin.size_bytes; 3518 } 3519 3520 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3521 struct bin_attribute *bin_attr, 3522 char *buffer, loff_t pos, size_t count) 3523 { 3524 struct device *dev = kobj_to_dev(kobj); 3525 struct drm_device *ddev = dev_get_drvdata(dev); 3526 struct amdgpu_device *adev = drm_to_adev(ddev); 3527 3528 adev->psp.vbflash_done = false; 3529 3530 /* Safeguard against memory drain */ 3531 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3532 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3533 kvfree(adev->psp.vbflash_tmp_buf); 3534 adev->psp.vbflash_tmp_buf = NULL; 3535 adev->psp.vbflash_image_size = 0; 3536 return -ENOMEM; 3537 } 3538 3539 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3540 if (!adev->psp.vbflash_tmp_buf) { 3541 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3542 if (!adev->psp.vbflash_tmp_buf) 3543 return -ENOMEM; 3544 } 3545 3546 mutex_lock(&adev->psp.mutex); 3547 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3548 adev->psp.vbflash_image_size += count; 3549 mutex_unlock(&adev->psp.mutex); 3550 3551 dev_info(adev->dev, "VBIOS flash write PSP done"); 3552 3553 return count; 3554 } 3555 3556 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3557 struct bin_attribute *bin_attr, char *buffer, 3558 loff_t pos, size_t count) 3559 { 3560 struct device *dev = kobj_to_dev(kobj); 3561 struct drm_device *ddev = dev_get_drvdata(dev); 3562 struct amdgpu_device *adev = drm_to_adev(ddev); 3563 struct amdgpu_bo *fw_buf_bo = NULL; 3564 uint64_t fw_pri_mc_addr; 3565 void *fw_pri_cpu_addr; 3566 int ret; 3567 3568 dev_info(adev->dev, "VBIOS flash to PSP started"); 3569 3570 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3571 AMDGPU_GPU_PAGE_SIZE, 3572 AMDGPU_GEM_DOMAIN_VRAM, 3573 &fw_buf_bo, 3574 &fw_pri_mc_addr, 3575 &fw_pri_cpu_addr); 3576 if (ret) 3577 goto rel_buf; 3578 3579 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3580 3581 mutex_lock(&adev->psp.mutex); 3582 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3583 mutex_unlock(&adev->psp.mutex); 3584 3585 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3586 3587 rel_buf: 3588 kvfree(adev->psp.vbflash_tmp_buf); 3589 adev->psp.vbflash_tmp_buf = NULL; 3590 adev->psp.vbflash_image_size = 0; 3591 3592 if (ret) { 3593 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret); 3594 return ret; 3595 } 3596 3597 dev_info(adev->dev, "VBIOS flash to PSP done"); 3598 return 0; 3599 } 3600 3601 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3602 struct device_attribute *attr, 3603 char *buf) 3604 { 3605 struct drm_device *ddev = dev_get_drvdata(dev); 3606 struct amdgpu_device *adev = drm_to_adev(ddev); 3607 uint32_t vbflash_status; 3608 3609 vbflash_status = psp_vbflash_status(&adev->psp); 3610 if (!adev->psp.vbflash_done) 3611 vbflash_status = 0; 3612 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3613 vbflash_status = 1; 3614 3615 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3616 } 3617 3618 static const struct bin_attribute psp_vbflash_bin_attr = { 3619 .attr = {.name = "psp_vbflash", .mode = 0664}, 3620 .size = 0, 3621 .write = amdgpu_psp_vbflash_write, 3622 .read = amdgpu_psp_vbflash_read, 3623 }; 3624 3625 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL); 3626 3627 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev) 3628 { 3629 int ret = 0; 3630 struct psp_context *psp = &adev->psp; 3631 3632 if (amdgpu_sriov_vf(adev)) 3633 return -EINVAL; 3634 3635 switch (adev->ip_versions[MP0_HWIP][0]) { 3636 case IP_VERSION(13, 0, 0): 3637 case IP_VERSION(13, 0, 7): 3638 case IP_VERSION(13, 0, 10): 3639 if (!psp->adev) { 3640 psp->adev = adev; 3641 psp_v13_0_set_psp_funcs(psp); 3642 } 3643 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3644 if (ret) 3645 dev_err(adev->dev, "Failed to create device file psp_vbflash"); 3646 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status); 3647 if (ret) 3648 dev_err(adev->dev, "Failed to create device file psp_vbflash_status"); 3649 return ret; 3650 default: 3651 return 0; 3652 } 3653 } 3654 3655 const struct amd_ip_funcs psp_ip_funcs = { 3656 .name = "psp", 3657 .early_init = psp_early_init, 3658 .late_init = NULL, 3659 .sw_init = psp_sw_init, 3660 .sw_fini = psp_sw_fini, 3661 .hw_init = psp_hw_init, 3662 .hw_fini = psp_hw_fini, 3663 .suspend = psp_suspend, 3664 .resume = psp_resume, 3665 .is_idle = NULL, 3666 .check_soft_reset = NULL, 3667 .wait_for_idle = NULL, 3668 .soft_reset = NULL, 3669 .set_clockgating_state = psp_set_clockgating_state, 3670 .set_powergating_state = psp_set_powergating_state, 3671 }; 3672 3673 static int psp_sysfs_init(struct amdgpu_device *adev) 3674 { 3675 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3676 3677 if (ret) 3678 DRM_ERROR("Failed to create USBC PD FW control file!"); 3679 3680 return ret; 3681 } 3682 3683 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev) 3684 { 3685 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3686 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status); 3687 } 3688 3689 static void psp_sysfs_fini(struct amdgpu_device *adev) 3690 { 3691 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3692 } 3693 3694 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 3695 .type = AMD_IP_BLOCK_TYPE_PSP, 3696 .major = 3, 3697 .minor = 1, 3698 .rev = 0, 3699 .funcs = &psp_ip_funcs, 3700 }; 3701 3702 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 3703 .type = AMD_IP_BLOCK_TYPE_PSP, 3704 .major = 10, 3705 .minor = 0, 3706 .rev = 0, 3707 .funcs = &psp_ip_funcs, 3708 }; 3709 3710 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 3711 .type = AMD_IP_BLOCK_TYPE_PSP, 3712 .major = 11, 3713 .minor = 0, 3714 .rev = 0, 3715 .funcs = &psp_ip_funcs, 3716 }; 3717 3718 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3719 .type = AMD_IP_BLOCK_TYPE_PSP, 3720 .major = 11, 3721 .minor = 0, 3722 .rev = 8, 3723 .funcs = &psp_ip_funcs, 3724 }; 3725 3726 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 3727 .type = AMD_IP_BLOCK_TYPE_PSP, 3728 .major = 12, 3729 .minor = 0, 3730 .rev = 0, 3731 .funcs = &psp_ip_funcs, 3732 }; 3733 3734 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3735 .type = AMD_IP_BLOCK_TYPE_PSP, 3736 .major = 13, 3737 .minor = 0, 3738 .rev = 0, 3739 .funcs = &psp_ip_funcs, 3740 }; 3741 3742 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3743 .type = AMD_IP_BLOCK_TYPE_PSP, 3744 .major = 13, 3745 .minor = 0, 3746 .rev = 4, 3747 .funcs = &psp_ip_funcs, 3748 }; 3749