1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/dma-mapping.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v3_1.h" 34 #include "psp_v10_0.h" 35 #include "psp_v11_0.h" 36 #include "psp_v12_0.h" 37 38 #include "amdgpu_ras.h" 39 40 static int psp_sysfs_init(struct amdgpu_device *adev); 41 static void psp_sysfs_fini(struct amdgpu_device *adev); 42 43 static int psp_load_smu_fw(struct psp_context *psp); 44 45 /* 46 * Due to DF Cstate management centralized to PMFW, the firmware 47 * loading sequence will be updated as below: 48 * - Load KDB 49 * - Load SYS_DRV 50 * - Load tOS 51 * - Load PMFW 52 * - Setup TMR 53 * - Load other non-psp fw 54 * - Load ASD 55 * - Load XGMI/RAS/HDCP/DTM TA if any 56 * 57 * This new sequence is required for 58 * - Arcturus 59 * - Navi12 and onwards 60 */ 61 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 62 { 63 struct amdgpu_device *adev = psp->adev; 64 65 psp->pmfw_centralized_cstate_management = false; 66 67 if (amdgpu_sriov_vf(adev)) 68 return; 69 70 if (adev->flags & AMD_IS_APU) 71 return; 72 73 if ((adev->asic_type == CHIP_ARCTURUS) || 74 (adev->asic_type >= CHIP_NAVI12)) 75 psp->pmfw_centralized_cstate_management = true; 76 } 77 78 static int psp_early_init(void *handle) 79 { 80 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 81 struct psp_context *psp = &adev->psp; 82 83 switch (adev->asic_type) { 84 case CHIP_VEGA10: 85 case CHIP_VEGA12: 86 psp_v3_1_set_psp_funcs(psp); 87 psp->autoload_supported = false; 88 break; 89 case CHIP_RAVEN: 90 psp_v10_0_set_psp_funcs(psp); 91 psp->autoload_supported = false; 92 break; 93 case CHIP_VEGA20: 94 case CHIP_ARCTURUS: 95 psp_v11_0_set_psp_funcs(psp); 96 psp->autoload_supported = false; 97 break; 98 case CHIP_NAVI10: 99 case CHIP_NAVI14: 100 case CHIP_NAVI12: 101 case CHIP_SIENNA_CICHLID: 102 case CHIP_NAVY_FLOUNDER: 103 case CHIP_VANGOGH: 104 case CHIP_DIMGREY_CAVEFISH: 105 psp_v11_0_set_psp_funcs(psp); 106 psp->autoload_supported = true; 107 break; 108 case CHIP_RENOIR: 109 psp_v12_0_set_psp_funcs(psp); 110 break; 111 default: 112 return -EINVAL; 113 } 114 115 psp->adev = adev; 116 117 psp_check_pmfw_centralized_cstate_management(psp); 118 119 return 0; 120 } 121 122 static void psp_memory_training_fini(struct psp_context *psp) 123 { 124 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 125 126 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 127 kfree(ctx->sys_cache); 128 ctx->sys_cache = NULL; 129 } 130 131 static int psp_memory_training_init(struct psp_context *psp) 132 { 133 int ret; 134 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 135 136 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 137 DRM_DEBUG("memory training is not supported!\n"); 138 return 0; 139 } 140 141 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 142 if (ctx->sys_cache == NULL) { 143 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 144 ret = -ENOMEM; 145 goto Err_out; 146 } 147 148 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 149 ctx->train_data_size, 150 ctx->p2c_train_data_offset, 151 ctx->c2p_train_data_offset); 152 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 153 return 0; 154 155 Err_out: 156 psp_memory_training_fini(psp); 157 return ret; 158 } 159 160 static int psp_sw_init(void *handle) 161 { 162 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 163 struct psp_context *psp = &adev->psp; 164 int ret; 165 166 if (!amdgpu_sriov_vf(adev)) { 167 ret = psp_init_microcode(psp); 168 if (ret) { 169 DRM_ERROR("Failed to load psp firmware!\n"); 170 return ret; 171 } 172 } 173 174 ret = psp_memory_training_init(psp); 175 if (ret) { 176 DRM_ERROR("Failed to initialize memory training!\n"); 177 return ret; 178 } 179 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 180 if (ret) { 181 DRM_ERROR("Failed to process memory training!\n"); 182 return ret; 183 } 184 185 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 186 ret= psp_sysfs_init(adev); 187 if (ret) { 188 return ret; 189 } 190 } 191 192 return 0; 193 } 194 195 static int psp_sw_fini(void *handle) 196 { 197 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 198 199 psp_memory_training_fini(&adev->psp); 200 if (adev->psp.sos_fw) { 201 release_firmware(adev->psp.sos_fw); 202 adev->psp.sos_fw = NULL; 203 } 204 if (adev->psp.asd_fw) { 205 release_firmware(adev->psp.asd_fw); 206 adev->psp.asd_fw = NULL; 207 } 208 if (adev->psp.ta_fw) { 209 release_firmware(adev->psp.ta_fw); 210 adev->psp.ta_fw = NULL; 211 } 212 213 if (adev->asic_type == CHIP_NAVI10 || 214 adev->asic_type == CHIP_SIENNA_CICHLID) 215 psp_sysfs_fini(adev); 216 217 return 0; 218 } 219 220 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 221 uint32_t reg_val, uint32_t mask, bool check_changed) 222 { 223 uint32_t val; 224 int i; 225 struct amdgpu_device *adev = psp->adev; 226 227 if (psp->adev->in_pci_err_recovery) 228 return 0; 229 230 for (i = 0; i < adev->usec_timeout; i++) { 231 val = RREG32(reg_index); 232 if (check_changed) { 233 if (val != reg_val) 234 return 0; 235 } else { 236 if ((val & mask) == reg_val) 237 return 0; 238 } 239 udelay(1); 240 } 241 242 return -ETIME; 243 } 244 245 static int 246 psp_cmd_submit_buf(struct psp_context *psp, 247 struct amdgpu_firmware_info *ucode, 248 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 249 { 250 int ret; 251 int index; 252 int timeout = 20000; 253 bool ras_intr = false; 254 bool skip_unsupport = false; 255 256 if (psp->adev->in_pci_err_recovery) 257 return 0; 258 259 mutex_lock(&psp->mutex); 260 261 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 262 263 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 264 265 index = atomic_inc_return(&psp->fence_value); 266 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 267 if (ret) { 268 atomic_dec(&psp->fence_value); 269 mutex_unlock(&psp->mutex); 270 return ret; 271 } 272 273 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 274 while (*((unsigned int *)psp->fence_buf) != index) { 275 if (--timeout == 0) 276 break; 277 /* 278 * Shouldn't wait for timeout when err_event_athub occurs, 279 * because gpu reset thread triggered and lock resource should 280 * be released for psp resume sequence. 281 */ 282 ras_intr = amdgpu_ras_intr_triggered(); 283 if (ras_intr) 284 break; 285 usleep_range(10, 100); 286 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 287 } 288 289 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 290 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 291 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 292 293 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 294 295 /* In some cases, psp response status is not 0 even there is no 296 * problem while the command is submitted. Some version of PSP FW 297 * doesn't write 0 to that field. 298 * So here we would like to only print a warning instead of an error 299 * during psp initialization to avoid breaking hw_init and it doesn't 300 * return -EINVAL. 301 */ 302 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 303 if (ucode) 304 DRM_WARN("failed to load ucode id (%d) ", 305 ucode->ucode_id); 306 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n", 307 psp->cmd_buf_mem->cmd_id, 308 psp->cmd_buf_mem->resp.status); 309 if (!timeout) { 310 mutex_unlock(&psp->mutex); 311 return -EINVAL; 312 } 313 } 314 315 if (ucode) { 316 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 317 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 318 } 319 mutex_unlock(&psp->mutex); 320 321 return ret; 322 } 323 324 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 325 struct psp_gfx_cmd_resp *cmd, 326 uint64_t tmr_mc, uint32_t size) 327 { 328 if (amdgpu_sriov_vf(psp->adev)) 329 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 330 else 331 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 332 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 333 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 334 cmd->cmd.cmd_setup_tmr.buf_size = size; 335 } 336 337 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 338 uint64_t pri_buf_mc, uint32_t size) 339 { 340 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 341 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 342 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 343 cmd->cmd.cmd_load_toc.toc_size = size; 344 } 345 346 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 347 static int psp_load_toc(struct psp_context *psp, 348 uint32_t *tmr_size) 349 { 350 int ret; 351 struct psp_gfx_cmd_resp *cmd; 352 353 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 354 if (!cmd) 355 return -ENOMEM; 356 /* Copy toc to psp firmware private buffer */ 357 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 358 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size); 359 360 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 361 362 ret = psp_cmd_submit_buf(psp, NULL, cmd, 363 psp->fence_buf_mc_addr); 364 if (!ret) 365 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 366 kfree(cmd); 367 return ret; 368 } 369 370 /* Set up Trusted Memory Region */ 371 static int psp_tmr_init(struct psp_context *psp) 372 { 373 int ret; 374 int tmr_size; 375 void *tmr_buf; 376 void **pptr; 377 378 /* 379 * According to HW engineer, they prefer the TMR address be "naturally 380 * aligned" , e.g. the start address be an integer divide of TMR size. 381 * 382 * Note: this memory need be reserved till the driver 383 * uninitializes. 384 */ 385 tmr_size = PSP_TMR_SIZE; 386 387 /* For ASICs support RLC autoload, psp will parse the toc 388 * and calculate the total size of TMR needed */ 389 if (!amdgpu_sriov_vf(psp->adev) && 390 psp->toc_start_addr && 391 psp->toc_bin_size && 392 psp->fw_pri_buf) { 393 ret = psp_load_toc(psp, &tmr_size); 394 if (ret) { 395 DRM_ERROR("Failed to load toc\n"); 396 return ret; 397 } 398 } 399 400 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 401 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE, 402 AMDGPU_GEM_DOMAIN_VRAM, 403 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 404 405 return ret; 406 } 407 408 static int psp_clear_vf_fw(struct psp_context *psp) 409 { 410 int ret; 411 struct psp_gfx_cmd_resp *cmd; 412 413 if (!amdgpu_sriov_vf(psp->adev) || psp->adev->asic_type != CHIP_NAVI12) 414 return 0; 415 416 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 417 if (!cmd) 418 return -ENOMEM; 419 420 cmd->cmd_id = GFX_CMD_ID_CLEAR_VF_FW; 421 422 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 423 kfree(cmd); 424 425 return ret; 426 } 427 428 static bool psp_skip_tmr(struct psp_context *psp) 429 { 430 switch (psp->adev->asic_type) { 431 case CHIP_NAVI12: 432 case CHIP_SIENNA_CICHLID: 433 return true; 434 default: 435 return false; 436 } 437 } 438 439 static int psp_tmr_load(struct psp_context *psp) 440 { 441 int ret; 442 struct psp_gfx_cmd_resp *cmd; 443 444 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 445 * Already set up by host driver. 446 */ 447 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 448 return 0; 449 450 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 451 if (!cmd) 452 return -ENOMEM; 453 454 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, 455 amdgpu_bo_size(psp->tmr_bo)); 456 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 457 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 458 459 ret = psp_cmd_submit_buf(psp, NULL, cmd, 460 psp->fence_buf_mc_addr); 461 462 kfree(cmd); 463 464 return ret; 465 } 466 467 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 468 struct psp_gfx_cmd_resp *cmd) 469 { 470 if (amdgpu_sriov_vf(psp->adev)) 471 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 472 else 473 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 474 } 475 476 static int psp_tmr_unload(struct psp_context *psp) 477 { 478 int ret; 479 struct psp_gfx_cmd_resp *cmd; 480 481 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 482 if (!cmd) 483 return -ENOMEM; 484 485 psp_prep_tmr_unload_cmd_buf(psp, cmd); 486 DRM_INFO("free PSP TMR buffer\n"); 487 488 ret = psp_cmd_submit_buf(psp, NULL, cmd, 489 psp->fence_buf_mc_addr); 490 491 kfree(cmd); 492 493 return ret; 494 } 495 496 static int psp_tmr_terminate(struct psp_context *psp) 497 { 498 int ret; 499 void *tmr_buf; 500 void **pptr; 501 502 ret = psp_tmr_unload(psp); 503 if (ret) 504 return ret; 505 506 /* free TMR memory buffer */ 507 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 508 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 509 510 return 0; 511 } 512 513 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 514 uint64_t *output_ptr) 515 { 516 int ret; 517 struct psp_gfx_cmd_resp *cmd; 518 519 if (!output_ptr) 520 return -EINVAL; 521 522 if (amdgpu_sriov_vf(psp->adev)) 523 return 0; 524 525 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 526 if (!cmd) 527 return -ENOMEM; 528 529 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 530 531 ret = psp_cmd_submit_buf(psp, NULL, cmd, 532 psp->fence_buf_mc_addr); 533 534 if (!ret) { 535 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 536 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 537 } 538 539 kfree(cmd); 540 541 return ret; 542 } 543 544 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 545 uint64_t asd_mc, uint32_t size) 546 { 547 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 548 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 549 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 550 cmd->cmd.cmd_load_ta.app_len = size; 551 552 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 553 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 554 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 555 } 556 557 static int psp_asd_load(struct psp_context *psp) 558 { 559 int ret; 560 struct psp_gfx_cmd_resp *cmd; 561 562 /* If PSP version doesn't match ASD version, asd loading will be failed. 563 * add workaround to bypass it for sriov now. 564 * TODO: add version check to make it common 565 */ 566 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size) 567 return 0; 568 569 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 570 if (!cmd) 571 return -ENOMEM; 572 573 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 574 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 575 576 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 577 psp->asd_ucode_size); 578 579 ret = psp_cmd_submit_buf(psp, NULL, cmd, 580 psp->fence_buf_mc_addr); 581 if (!ret) { 582 psp->asd_context.asd_initialized = true; 583 psp->asd_context.session_id = cmd->resp.session_id; 584 } 585 586 kfree(cmd); 587 588 return ret; 589 } 590 591 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 592 uint32_t session_id) 593 { 594 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 595 cmd->cmd.cmd_unload_ta.session_id = session_id; 596 } 597 598 static int psp_asd_unload(struct psp_context *psp) 599 { 600 int ret; 601 struct psp_gfx_cmd_resp *cmd; 602 603 if (amdgpu_sriov_vf(psp->adev)) 604 return 0; 605 606 if (!psp->asd_context.asd_initialized) 607 return 0; 608 609 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 610 if (!cmd) 611 return -ENOMEM; 612 613 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 614 615 ret = psp_cmd_submit_buf(psp, NULL, cmd, 616 psp->fence_buf_mc_addr); 617 if (!ret) 618 psp->asd_context.asd_initialized = false; 619 620 kfree(cmd); 621 622 return ret; 623 } 624 625 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 626 uint32_t id, uint32_t value) 627 { 628 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 629 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 630 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 631 } 632 633 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 634 uint32_t value) 635 { 636 struct psp_gfx_cmd_resp *cmd = NULL; 637 int ret = 0; 638 639 if (reg >= PSP_REG_LAST) 640 return -EINVAL; 641 642 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 643 if (!cmd) 644 return -ENOMEM; 645 646 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 647 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 648 649 kfree(cmd); 650 return ret; 651 } 652 653 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 654 uint64_t ta_bin_mc, 655 uint32_t ta_bin_size, 656 uint64_t ta_shared_mc, 657 uint32_t ta_shared_size) 658 { 659 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 660 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 661 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 662 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 663 664 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 665 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 666 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 667 } 668 669 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 670 { 671 int ret; 672 673 /* 674 * Allocate 16k memory aligned to 4k from Frame Buffer (local 675 * physical) for xgmi ta <-> Driver 676 */ 677 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 678 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 679 &psp->xgmi_context.xgmi_shared_bo, 680 &psp->xgmi_context.xgmi_shared_mc_addr, 681 &psp->xgmi_context.xgmi_shared_buf); 682 683 return ret; 684 } 685 686 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 687 uint32_t ta_cmd_id, 688 uint32_t session_id) 689 { 690 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 691 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 692 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 693 } 694 695 static int psp_ta_invoke(struct psp_context *psp, 696 uint32_t ta_cmd_id, 697 uint32_t session_id) 698 { 699 int ret; 700 struct psp_gfx_cmd_resp *cmd; 701 702 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 703 if (!cmd) 704 return -ENOMEM; 705 706 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 707 708 ret = psp_cmd_submit_buf(psp, NULL, cmd, 709 psp->fence_buf_mc_addr); 710 711 kfree(cmd); 712 713 return ret; 714 } 715 716 static int psp_xgmi_load(struct psp_context *psp) 717 { 718 int ret; 719 struct psp_gfx_cmd_resp *cmd; 720 721 /* 722 * TODO: bypass the loading in sriov for now 723 */ 724 725 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 726 if (!cmd) 727 return -ENOMEM; 728 729 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 730 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 731 732 psp_prep_ta_load_cmd_buf(cmd, 733 psp->fw_pri_mc_addr, 734 psp->ta_xgmi_ucode_size, 735 psp->xgmi_context.xgmi_shared_mc_addr, 736 PSP_XGMI_SHARED_MEM_SIZE); 737 738 ret = psp_cmd_submit_buf(psp, NULL, cmd, 739 psp->fence_buf_mc_addr); 740 741 if (!ret) { 742 psp->xgmi_context.initialized = 1; 743 psp->xgmi_context.session_id = cmd->resp.session_id; 744 } 745 746 kfree(cmd); 747 748 return ret; 749 } 750 751 static int psp_xgmi_unload(struct psp_context *psp) 752 { 753 int ret; 754 struct psp_gfx_cmd_resp *cmd; 755 struct amdgpu_device *adev = psp->adev; 756 757 /* XGMI TA unload currently is not supported on Arcturus */ 758 if (adev->asic_type == CHIP_ARCTURUS) 759 return 0; 760 761 /* 762 * TODO: bypass the unloading in sriov for now 763 */ 764 765 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 766 if (!cmd) 767 return -ENOMEM; 768 769 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 770 771 ret = psp_cmd_submit_buf(psp, NULL, cmd, 772 psp->fence_buf_mc_addr); 773 774 kfree(cmd); 775 776 return ret; 777 } 778 779 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 780 { 781 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 782 } 783 784 int psp_xgmi_terminate(struct psp_context *psp) 785 { 786 int ret; 787 788 if (!psp->xgmi_context.initialized) 789 return 0; 790 791 ret = psp_xgmi_unload(psp); 792 if (ret) 793 return ret; 794 795 psp->xgmi_context.initialized = 0; 796 797 /* free xgmi shared memory */ 798 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 799 &psp->xgmi_context.xgmi_shared_mc_addr, 800 &psp->xgmi_context.xgmi_shared_buf); 801 802 return 0; 803 } 804 805 int psp_xgmi_initialize(struct psp_context *psp) 806 { 807 struct ta_xgmi_shared_memory *xgmi_cmd; 808 int ret; 809 810 if (!psp->adev->psp.ta_fw || 811 !psp->adev->psp.ta_xgmi_ucode_size || 812 !psp->adev->psp.ta_xgmi_start_addr) 813 return -ENOENT; 814 815 if (!psp->xgmi_context.initialized) { 816 ret = psp_xgmi_init_shared_buf(psp); 817 if (ret) 818 return ret; 819 } 820 821 /* Load XGMI TA */ 822 ret = psp_xgmi_load(psp); 823 if (ret) 824 return ret; 825 826 /* Initialize XGMI session */ 827 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 828 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 829 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 830 831 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 832 833 return ret; 834 } 835 836 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 837 { 838 struct ta_xgmi_shared_memory *xgmi_cmd; 839 int ret; 840 841 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 842 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 843 844 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 845 846 /* Invoke xgmi ta to get hive id */ 847 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 848 if (ret) 849 return ret; 850 851 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 852 853 return 0; 854 } 855 856 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 857 { 858 struct ta_xgmi_shared_memory *xgmi_cmd; 859 int ret; 860 861 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 862 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 863 864 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 865 866 /* Invoke xgmi ta to get the node id */ 867 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 868 if (ret) 869 return ret; 870 871 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 872 873 return 0; 874 } 875 876 int psp_xgmi_get_topology_info(struct psp_context *psp, 877 int number_devices, 878 struct psp_xgmi_topology_info *topology) 879 { 880 struct ta_xgmi_shared_memory *xgmi_cmd; 881 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 882 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 883 int i; 884 int ret; 885 886 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 887 return -EINVAL; 888 889 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 890 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 891 892 /* Fill in the shared memory with topology information as input */ 893 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 894 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 895 topology_info_input->num_nodes = number_devices; 896 897 for (i = 0; i < topology_info_input->num_nodes; i++) { 898 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 899 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 900 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 901 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 902 } 903 904 /* Invoke xgmi ta to get the topology information */ 905 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 906 if (ret) 907 return ret; 908 909 /* Read the output topology information from the shared memory */ 910 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 911 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 912 for (i = 0; i < topology->num_nodes; i++) { 913 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 914 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 915 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 916 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 917 } 918 919 return 0; 920 } 921 922 int psp_xgmi_set_topology_info(struct psp_context *psp, 923 int number_devices, 924 struct psp_xgmi_topology_info *topology) 925 { 926 struct ta_xgmi_shared_memory *xgmi_cmd; 927 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 928 int i; 929 930 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 931 return -EINVAL; 932 933 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 934 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 935 936 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 937 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 938 topology_info_input->num_nodes = number_devices; 939 940 for (i = 0; i < topology_info_input->num_nodes; i++) { 941 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 942 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 943 topology_info_input->nodes[i].is_sharing_enabled = 1; 944 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 945 } 946 947 /* Invoke xgmi ta to set topology information */ 948 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 949 } 950 951 // ras begin 952 static int psp_ras_init_shared_buf(struct psp_context *psp) 953 { 954 int ret; 955 956 /* 957 * Allocate 16k memory aligned to 4k from Frame Buffer (local 958 * physical) for ras ta <-> Driver 959 */ 960 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 961 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 962 &psp->ras.ras_shared_bo, 963 &psp->ras.ras_shared_mc_addr, 964 &psp->ras.ras_shared_buf); 965 966 return ret; 967 } 968 969 static int psp_ras_load(struct psp_context *psp) 970 { 971 int ret; 972 struct psp_gfx_cmd_resp *cmd; 973 struct ta_ras_shared_memory *ras_cmd; 974 975 /* 976 * TODO: bypass the loading in sriov for now 977 */ 978 if (amdgpu_sriov_vf(psp->adev)) 979 return 0; 980 981 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 982 if (!cmd) 983 return -ENOMEM; 984 985 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 986 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 987 988 psp_prep_ta_load_cmd_buf(cmd, 989 psp->fw_pri_mc_addr, 990 psp->ta_ras_ucode_size, 991 psp->ras.ras_shared_mc_addr, 992 PSP_RAS_SHARED_MEM_SIZE); 993 994 ret = psp_cmd_submit_buf(psp, NULL, cmd, 995 psp->fence_buf_mc_addr); 996 997 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 998 999 if (!ret) { 1000 psp->ras.session_id = cmd->resp.session_id; 1001 1002 if (!ras_cmd->ras_status) 1003 psp->ras.ras_initialized = true; 1004 else 1005 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1006 } 1007 1008 if (ret || ras_cmd->ras_status) 1009 amdgpu_ras_fini(psp->adev); 1010 1011 kfree(cmd); 1012 1013 return ret; 1014 } 1015 1016 static int psp_ras_unload(struct psp_context *psp) 1017 { 1018 int ret; 1019 struct psp_gfx_cmd_resp *cmd; 1020 1021 /* 1022 * TODO: bypass the unloading in sriov for now 1023 */ 1024 if (amdgpu_sriov_vf(psp->adev)) 1025 return 0; 1026 1027 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1028 if (!cmd) 1029 return -ENOMEM; 1030 1031 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 1032 1033 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1034 psp->fence_buf_mc_addr); 1035 1036 kfree(cmd); 1037 1038 return ret; 1039 } 1040 1041 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1042 { 1043 struct ta_ras_shared_memory *ras_cmd; 1044 int ret; 1045 1046 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1047 1048 /* 1049 * TODO: bypass the loading in sriov for now 1050 */ 1051 if (amdgpu_sriov_vf(psp->adev)) 1052 return 0; 1053 1054 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 1055 1056 if (amdgpu_ras_intr_triggered()) 1057 return ret; 1058 1059 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1060 { 1061 DRM_WARN("RAS: Unsupported Interface"); 1062 return -EINVAL; 1063 } 1064 1065 if (!ret) { 1066 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1067 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1068 1069 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1070 } 1071 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1072 dev_warn(psp->adev->dev, 1073 "RAS internal register access blocked\n"); 1074 } 1075 1076 return ret; 1077 } 1078 1079 int psp_ras_enable_features(struct psp_context *psp, 1080 union ta_ras_cmd_input *info, bool enable) 1081 { 1082 struct ta_ras_shared_memory *ras_cmd; 1083 int ret; 1084 1085 if (!psp->ras.ras_initialized) 1086 return -EINVAL; 1087 1088 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1089 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1090 1091 if (enable) 1092 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1093 else 1094 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1095 1096 ras_cmd->ras_in_message = *info; 1097 1098 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1099 if (ret) 1100 return -EINVAL; 1101 1102 return ras_cmd->ras_status; 1103 } 1104 1105 static int psp_ras_terminate(struct psp_context *psp) 1106 { 1107 int ret; 1108 1109 /* 1110 * TODO: bypass the terminate in sriov for now 1111 */ 1112 if (amdgpu_sriov_vf(psp->adev)) 1113 return 0; 1114 1115 if (!psp->ras.ras_initialized) 1116 return 0; 1117 1118 ret = psp_ras_unload(psp); 1119 if (ret) 1120 return ret; 1121 1122 psp->ras.ras_initialized = false; 1123 1124 /* free ras shared memory */ 1125 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1126 &psp->ras.ras_shared_mc_addr, 1127 &psp->ras.ras_shared_buf); 1128 1129 return 0; 1130 } 1131 1132 static int psp_ras_initialize(struct psp_context *psp) 1133 { 1134 int ret; 1135 1136 /* 1137 * TODO: bypass the initialize in sriov for now 1138 */ 1139 if (amdgpu_sriov_vf(psp->adev)) 1140 return 0; 1141 1142 if (!psp->adev->psp.ta_ras_ucode_size || 1143 !psp->adev->psp.ta_ras_start_addr) { 1144 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n"); 1145 return 0; 1146 } 1147 1148 if (!psp->ras.ras_initialized) { 1149 ret = psp_ras_init_shared_buf(psp); 1150 if (ret) 1151 return ret; 1152 } 1153 1154 ret = psp_ras_load(psp); 1155 if (ret) 1156 return ret; 1157 1158 return 0; 1159 } 1160 1161 int psp_ras_trigger_error(struct psp_context *psp, 1162 struct ta_ras_trigger_error_input *info) 1163 { 1164 struct ta_ras_shared_memory *ras_cmd; 1165 int ret; 1166 1167 if (!psp->ras.ras_initialized) 1168 return -EINVAL; 1169 1170 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1171 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1172 1173 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1174 ras_cmd->ras_in_message.trigger_error = *info; 1175 1176 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1177 if (ret) 1178 return -EINVAL; 1179 1180 /* If err_event_athub occurs error inject was successful, however 1181 return status from TA is no long reliable */ 1182 if (amdgpu_ras_intr_triggered()) 1183 return 0; 1184 1185 return ras_cmd->ras_status; 1186 } 1187 // ras end 1188 1189 // HDCP start 1190 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1191 { 1192 int ret; 1193 1194 /* 1195 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1196 * physical) for hdcp ta <-> Driver 1197 */ 1198 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1199 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1200 &psp->hdcp_context.hdcp_shared_bo, 1201 &psp->hdcp_context.hdcp_shared_mc_addr, 1202 &psp->hdcp_context.hdcp_shared_buf); 1203 1204 return ret; 1205 } 1206 1207 static int psp_hdcp_load(struct psp_context *psp) 1208 { 1209 int ret; 1210 struct psp_gfx_cmd_resp *cmd; 1211 1212 /* 1213 * TODO: bypass the loading in sriov for now 1214 */ 1215 if (amdgpu_sriov_vf(psp->adev)) 1216 return 0; 1217 1218 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1219 if (!cmd) 1220 return -ENOMEM; 1221 1222 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1223 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr, 1224 psp->ta_hdcp_ucode_size); 1225 1226 psp_prep_ta_load_cmd_buf(cmd, 1227 psp->fw_pri_mc_addr, 1228 psp->ta_hdcp_ucode_size, 1229 psp->hdcp_context.hdcp_shared_mc_addr, 1230 PSP_HDCP_SHARED_MEM_SIZE); 1231 1232 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1233 1234 if (!ret) { 1235 psp->hdcp_context.hdcp_initialized = true; 1236 psp->hdcp_context.session_id = cmd->resp.session_id; 1237 mutex_init(&psp->hdcp_context.mutex); 1238 } 1239 1240 kfree(cmd); 1241 1242 return ret; 1243 } 1244 static int psp_hdcp_initialize(struct psp_context *psp) 1245 { 1246 int ret; 1247 1248 /* 1249 * TODO: bypass the initialize in sriov for now 1250 */ 1251 if (amdgpu_sriov_vf(psp->adev)) 1252 return 0; 1253 1254 if (!psp->adev->psp.ta_hdcp_ucode_size || 1255 !psp->adev->psp.ta_hdcp_start_addr) { 1256 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1257 return 0; 1258 } 1259 1260 if (!psp->hdcp_context.hdcp_initialized) { 1261 ret = psp_hdcp_init_shared_buf(psp); 1262 if (ret) 1263 return ret; 1264 } 1265 1266 ret = psp_hdcp_load(psp); 1267 if (ret) 1268 return ret; 1269 1270 return 0; 1271 } 1272 1273 static int psp_hdcp_unload(struct psp_context *psp) 1274 { 1275 int ret; 1276 struct psp_gfx_cmd_resp *cmd; 1277 1278 /* 1279 * TODO: bypass the unloading in sriov for now 1280 */ 1281 if (amdgpu_sriov_vf(psp->adev)) 1282 return 0; 1283 1284 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1285 if (!cmd) 1286 return -ENOMEM; 1287 1288 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1289 1290 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1291 1292 kfree(cmd); 1293 1294 return ret; 1295 } 1296 1297 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1298 { 1299 /* 1300 * TODO: bypass the loading in sriov for now 1301 */ 1302 if (amdgpu_sriov_vf(psp->adev)) 1303 return 0; 1304 1305 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1306 } 1307 1308 static int psp_hdcp_terminate(struct psp_context *psp) 1309 { 1310 int ret; 1311 1312 /* 1313 * TODO: bypass the terminate in sriov for now 1314 */ 1315 if (amdgpu_sriov_vf(psp->adev)) 1316 return 0; 1317 1318 if (!psp->hdcp_context.hdcp_initialized) { 1319 if (psp->hdcp_context.hdcp_shared_buf) 1320 goto out; 1321 else 1322 return 0; 1323 } 1324 1325 ret = psp_hdcp_unload(psp); 1326 if (ret) 1327 return ret; 1328 1329 psp->hdcp_context.hdcp_initialized = false; 1330 1331 out: 1332 /* free hdcp shared memory */ 1333 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1334 &psp->hdcp_context.hdcp_shared_mc_addr, 1335 &psp->hdcp_context.hdcp_shared_buf); 1336 1337 return 0; 1338 } 1339 // HDCP end 1340 1341 // DTM start 1342 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1343 { 1344 int ret; 1345 1346 /* 1347 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1348 * physical) for dtm ta <-> Driver 1349 */ 1350 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1351 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1352 &psp->dtm_context.dtm_shared_bo, 1353 &psp->dtm_context.dtm_shared_mc_addr, 1354 &psp->dtm_context.dtm_shared_buf); 1355 1356 return ret; 1357 } 1358 1359 static int psp_dtm_load(struct psp_context *psp) 1360 { 1361 int ret; 1362 struct psp_gfx_cmd_resp *cmd; 1363 1364 /* 1365 * TODO: bypass the loading in sriov for now 1366 */ 1367 if (amdgpu_sriov_vf(psp->adev)) 1368 return 0; 1369 1370 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1371 if (!cmd) 1372 return -ENOMEM; 1373 1374 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1375 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1376 1377 psp_prep_ta_load_cmd_buf(cmd, 1378 psp->fw_pri_mc_addr, 1379 psp->ta_dtm_ucode_size, 1380 psp->dtm_context.dtm_shared_mc_addr, 1381 PSP_DTM_SHARED_MEM_SIZE); 1382 1383 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1384 1385 if (!ret) { 1386 psp->dtm_context.dtm_initialized = true; 1387 psp->dtm_context.session_id = cmd->resp.session_id; 1388 mutex_init(&psp->dtm_context.mutex); 1389 } 1390 1391 kfree(cmd); 1392 1393 return ret; 1394 } 1395 1396 static int psp_dtm_initialize(struct psp_context *psp) 1397 { 1398 int ret; 1399 1400 /* 1401 * TODO: bypass the initialize in sriov for now 1402 */ 1403 if (amdgpu_sriov_vf(psp->adev)) 1404 return 0; 1405 1406 if (!psp->adev->psp.ta_dtm_ucode_size || 1407 !psp->adev->psp.ta_dtm_start_addr) { 1408 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1409 return 0; 1410 } 1411 1412 if (!psp->dtm_context.dtm_initialized) { 1413 ret = psp_dtm_init_shared_buf(psp); 1414 if (ret) 1415 return ret; 1416 } 1417 1418 ret = psp_dtm_load(psp); 1419 if (ret) 1420 return ret; 1421 1422 return 0; 1423 } 1424 1425 static int psp_dtm_unload(struct psp_context *psp) 1426 { 1427 int ret; 1428 struct psp_gfx_cmd_resp *cmd; 1429 1430 /* 1431 * TODO: bypass the unloading in sriov for now 1432 */ 1433 if (amdgpu_sriov_vf(psp->adev)) 1434 return 0; 1435 1436 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1437 if (!cmd) 1438 return -ENOMEM; 1439 1440 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1441 1442 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1443 1444 kfree(cmd); 1445 1446 return ret; 1447 } 1448 1449 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1450 { 1451 /* 1452 * TODO: bypass the loading in sriov for now 1453 */ 1454 if (amdgpu_sriov_vf(psp->adev)) 1455 return 0; 1456 1457 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1458 } 1459 1460 static int psp_dtm_terminate(struct psp_context *psp) 1461 { 1462 int ret; 1463 1464 /* 1465 * TODO: bypass the terminate in sriov for now 1466 */ 1467 if (amdgpu_sriov_vf(psp->adev)) 1468 return 0; 1469 1470 if (!psp->dtm_context.dtm_initialized) { 1471 if (psp->dtm_context.dtm_shared_buf) 1472 goto out; 1473 else 1474 return 0; 1475 } 1476 1477 ret = psp_dtm_unload(psp); 1478 if (ret) 1479 return ret; 1480 1481 psp->dtm_context.dtm_initialized = false; 1482 1483 out: 1484 /* free hdcp shared memory */ 1485 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1486 &psp->dtm_context.dtm_shared_mc_addr, 1487 &psp->dtm_context.dtm_shared_buf); 1488 1489 return 0; 1490 } 1491 // DTM end 1492 1493 // RAP start 1494 static int psp_rap_init_shared_buf(struct psp_context *psp) 1495 { 1496 int ret; 1497 1498 /* 1499 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1500 * physical) for rap ta <-> Driver 1501 */ 1502 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE, 1503 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1504 &psp->rap_context.rap_shared_bo, 1505 &psp->rap_context.rap_shared_mc_addr, 1506 &psp->rap_context.rap_shared_buf); 1507 1508 return ret; 1509 } 1510 1511 static int psp_rap_load(struct psp_context *psp) 1512 { 1513 int ret; 1514 struct psp_gfx_cmd_resp *cmd; 1515 1516 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1517 if (!cmd) 1518 return -ENOMEM; 1519 1520 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1521 memcpy(psp->fw_pri_buf, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); 1522 1523 psp_prep_ta_load_cmd_buf(cmd, 1524 psp->fw_pri_mc_addr, 1525 psp->ta_rap_ucode_size, 1526 psp->rap_context.rap_shared_mc_addr, 1527 PSP_RAP_SHARED_MEM_SIZE); 1528 1529 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1530 1531 if (!ret) { 1532 psp->rap_context.rap_initialized = true; 1533 psp->rap_context.session_id = cmd->resp.session_id; 1534 mutex_init(&psp->rap_context.mutex); 1535 } 1536 1537 kfree(cmd); 1538 1539 return ret; 1540 } 1541 1542 static int psp_rap_unload(struct psp_context *psp) 1543 { 1544 int ret; 1545 struct psp_gfx_cmd_resp *cmd; 1546 1547 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1548 if (!cmd) 1549 return -ENOMEM; 1550 1551 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id); 1552 1553 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1554 1555 kfree(cmd); 1556 1557 return ret; 1558 } 1559 1560 static int psp_rap_initialize(struct psp_context *psp) 1561 { 1562 int ret; 1563 1564 /* 1565 * TODO: bypass the initialize in sriov for now 1566 */ 1567 if (amdgpu_sriov_vf(psp->adev)) 1568 return 0; 1569 1570 if (!psp->adev->psp.ta_rap_ucode_size || 1571 !psp->adev->psp.ta_rap_start_addr) { 1572 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1573 return 0; 1574 } 1575 1576 if (!psp->rap_context.rap_initialized) { 1577 ret = psp_rap_init_shared_buf(psp); 1578 if (ret) 1579 return ret; 1580 } 1581 1582 ret = psp_rap_load(psp); 1583 if (ret) 1584 return ret; 1585 1586 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE); 1587 if (ret != TA_RAP_STATUS__SUCCESS) { 1588 psp_rap_unload(psp); 1589 1590 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1591 &psp->rap_context.rap_shared_mc_addr, 1592 &psp->rap_context.rap_shared_buf); 1593 1594 psp->rap_context.rap_initialized = false; 1595 1596 dev_warn(psp->adev->dev, "RAP TA initialize fail.\n"); 1597 return -EINVAL; 1598 } 1599 1600 return 0; 1601 } 1602 1603 static int psp_rap_terminate(struct psp_context *psp) 1604 { 1605 int ret; 1606 1607 if (!psp->rap_context.rap_initialized) 1608 return 0; 1609 1610 ret = psp_rap_unload(psp); 1611 1612 psp->rap_context.rap_initialized = false; 1613 1614 /* free rap shared memory */ 1615 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1616 &psp->rap_context.rap_shared_mc_addr, 1617 &psp->rap_context.rap_shared_buf); 1618 1619 return ret; 1620 } 1621 1622 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1623 { 1624 struct ta_rap_shared_memory *rap_cmd; 1625 int ret; 1626 1627 if (!psp->rap_context.rap_initialized) 1628 return -EINVAL; 1629 1630 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1631 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1632 return -EINVAL; 1633 1634 mutex_lock(&psp->rap_context.mutex); 1635 1636 rap_cmd = (struct ta_rap_shared_memory *) 1637 psp->rap_context.rap_shared_buf; 1638 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1639 1640 rap_cmd->cmd_id = ta_cmd_id; 1641 rap_cmd->validation_method_id = METHOD_A; 1642 1643 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id); 1644 if (ret) { 1645 mutex_unlock(&psp->rap_context.mutex); 1646 return ret; 1647 } 1648 1649 mutex_unlock(&psp->rap_context.mutex); 1650 1651 return rap_cmd->rap_status; 1652 } 1653 // RAP end 1654 1655 static int psp_hw_start(struct psp_context *psp) 1656 { 1657 struct amdgpu_device *adev = psp->adev; 1658 int ret; 1659 1660 if (!amdgpu_sriov_vf(adev)) { 1661 if (psp->kdb_bin_size && 1662 (psp->funcs->bootloader_load_kdb != NULL)) { 1663 ret = psp_bootloader_load_kdb(psp); 1664 if (ret) { 1665 DRM_ERROR("PSP load kdb failed!\n"); 1666 return ret; 1667 } 1668 } 1669 1670 if (psp->spl_bin_size) { 1671 ret = psp_bootloader_load_spl(psp); 1672 if (ret) { 1673 DRM_ERROR("PSP load spl failed!\n"); 1674 return ret; 1675 } 1676 } 1677 1678 ret = psp_bootloader_load_sysdrv(psp); 1679 if (ret) { 1680 DRM_ERROR("PSP load sysdrv failed!\n"); 1681 return ret; 1682 } 1683 1684 ret = psp_bootloader_load_sos(psp); 1685 if (ret) { 1686 DRM_ERROR("PSP load sos failed!\n"); 1687 return ret; 1688 } 1689 } 1690 1691 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1692 if (ret) { 1693 DRM_ERROR("PSP create ring failed!\n"); 1694 return ret; 1695 } 1696 1697 ret = psp_clear_vf_fw(psp); 1698 if (ret) { 1699 DRM_ERROR("PSP clear vf fw!\n"); 1700 return ret; 1701 } 1702 1703 ret = psp_tmr_init(psp); 1704 if (ret) { 1705 DRM_ERROR("PSP tmr init failed!\n"); 1706 return ret; 1707 } 1708 1709 /* 1710 * For ASICs with DF Cstate management centralized 1711 * to PMFW, TMR setup should be performed after PMFW 1712 * loaded and before other non-psp firmware loaded. 1713 */ 1714 if (psp->pmfw_centralized_cstate_management) { 1715 ret = psp_load_smu_fw(psp); 1716 if (ret) 1717 return ret; 1718 } 1719 1720 ret = psp_tmr_load(psp); 1721 if (ret) { 1722 DRM_ERROR("PSP load tmr failed!\n"); 1723 return ret; 1724 } 1725 1726 return 0; 1727 } 1728 1729 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 1730 enum psp_gfx_fw_type *type) 1731 { 1732 switch (ucode->ucode_id) { 1733 case AMDGPU_UCODE_ID_SDMA0: 1734 *type = GFX_FW_TYPE_SDMA0; 1735 break; 1736 case AMDGPU_UCODE_ID_SDMA1: 1737 *type = GFX_FW_TYPE_SDMA1; 1738 break; 1739 case AMDGPU_UCODE_ID_SDMA2: 1740 *type = GFX_FW_TYPE_SDMA2; 1741 break; 1742 case AMDGPU_UCODE_ID_SDMA3: 1743 *type = GFX_FW_TYPE_SDMA3; 1744 break; 1745 case AMDGPU_UCODE_ID_SDMA4: 1746 *type = GFX_FW_TYPE_SDMA4; 1747 break; 1748 case AMDGPU_UCODE_ID_SDMA5: 1749 *type = GFX_FW_TYPE_SDMA5; 1750 break; 1751 case AMDGPU_UCODE_ID_SDMA6: 1752 *type = GFX_FW_TYPE_SDMA6; 1753 break; 1754 case AMDGPU_UCODE_ID_SDMA7: 1755 *type = GFX_FW_TYPE_SDMA7; 1756 break; 1757 case AMDGPU_UCODE_ID_CP_MES: 1758 *type = GFX_FW_TYPE_CP_MES; 1759 break; 1760 case AMDGPU_UCODE_ID_CP_MES_DATA: 1761 *type = GFX_FW_TYPE_MES_STACK; 1762 break; 1763 case AMDGPU_UCODE_ID_CP_CE: 1764 *type = GFX_FW_TYPE_CP_CE; 1765 break; 1766 case AMDGPU_UCODE_ID_CP_PFP: 1767 *type = GFX_FW_TYPE_CP_PFP; 1768 break; 1769 case AMDGPU_UCODE_ID_CP_ME: 1770 *type = GFX_FW_TYPE_CP_ME; 1771 break; 1772 case AMDGPU_UCODE_ID_CP_MEC1: 1773 *type = GFX_FW_TYPE_CP_MEC; 1774 break; 1775 case AMDGPU_UCODE_ID_CP_MEC1_JT: 1776 *type = GFX_FW_TYPE_CP_MEC_ME1; 1777 break; 1778 case AMDGPU_UCODE_ID_CP_MEC2: 1779 *type = GFX_FW_TYPE_CP_MEC; 1780 break; 1781 case AMDGPU_UCODE_ID_CP_MEC2_JT: 1782 *type = GFX_FW_TYPE_CP_MEC_ME2; 1783 break; 1784 case AMDGPU_UCODE_ID_RLC_G: 1785 *type = GFX_FW_TYPE_RLC_G; 1786 break; 1787 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 1788 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 1789 break; 1790 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 1791 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 1792 break; 1793 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 1794 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 1795 break; 1796 case AMDGPU_UCODE_ID_RLC_IRAM: 1797 *type = GFX_FW_TYPE_RLC_IRAM; 1798 break; 1799 case AMDGPU_UCODE_ID_RLC_DRAM: 1800 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 1801 break; 1802 case AMDGPU_UCODE_ID_SMC: 1803 *type = GFX_FW_TYPE_SMU; 1804 break; 1805 case AMDGPU_UCODE_ID_UVD: 1806 *type = GFX_FW_TYPE_UVD; 1807 break; 1808 case AMDGPU_UCODE_ID_UVD1: 1809 *type = GFX_FW_TYPE_UVD1; 1810 break; 1811 case AMDGPU_UCODE_ID_VCE: 1812 *type = GFX_FW_TYPE_VCE; 1813 break; 1814 case AMDGPU_UCODE_ID_VCN: 1815 *type = GFX_FW_TYPE_VCN; 1816 break; 1817 case AMDGPU_UCODE_ID_VCN1: 1818 *type = GFX_FW_TYPE_VCN1; 1819 break; 1820 case AMDGPU_UCODE_ID_DMCU_ERAM: 1821 *type = GFX_FW_TYPE_DMCU_ERAM; 1822 break; 1823 case AMDGPU_UCODE_ID_DMCU_INTV: 1824 *type = GFX_FW_TYPE_DMCU_ISR; 1825 break; 1826 case AMDGPU_UCODE_ID_VCN0_RAM: 1827 *type = GFX_FW_TYPE_VCN0_RAM; 1828 break; 1829 case AMDGPU_UCODE_ID_VCN1_RAM: 1830 *type = GFX_FW_TYPE_VCN1_RAM; 1831 break; 1832 case AMDGPU_UCODE_ID_DMCUB: 1833 *type = GFX_FW_TYPE_DMUB; 1834 break; 1835 case AMDGPU_UCODE_ID_MAXIMUM: 1836 default: 1837 return -EINVAL; 1838 } 1839 1840 return 0; 1841 } 1842 1843 static void psp_print_fw_hdr(struct psp_context *psp, 1844 struct amdgpu_firmware_info *ucode) 1845 { 1846 struct amdgpu_device *adev = psp->adev; 1847 struct common_firmware_header *hdr; 1848 1849 switch (ucode->ucode_id) { 1850 case AMDGPU_UCODE_ID_SDMA0: 1851 case AMDGPU_UCODE_ID_SDMA1: 1852 case AMDGPU_UCODE_ID_SDMA2: 1853 case AMDGPU_UCODE_ID_SDMA3: 1854 case AMDGPU_UCODE_ID_SDMA4: 1855 case AMDGPU_UCODE_ID_SDMA5: 1856 case AMDGPU_UCODE_ID_SDMA6: 1857 case AMDGPU_UCODE_ID_SDMA7: 1858 hdr = (struct common_firmware_header *) 1859 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 1860 amdgpu_ucode_print_sdma_hdr(hdr); 1861 break; 1862 case AMDGPU_UCODE_ID_CP_CE: 1863 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 1864 amdgpu_ucode_print_gfx_hdr(hdr); 1865 break; 1866 case AMDGPU_UCODE_ID_CP_PFP: 1867 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 1868 amdgpu_ucode_print_gfx_hdr(hdr); 1869 break; 1870 case AMDGPU_UCODE_ID_CP_ME: 1871 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 1872 amdgpu_ucode_print_gfx_hdr(hdr); 1873 break; 1874 case AMDGPU_UCODE_ID_CP_MEC1: 1875 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 1876 amdgpu_ucode_print_gfx_hdr(hdr); 1877 break; 1878 case AMDGPU_UCODE_ID_RLC_G: 1879 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 1880 amdgpu_ucode_print_rlc_hdr(hdr); 1881 break; 1882 case AMDGPU_UCODE_ID_SMC: 1883 hdr = (struct common_firmware_header *)adev->pm.fw->data; 1884 amdgpu_ucode_print_smc_hdr(hdr); 1885 break; 1886 default: 1887 break; 1888 } 1889 } 1890 1891 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 1892 struct psp_gfx_cmd_resp *cmd) 1893 { 1894 int ret; 1895 uint64_t fw_mem_mc_addr = ucode->mc_addr; 1896 1897 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 1898 1899 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1900 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 1901 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 1902 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 1903 1904 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 1905 if (ret) 1906 DRM_ERROR("Unknown firmware type\n"); 1907 1908 return ret; 1909 } 1910 1911 static int psp_execute_np_fw_load(struct psp_context *psp, 1912 struct amdgpu_firmware_info *ucode) 1913 { 1914 int ret = 0; 1915 1916 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 1917 if (ret) 1918 return ret; 1919 1920 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 1921 psp->fence_buf_mc_addr); 1922 1923 return ret; 1924 } 1925 1926 static int psp_load_smu_fw(struct psp_context *psp) 1927 { 1928 int ret; 1929 struct amdgpu_device *adev = psp->adev; 1930 struct amdgpu_firmware_info *ucode = 1931 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 1932 struct amdgpu_ras *ras = psp->ras.ras; 1933 1934 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 1935 return 0; 1936 1937 1938 if (amdgpu_in_reset(adev) && ras && ras->supported && 1939 adev->asic_type == CHIP_ARCTURUS) { 1940 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 1941 if (ret) { 1942 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 1943 } 1944 } 1945 1946 ret = psp_execute_np_fw_load(psp, ucode); 1947 1948 if (ret) 1949 DRM_ERROR("PSP load smu failed!\n"); 1950 1951 return ret; 1952 } 1953 1954 static bool fw_load_skip_check(struct psp_context *psp, 1955 struct amdgpu_firmware_info *ucode) 1956 { 1957 if (!ucode->fw) 1958 return true; 1959 1960 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 1961 (psp_smu_reload_quirk(psp) || 1962 psp->autoload_supported || 1963 psp->pmfw_centralized_cstate_management)) 1964 return true; 1965 1966 if (amdgpu_sriov_vf(psp->adev) && 1967 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 1968 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 1969 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 1970 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 1971 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 1972 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 1973 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 1974 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 1975 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 1976 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 1977 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 1978 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 1979 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 1980 /*skip ucode loading in SRIOV VF */ 1981 return true; 1982 1983 if (psp->autoload_supported && 1984 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 1985 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 1986 /* skip mec JT when autoload is enabled */ 1987 return true; 1988 1989 return false; 1990 } 1991 1992 static int psp_np_fw_load(struct psp_context *psp) 1993 { 1994 int i, ret; 1995 struct amdgpu_firmware_info *ucode; 1996 struct amdgpu_device *adev = psp->adev; 1997 1998 if (psp->autoload_supported && 1999 !psp->pmfw_centralized_cstate_management) { 2000 ret = psp_load_smu_fw(psp); 2001 if (ret) 2002 return ret; 2003 } 2004 2005 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2006 ucode = &adev->firmware.ucode[i]; 2007 2008 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2009 !fw_load_skip_check(psp, ucode)) { 2010 ret = psp_load_smu_fw(psp); 2011 if (ret) 2012 return ret; 2013 continue; 2014 } 2015 2016 if (fw_load_skip_check(psp, ucode)) 2017 continue; 2018 2019 if (psp->autoload_supported && 2020 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2021 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2022 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2023 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2024 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2025 /* PSP only receive one SDMA fw for sienna_cichlid, 2026 * as all four sdma fw are same */ 2027 continue; 2028 2029 psp_print_fw_hdr(psp, ucode); 2030 2031 ret = psp_execute_np_fw_load(psp, ucode); 2032 if (ret) 2033 return ret; 2034 2035 /* Start rlc autoload after psp recieved all the gfx firmware */ 2036 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2037 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2038 ret = psp_rlc_autoload_start(psp); 2039 if (ret) { 2040 DRM_ERROR("Failed to start rlc autoload\n"); 2041 return ret; 2042 } 2043 } 2044 } 2045 2046 return 0; 2047 } 2048 2049 static int psp_load_fw(struct amdgpu_device *adev) 2050 { 2051 int ret; 2052 struct psp_context *psp = &adev->psp; 2053 2054 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2055 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2056 goto skip_memalloc; 2057 } 2058 2059 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2060 if (!psp->cmd) 2061 return -ENOMEM; 2062 2063 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2064 AMDGPU_GEM_DOMAIN_GTT, 2065 &psp->fw_pri_bo, 2066 &psp->fw_pri_mc_addr, 2067 &psp->fw_pri_buf); 2068 if (ret) 2069 goto failed; 2070 2071 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2072 AMDGPU_GEM_DOMAIN_VRAM, 2073 &psp->fence_buf_bo, 2074 &psp->fence_buf_mc_addr, 2075 &psp->fence_buf); 2076 if (ret) 2077 goto failed; 2078 2079 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2080 AMDGPU_GEM_DOMAIN_VRAM, 2081 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2082 (void **)&psp->cmd_buf_mem); 2083 if (ret) 2084 goto failed; 2085 2086 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2087 2088 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2089 if (ret) { 2090 DRM_ERROR("PSP ring init failed!\n"); 2091 goto failed; 2092 } 2093 2094 skip_memalloc: 2095 ret = psp_hw_start(psp); 2096 if (ret) 2097 goto failed; 2098 2099 ret = psp_np_fw_load(psp); 2100 if (ret) 2101 goto failed; 2102 2103 ret = psp_asd_load(psp); 2104 if (ret) { 2105 DRM_ERROR("PSP load asd failed!\n"); 2106 return ret; 2107 } 2108 2109 if (psp->adev->psp.ta_fw) { 2110 ret = psp_ras_initialize(psp); 2111 if (ret) 2112 dev_err(psp->adev->dev, 2113 "RAS: Failed to initialize RAS\n"); 2114 2115 ret = psp_hdcp_initialize(psp); 2116 if (ret) 2117 dev_err(psp->adev->dev, 2118 "HDCP: Failed to initialize HDCP\n"); 2119 2120 ret = psp_dtm_initialize(psp); 2121 if (ret) 2122 dev_err(psp->adev->dev, 2123 "DTM: Failed to initialize DTM\n"); 2124 2125 ret = psp_rap_initialize(psp); 2126 if (ret) 2127 dev_err(psp->adev->dev, 2128 "RAP: Failed to initialize RAP\n"); 2129 } 2130 2131 return 0; 2132 2133 failed: 2134 /* 2135 * all cleanup jobs (xgmi terminate, ras terminate, 2136 * ring destroy, cmd/fence/fw buffers destory, 2137 * psp->cmd destory) are delayed to psp_hw_fini 2138 */ 2139 return ret; 2140 } 2141 2142 static int psp_hw_init(void *handle) 2143 { 2144 int ret; 2145 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2146 2147 mutex_lock(&adev->firmware.mutex); 2148 /* 2149 * This sequence is just used on hw_init only once, no need on 2150 * resume. 2151 */ 2152 ret = amdgpu_ucode_init_bo(adev); 2153 if (ret) 2154 goto failed; 2155 2156 ret = psp_load_fw(adev); 2157 if (ret) { 2158 DRM_ERROR("PSP firmware loading failed\n"); 2159 goto failed; 2160 } 2161 2162 mutex_unlock(&adev->firmware.mutex); 2163 return 0; 2164 2165 failed: 2166 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2167 mutex_unlock(&adev->firmware.mutex); 2168 return -EINVAL; 2169 } 2170 2171 static int psp_hw_fini(void *handle) 2172 { 2173 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2174 struct psp_context *psp = &adev->psp; 2175 int ret; 2176 2177 if (psp->adev->psp.ta_fw) { 2178 psp_ras_terminate(psp); 2179 psp_rap_terminate(psp); 2180 psp_dtm_terminate(psp); 2181 psp_hdcp_terminate(psp); 2182 } 2183 2184 psp_asd_unload(psp); 2185 ret = psp_clear_vf_fw(psp); 2186 if (ret) { 2187 DRM_ERROR("PSP clear vf fw!\n"); 2188 return ret; 2189 } 2190 2191 psp_tmr_terminate(psp); 2192 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2193 2194 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2195 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2196 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2197 &psp->fence_buf_mc_addr, &psp->fence_buf); 2198 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2199 (void **)&psp->cmd_buf_mem); 2200 2201 kfree(psp->cmd); 2202 psp->cmd = NULL; 2203 2204 return 0; 2205 } 2206 2207 static int psp_suspend(void *handle) 2208 { 2209 int ret; 2210 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2211 struct psp_context *psp = &adev->psp; 2212 2213 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2214 psp->xgmi_context.initialized == 1) { 2215 ret = psp_xgmi_terminate(psp); 2216 if (ret) { 2217 DRM_ERROR("Failed to terminate xgmi ta\n"); 2218 return ret; 2219 } 2220 } 2221 2222 if (psp->adev->psp.ta_fw) { 2223 ret = psp_ras_terminate(psp); 2224 if (ret) { 2225 DRM_ERROR("Failed to terminate ras ta\n"); 2226 return ret; 2227 } 2228 ret = psp_hdcp_terminate(psp); 2229 if (ret) { 2230 DRM_ERROR("Failed to terminate hdcp ta\n"); 2231 return ret; 2232 } 2233 ret = psp_dtm_terminate(psp); 2234 if (ret) { 2235 DRM_ERROR("Failed to terminate dtm ta\n"); 2236 return ret; 2237 } 2238 ret = psp_rap_terminate(psp); 2239 if (ret) { 2240 DRM_ERROR("Failed to terminate rap ta\n"); 2241 return ret; 2242 } 2243 } 2244 2245 ret = psp_asd_unload(psp); 2246 if (ret) { 2247 DRM_ERROR("Failed to unload asd\n"); 2248 return ret; 2249 } 2250 2251 ret = psp_tmr_terminate(psp); 2252 if (ret) { 2253 DRM_ERROR("Failed to terminate tmr\n"); 2254 return ret; 2255 } 2256 2257 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2258 if (ret) { 2259 DRM_ERROR("PSP ring stop failed\n"); 2260 return ret; 2261 } 2262 2263 return 0; 2264 } 2265 2266 static int psp_resume(void *handle) 2267 { 2268 int ret; 2269 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2270 struct psp_context *psp = &adev->psp; 2271 2272 DRM_INFO("PSP is resuming...\n"); 2273 2274 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2275 if (ret) { 2276 DRM_ERROR("Failed to process memory training!\n"); 2277 return ret; 2278 } 2279 2280 mutex_lock(&adev->firmware.mutex); 2281 2282 ret = psp_hw_start(psp); 2283 if (ret) 2284 goto failed; 2285 2286 ret = psp_np_fw_load(psp); 2287 if (ret) 2288 goto failed; 2289 2290 ret = psp_asd_load(psp); 2291 if (ret) { 2292 DRM_ERROR("PSP load asd failed!\n"); 2293 goto failed; 2294 } 2295 2296 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2297 ret = psp_xgmi_initialize(psp); 2298 /* Warning the XGMI seesion initialize failure 2299 * Instead of stop driver initialization 2300 */ 2301 if (ret) 2302 dev_err(psp->adev->dev, 2303 "XGMI: Failed to initialize XGMI session\n"); 2304 } 2305 2306 if (psp->adev->psp.ta_fw) { 2307 ret = psp_ras_initialize(psp); 2308 if (ret) 2309 dev_err(psp->adev->dev, 2310 "RAS: Failed to initialize RAS\n"); 2311 2312 ret = psp_hdcp_initialize(psp); 2313 if (ret) 2314 dev_err(psp->adev->dev, 2315 "HDCP: Failed to initialize HDCP\n"); 2316 2317 ret = psp_dtm_initialize(psp); 2318 if (ret) 2319 dev_err(psp->adev->dev, 2320 "DTM: Failed to initialize DTM\n"); 2321 2322 ret = psp_rap_initialize(psp); 2323 if (ret) 2324 dev_err(psp->adev->dev, 2325 "RAP: Failed to initialize RAP\n"); 2326 } 2327 2328 mutex_unlock(&adev->firmware.mutex); 2329 2330 return 0; 2331 2332 failed: 2333 DRM_ERROR("PSP resume failed\n"); 2334 mutex_unlock(&adev->firmware.mutex); 2335 return ret; 2336 } 2337 2338 int psp_gpu_reset(struct amdgpu_device *adev) 2339 { 2340 int ret; 2341 2342 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2343 return 0; 2344 2345 mutex_lock(&adev->psp.mutex); 2346 ret = psp_mode1_reset(&adev->psp); 2347 mutex_unlock(&adev->psp.mutex); 2348 2349 return ret; 2350 } 2351 2352 int psp_rlc_autoload_start(struct psp_context *psp) 2353 { 2354 int ret; 2355 struct psp_gfx_cmd_resp *cmd; 2356 2357 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2358 if (!cmd) 2359 return -ENOMEM; 2360 2361 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2362 2363 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2364 psp->fence_buf_mc_addr); 2365 kfree(cmd); 2366 return ret; 2367 } 2368 2369 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2370 uint64_t cmd_gpu_addr, int cmd_size) 2371 { 2372 struct amdgpu_firmware_info ucode = {0}; 2373 2374 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2375 AMDGPU_UCODE_ID_VCN0_RAM; 2376 ucode.mc_addr = cmd_gpu_addr; 2377 ucode.ucode_size = cmd_size; 2378 2379 return psp_execute_np_fw_load(&adev->psp, &ucode); 2380 } 2381 2382 int psp_ring_cmd_submit(struct psp_context *psp, 2383 uint64_t cmd_buf_mc_addr, 2384 uint64_t fence_mc_addr, 2385 int index) 2386 { 2387 unsigned int psp_write_ptr_reg = 0; 2388 struct psp_gfx_rb_frame *write_frame; 2389 struct psp_ring *ring = &psp->km_ring; 2390 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2391 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2392 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2393 struct amdgpu_device *adev = psp->adev; 2394 uint32_t ring_size_dw = ring->ring_size / 4; 2395 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2396 2397 /* KM (GPCOM) prepare write pointer */ 2398 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2399 2400 /* Update KM RB frame pointer to new frame */ 2401 /* write_frame ptr increments by size of rb_frame in bytes */ 2402 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2403 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2404 write_frame = ring_buffer_start; 2405 else 2406 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2407 /* Check invalid write_frame ptr address */ 2408 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2409 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2410 ring_buffer_start, ring_buffer_end, write_frame); 2411 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2412 return -EINVAL; 2413 } 2414 2415 /* Initialize KM RB frame */ 2416 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2417 2418 /* Update KM RB frame */ 2419 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2420 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2421 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2422 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2423 write_frame->fence_value = index; 2424 amdgpu_asic_flush_hdp(adev, NULL); 2425 2426 /* Update the write Pointer in DWORDs */ 2427 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2428 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2429 return 0; 2430 } 2431 2432 int psp_init_asd_microcode(struct psp_context *psp, 2433 const char *chip_name) 2434 { 2435 struct amdgpu_device *adev = psp->adev; 2436 char fw_name[PSP_FW_NAME_LEN]; 2437 const struct psp_firmware_header_v1_0 *asd_hdr; 2438 int err = 0; 2439 2440 if (!chip_name) { 2441 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2442 return -EINVAL; 2443 } 2444 2445 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2446 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2447 if (err) 2448 goto out; 2449 2450 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2451 if (err) 2452 goto out; 2453 2454 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2455 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2456 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 2457 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2458 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2459 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2460 return 0; 2461 out: 2462 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2463 release_firmware(adev->psp.asd_fw); 2464 adev->psp.asd_fw = NULL; 2465 return err; 2466 } 2467 2468 int psp_init_toc_microcode(struct psp_context *psp, 2469 const char *chip_name) 2470 { 2471 struct amdgpu_device *adev = psp->adev; 2472 char fw_name[30]; 2473 const struct psp_firmware_header_v1_0 *toc_hdr; 2474 int err = 0; 2475 2476 if (!chip_name) { 2477 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2478 return -EINVAL; 2479 } 2480 2481 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2482 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2483 if (err) 2484 goto out; 2485 2486 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2487 if (err) 2488 goto out; 2489 2490 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2491 adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2492 adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version); 2493 adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2494 adev->psp.toc_start_addr = (uint8_t *)toc_hdr + 2495 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2496 return 0; 2497 out: 2498 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2499 release_firmware(adev->psp.toc_fw); 2500 adev->psp.toc_fw = NULL; 2501 return err; 2502 } 2503 2504 int psp_init_sos_microcode(struct psp_context *psp, 2505 const char *chip_name) 2506 { 2507 struct amdgpu_device *adev = psp->adev; 2508 char fw_name[PSP_FW_NAME_LEN]; 2509 const struct psp_firmware_header_v1_0 *sos_hdr; 2510 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 2511 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 2512 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2513 int err = 0; 2514 2515 if (!chip_name) { 2516 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 2517 return -EINVAL; 2518 } 2519 2520 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 2521 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 2522 if (err) 2523 goto out; 2524 2525 err = amdgpu_ucode_validate(adev->psp.sos_fw); 2526 if (err) 2527 goto out; 2528 2529 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2530 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 2531 2532 switch (sos_hdr->header.header_version_major) { 2533 case 1: 2534 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 2535 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 2536 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 2537 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 2538 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 2539 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2540 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2541 le32_to_cpu(sos_hdr->sos_offset_bytes); 2542 if (sos_hdr->header.header_version_minor == 1) { 2543 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 2544 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 2545 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2546 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 2547 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); 2548 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2549 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); 2550 } 2551 if (sos_hdr->header.header_version_minor == 2) { 2552 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 2553 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); 2554 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2555 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); 2556 } 2557 if (sos_hdr->header.header_version_minor == 3) { 2558 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 2559 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes); 2560 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2561 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes); 2562 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes); 2563 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2564 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes); 2565 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes); 2566 adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2567 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes); 2568 } 2569 break; 2570 default: 2571 dev_err(adev->dev, 2572 "unsupported psp sos firmware\n"); 2573 err = -EINVAL; 2574 goto out; 2575 } 2576 2577 return 0; 2578 out: 2579 dev_err(adev->dev, 2580 "failed to init sos firmware\n"); 2581 release_firmware(adev->psp.sos_fw); 2582 adev->psp.sos_fw = NULL; 2583 2584 return err; 2585 } 2586 2587 static int parse_ta_bin_descriptor(struct psp_context *psp, 2588 const struct ta_fw_bin_desc *desc, 2589 const struct ta_firmware_header_v2_0 *ta_hdr) 2590 { 2591 uint8_t *ucode_start_addr = NULL; 2592 2593 if (!psp || !desc || !ta_hdr) 2594 return -EINVAL; 2595 2596 ucode_start_addr = (uint8_t *)ta_hdr + 2597 le32_to_cpu(desc->offset_bytes) + 2598 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 2599 2600 switch (desc->fw_type) { 2601 case TA_FW_TYPE_PSP_ASD: 2602 psp->asd_fw_version = le32_to_cpu(desc->fw_version); 2603 psp->asd_feature_version = le32_to_cpu(desc->fw_version); 2604 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 2605 psp->asd_start_addr = ucode_start_addr; 2606 break; 2607 case TA_FW_TYPE_PSP_XGMI: 2608 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 2609 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 2610 psp->ta_xgmi_start_addr = ucode_start_addr; 2611 break; 2612 case TA_FW_TYPE_PSP_RAS: 2613 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 2614 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 2615 psp->ta_ras_start_addr = ucode_start_addr; 2616 break; 2617 case TA_FW_TYPE_PSP_HDCP: 2618 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 2619 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 2620 psp->ta_hdcp_start_addr = ucode_start_addr; 2621 break; 2622 case TA_FW_TYPE_PSP_DTM: 2623 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 2624 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 2625 psp->ta_dtm_start_addr = ucode_start_addr; 2626 break; 2627 case TA_FW_TYPE_PSP_RAP: 2628 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version); 2629 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes); 2630 psp->ta_rap_start_addr = ucode_start_addr; 2631 break; 2632 default: 2633 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 2634 break; 2635 } 2636 2637 return 0; 2638 } 2639 2640 int psp_init_ta_microcode(struct psp_context *psp, 2641 const char *chip_name) 2642 { 2643 struct amdgpu_device *adev = psp->adev; 2644 char fw_name[PSP_FW_NAME_LEN]; 2645 const struct ta_firmware_header_v2_0 *ta_hdr; 2646 int err = 0; 2647 int ta_index = 0; 2648 2649 if (!chip_name) { 2650 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 2651 return -EINVAL; 2652 } 2653 2654 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 2655 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 2656 if (err) 2657 goto out; 2658 2659 err = amdgpu_ucode_validate(adev->psp.ta_fw); 2660 if (err) 2661 goto out; 2662 2663 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 2664 2665 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 2666 dev_err(adev->dev, "unsupported TA header version\n"); 2667 err = -EINVAL; 2668 goto out; 2669 } 2670 2671 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) { 2672 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 2673 err = -EINVAL; 2674 goto out; 2675 } 2676 2677 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 2678 err = parse_ta_bin_descriptor(psp, 2679 &ta_hdr->ta_fw_bin[ta_index], 2680 ta_hdr); 2681 if (err) 2682 goto out; 2683 } 2684 2685 return 0; 2686 out: 2687 dev_err(adev->dev, "fail to initialize ta microcode\n"); 2688 release_firmware(adev->psp.ta_fw); 2689 adev->psp.ta_fw = NULL; 2690 return err; 2691 } 2692 2693 static int psp_set_clockgating_state(void *handle, 2694 enum amd_clockgating_state state) 2695 { 2696 return 0; 2697 } 2698 2699 static int psp_set_powergating_state(void *handle, 2700 enum amd_powergating_state state) 2701 { 2702 return 0; 2703 } 2704 2705 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 2706 struct device_attribute *attr, 2707 char *buf) 2708 { 2709 struct drm_device *ddev = dev_get_drvdata(dev); 2710 struct amdgpu_device *adev = drm_to_adev(ddev); 2711 uint32_t fw_ver; 2712 int ret; 2713 2714 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2715 DRM_INFO("PSP block is not ready yet."); 2716 return -EBUSY; 2717 } 2718 2719 mutex_lock(&adev->psp.mutex); 2720 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 2721 mutex_unlock(&adev->psp.mutex); 2722 2723 if (ret) { 2724 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 2725 return ret; 2726 } 2727 2728 return snprintf(buf, PAGE_SIZE, "%x\n", fw_ver); 2729 } 2730 2731 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 2732 struct device_attribute *attr, 2733 const char *buf, 2734 size_t count) 2735 { 2736 struct drm_device *ddev = dev_get_drvdata(dev); 2737 struct amdgpu_device *adev = drm_to_adev(ddev); 2738 void *cpu_addr; 2739 dma_addr_t dma_addr; 2740 int ret; 2741 char fw_name[100]; 2742 const struct firmware *usbc_pd_fw; 2743 2744 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2745 DRM_INFO("PSP block is not ready yet."); 2746 return -EBUSY; 2747 } 2748 2749 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 2750 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 2751 if (ret) 2752 goto fail; 2753 2754 /* We need contiguous physical mem to place the FW for psp to access */ 2755 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL); 2756 2757 ret = dma_mapping_error(adev->dev, dma_addr); 2758 if (ret) 2759 goto rel_buf; 2760 2761 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 2762 2763 /* 2764 * x86 specific workaround. 2765 * Without it the buffer is invisible in PSP. 2766 * 2767 * TODO Remove once PSP starts snooping CPU cache 2768 */ 2769 #ifdef CONFIG_X86 2770 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1))); 2771 #endif 2772 2773 mutex_lock(&adev->psp.mutex); 2774 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr); 2775 mutex_unlock(&adev->psp.mutex); 2776 2777 rel_buf: 2778 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr); 2779 release_firmware(usbc_pd_fw); 2780 2781 fail: 2782 if (ret) { 2783 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 2784 return ret; 2785 } 2786 2787 return count; 2788 } 2789 2790 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 2791 psp_usbc_pd_fw_sysfs_read, 2792 psp_usbc_pd_fw_sysfs_write); 2793 2794 2795 2796 const struct amd_ip_funcs psp_ip_funcs = { 2797 .name = "psp", 2798 .early_init = psp_early_init, 2799 .late_init = NULL, 2800 .sw_init = psp_sw_init, 2801 .sw_fini = psp_sw_fini, 2802 .hw_init = psp_hw_init, 2803 .hw_fini = psp_hw_fini, 2804 .suspend = psp_suspend, 2805 .resume = psp_resume, 2806 .is_idle = NULL, 2807 .check_soft_reset = NULL, 2808 .wait_for_idle = NULL, 2809 .soft_reset = NULL, 2810 .set_clockgating_state = psp_set_clockgating_state, 2811 .set_powergating_state = psp_set_powergating_state, 2812 }; 2813 2814 static int psp_sysfs_init(struct amdgpu_device *adev) 2815 { 2816 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 2817 2818 if (ret) 2819 DRM_ERROR("Failed to create USBC PD FW control file!"); 2820 2821 return ret; 2822 } 2823 2824 static void psp_sysfs_fini(struct amdgpu_device *adev) 2825 { 2826 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 2827 } 2828 2829 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 2830 { 2831 .type = AMD_IP_BLOCK_TYPE_PSP, 2832 .major = 3, 2833 .minor = 1, 2834 .rev = 0, 2835 .funcs = &psp_ip_funcs, 2836 }; 2837 2838 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 2839 { 2840 .type = AMD_IP_BLOCK_TYPE_PSP, 2841 .major = 10, 2842 .minor = 0, 2843 .rev = 0, 2844 .funcs = &psp_ip_funcs, 2845 }; 2846 2847 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 2848 { 2849 .type = AMD_IP_BLOCK_TYPE_PSP, 2850 .major = 11, 2851 .minor = 0, 2852 .rev = 0, 2853 .funcs = &psp_ip_funcs, 2854 }; 2855 2856 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 2857 { 2858 .type = AMD_IP_BLOCK_TYPE_PSP, 2859 .major = 12, 2860 .minor = 0, 2861 .rev = 0, 2862 .funcs = &psp_ip_funcs, 2863 }; 2864