1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 #include "psp_v10_0.h" 34 #include "psp_v11_0.h" 35 36 static void psp_set_funcs(struct amdgpu_device *adev); 37 38 static int psp_early_init(void *handle) 39 { 40 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 41 42 psp_set_funcs(adev); 43 44 return 0; 45 } 46 47 static int psp_sw_init(void *handle) 48 { 49 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 50 struct psp_context *psp = &adev->psp; 51 int ret; 52 53 switch (adev->asic_type) { 54 case CHIP_VEGA10: 55 case CHIP_VEGA12: 56 psp_v3_1_set_psp_funcs(psp); 57 break; 58 case CHIP_RAVEN: 59 psp_v10_0_set_psp_funcs(psp); 60 break; 61 case CHIP_VEGA20: 62 psp_v11_0_set_psp_funcs(psp); 63 break; 64 default: 65 return -EINVAL; 66 } 67 68 psp->adev = adev; 69 70 ret = psp_init_microcode(psp); 71 if (ret) { 72 DRM_ERROR("Failed to load psp firmware!\n"); 73 return ret; 74 } 75 76 return 0; 77 } 78 79 static int psp_sw_fini(void *handle) 80 { 81 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 82 83 release_firmware(adev->psp.sos_fw); 84 adev->psp.sos_fw = NULL; 85 release_firmware(adev->psp.asd_fw); 86 adev->psp.asd_fw = NULL; 87 release_firmware(adev->psp.ta_fw); 88 adev->psp.ta_fw = NULL; 89 return 0; 90 } 91 92 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 93 uint32_t reg_val, uint32_t mask, bool check_changed) 94 { 95 uint32_t val; 96 int i; 97 struct amdgpu_device *adev = psp->adev; 98 99 for (i = 0; i < adev->usec_timeout; i++) { 100 val = RREG32(reg_index); 101 if (check_changed) { 102 if (val != reg_val) 103 return 0; 104 } else { 105 if ((val & mask) == reg_val) 106 return 0; 107 } 108 udelay(1); 109 } 110 111 return -ETIME; 112 } 113 114 static int 115 psp_cmd_submit_buf(struct psp_context *psp, 116 struct amdgpu_firmware_info *ucode, 117 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 118 { 119 int ret; 120 int index; 121 122 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 123 124 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 125 126 index = atomic_inc_return(&psp->fence_value); 127 ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr, 128 fence_mc_addr, index); 129 if (ret) { 130 atomic_dec(&psp->fence_value); 131 return ret; 132 } 133 134 while (*((unsigned int *)psp->fence_buf) != index) 135 msleep(1); 136 137 /* In some cases, psp response status is not 0 even there is no 138 * problem while the command is submitted. Some version of PSP FW 139 * doesn't write 0 to that field. 140 * So here we would like to only print a warning instead of an error 141 * during psp initialization to avoid breaking hw_init and it doesn't 142 * return -EINVAL. 143 */ 144 if (psp->cmd_buf_mem->resp.status) { 145 if (ucode) 146 DRM_WARN("failed to load ucode id (%d) ", 147 ucode->ucode_id); 148 DRM_WARN("psp command failed and response status is (%d)\n", 149 psp->cmd_buf_mem->resp.status); 150 } 151 152 /* get xGMI session id from response buffer */ 153 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id; 154 155 if (ucode) { 156 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 157 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 158 } 159 160 return ret; 161 } 162 163 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 164 struct psp_gfx_cmd_resp *cmd, 165 uint64_t tmr_mc, uint32_t size) 166 { 167 if (psp_support_vmr_ring(psp)) 168 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 169 else 170 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 171 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 172 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 173 cmd->cmd.cmd_setup_tmr.buf_size = size; 174 } 175 176 /* Set up Trusted Memory Region */ 177 static int psp_tmr_init(struct psp_context *psp) 178 { 179 int ret; 180 181 /* 182 * Allocate 3M memory aligned to 1M from Frame Buffer (local 183 * physical). 184 * 185 * Note: this memory need be reserved till the driver 186 * uninitializes. 187 */ 188 ret = amdgpu_bo_create_kernel(psp->adev, PSP_TMR_SIZE, 0x100000, 189 AMDGPU_GEM_DOMAIN_VRAM, 190 &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 191 192 return ret; 193 } 194 195 static int psp_tmr_load(struct psp_context *psp) 196 { 197 int ret; 198 struct psp_gfx_cmd_resp *cmd; 199 200 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 201 if (!cmd) 202 return -ENOMEM; 203 204 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, PSP_TMR_SIZE); 205 DRM_INFO("reserve 0x%x from 0x%llx for PSP TMR SIZE\n", 206 PSP_TMR_SIZE, psp->tmr_mc_addr); 207 208 ret = psp_cmd_submit_buf(psp, NULL, cmd, 209 psp->fence_buf_mc_addr); 210 if (ret) 211 goto failed; 212 213 kfree(cmd); 214 215 return 0; 216 217 failed: 218 kfree(cmd); 219 return ret; 220 } 221 222 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd, 223 uint64_t asd_mc, uint64_t asd_mc_shared, 224 uint32_t size, uint32_t shared_size) 225 { 226 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 227 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 228 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 229 cmd->cmd.cmd_load_ta.app_len = size; 230 231 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared); 232 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared); 233 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 234 } 235 236 static int psp_asd_init(struct psp_context *psp) 237 { 238 int ret; 239 240 /* 241 * Allocate 16k memory aligned to 4k from Frame Buffer (local 242 * physical) for shared ASD <-> Driver 243 */ 244 ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE, 245 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 246 &psp->asd_shared_bo, 247 &psp->asd_shared_mc_addr, 248 &psp->asd_shared_buf); 249 250 return ret; 251 } 252 253 static int psp_asd_load(struct psp_context *psp) 254 { 255 int ret; 256 struct psp_gfx_cmd_resp *cmd; 257 258 /* If PSP version doesn't match ASD version, asd loading will be failed. 259 * add workaround to bypass it for sriov now. 260 * TODO: add version check to make it common 261 */ 262 if (amdgpu_sriov_vf(psp->adev)) 263 return 0; 264 265 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 266 if (!cmd) 267 return -ENOMEM; 268 269 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 270 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 271 272 psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr, 273 psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE); 274 275 ret = psp_cmd_submit_buf(psp, NULL, cmd, 276 psp->fence_buf_mc_addr); 277 278 kfree(cmd); 279 280 return ret; 281 } 282 283 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 284 uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared, 285 uint32_t xgmi_ta_size, uint32_t shared_size) 286 { 287 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 288 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc); 289 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc); 290 cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size; 291 292 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared); 293 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared); 294 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 295 } 296 297 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 298 { 299 int ret; 300 301 /* 302 * Allocate 16k memory aligned to 4k from Frame Buffer (local 303 * physical) for xgmi ta <-> Driver 304 */ 305 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 306 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 307 &psp->xgmi_context.xgmi_shared_bo, 308 &psp->xgmi_context.xgmi_shared_mc_addr, 309 &psp->xgmi_context.xgmi_shared_buf); 310 311 return ret; 312 } 313 314 static int psp_xgmi_load(struct psp_context *psp) 315 { 316 int ret; 317 struct psp_gfx_cmd_resp *cmd; 318 319 /* 320 * TODO: bypass the loading in sriov for now 321 */ 322 if (amdgpu_sriov_vf(psp->adev)) 323 return 0; 324 325 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 326 if (!cmd) 327 return -ENOMEM; 328 329 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 330 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 331 332 psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 333 psp->xgmi_context.xgmi_shared_mc_addr, 334 psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE); 335 336 ret = psp_cmd_submit_buf(psp, NULL, cmd, 337 psp->fence_buf_mc_addr); 338 339 if (!ret) { 340 psp->xgmi_context.initialized = 1; 341 psp->xgmi_context.session_id = cmd->resp.session_id; 342 } 343 344 kfree(cmd); 345 346 return ret; 347 } 348 349 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 350 uint32_t xgmi_session_id) 351 { 352 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 353 cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id; 354 } 355 356 static int psp_xgmi_unload(struct psp_context *psp) 357 { 358 int ret; 359 struct psp_gfx_cmd_resp *cmd; 360 361 /* 362 * TODO: bypass the unloading in sriov for now 363 */ 364 if (amdgpu_sriov_vf(psp->adev)) 365 return 0; 366 367 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 368 if (!cmd) 369 return -ENOMEM; 370 371 psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 372 373 ret = psp_cmd_submit_buf(psp, NULL, cmd, 374 psp->fence_buf_mc_addr); 375 376 kfree(cmd); 377 378 return ret; 379 } 380 381 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 382 uint32_t ta_cmd_id, 383 uint32_t xgmi_session_id) 384 { 385 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 386 cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id; 387 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 388 /* Note: cmd_invoke_cmd.buf is not used for now */ 389 } 390 391 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 392 { 393 int ret; 394 struct psp_gfx_cmd_resp *cmd; 395 396 /* 397 * TODO: bypass the loading in sriov for now 398 */ 399 if (amdgpu_sriov_vf(psp->adev)) 400 return 0; 401 402 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 403 if (!cmd) 404 return -ENOMEM; 405 406 psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id, 407 psp->xgmi_context.session_id); 408 409 ret = psp_cmd_submit_buf(psp, NULL, cmd, 410 psp->fence_buf_mc_addr); 411 412 kfree(cmd); 413 414 return ret; 415 } 416 417 static int psp_xgmi_terminate(struct psp_context *psp) 418 { 419 int ret; 420 421 if (!psp->xgmi_context.initialized) 422 return 0; 423 424 ret = psp_xgmi_unload(psp); 425 if (ret) 426 return ret; 427 428 psp->xgmi_context.initialized = 0; 429 430 /* free xgmi shared memory */ 431 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 432 &psp->xgmi_context.xgmi_shared_mc_addr, 433 &psp->xgmi_context.xgmi_shared_buf); 434 435 return 0; 436 } 437 438 static int psp_xgmi_initialize(struct psp_context *psp) 439 { 440 struct ta_xgmi_shared_memory *xgmi_cmd; 441 int ret; 442 443 if (!psp->xgmi_context.initialized) { 444 ret = psp_xgmi_init_shared_buf(psp); 445 if (ret) 446 return ret; 447 } 448 449 /* Load XGMI TA */ 450 ret = psp_xgmi_load(psp); 451 if (ret) 452 return ret; 453 454 /* Initialize XGMI session */ 455 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 456 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 457 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 458 459 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 460 461 return ret; 462 } 463 464 static int psp_hw_start(struct psp_context *psp) 465 { 466 struct amdgpu_device *adev = psp->adev; 467 int ret; 468 469 if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) { 470 ret = psp_bootloader_load_sysdrv(psp); 471 if (ret) 472 return ret; 473 474 ret = psp_bootloader_load_sos(psp); 475 if (ret) 476 return ret; 477 } 478 479 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 480 if (ret) 481 return ret; 482 483 ret = psp_tmr_load(psp); 484 if (ret) 485 return ret; 486 487 ret = psp_asd_load(psp); 488 if (ret) 489 return ret; 490 491 if (adev->gmc.xgmi.num_physical_nodes > 1) { 492 ret = psp_xgmi_initialize(psp); 493 /* Warning the XGMI seesion initialize failure 494 * Instead of stop driver initialization 495 */ 496 if (ret) 497 dev_err(psp->adev->dev, 498 "XGMI: Failed to initialize XGMI session\n"); 499 } 500 return 0; 501 } 502 503 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 504 enum psp_gfx_fw_type *type) 505 { 506 switch (ucode->ucode_id) { 507 case AMDGPU_UCODE_ID_SDMA0: 508 *type = GFX_FW_TYPE_SDMA0; 509 break; 510 case AMDGPU_UCODE_ID_SDMA1: 511 *type = GFX_FW_TYPE_SDMA1; 512 break; 513 case AMDGPU_UCODE_ID_CP_CE: 514 *type = GFX_FW_TYPE_CP_CE; 515 break; 516 case AMDGPU_UCODE_ID_CP_PFP: 517 *type = GFX_FW_TYPE_CP_PFP; 518 break; 519 case AMDGPU_UCODE_ID_CP_ME: 520 *type = GFX_FW_TYPE_CP_ME; 521 break; 522 case AMDGPU_UCODE_ID_CP_MEC1: 523 *type = GFX_FW_TYPE_CP_MEC; 524 break; 525 case AMDGPU_UCODE_ID_CP_MEC1_JT: 526 *type = GFX_FW_TYPE_CP_MEC_ME1; 527 break; 528 case AMDGPU_UCODE_ID_CP_MEC2: 529 *type = GFX_FW_TYPE_CP_MEC; 530 break; 531 case AMDGPU_UCODE_ID_CP_MEC2_JT: 532 *type = GFX_FW_TYPE_CP_MEC_ME2; 533 break; 534 case AMDGPU_UCODE_ID_RLC_G: 535 *type = GFX_FW_TYPE_RLC_G; 536 break; 537 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 538 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 539 break; 540 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 541 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 542 break; 543 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 544 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 545 break; 546 case AMDGPU_UCODE_ID_SMC: 547 *type = GFX_FW_TYPE_SMU; 548 break; 549 case AMDGPU_UCODE_ID_UVD: 550 *type = GFX_FW_TYPE_UVD; 551 break; 552 case AMDGPU_UCODE_ID_UVD1: 553 *type = GFX_FW_TYPE_UVD1; 554 break; 555 case AMDGPU_UCODE_ID_VCE: 556 *type = GFX_FW_TYPE_VCE; 557 break; 558 case AMDGPU_UCODE_ID_VCN: 559 *type = GFX_FW_TYPE_VCN; 560 break; 561 case AMDGPU_UCODE_ID_DMCU_ERAM: 562 *type = GFX_FW_TYPE_DMCU_ERAM; 563 break; 564 case AMDGPU_UCODE_ID_DMCU_INTV: 565 *type = GFX_FW_TYPE_DMCU_ISR; 566 break; 567 case AMDGPU_UCODE_ID_MAXIMUM: 568 default: 569 return -EINVAL; 570 } 571 572 return 0; 573 } 574 575 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 576 struct psp_gfx_cmd_resp *cmd) 577 { 578 int ret; 579 uint64_t fw_mem_mc_addr = ucode->mc_addr; 580 581 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 582 583 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 584 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 585 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 586 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 587 588 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 589 if (ret) 590 DRM_ERROR("Unknown firmware type\n"); 591 592 return ret; 593 } 594 595 static int psp_np_fw_load(struct psp_context *psp) 596 { 597 int i, ret; 598 struct amdgpu_firmware_info *ucode; 599 struct amdgpu_device* adev = psp->adev; 600 601 for (i = 0; i < adev->firmware.max_ucodes; i++) { 602 ucode = &adev->firmware.ucode[i]; 603 if (!ucode->fw) 604 continue; 605 606 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 607 psp_smu_reload_quirk(psp)) 608 continue; 609 if (amdgpu_sriov_vf(adev) && 610 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 611 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 612 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) 613 /*skip ucode loading in SRIOV VF */ 614 continue; 615 616 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 617 if (ret) 618 return ret; 619 620 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 621 psp->fence_buf_mc_addr); 622 if (ret) 623 return ret; 624 625 #if 0 626 /* check if firmware loaded sucessfully */ 627 if (!amdgpu_psp_check_fw_loading_status(adev, i)) 628 return -EINVAL; 629 #endif 630 } 631 632 return 0; 633 } 634 635 static int psp_load_fw(struct amdgpu_device *adev) 636 { 637 int ret; 638 struct psp_context *psp = &adev->psp; 639 640 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) { 641 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 642 goto skip_memalloc; 643 } 644 645 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 646 if (!psp->cmd) 647 return -ENOMEM; 648 649 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 650 AMDGPU_GEM_DOMAIN_GTT, 651 &psp->fw_pri_bo, 652 &psp->fw_pri_mc_addr, 653 &psp->fw_pri_buf); 654 if (ret) 655 goto failed; 656 657 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 658 AMDGPU_GEM_DOMAIN_VRAM, 659 &psp->fence_buf_bo, 660 &psp->fence_buf_mc_addr, 661 &psp->fence_buf); 662 if (ret) 663 goto failed_mem2; 664 665 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 666 AMDGPU_GEM_DOMAIN_VRAM, 667 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 668 (void **)&psp->cmd_buf_mem); 669 if (ret) 670 goto failed_mem1; 671 672 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 673 674 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 675 if (ret) 676 goto failed_mem; 677 678 ret = psp_tmr_init(psp); 679 if (ret) 680 goto failed_mem; 681 682 ret = psp_asd_init(psp); 683 if (ret) 684 goto failed_mem; 685 686 skip_memalloc: 687 ret = psp_hw_start(psp); 688 if (ret) 689 goto failed_mem; 690 691 ret = psp_np_fw_load(psp); 692 if (ret) 693 goto failed_mem; 694 695 return 0; 696 697 failed_mem: 698 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, 699 &psp->cmd_buf_mc_addr, 700 (void **)&psp->cmd_buf_mem); 701 failed_mem1: 702 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 703 &psp->fence_buf_mc_addr, &psp->fence_buf); 704 failed_mem2: 705 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 706 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 707 failed: 708 kfree(psp->cmd); 709 psp->cmd = NULL; 710 return ret; 711 } 712 713 static int psp_hw_init(void *handle) 714 { 715 int ret; 716 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 717 718 mutex_lock(&adev->firmware.mutex); 719 /* 720 * This sequence is just used on hw_init only once, no need on 721 * resume. 722 */ 723 ret = amdgpu_ucode_init_bo(adev); 724 if (ret) 725 goto failed; 726 727 ret = psp_load_fw(adev); 728 if (ret) { 729 DRM_ERROR("PSP firmware loading failed\n"); 730 goto failed; 731 } 732 733 mutex_unlock(&adev->firmware.mutex); 734 return 0; 735 736 failed: 737 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 738 mutex_unlock(&adev->firmware.mutex); 739 return -EINVAL; 740 } 741 742 static int psp_hw_fini(void *handle) 743 { 744 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 745 struct psp_context *psp = &adev->psp; 746 747 if (adev->gmc.xgmi.num_physical_nodes > 1 && 748 psp->xgmi_context.initialized == 1) 749 psp_xgmi_terminate(psp); 750 751 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 752 753 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 754 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 755 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 756 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 757 &psp->fence_buf_mc_addr, &psp->fence_buf); 758 amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr, 759 &psp->asd_shared_buf); 760 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 761 (void **)&psp->cmd_buf_mem); 762 763 kfree(psp->cmd); 764 psp->cmd = NULL; 765 766 return 0; 767 } 768 769 static int psp_suspend(void *handle) 770 { 771 int ret; 772 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 773 struct psp_context *psp = &adev->psp; 774 775 if (adev->gmc.xgmi.num_physical_nodes > 1 && 776 psp->xgmi_context.initialized == 1) { 777 ret = psp_xgmi_terminate(psp); 778 if (ret) { 779 DRM_ERROR("Failed to terminate xgmi ta\n"); 780 return ret; 781 } 782 } 783 784 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 785 if (ret) { 786 DRM_ERROR("PSP ring stop failed\n"); 787 return ret; 788 } 789 790 return 0; 791 } 792 793 static int psp_resume(void *handle) 794 { 795 int ret; 796 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 797 struct psp_context *psp = &adev->psp; 798 799 DRM_INFO("PSP is resuming...\n"); 800 801 mutex_lock(&adev->firmware.mutex); 802 803 ret = psp_hw_start(psp); 804 if (ret) 805 goto failed; 806 807 ret = psp_np_fw_load(psp); 808 if (ret) 809 goto failed; 810 811 mutex_unlock(&adev->firmware.mutex); 812 813 return 0; 814 815 failed: 816 DRM_ERROR("PSP resume failed\n"); 817 mutex_unlock(&adev->firmware.mutex); 818 return ret; 819 } 820 821 int psp_gpu_reset(struct amdgpu_device *adev) 822 { 823 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 824 return 0; 825 826 return psp_mode1_reset(&adev->psp); 827 } 828 829 static bool psp_check_fw_loading_status(struct amdgpu_device *adev, 830 enum AMDGPU_UCODE_ID ucode_type) 831 { 832 struct amdgpu_firmware_info *ucode = NULL; 833 834 if (!adev->firmware.fw_size) 835 return false; 836 837 ucode = &adev->firmware.ucode[ucode_type]; 838 if (!ucode->fw || !ucode->ucode_size) 839 return false; 840 841 return psp_compare_sram_data(&adev->psp, ucode, ucode_type); 842 } 843 844 static int psp_set_clockgating_state(void *handle, 845 enum amd_clockgating_state state) 846 { 847 return 0; 848 } 849 850 static int psp_set_powergating_state(void *handle, 851 enum amd_powergating_state state) 852 { 853 return 0; 854 } 855 856 const struct amd_ip_funcs psp_ip_funcs = { 857 .name = "psp", 858 .early_init = psp_early_init, 859 .late_init = NULL, 860 .sw_init = psp_sw_init, 861 .sw_fini = psp_sw_fini, 862 .hw_init = psp_hw_init, 863 .hw_fini = psp_hw_fini, 864 .suspend = psp_suspend, 865 .resume = psp_resume, 866 .is_idle = NULL, 867 .check_soft_reset = NULL, 868 .wait_for_idle = NULL, 869 .soft_reset = NULL, 870 .set_clockgating_state = psp_set_clockgating_state, 871 .set_powergating_state = psp_set_powergating_state, 872 }; 873 874 static const struct amdgpu_psp_funcs psp_funcs = { 875 .check_fw_loading_status = psp_check_fw_loading_status, 876 }; 877 878 static void psp_set_funcs(struct amdgpu_device *adev) 879 { 880 if (NULL == adev->firmware.funcs) 881 adev->firmware.funcs = &psp_funcs; 882 } 883 884 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 885 { 886 .type = AMD_IP_BLOCK_TYPE_PSP, 887 .major = 3, 888 .minor = 1, 889 .rev = 0, 890 .funcs = &psp_ip_funcs, 891 }; 892 893 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 894 { 895 .type = AMD_IP_BLOCK_TYPE_PSP, 896 .major = 10, 897 .minor = 0, 898 .rev = 0, 899 .funcs = &psp_ip_funcs, 900 }; 901 902 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 903 { 904 .type = AMD_IP_BLOCK_TYPE_PSP, 905 .major = 11, 906 .minor = 0, 907 .rev = 0, 908 .funcs = &psp_ip_funcs, 909 }; 910