1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 #include "psp_v10_0.h" 34 #include "psp_v11_0.h" 35 36 static void psp_set_funcs(struct amdgpu_device *adev); 37 38 static int psp_early_init(void *handle) 39 { 40 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 41 42 psp_set_funcs(adev); 43 44 return 0; 45 } 46 47 static int psp_sw_init(void *handle) 48 { 49 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 50 struct psp_context *psp = &adev->psp; 51 int ret; 52 53 switch (adev->asic_type) { 54 case CHIP_VEGA10: 55 case CHIP_VEGA12: 56 psp_v3_1_set_psp_funcs(psp); 57 break; 58 case CHIP_RAVEN: 59 psp_v10_0_set_psp_funcs(psp); 60 break; 61 case CHIP_VEGA20: 62 psp_v11_0_set_psp_funcs(psp); 63 break; 64 default: 65 return -EINVAL; 66 } 67 68 psp->adev = adev; 69 70 ret = psp_init_microcode(psp); 71 if (ret) { 72 DRM_ERROR("Failed to load psp firmware!\n"); 73 return ret; 74 } 75 76 return 0; 77 } 78 79 static int psp_sw_fini(void *handle) 80 { 81 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 82 83 release_firmware(adev->psp.sos_fw); 84 adev->psp.sos_fw = NULL; 85 release_firmware(adev->psp.asd_fw); 86 adev->psp.asd_fw = NULL; 87 if (adev->psp.ta_fw) { 88 release_firmware(adev->psp.ta_fw); 89 adev->psp.ta_fw = NULL; 90 } 91 return 0; 92 } 93 94 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 95 uint32_t reg_val, uint32_t mask, bool check_changed) 96 { 97 uint32_t val; 98 int i; 99 struct amdgpu_device *adev = psp->adev; 100 101 for (i = 0; i < adev->usec_timeout; i++) { 102 val = RREG32(reg_index); 103 if (check_changed) { 104 if (val != reg_val) 105 return 0; 106 } else { 107 if ((val & mask) == reg_val) 108 return 0; 109 } 110 udelay(1); 111 } 112 113 return -ETIME; 114 } 115 116 static int 117 psp_cmd_submit_buf(struct psp_context *psp, 118 struct amdgpu_firmware_info *ucode, 119 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 120 { 121 int ret; 122 int index; 123 124 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 125 126 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 127 128 index = atomic_inc_return(&psp->fence_value); 129 ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr, 130 fence_mc_addr, index); 131 if (ret) { 132 atomic_dec(&psp->fence_value); 133 return ret; 134 } 135 136 while (*((unsigned int *)psp->fence_buf) != index) 137 msleep(1); 138 139 /* In some cases, psp response status is not 0 even there is no 140 * problem while the command is submitted. Some version of PSP FW 141 * doesn't write 0 to that field. 142 * So here we would like to only print a warning instead of an error 143 * during psp initialization to avoid breaking hw_init and it doesn't 144 * return -EINVAL. 145 */ 146 if (psp->cmd_buf_mem->resp.status) { 147 if (ucode) 148 DRM_WARN("failed to load ucode id (%d) ", 149 ucode->ucode_id); 150 DRM_WARN("psp command failed and response status is (%d)\n", 151 psp->cmd_buf_mem->resp.status); 152 } 153 154 /* get xGMI session id from response buffer */ 155 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id; 156 157 if (ucode) { 158 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 159 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 160 } 161 162 return ret; 163 } 164 165 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 166 struct psp_gfx_cmd_resp *cmd, 167 uint64_t tmr_mc, uint32_t size) 168 { 169 if (psp_support_vmr_ring(psp)) 170 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 171 else 172 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 173 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 174 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 175 cmd->cmd.cmd_setup_tmr.buf_size = size; 176 } 177 178 /* Set up Trusted Memory Region */ 179 static int psp_tmr_init(struct psp_context *psp) 180 { 181 int ret; 182 183 /* 184 * Allocate 3M memory aligned to 1M from Frame Buffer (local 185 * physical). 186 * 187 * Note: this memory need be reserved till the driver 188 * uninitializes. 189 */ 190 ret = amdgpu_bo_create_kernel(psp->adev, PSP_TMR_SIZE, 0x100000, 191 AMDGPU_GEM_DOMAIN_VRAM, 192 &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 193 194 return ret; 195 } 196 197 static int psp_tmr_load(struct psp_context *psp) 198 { 199 int ret; 200 struct psp_gfx_cmd_resp *cmd; 201 202 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 203 if (!cmd) 204 return -ENOMEM; 205 206 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, PSP_TMR_SIZE); 207 DRM_INFO("reserve 0x%x from 0x%llx for PSP TMR SIZE\n", 208 PSP_TMR_SIZE, psp->tmr_mc_addr); 209 210 ret = psp_cmd_submit_buf(psp, NULL, cmd, 211 psp->fence_buf_mc_addr); 212 if (ret) 213 goto failed; 214 215 kfree(cmd); 216 217 return 0; 218 219 failed: 220 kfree(cmd); 221 return ret; 222 } 223 224 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd, 225 uint64_t asd_mc, uint64_t asd_mc_shared, 226 uint32_t size, uint32_t shared_size) 227 { 228 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 229 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 230 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 231 cmd->cmd.cmd_load_ta.app_len = size; 232 233 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared); 234 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared); 235 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 236 } 237 238 static int psp_asd_init(struct psp_context *psp) 239 { 240 int ret; 241 242 /* 243 * Allocate 16k memory aligned to 4k from Frame Buffer (local 244 * physical) for shared ASD <-> Driver 245 */ 246 ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE, 247 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 248 &psp->asd_shared_bo, 249 &psp->asd_shared_mc_addr, 250 &psp->asd_shared_buf); 251 252 return ret; 253 } 254 255 static int psp_asd_load(struct psp_context *psp) 256 { 257 int ret; 258 struct psp_gfx_cmd_resp *cmd; 259 260 /* If PSP version doesn't match ASD version, asd loading will be failed. 261 * add workaround to bypass it for sriov now. 262 * TODO: add version check to make it common 263 */ 264 if (amdgpu_sriov_vf(psp->adev)) 265 return 0; 266 267 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 268 if (!cmd) 269 return -ENOMEM; 270 271 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 272 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 273 274 psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr, 275 psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE); 276 277 ret = psp_cmd_submit_buf(psp, NULL, cmd, 278 psp->fence_buf_mc_addr); 279 280 kfree(cmd); 281 282 return ret; 283 } 284 285 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 286 uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared, 287 uint32_t xgmi_ta_size, uint32_t shared_size) 288 { 289 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 290 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc); 291 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc); 292 cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size; 293 294 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared); 295 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared); 296 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 297 } 298 299 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 300 { 301 int ret; 302 303 /* 304 * Allocate 16k memory aligned to 4k from Frame Buffer (local 305 * physical) for xgmi ta <-> Driver 306 */ 307 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 308 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 309 &psp->xgmi_context.xgmi_shared_bo, 310 &psp->xgmi_context.xgmi_shared_mc_addr, 311 &psp->xgmi_context.xgmi_shared_buf); 312 313 return ret; 314 } 315 316 static int psp_xgmi_load(struct psp_context *psp) 317 { 318 int ret; 319 struct psp_gfx_cmd_resp *cmd; 320 321 /* 322 * TODO: bypass the loading in sriov for now 323 */ 324 if (amdgpu_sriov_vf(psp->adev)) 325 return 0; 326 327 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 328 if (!cmd) 329 return -ENOMEM; 330 331 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 332 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 333 334 psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 335 psp->xgmi_context.xgmi_shared_mc_addr, 336 psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE); 337 338 ret = psp_cmd_submit_buf(psp, NULL, cmd, 339 psp->fence_buf_mc_addr); 340 341 if (!ret) { 342 psp->xgmi_context.initialized = 1; 343 psp->xgmi_context.session_id = cmd->resp.session_id; 344 } 345 346 kfree(cmd); 347 348 return ret; 349 } 350 351 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 352 uint32_t xgmi_session_id) 353 { 354 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 355 cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id; 356 } 357 358 static int psp_xgmi_unload(struct psp_context *psp) 359 { 360 int ret; 361 struct psp_gfx_cmd_resp *cmd; 362 363 /* 364 * TODO: bypass the unloading in sriov for now 365 */ 366 if (amdgpu_sriov_vf(psp->adev)) 367 return 0; 368 369 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 370 if (!cmd) 371 return -ENOMEM; 372 373 psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 374 375 ret = psp_cmd_submit_buf(psp, NULL, cmd, 376 psp->fence_buf_mc_addr); 377 378 kfree(cmd); 379 380 return ret; 381 } 382 383 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 384 uint32_t ta_cmd_id, 385 uint32_t xgmi_session_id) 386 { 387 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 388 cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id; 389 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 390 /* Note: cmd_invoke_cmd.buf is not used for now */ 391 } 392 393 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 394 { 395 int ret; 396 struct psp_gfx_cmd_resp *cmd; 397 398 /* 399 * TODO: bypass the loading in sriov for now 400 */ 401 if (amdgpu_sriov_vf(psp->adev)) 402 return 0; 403 404 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 405 if (!cmd) 406 return -ENOMEM; 407 408 psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id, 409 psp->xgmi_context.session_id); 410 411 ret = psp_cmd_submit_buf(psp, NULL, cmd, 412 psp->fence_buf_mc_addr); 413 414 kfree(cmd); 415 416 return ret; 417 } 418 419 static int psp_xgmi_terminate(struct psp_context *psp) 420 { 421 int ret; 422 423 if (!psp->xgmi_context.initialized) 424 return 0; 425 426 ret = psp_xgmi_unload(psp); 427 if (ret) 428 return ret; 429 430 psp->xgmi_context.initialized = 0; 431 432 /* free xgmi shared memory */ 433 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 434 &psp->xgmi_context.xgmi_shared_mc_addr, 435 &psp->xgmi_context.xgmi_shared_buf); 436 437 return 0; 438 } 439 440 static int psp_xgmi_initialize(struct psp_context *psp) 441 { 442 struct ta_xgmi_shared_memory *xgmi_cmd; 443 int ret; 444 445 if (!psp->adev->psp.ta_fw) 446 return -ENOENT; 447 448 if (!psp->xgmi_context.initialized) { 449 ret = psp_xgmi_init_shared_buf(psp); 450 if (ret) 451 return ret; 452 } 453 454 /* Load XGMI TA */ 455 ret = psp_xgmi_load(psp); 456 if (ret) 457 return ret; 458 459 /* Initialize XGMI session */ 460 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 461 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 462 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 463 464 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 465 466 return ret; 467 } 468 469 static int psp_hw_start(struct psp_context *psp) 470 { 471 struct amdgpu_device *adev = psp->adev; 472 int ret; 473 474 if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) { 475 ret = psp_bootloader_load_sysdrv(psp); 476 if (ret) 477 return ret; 478 479 ret = psp_bootloader_load_sos(psp); 480 if (ret) 481 return ret; 482 } 483 484 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 485 if (ret) 486 return ret; 487 488 ret = psp_tmr_load(psp); 489 if (ret) 490 return ret; 491 492 ret = psp_asd_load(psp); 493 if (ret) 494 return ret; 495 496 if (adev->gmc.xgmi.num_physical_nodes > 1) { 497 ret = psp_xgmi_initialize(psp); 498 /* Warning the XGMI seesion initialize failure 499 * Instead of stop driver initialization 500 */ 501 if (ret) 502 dev_err(psp->adev->dev, 503 "XGMI: Failed to initialize XGMI session\n"); 504 } 505 return 0; 506 } 507 508 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 509 enum psp_gfx_fw_type *type) 510 { 511 switch (ucode->ucode_id) { 512 case AMDGPU_UCODE_ID_SDMA0: 513 *type = GFX_FW_TYPE_SDMA0; 514 break; 515 case AMDGPU_UCODE_ID_SDMA1: 516 *type = GFX_FW_TYPE_SDMA1; 517 break; 518 case AMDGPU_UCODE_ID_CP_CE: 519 *type = GFX_FW_TYPE_CP_CE; 520 break; 521 case AMDGPU_UCODE_ID_CP_PFP: 522 *type = GFX_FW_TYPE_CP_PFP; 523 break; 524 case AMDGPU_UCODE_ID_CP_ME: 525 *type = GFX_FW_TYPE_CP_ME; 526 break; 527 case AMDGPU_UCODE_ID_CP_MEC1: 528 *type = GFX_FW_TYPE_CP_MEC; 529 break; 530 case AMDGPU_UCODE_ID_CP_MEC1_JT: 531 *type = GFX_FW_TYPE_CP_MEC_ME1; 532 break; 533 case AMDGPU_UCODE_ID_CP_MEC2: 534 *type = GFX_FW_TYPE_CP_MEC; 535 break; 536 case AMDGPU_UCODE_ID_CP_MEC2_JT: 537 *type = GFX_FW_TYPE_CP_MEC_ME2; 538 break; 539 case AMDGPU_UCODE_ID_RLC_G: 540 *type = GFX_FW_TYPE_RLC_G; 541 break; 542 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 543 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 544 break; 545 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 546 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 547 break; 548 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 549 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 550 break; 551 case AMDGPU_UCODE_ID_SMC: 552 *type = GFX_FW_TYPE_SMU; 553 break; 554 case AMDGPU_UCODE_ID_UVD: 555 *type = GFX_FW_TYPE_UVD; 556 break; 557 case AMDGPU_UCODE_ID_UVD1: 558 *type = GFX_FW_TYPE_UVD1; 559 break; 560 case AMDGPU_UCODE_ID_VCE: 561 *type = GFX_FW_TYPE_VCE; 562 break; 563 case AMDGPU_UCODE_ID_VCN: 564 *type = GFX_FW_TYPE_VCN; 565 break; 566 case AMDGPU_UCODE_ID_DMCU_ERAM: 567 *type = GFX_FW_TYPE_DMCU_ERAM; 568 break; 569 case AMDGPU_UCODE_ID_DMCU_INTV: 570 *type = GFX_FW_TYPE_DMCU_ISR; 571 break; 572 case AMDGPU_UCODE_ID_MAXIMUM: 573 default: 574 return -EINVAL; 575 } 576 577 return 0; 578 } 579 580 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 581 struct psp_gfx_cmd_resp *cmd) 582 { 583 int ret; 584 uint64_t fw_mem_mc_addr = ucode->mc_addr; 585 586 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 587 588 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 589 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 590 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 591 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 592 593 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 594 if (ret) 595 DRM_ERROR("Unknown firmware type\n"); 596 597 return ret; 598 } 599 600 static int psp_np_fw_load(struct psp_context *psp) 601 { 602 int i, ret; 603 struct amdgpu_firmware_info *ucode; 604 struct amdgpu_device* adev = psp->adev; 605 606 for (i = 0; i < adev->firmware.max_ucodes; i++) { 607 ucode = &adev->firmware.ucode[i]; 608 if (!ucode->fw) 609 continue; 610 611 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 612 psp_smu_reload_quirk(psp)) 613 continue; 614 if (amdgpu_sriov_vf(adev) && 615 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 616 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 617 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) 618 /*skip ucode loading in SRIOV VF */ 619 continue; 620 621 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 622 if (ret) 623 return ret; 624 625 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 626 psp->fence_buf_mc_addr); 627 if (ret) 628 return ret; 629 630 #if 0 631 /* check if firmware loaded sucessfully */ 632 if (!amdgpu_psp_check_fw_loading_status(adev, i)) 633 return -EINVAL; 634 #endif 635 } 636 637 return 0; 638 } 639 640 static int psp_load_fw(struct amdgpu_device *adev) 641 { 642 int ret; 643 struct psp_context *psp = &adev->psp; 644 645 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) { 646 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 647 goto skip_memalloc; 648 } 649 650 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 651 if (!psp->cmd) 652 return -ENOMEM; 653 654 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 655 AMDGPU_GEM_DOMAIN_GTT, 656 &psp->fw_pri_bo, 657 &psp->fw_pri_mc_addr, 658 &psp->fw_pri_buf); 659 if (ret) 660 goto failed; 661 662 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 663 AMDGPU_GEM_DOMAIN_VRAM, 664 &psp->fence_buf_bo, 665 &psp->fence_buf_mc_addr, 666 &psp->fence_buf); 667 if (ret) 668 goto failed_mem2; 669 670 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 671 AMDGPU_GEM_DOMAIN_VRAM, 672 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 673 (void **)&psp->cmd_buf_mem); 674 if (ret) 675 goto failed_mem1; 676 677 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 678 679 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 680 if (ret) 681 goto failed_mem; 682 683 ret = psp_tmr_init(psp); 684 if (ret) 685 goto failed_mem; 686 687 ret = psp_asd_init(psp); 688 if (ret) 689 goto failed_mem; 690 691 skip_memalloc: 692 ret = psp_hw_start(psp); 693 if (ret) 694 goto failed_mem; 695 696 ret = psp_np_fw_load(psp); 697 if (ret) 698 goto failed_mem; 699 700 return 0; 701 702 failed_mem: 703 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, 704 &psp->cmd_buf_mc_addr, 705 (void **)&psp->cmd_buf_mem); 706 failed_mem1: 707 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 708 &psp->fence_buf_mc_addr, &psp->fence_buf); 709 failed_mem2: 710 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 711 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 712 failed: 713 kfree(psp->cmd); 714 psp->cmd = NULL; 715 return ret; 716 } 717 718 static int psp_hw_init(void *handle) 719 { 720 int ret; 721 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 722 723 mutex_lock(&adev->firmware.mutex); 724 /* 725 * This sequence is just used on hw_init only once, no need on 726 * resume. 727 */ 728 ret = amdgpu_ucode_init_bo(adev); 729 if (ret) 730 goto failed; 731 732 ret = psp_load_fw(adev); 733 if (ret) { 734 DRM_ERROR("PSP firmware loading failed\n"); 735 goto failed; 736 } 737 738 mutex_unlock(&adev->firmware.mutex); 739 return 0; 740 741 failed: 742 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 743 mutex_unlock(&adev->firmware.mutex); 744 return -EINVAL; 745 } 746 747 static int psp_hw_fini(void *handle) 748 { 749 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 750 struct psp_context *psp = &adev->psp; 751 752 if (adev->gmc.xgmi.num_physical_nodes > 1 && 753 psp->xgmi_context.initialized == 1) 754 psp_xgmi_terminate(psp); 755 756 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 757 758 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 759 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 760 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 761 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 762 &psp->fence_buf_mc_addr, &psp->fence_buf); 763 amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr, 764 &psp->asd_shared_buf); 765 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 766 (void **)&psp->cmd_buf_mem); 767 768 kfree(psp->cmd); 769 psp->cmd = NULL; 770 771 return 0; 772 } 773 774 static int psp_suspend(void *handle) 775 { 776 int ret; 777 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 778 struct psp_context *psp = &adev->psp; 779 780 if (adev->gmc.xgmi.num_physical_nodes > 1 && 781 psp->xgmi_context.initialized == 1) { 782 ret = psp_xgmi_terminate(psp); 783 if (ret) { 784 DRM_ERROR("Failed to terminate xgmi ta\n"); 785 return ret; 786 } 787 } 788 789 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 790 if (ret) { 791 DRM_ERROR("PSP ring stop failed\n"); 792 return ret; 793 } 794 795 return 0; 796 } 797 798 static int psp_resume(void *handle) 799 { 800 int ret; 801 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 802 struct psp_context *psp = &adev->psp; 803 804 DRM_INFO("PSP is resuming...\n"); 805 806 mutex_lock(&adev->firmware.mutex); 807 808 ret = psp_hw_start(psp); 809 if (ret) 810 goto failed; 811 812 ret = psp_np_fw_load(psp); 813 if (ret) 814 goto failed; 815 816 mutex_unlock(&adev->firmware.mutex); 817 818 return 0; 819 820 failed: 821 DRM_ERROR("PSP resume failed\n"); 822 mutex_unlock(&adev->firmware.mutex); 823 return ret; 824 } 825 826 int psp_gpu_reset(struct amdgpu_device *adev) 827 { 828 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 829 return 0; 830 831 return psp_mode1_reset(&adev->psp); 832 } 833 834 static bool psp_check_fw_loading_status(struct amdgpu_device *adev, 835 enum AMDGPU_UCODE_ID ucode_type) 836 { 837 struct amdgpu_firmware_info *ucode = NULL; 838 839 if (!adev->firmware.fw_size) 840 return false; 841 842 ucode = &adev->firmware.ucode[ucode_type]; 843 if (!ucode->fw || !ucode->ucode_size) 844 return false; 845 846 return psp_compare_sram_data(&adev->psp, ucode, ucode_type); 847 } 848 849 static int psp_set_clockgating_state(void *handle, 850 enum amd_clockgating_state state) 851 { 852 return 0; 853 } 854 855 static int psp_set_powergating_state(void *handle, 856 enum amd_powergating_state state) 857 { 858 return 0; 859 } 860 861 const struct amd_ip_funcs psp_ip_funcs = { 862 .name = "psp", 863 .early_init = psp_early_init, 864 .late_init = NULL, 865 .sw_init = psp_sw_init, 866 .sw_fini = psp_sw_fini, 867 .hw_init = psp_hw_init, 868 .hw_fini = psp_hw_fini, 869 .suspend = psp_suspend, 870 .resume = psp_resume, 871 .is_idle = NULL, 872 .check_soft_reset = NULL, 873 .wait_for_idle = NULL, 874 .soft_reset = NULL, 875 .set_clockgating_state = psp_set_clockgating_state, 876 .set_powergating_state = psp_set_powergating_state, 877 }; 878 879 static const struct amdgpu_psp_funcs psp_funcs = { 880 .check_fw_loading_status = psp_check_fw_loading_status, 881 }; 882 883 static void psp_set_funcs(struct amdgpu_device *adev) 884 { 885 if (NULL == adev->firmware.funcs) 886 adev->firmware.funcs = &psp_funcs; 887 } 888 889 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 890 { 891 .type = AMD_IP_BLOCK_TYPE_PSP, 892 .major = 3, 893 .minor = 1, 894 .rev = 0, 895 .funcs = &psp_ip_funcs, 896 }; 897 898 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 899 { 900 .type = AMD_IP_BLOCK_TYPE_PSP, 901 .major = 10, 902 .minor = 0, 903 .rev = 0, 904 .funcs = &psp_ip_funcs, 905 }; 906 907 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 908 { 909 .type = AMD_IP_BLOCK_TYPE_PSP, 910 .major = 11, 911 .minor = 0, 912 .rev = 0, 913 .funcs = &psp_ip_funcs, 914 }; 915