1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 41 #include "amdgpu_ras.h" 42 #include "amdgpu_securedisplay.h" 43 #include "amdgpu_atomfirmware.h" 44 45 static int psp_sysfs_init(struct amdgpu_device *adev); 46 static void psp_sysfs_fini(struct amdgpu_device *adev); 47 48 static int psp_load_smu_fw(struct psp_context *psp); 49 static int psp_ta_unload(struct psp_context *psp, struct ta_context *context); 50 static int psp_ta_load(struct psp_context *psp, struct ta_context *context); 51 static int psp_rap_terminate(struct psp_context *psp); 52 static int psp_securedisplay_terminate(struct psp_context *psp); 53 54 /* 55 * Due to DF Cstate management centralized to PMFW, the firmware 56 * loading sequence will be updated as below: 57 * - Load KDB 58 * - Load SYS_DRV 59 * - Load tOS 60 * - Load PMFW 61 * - Setup TMR 62 * - Load other non-psp fw 63 * - Load ASD 64 * - Load XGMI/RAS/HDCP/DTM TA if any 65 * 66 * This new sequence is required for 67 * - Arcturus and onwards 68 * - Navi12 and onwards 69 */ 70 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 71 { 72 struct amdgpu_device *adev = psp->adev; 73 74 psp->pmfw_centralized_cstate_management = false; 75 76 if (amdgpu_sriov_vf(adev)) 77 return; 78 79 if (adev->flags & AMD_IS_APU) 80 return; 81 82 if ((adev->asic_type >= CHIP_ARCTURUS) || 83 (adev->asic_type >= CHIP_NAVI12)) 84 psp->pmfw_centralized_cstate_management = true; 85 } 86 87 static int psp_early_init(void *handle) 88 { 89 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 90 struct psp_context *psp = &adev->psp; 91 92 switch (adev->asic_type) { 93 case CHIP_VEGA10: 94 case CHIP_VEGA12: 95 psp_v3_1_set_psp_funcs(psp); 96 psp->autoload_supported = false; 97 break; 98 case CHIP_RAVEN: 99 psp_v10_0_set_psp_funcs(psp); 100 psp->autoload_supported = false; 101 break; 102 case CHIP_VEGA20: 103 case CHIP_ARCTURUS: 104 psp_v11_0_set_psp_funcs(psp); 105 psp->autoload_supported = false; 106 break; 107 case CHIP_NAVI10: 108 case CHIP_NAVI14: 109 case CHIP_NAVI12: 110 case CHIP_SIENNA_CICHLID: 111 case CHIP_NAVY_FLOUNDER: 112 case CHIP_VANGOGH: 113 case CHIP_DIMGREY_CAVEFISH: 114 case CHIP_BEIGE_GOBY: 115 psp_v11_0_set_psp_funcs(psp); 116 psp->autoload_supported = true; 117 break; 118 case CHIP_RENOIR: 119 psp_v12_0_set_psp_funcs(psp); 120 break; 121 case CHIP_ALDEBARAN: 122 psp_v13_0_set_psp_funcs(psp); 123 break; 124 case CHIP_YELLOW_CARP: 125 psp_v13_0_set_psp_funcs(psp); 126 psp->autoload_supported = true; 127 break; 128 case CHIP_CYAN_SKILLFISH: 129 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 130 psp_v11_0_8_set_psp_funcs(psp); 131 psp->autoload_supported = false; 132 } 133 break; 134 default: 135 return -EINVAL; 136 } 137 138 psp->adev = adev; 139 140 psp_check_pmfw_centralized_cstate_management(psp); 141 142 return 0; 143 } 144 145 static void psp_memory_training_fini(struct psp_context *psp) 146 { 147 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 148 149 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 150 kfree(ctx->sys_cache); 151 ctx->sys_cache = NULL; 152 } 153 154 static int psp_memory_training_init(struct psp_context *psp) 155 { 156 int ret; 157 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 158 159 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 160 DRM_DEBUG("memory training is not supported!\n"); 161 return 0; 162 } 163 164 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 165 if (ctx->sys_cache == NULL) { 166 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 167 ret = -ENOMEM; 168 goto Err_out; 169 } 170 171 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 172 ctx->train_data_size, 173 ctx->p2c_train_data_offset, 174 ctx->c2p_train_data_offset); 175 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 176 return 0; 177 178 Err_out: 179 psp_memory_training_fini(psp); 180 return ret; 181 } 182 183 /* 184 * Helper funciton to query psp runtime database entry 185 * 186 * @adev: amdgpu_device pointer 187 * @entry_type: the type of psp runtime database entry 188 * @db_entry: runtime database entry pointer 189 * 190 * Return false if runtime database doesn't exit or entry is invalid 191 * or true if the specific database entry is found, and copy to @db_entry 192 */ 193 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 194 enum psp_runtime_entry_type entry_type, 195 void *db_entry) 196 { 197 uint64_t db_header_pos, db_dir_pos; 198 struct psp_runtime_data_header db_header = {0}; 199 struct psp_runtime_data_directory db_dir = {0}; 200 bool ret = false; 201 int i; 202 203 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 204 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 205 206 /* read runtime db header from vram */ 207 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 208 sizeof(struct psp_runtime_data_header), false); 209 210 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 211 /* runtime db doesn't exist, exit */ 212 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 213 return false; 214 } 215 216 /* read runtime database entry from vram */ 217 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 218 sizeof(struct psp_runtime_data_directory), false); 219 220 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 221 /* invalid db entry count, exit */ 222 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 223 return false; 224 } 225 226 /* look up for requested entry type */ 227 for (i = 0; i < db_dir.entry_count && !ret; i++) { 228 if (db_dir.entry_list[i].entry_type == entry_type) { 229 switch (entry_type) { 230 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 231 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 232 /* invalid db entry size */ 233 dev_warn(adev->dev, "Invalid PSP runtime database entry size\n"); 234 return false; 235 } 236 /* read runtime database entry */ 237 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 238 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 239 ret = true; 240 break; 241 default: 242 ret = false; 243 break; 244 } 245 } 246 } 247 248 return ret; 249 } 250 251 static int psp_sw_init(void *handle) 252 { 253 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 254 struct psp_context *psp = &adev->psp; 255 int ret; 256 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 257 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 258 259 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 260 if (!psp->cmd) { 261 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 262 ret = -ENOMEM; 263 } 264 265 if (!amdgpu_sriov_vf(adev)) { 266 ret = psp_init_microcode(psp); 267 if (ret) { 268 DRM_ERROR("Failed to load psp firmware!\n"); 269 return ret; 270 } 271 } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) { 272 ret = psp_init_ta_microcode(psp, "aldebaran"); 273 if (ret) { 274 DRM_ERROR("Failed to initialize ta microcode!\n"); 275 return ret; 276 } 277 } 278 279 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 280 if (psp_get_runtime_db_entry(adev, 281 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 282 &boot_cfg_entry)) { 283 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 284 if ((psp->boot_cfg_bitmask) & 285 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 286 /* If psp runtime database exists, then 287 * only enable two stage memory training 288 * when TWO_STAGE_DRAM_TRAINING bit is set 289 * in runtime database */ 290 mem_training_ctx->enable_mem_training = true; 291 } 292 293 } else { 294 /* If psp runtime database doesn't exist or 295 * is invalid, force enable two stage memory 296 * training */ 297 mem_training_ctx->enable_mem_training = true; 298 } 299 300 if (mem_training_ctx->enable_mem_training) { 301 ret = psp_memory_training_init(psp); 302 if (ret) { 303 DRM_ERROR("Failed to initialize memory training!\n"); 304 return ret; 305 } 306 307 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 308 if (ret) { 309 DRM_ERROR("Failed to process memory training!\n"); 310 return ret; 311 } 312 } 313 314 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 315 ret= psp_sysfs_init(adev); 316 if (ret) { 317 return ret; 318 } 319 } 320 321 return 0; 322 } 323 324 static int psp_sw_fini(void *handle) 325 { 326 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 327 struct psp_context *psp = &adev->psp; 328 struct psp_gfx_cmd_resp *cmd = psp->cmd; 329 330 psp_memory_training_fini(psp); 331 if (psp->sos_fw) { 332 release_firmware(psp->sos_fw); 333 psp->sos_fw = NULL; 334 } 335 if (psp->asd_fw) { 336 release_firmware(psp->asd_fw); 337 psp->asd_fw = NULL; 338 } 339 if (psp->ta_fw) { 340 release_firmware(psp->ta_fw); 341 psp->ta_fw = NULL; 342 } 343 344 if (adev->asic_type == CHIP_NAVI10 || 345 adev->asic_type == CHIP_SIENNA_CICHLID) 346 psp_sysfs_fini(adev); 347 348 kfree(cmd); 349 cmd = NULL; 350 351 return 0; 352 } 353 354 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 355 uint32_t reg_val, uint32_t mask, bool check_changed) 356 { 357 uint32_t val; 358 int i; 359 struct amdgpu_device *adev = psp->adev; 360 361 if (psp->adev->no_hw_access) 362 return 0; 363 364 for (i = 0; i < adev->usec_timeout; i++) { 365 val = RREG32(reg_index); 366 if (check_changed) { 367 if (val != reg_val) 368 return 0; 369 } else { 370 if ((val & mask) == reg_val) 371 return 0; 372 } 373 udelay(1); 374 } 375 376 return -ETIME; 377 } 378 379 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 380 { 381 switch (cmd_id) { 382 case GFX_CMD_ID_LOAD_TA: 383 return "LOAD_TA"; 384 case GFX_CMD_ID_UNLOAD_TA: 385 return "UNLOAD_TA"; 386 case GFX_CMD_ID_INVOKE_CMD: 387 return "INVOKE_CMD"; 388 case GFX_CMD_ID_LOAD_ASD: 389 return "LOAD_ASD"; 390 case GFX_CMD_ID_SETUP_TMR: 391 return "SETUP_TMR"; 392 case GFX_CMD_ID_LOAD_IP_FW: 393 return "LOAD_IP_FW"; 394 case GFX_CMD_ID_DESTROY_TMR: 395 return "DESTROY_TMR"; 396 case GFX_CMD_ID_SAVE_RESTORE: 397 return "SAVE_RESTORE_IP_FW"; 398 case GFX_CMD_ID_SETUP_VMR: 399 return "SETUP_VMR"; 400 case GFX_CMD_ID_DESTROY_VMR: 401 return "DESTROY_VMR"; 402 case GFX_CMD_ID_PROG_REG: 403 return "PROG_REG"; 404 case GFX_CMD_ID_GET_FW_ATTESTATION: 405 return "GET_FW_ATTESTATION"; 406 case GFX_CMD_ID_LOAD_TOC: 407 return "ID_LOAD_TOC"; 408 case GFX_CMD_ID_AUTOLOAD_RLC: 409 return "AUTOLOAD_RLC"; 410 case GFX_CMD_ID_BOOT_CFG: 411 return "BOOT_CFG"; 412 default: 413 return "UNKNOWN CMD"; 414 } 415 } 416 417 static int 418 psp_cmd_submit_buf(struct psp_context *psp, 419 struct amdgpu_firmware_info *ucode, 420 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 421 { 422 int ret; 423 int index, idx; 424 int timeout = 20000; 425 bool ras_intr = false; 426 bool skip_unsupport = false; 427 428 if (psp->adev->no_hw_access) 429 return 0; 430 431 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 432 return 0; 433 434 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 435 436 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 437 438 index = atomic_inc_return(&psp->fence_value); 439 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 440 if (ret) { 441 atomic_dec(&psp->fence_value); 442 goto exit; 443 } 444 445 amdgpu_device_invalidate_hdp(psp->adev, NULL); 446 while (*((unsigned int *)psp->fence_buf) != index) { 447 if (--timeout == 0) 448 break; 449 /* 450 * Shouldn't wait for timeout when err_event_athub occurs, 451 * because gpu reset thread triggered and lock resource should 452 * be released for psp resume sequence. 453 */ 454 ras_intr = amdgpu_ras_intr_triggered(); 455 if (ras_intr) 456 break; 457 usleep_range(10, 100); 458 amdgpu_device_invalidate_hdp(psp->adev, NULL); 459 } 460 461 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 462 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 463 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 464 465 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 466 467 /* In some cases, psp response status is not 0 even there is no 468 * problem while the command is submitted. Some version of PSP FW 469 * doesn't write 0 to that field. 470 * So here we would like to only print a warning instead of an error 471 * during psp initialization to avoid breaking hw_init and it doesn't 472 * return -EINVAL. 473 */ 474 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 475 if (ucode) 476 DRM_WARN("failed to load ucode %s(0x%X) ", 477 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 478 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 479 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 480 psp->cmd_buf_mem->resp.status); 481 if (!timeout) { 482 ret = -EINVAL; 483 goto exit; 484 } 485 } 486 487 if (ucode) { 488 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 489 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 490 } 491 492 exit: 493 drm_dev_exit(idx); 494 return ret; 495 } 496 497 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 498 { 499 struct psp_gfx_cmd_resp *cmd = psp->cmd; 500 501 mutex_lock(&psp->mutex); 502 503 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 504 505 return cmd; 506 } 507 508 void release_psp_cmd_buf(struct psp_context *psp) 509 { 510 mutex_unlock(&psp->mutex); 511 } 512 513 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 514 struct psp_gfx_cmd_resp *cmd, 515 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 516 { 517 struct amdgpu_device *adev = psp->adev; 518 uint32_t size = amdgpu_bo_size(tmr_bo); 519 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 520 521 if (amdgpu_sriov_vf(psp->adev)) 522 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 523 else 524 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 525 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 526 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 527 cmd->cmd.cmd_setup_tmr.buf_size = size; 528 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 529 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 530 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 531 } 532 533 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 534 uint64_t pri_buf_mc, uint32_t size) 535 { 536 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 537 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 538 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 539 cmd->cmd.cmd_load_toc.toc_size = size; 540 } 541 542 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 543 static int psp_load_toc(struct psp_context *psp, 544 uint32_t *tmr_size) 545 { 546 int ret; 547 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 548 549 /* Copy toc to psp firmware private buffer */ 550 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 551 552 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 553 554 ret = psp_cmd_submit_buf(psp, NULL, cmd, 555 psp->fence_buf_mc_addr); 556 if (!ret) 557 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 558 559 release_psp_cmd_buf(psp); 560 561 return ret; 562 } 563 564 /* Set up Trusted Memory Region */ 565 static int psp_tmr_init(struct psp_context *psp) 566 { 567 int ret; 568 int tmr_size; 569 void *tmr_buf; 570 void **pptr; 571 572 /* 573 * According to HW engineer, they prefer the TMR address be "naturally 574 * aligned" , e.g. the start address be an integer divide of TMR size. 575 * 576 * Note: this memory need be reserved till the driver 577 * uninitializes. 578 */ 579 tmr_size = PSP_TMR_SIZE(psp->adev); 580 581 /* For ASICs support RLC autoload, psp will parse the toc 582 * and calculate the total size of TMR needed */ 583 if (!amdgpu_sriov_vf(psp->adev) && 584 psp->toc.start_addr && 585 psp->toc.size_bytes && 586 psp->fw_pri_buf) { 587 ret = psp_load_toc(psp, &tmr_size); 588 if (ret) { 589 DRM_ERROR("Failed to load toc\n"); 590 return ret; 591 } 592 } 593 594 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 595 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 596 AMDGPU_GEM_DOMAIN_VRAM, 597 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 598 599 return ret; 600 } 601 602 static bool psp_skip_tmr(struct psp_context *psp) 603 { 604 switch (psp->adev->asic_type) { 605 case CHIP_NAVI12: 606 case CHIP_SIENNA_CICHLID: 607 case CHIP_ALDEBARAN: 608 return true; 609 default: 610 return false; 611 } 612 } 613 614 static int psp_tmr_load(struct psp_context *psp) 615 { 616 int ret; 617 struct psp_gfx_cmd_resp *cmd; 618 619 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 620 * Already set up by host driver. 621 */ 622 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 623 return 0; 624 625 cmd = acquire_psp_cmd_buf(psp); 626 627 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 628 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 629 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 630 631 ret = psp_cmd_submit_buf(psp, NULL, cmd, 632 psp->fence_buf_mc_addr); 633 634 release_psp_cmd_buf(psp); 635 636 return ret; 637 } 638 639 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 640 struct psp_gfx_cmd_resp *cmd) 641 { 642 if (amdgpu_sriov_vf(psp->adev)) 643 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 644 else 645 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 646 } 647 648 static int psp_tmr_unload(struct psp_context *psp) 649 { 650 int ret; 651 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 652 653 psp_prep_tmr_unload_cmd_buf(psp, cmd); 654 DRM_INFO("free PSP TMR buffer\n"); 655 656 ret = psp_cmd_submit_buf(psp, NULL, cmd, 657 psp->fence_buf_mc_addr); 658 659 release_psp_cmd_buf(psp); 660 661 return ret; 662 } 663 664 static int psp_tmr_terminate(struct psp_context *psp) 665 { 666 int ret; 667 void *tmr_buf; 668 void **pptr; 669 670 ret = psp_tmr_unload(psp); 671 if (ret) 672 return ret; 673 674 /* free TMR memory buffer */ 675 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 676 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 677 678 return 0; 679 } 680 681 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 682 uint64_t *output_ptr) 683 { 684 int ret; 685 struct psp_gfx_cmd_resp *cmd; 686 687 if (!output_ptr) 688 return -EINVAL; 689 690 if (amdgpu_sriov_vf(psp->adev)) 691 return 0; 692 693 cmd = acquire_psp_cmd_buf(psp); 694 695 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 696 697 ret = psp_cmd_submit_buf(psp, NULL, cmd, 698 psp->fence_buf_mc_addr); 699 700 if (!ret) { 701 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 702 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 703 } 704 705 release_psp_cmd_buf(psp); 706 707 return ret; 708 } 709 710 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 711 { 712 struct psp_context *psp = &adev->psp; 713 struct psp_gfx_cmd_resp *cmd; 714 int ret; 715 716 if (amdgpu_sriov_vf(adev)) 717 return 0; 718 719 cmd = acquire_psp_cmd_buf(psp); 720 721 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 722 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 723 724 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 725 if (!ret) { 726 *boot_cfg = 727 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 728 } 729 730 release_psp_cmd_buf(psp); 731 732 return ret; 733 } 734 735 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 736 { 737 int ret; 738 struct psp_context *psp = &adev->psp; 739 struct psp_gfx_cmd_resp *cmd; 740 741 if (amdgpu_sriov_vf(adev)) 742 return 0; 743 744 cmd = acquire_psp_cmd_buf(psp); 745 746 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 747 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 748 cmd->cmd.boot_cfg.boot_config = boot_cfg; 749 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 750 751 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 752 753 release_psp_cmd_buf(psp); 754 755 return ret; 756 } 757 758 static int psp_rl_load(struct amdgpu_device *adev) 759 { 760 int ret; 761 struct psp_context *psp = &adev->psp; 762 struct psp_gfx_cmd_resp *cmd; 763 764 if (!is_psp_fw_valid(psp->rl)) 765 return 0; 766 767 cmd = acquire_psp_cmd_buf(psp); 768 769 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 770 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 771 772 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 773 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 774 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 775 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 776 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 777 778 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 779 780 release_psp_cmd_buf(psp); 781 782 return ret; 783 } 784 785 static int psp_asd_load(struct psp_context *psp) 786 { 787 return psp_ta_load(psp, &psp->asd_context); 788 } 789 790 static int psp_asd_initialize(struct psp_context *psp) 791 { 792 int ret; 793 794 /* If PSP version doesn't match ASD version, asd loading will be failed. 795 * add workaround to bypass it for sriov now. 796 * TODO: add version check to make it common 797 */ 798 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 799 return 0; 800 801 psp->asd_context.mem_context.shared_mc_addr = 0; 802 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 803 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 804 805 ret = psp_asd_load(psp); 806 if (!ret) 807 psp->asd_context.initialized = true; 808 809 return ret; 810 } 811 812 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 813 uint32_t session_id) 814 { 815 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 816 cmd->cmd.cmd_unload_ta.session_id = session_id; 817 } 818 819 static int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 820 { 821 int ret; 822 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 823 824 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 825 826 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 827 828 release_psp_cmd_buf(psp); 829 830 return ret; 831 } 832 833 static int psp_asd_unload(struct psp_context *psp) 834 { 835 return psp_ta_unload(psp, &psp->asd_context); 836 } 837 838 static int psp_asd_terminate(struct psp_context *psp) 839 { 840 int ret; 841 842 if (amdgpu_sriov_vf(psp->adev)) 843 return 0; 844 845 if (!psp->asd_context.initialized) 846 return 0; 847 848 ret = psp_asd_unload(psp); 849 850 if (!ret) 851 psp->asd_context.initialized = false; 852 853 return ret; 854 } 855 856 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 857 uint32_t id, uint32_t value) 858 { 859 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 860 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 861 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 862 } 863 864 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 865 uint32_t value) 866 { 867 struct psp_gfx_cmd_resp *cmd; 868 int ret = 0; 869 870 if (reg >= PSP_REG_LAST) 871 return -EINVAL; 872 873 cmd = acquire_psp_cmd_buf(psp); 874 875 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 876 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 877 if (ret) 878 DRM_ERROR("PSP failed to program reg id %d", reg); 879 880 release_psp_cmd_buf(psp); 881 882 return ret; 883 } 884 885 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 886 uint64_t ta_bin_mc, 887 struct ta_context *context) 888 { 889 cmd->cmd_id = context->ta_load_type; 890 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 891 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 892 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 893 894 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 895 lower_32_bits(context->mem_context.shared_mc_addr); 896 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 897 upper_32_bits(context->mem_context.shared_mc_addr); 898 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 899 } 900 901 static int psp_ta_init_shared_buf(struct psp_context *psp, 902 struct ta_mem_context *mem_ctx) 903 { 904 int ret; 905 906 /* 907 * Allocate 16k memory aligned to 4k from Frame Buffer (local 908 * physical) for ta to host memory 909 */ 910 ret = amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 911 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 912 &mem_ctx->shared_bo, 913 &mem_ctx->shared_mc_addr, 914 &mem_ctx->shared_buf); 915 916 return ret; 917 } 918 919 static void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 920 { 921 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 922 &mem_ctx->shared_buf); 923 } 924 925 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 926 { 927 return psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 928 } 929 930 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 931 uint32_t ta_cmd_id, 932 uint32_t session_id) 933 { 934 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 935 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 936 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 937 } 938 939 static int psp_ta_invoke(struct psp_context *psp, 940 uint32_t ta_cmd_id, 941 struct ta_context *context) 942 { 943 int ret; 944 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 945 946 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 947 948 ret = psp_cmd_submit_buf(psp, NULL, cmd, 949 psp->fence_buf_mc_addr); 950 951 release_psp_cmd_buf(psp); 952 953 return ret; 954 } 955 956 static int psp_ta_load(struct psp_context *psp, struct ta_context *context) 957 { 958 int ret; 959 struct psp_gfx_cmd_resp *cmd; 960 961 cmd = acquire_psp_cmd_buf(psp); 962 963 psp_copy_fw(psp, context->bin_desc.start_addr, 964 context->bin_desc.size_bytes); 965 966 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 967 968 ret = psp_cmd_submit_buf(psp, NULL, cmd, 969 psp->fence_buf_mc_addr); 970 971 if (!ret) { 972 context->session_id = cmd->resp.session_id; 973 } 974 975 release_psp_cmd_buf(psp); 976 977 return ret; 978 } 979 980 static int psp_xgmi_load(struct psp_context *psp) 981 { 982 return psp_ta_load(psp, &psp->xgmi_context.context); 983 } 984 985 static int psp_xgmi_unload(struct psp_context *psp) 986 { 987 return psp_ta_unload(psp, &psp->xgmi_context.context); 988 } 989 990 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 991 { 992 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 993 } 994 995 int psp_xgmi_terminate(struct psp_context *psp) 996 { 997 int ret; 998 struct amdgpu_device *adev = psp->adev; 999 1000 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1001 if (adev->asic_type == CHIP_ARCTURUS || 1002 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu)) 1003 return 0; 1004 1005 if (!psp->xgmi_context.context.initialized) 1006 return 0; 1007 1008 ret = psp_xgmi_unload(psp); 1009 if (ret) 1010 return ret; 1011 1012 psp->xgmi_context.context.initialized = false; 1013 1014 /* free xgmi shared memory */ 1015 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 1016 1017 return 0; 1018 } 1019 1020 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1021 { 1022 struct ta_xgmi_shared_memory *xgmi_cmd; 1023 int ret; 1024 1025 if (!psp->ta_fw || 1026 !psp->xgmi_context.context.bin_desc.size_bytes || 1027 !psp->xgmi_context.context.bin_desc.start_addr) 1028 return -ENOENT; 1029 1030 if (!load_ta) 1031 goto invoke; 1032 1033 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1034 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1035 1036 if (!psp->xgmi_context.context.initialized) { 1037 ret = psp_xgmi_init_shared_buf(psp); 1038 if (ret) 1039 return ret; 1040 } 1041 1042 /* Load XGMI TA */ 1043 ret = psp_xgmi_load(psp); 1044 if (!ret) 1045 psp->xgmi_context.context.initialized = true; 1046 else 1047 return ret; 1048 1049 invoke: 1050 /* Initialize XGMI session */ 1051 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1052 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1053 xgmi_cmd->flag_extend_link_record = set_extended_data; 1054 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1055 1056 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1057 1058 return ret; 1059 } 1060 1061 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1062 { 1063 struct ta_xgmi_shared_memory *xgmi_cmd; 1064 int ret; 1065 1066 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1067 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1068 1069 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1070 1071 /* Invoke xgmi ta to get hive id */ 1072 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1073 if (ret) 1074 return ret; 1075 1076 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1077 1078 return 0; 1079 } 1080 1081 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1082 { 1083 struct ta_xgmi_shared_memory *xgmi_cmd; 1084 int ret; 1085 1086 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1087 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1088 1089 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1090 1091 /* Invoke xgmi ta to get the node id */ 1092 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1093 if (ret) 1094 return ret; 1095 1096 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1097 1098 return 0; 1099 } 1100 1101 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1102 { 1103 return psp->adev->asic_type == CHIP_ALDEBARAN && 1104 psp->xgmi_context.context.bin_desc.feature_version >= 0x2000000b; 1105 } 1106 1107 /* 1108 * Chips that support extended topology information require the driver to 1109 * reflect topology information in the opposite direction. This is 1110 * because the TA has already exceeded its link record limit and if the 1111 * TA holds bi-directional information, the driver would have to do 1112 * multiple fetches instead of just two. 1113 */ 1114 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1115 struct psp_xgmi_node_info node_info) 1116 { 1117 struct amdgpu_device *mirror_adev; 1118 struct amdgpu_hive_info *hive; 1119 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1120 uint64_t dst_node_id = node_info.node_id; 1121 uint8_t dst_num_hops = node_info.num_hops; 1122 uint8_t dst_num_links = node_info.num_links; 1123 1124 hive = amdgpu_get_xgmi_hive(psp->adev); 1125 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1126 struct psp_xgmi_topology_info *mirror_top_info; 1127 int j; 1128 1129 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1130 continue; 1131 1132 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1133 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1134 if (mirror_top_info->nodes[j].node_id != src_node_id) 1135 continue; 1136 1137 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1138 /* 1139 * prevent 0 num_links value re-reflection since reflection 1140 * criteria is based on num_hops (direct or indirect). 1141 * 1142 */ 1143 if (dst_num_links) 1144 mirror_top_info->nodes[j].num_links = dst_num_links; 1145 1146 break; 1147 } 1148 1149 break; 1150 } 1151 } 1152 1153 int psp_xgmi_get_topology_info(struct psp_context *psp, 1154 int number_devices, 1155 struct psp_xgmi_topology_info *topology, 1156 bool get_extended_data) 1157 { 1158 struct ta_xgmi_shared_memory *xgmi_cmd; 1159 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1160 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1161 int i; 1162 int ret; 1163 1164 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1165 return -EINVAL; 1166 1167 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1168 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1169 xgmi_cmd->flag_extend_link_record = get_extended_data; 1170 1171 /* Fill in the shared memory with topology information as input */ 1172 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1173 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1174 topology_info_input->num_nodes = number_devices; 1175 1176 for (i = 0; i < topology_info_input->num_nodes; i++) { 1177 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1178 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1179 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1180 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1181 } 1182 1183 /* Invoke xgmi ta to get the topology information */ 1184 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1185 if (ret) 1186 return ret; 1187 1188 /* Read the output topology information from the shared memory */ 1189 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1190 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1191 for (i = 0; i < topology->num_nodes; i++) { 1192 /* extended data will either be 0 or equal to non-extended data */ 1193 if (topology_info_output->nodes[i].num_hops) 1194 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1195 1196 /* non-extended data gets everything here so no need to update */ 1197 if (!get_extended_data) { 1198 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1199 topology->nodes[i].is_sharing_enabled = 1200 topology_info_output->nodes[i].is_sharing_enabled; 1201 topology->nodes[i].sdma_engine = 1202 topology_info_output->nodes[i].sdma_engine; 1203 } 1204 1205 } 1206 1207 /* Invoke xgmi ta again to get the link information */ 1208 if (psp_xgmi_peer_link_info_supported(psp)) { 1209 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1210 1211 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1212 1213 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1214 1215 if (ret) 1216 return ret; 1217 1218 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1219 for (i = 0; i < topology->num_nodes; i++) { 1220 /* accumulate num_links on extended data */ 1221 topology->nodes[i].num_links = get_extended_data ? 1222 topology->nodes[i].num_links + 1223 link_info_output->nodes[i].num_links : 1224 link_info_output->nodes[i].num_links; 1225 1226 /* reflect the topology information for bi-directionality */ 1227 if (psp->xgmi_context.supports_extended_data && 1228 get_extended_data && topology->nodes[i].num_hops) 1229 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1230 } 1231 } 1232 1233 return 0; 1234 } 1235 1236 int psp_xgmi_set_topology_info(struct psp_context *psp, 1237 int number_devices, 1238 struct psp_xgmi_topology_info *topology) 1239 { 1240 struct ta_xgmi_shared_memory *xgmi_cmd; 1241 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1242 int i; 1243 1244 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1245 return -EINVAL; 1246 1247 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1248 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1249 1250 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1251 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1252 topology_info_input->num_nodes = number_devices; 1253 1254 for (i = 0; i < topology_info_input->num_nodes; i++) { 1255 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1256 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1257 topology_info_input->nodes[i].is_sharing_enabled = 1; 1258 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1259 } 1260 1261 /* Invoke xgmi ta to set topology information */ 1262 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1263 } 1264 1265 // ras begin 1266 static int psp_ras_init_shared_buf(struct psp_context *psp) 1267 { 1268 return psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1269 } 1270 1271 static int psp_ras_load(struct psp_context *psp) 1272 { 1273 return psp_ta_load(psp, &psp->ras_context.context); 1274 } 1275 1276 static int psp_ras_unload(struct psp_context *psp) 1277 { 1278 return psp_ta_unload(psp, &psp->ras_context.context); 1279 } 1280 1281 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1282 { 1283 struct ta_ras_shared_memory *ras_cmd; 1284 int ret; 1285 1286 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1287 1288 /* 1289 * TODO: bypass the loading in sriov for now 1290 */ 1291 if (amdgpu_sriov_vf(psp->adev)) 1292 return 0; 1293 1294 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1295 1296 if (amdgpu_ras_intr_triggered()) 1297 return ret; 1298 1299 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1300 { 1301 DRM_WARN("RAS: Unsupported Interface"); 1302 return -EINVAL; 1303 } 1304 1305 if (!ret) { 1306 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1307 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1308 1309 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1310 } 1311 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1312 dev_warn(psp->adev->dev, 1313 "RAS internal register access blocked\n"); 1314 1315 if (ras_cmd->ras_status == TA_RAS_STATUS__ERROR_UNSUPPORTED_IP) 1316 dev_warn(psp->adev->dev, "RAS WARNING: cmd failed due to unsupported ip\n"); 1317 else if (ras_cmd->ras_status) 1318 dev_warn(psp->adev->dev, "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1319 } 1320 1321 return ret; 1322 } 1323 1324 int psp_ras_enable_features(struct psp_context *psp, 1325 union ta_ras_cmd_input *info, bool enable) 1326 { 1327 struct ta_ras_shared_memory *ras_cmd; 1328 int ret; 1329 1330 if (!psp->ras_context.context.initialized) 1331 return -EINVAL; 1332 1333 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1334 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1335 1336 if (enable) 1337 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1338 else 1339 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1340 1341 ras_cmd->ras_in_message = *info; 1342 1343 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1344 if (ret) 1345 return -EINVAL; 1346 1347 return 0; 1348 } 1349 1350 static int psp_ras_terminate(struct psp_context *psp) 1351 { 1352 int ret; 1353 1354 /* 1355 * TODO: bypass the terminate in sriov for now 1356 */ 1357 if (amdgpu_sriov_vf(psp->adev)) 1358 return 0; 1359 1360 if (!psp->ras_context.context.initialized) 1361 return 0; 1362 1363 ret = psp_ras_unload(psp); 1364 if (ret) 1365 return ret; 1366 1367 psp->ras_context.context.initialized = false; 1368 1369 /* free ras shared memory */ 1370 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 1371 1372 return 0; 1373 } 1374 1375 static int psp_ras_initialize(struct psp_context *psp) 1376 { 1377 int ret; 1378 uint32_t boot_cfg = 0xFF; 1379 struct amdgpu_device *adev = psp->adev; 1380 struct ta_ras_shared_memory *ras_cmd; 1381 1382 /* 1383 * TODO: bypass the initialize in sriov for now 1384 */ 1385 if (amdgpu_sriov_vf(adev)) 1386 return 0; 1387 1388 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1389 !adev->psp.ras_context.context.bin_desc.start_addr) { 1390 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1391 return 0; 1392 } 1393 1394 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1395 /* query GECC enablement status from boot config 1396 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1397 */ 1398 ret = psp_boot_config_get(adev, &boot_cfg); 1399 if (ret) 1400 dev_warn(adev->dev, "PSP get boot config failed\n"); 1401 1402 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1403 if (!boot_cfg) { 1404 dev_info(adev->dev, "GECC is disabled\n"); 1405 } else { 1406 /* disable GECC in next boot cycle if ras is 1407 * disabled by module parameter amdgpu_ras_enable 1408 * and/or amdgpu_ras_mask, or boot_config_get call 1409 * is failed 1410 */ 1411 ret = psp_boot_config_set(adev, 0); 1412 if (ret) 1413 dev_warn(adev->dev, "PSP set boot config failed\n"); 1414 else 1415 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1416 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1417 } 1418 } else { 1419 if (1 == boot_cfg) { 1420 dev_info(adev->dev, "GECC is enabled\n"); 1421 } else { 1422 /* enable GECC in next boot cycle if it is disabled 1423 * in boot config, or force enable GECC if failed to 1424 * get boot configuration 1425 */ 1426 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1427 if (ret) 1428 dev_warn(adev->dev, "PSP set boot config failed\n"); 1429 else 1430 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1431 } 1432 } 1433 } 1434 1435 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1436 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1437 1438 if (!psp->ras_context.context.initialized) { 1439 ret = psp_ras_init_shared_buf(psp); 1440 if (ret) 1441 return ret; 1442 } 1443 1444 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1445 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1446 1447 if (amdgpu_ras_is_poison_mode_supported(adev)) 1448 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1449 if (!adev->gmc.xgmi.connected_to_cpu) 1450 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1451 1452 ret = psp_ras_load(psp); 1453 1454 if (!ret && !ras_cmd->ras_status) 1455 psp->ras_context.context.initialized = true; 1456 else { 1457 if (ras_cmd->ras_status) 1458 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1459 amdgpu_ras_fini(psp->adev); 1460 } 1461 1462 return ret; 1463 } 1464 1465 int psp_ras_trigger_error(struct psp_context *psp, 1466 struct ta_ras_trigger_error_input *info) 1467 { 1468 struct ta_ras_shared_memory *ras_cmd; 1469 int ret; 1470 1471 if (!psp->ras_context.context.initialized) 1472 return -EINVAL; 1473 1474 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1475 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1476 1477 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1478 ras_cmd->ras_in_message.trigger_error = *info; 1479 1480 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1481 if (ret) 1482 return -EINVAL; 1483 1484 /* If err_event_athub occurs error inject was successful, however 1485 return status from TA is no long reliable */ 1486 if (amdgpu_ras_intr_triggered()) 1487 return 0; 1488 1489 if (ras_cmd->ras_status) 1490 return -EINVAL; 1491 1492 return 0; 1493 } 1494 // ras end 1495 1496 // HDCP start 1497 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1498 { 1499 return psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1500 } 1501 1502 static int psp_hdcp_load(struct psp_context *psp) 1503 { 1504 return psp_ta_load(psp, &psp->hdcp_context.context); 1505 } 1506 1507 static int psp_hdcp_initialize(struct psp_context *psp) 1508 { 1509 int ret; 1510 1511 /* 1512 * TODO: bypass the initialize in sriov for now 1513 */ 1514 if (amdgpu_sriov_vf(psp->adev)) 1515 return 0; 1516 1517 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1518 !psp->hdcp_context.context.bin_desc.start_addr) { 1519 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1520 return 0; 1521 } 1522 1523 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1524 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1525 1526 if (!psp->hdcp_context.context.initialized) { 1527 ret = psp_hdcp_init_shared_buf(psp); 1528 if (ret) 1529 return ret; 1530 } 1531 1532 ret = psp_hdcp_load(psp); 1533 if (!ret) { 1534 psp->hdcp_context.context.initialized = true; 1535 mutex_init(&psp->hdcp_context.mutex); 1536 } 1537 1538 return ret; 1539 } 1540 1541 static int psp_hdcp_unload(struct psp_context *psp) 1542 { 1543 return psp_ta_unload(psp, &psp->hdcp_context.context); 1544 } 1545 1546 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1547 { 1548 /* 1549 * TODO: bypass the loading in sriov for now 1550 */ 1551 if (amdgpu_sriov_vf(psp->adev)) 1552 return 0; 1553 1554 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1555 } 1556 1557 static int psp_hdcp_terminate(struct psp_context *psp) 1558 { 1559 int ret; 1560 1561 /* 1562 * TODO: bypass the terminate in sriov for now 1563 */ 1564 if (amdgpu_sriov_vf(psp->adev)) 1565 return 0; 1566 1567 if (!psp->hdcp_context.context.initialized) { 1568 if (psp->hdcp_context.context.mem_context.shared_buf) 1569 goto out; 1570 else 1571 return 0; 1572 } 1573 1574 ret = psp_hdcp_unload(psp); 1575 if (ret) 1576 return ret; 1577 1578 psp->hdcp_context.context.initialized = false; 1579 1580 out: 1581 /* free hdcp shared memory */ 1582 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 1583 1584 return 0; 1585 } 1586 // HDCP end 1587 1588 // DTM start 1589 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1590 { 1591 return psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1592 } 1593 1594 static int psp_dtm_load(struct psp_context *psp) 1595 { 1596 return psp_ta_load(psp, &psp->dtm_context.context); 1597 } 1598 1599 static int psp_dtm_initialize(struct psp_context *psp) 1600 { 1601 int ret; 1602 1603 /* 1604 * TODO: bypass the initialize in sriov for now 1605 */ 1606 if (amdgpu_sriov_vf(psp->adev)) 1607 return 0; 1608 1609 if (!psp->dtm_context.context.bin_desc.size_bytes || 1610 !psp->dtm_context.context.bin_desc.start_addr) { 1611 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1612 return 0; 1613 } 1614 1615 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1616 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1617 1618 if (!psp->dtm_context.context.initialized) { 1619 ret = psp_dtm_init_shared_buf(psp); 1620 if (ret) 1621 return ret; 1622 } 1623 1624 ret = psp_dtm_load(psp); 1625 if (!ret) { 1626 psp->dtm_context.context.initialized = true; 1627 mutex_init(&psp->dtm_context.mutex); 1628 } 1629 1630 return ret; 1631 } 1632 1633 static int psp_dtm_unload(struct psp_context *psp) 1634 { 1635 return psp_ta_unload(psp, &psp->dtm_context.context); 1636 } 1637 1638 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1639 { 1640 /* 1641 * TODO: bypass the loading in sriov for now 1642 */ 1643 if (amdgpu_sriov_vf(psp->adev)) 1644 return 0; 1645 1646 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1647 } 1648 1649 static int psp_dtm_terminate(struct psp_context *psp) 1650 { 1651 int ret; 1652 1653 /* 1654 * TODO: bypass the terminate in sriov for now 1655 */ 1656 if (amdgpu_sriov_vf(psp->adev)) 1657 return 0; 1658 1659 if (!psp->dtm_context.context.initialized) { 1660 if (psp->dtm_context.context.mem_context.shared_buf) 1661 goto out; 1662 else 1663 return 0; 1664 } 1665 1666 ret = psp_dtm_unload(psp); 1667 if (ret) 1668 return ret; 1669 1670 psp->dtm_context.context.initialized = false; 1671 1672 out: 1673 /* free dtm shared memory */ 1674 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 1675 1676 return 0; 1677 } 1678 // DTM end 1679 1680 // RAP start 1681 static int psp_rap_init_shared_buf(struct psp_context *psp) 1682 { 1683 return psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1684 } 1685 1686 static int psp_rap_load(struct psp_context *psp) 1687 { 1688 return psp_ta_load(psp, &psp->rap_context.context); 1689 } 1690 1691 static int psp_rap_unload(struct psp_context *psp) 1692 { 1693 return psp_ta_unload(psp, &psp->rap_context.context); 1694 } 1695 1696 static int psp_rap_initialize(struct psp_context *psp) 1697 { 1698 int ret; 1699 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1700 1701 /* 1702 * TODO: bypass the initialize in sriov for now 1703 */ 1704 if (amdgpu_sriov_vf(psp->adev)) 1705 return 0; 1706 1707 if (!psp->rap_context.context.bin_desc.size_bytes || 1708 !psp->rap_context.context.bin_desc.start_addr) { 1709 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1710 return 0; 1711 } 1712 1713 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1714 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1715 1716 if (!psp->rap_context.context.initialized) { 1717 ret = psp_rap_init_shared_buf(psp); 1718 if (ret) 1719 return ret; 1720 } 1721 1722 ret = psp_rap_load(psp); 1723 if (!ret) { 1724 psp->rap_context.context.initialized = true; 1725 mutex_init(&psp->rap_context.mutex); 1726 } else 1727 return ret; 1728 1729 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1730 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1731 psp_rap_terminate(psp); 1732 1733 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1734 ret, status); 1735 1736 return ret; 1737 } 1738 1739 return 0; 1740 } 1741 1742 static int psp_rap_terminate(struct psp_context *psp) 1743 { 1744 int ret; 1745 1746 if (!psp->rap_context.context.initialized) 1747 return 0; 1748 1749 ret = psp_rap_unload(psp); 1750 1751 psp->rap_context.context.initialized = false; 1752 1753 /* free rap shared memory */ 1754 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1755 1756 return ret; 1757 } 1758 1759 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1760 { 1761 struct ta_rap_shared_memory *rap_cmd; 1762 int ret = 0; 1763 1764 if (!psp->rap_context.context.initialized) 1765 return 0; 1766 1767 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1768 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1769 return -EINVAL; 1770 1771 mutex_lock(&psp->rap_context.mutex); 1772 1773 rap_cmd = (struct ta_rap_shared_memory *) 1774 psp->rap_context.context.mem_context.shared_buf; 1775 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1776 1777 rap_cmd->cmd_id = ta_cmd_id; 1778 rap_cmd->validation_method_id = METHOD_A; 1779 1780 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1781 if (ret) 1782 goto out_unlock; 1783 1784 if (status) 1785 *status = rap_cmd->rap_status; 1786 1787 out_unlock: 1788 mutex_unlock(&psp->rap_context.mutex); 1789 1790 return ret; 1791 } 1792 // RAP end 1793 1794 /* securedisplay start */ 1795 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1796 { 1797 return psp_ta_init_shared_buf( 1798 psp, &psp->securedisplay_context.context.mem_context); 1799 } 1800 1801 static int psp_securedisplay_load(struct psp_context *psp) 1802 { 1803 return psp_ta_load(psp, &psp->securedisplay_context.context); 1804 } 1805 1806 static int psp_securedisplay_unload(struct psp_context *psp) 1807 { 1808 return psp_ta_unload(psp, &psp->securedisplay_context.context); 1809 } 1810 1811 static int psp_securedisplay_initialize(struct psp_context *psp) 1812 { 1813 int ret; 1814 struct securedisplay_cmd *securedisplay_cmd; 1815 1816 /* 1817 * TODO: bypass the initialize in sriov for now 1818 */ 1819 if (amdgpu_sriov_vf(psp->adev)) 1820 return 0; 1821 1822 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1823 !psp->securedisplay_context.context.bin_desc.start_addr) { 1824 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1825 return 0; 1826 } 1827 1828 psp->securedisplay_context.context.mem_context.shared_mem_size = 1829 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1830 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1831 1832 if (!psp->securedisplay_context.context.initialized) { 1833 ret = psp_securedisplay_init_shared_buf(psp); 1834 if (ret) 1835 return ret; 1836 } 1837 1838 ret = psp_securedisplay_load(psp); 1839 if (!ret) { 1840 psp->securedisplay_context.context.initialized = true; 1841 mutex_init(&psp->securedisplay_context.mutex); 1842 } else 1843 return ret; 1844 1845 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1846 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1847 1848 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1849 if (ret) { 1850 psp_securedisplay_terminate(psp); 1851 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1852 return -EINVAL; 1853 } 1854 1855 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1856 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1857 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1858 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1859 } 1860 1861 return 0; 1862 } 1863 1864 static int psp_securedisplay_terminate(struct psp_context *psp) 1865 { 1866 int ret; 1867 1868 /* 1869 * TODO:bypass the terminate in sriov for now 1870 */ 1871 if (amdgpu_sriov_vf(psp->adev)) 1872 return 0; 1873 1874 if (!psp->securedisplay_context.context.initialized) 1875 return 0; 1876 1877 ret = psp_securedisplay_unload(psp); 1878 if (ret) 1879 return ret; 1880 1881 psp->securedisplay_context.context.initialized = false; 1882 1883 /* free securedisplay shared memory */ 1884 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1885 1886 return ret; 1887 } 1888 1889 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1890 { 1891 int ret; 1892 1893 if (!psp->securedisplay_context.context.initialized) 1894 return -EINVAL; 1895 1896 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1897 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1898 return -EINVAL; 1899 1900 mutex_lock(&psp->securedisplay_context.mutex); 1901 1902 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1903 1904 mutex_unlock(&psp->securedisplay_context.mutex); 1905 1906 return ret; 1907 } 1908 /* SECUREDISPLAY end */ 1909 1910 static int psp_hw_start(struct psp_context *psp) 1911 { 1912 struct amdgpu_device *adev = psp->adev; 1913 int ret; 1914 1915 if (!amdgpu_sriov_vf(adev)) { 1916 if ((is_psp_fw_valid(psp->kdb)) && 1917 (psp->funcs->bootloader_load_kdb != NULL)) { 1918 ret = psp_bootloader_load_kdb(psp); 1919 if (ret) { 1920 DRM_ERROR("PSP load kdb failed!\n"); 1921 return ret; 1922 } 1923 } 1924 1925 if ((is_psp_fw_valid(psp->spl)) && 1926 (psp->funcs->bootloader_load_spl != NULL)) { 1927 ret = psp_bootloader_load_spl(psp); 1928 if (ret) { 1929 DRM_ERROR("PSP load spl failed!\n"); 1930 return ret; 1931 } 1932 } 1933 1934 if ((is_psp_fw_valid(psp->sys)) && 1935 (psp->funcs->bootloader_load_sysdrv != NULL)) { 1936 ret = psp_bootloader_load_sysdrv(psp); 1937 if (ret) { 1938 DRM_ERROR("PSP load sys drv failed!\n"); 1939 return ret; 1940 } 1941 } 1942 1943 if ((is_psp_fw_valid(psp->soc_drv)) && 1944 (psp->funcs->bootloader_load_soc_drv != NULL)) { 1945 ret = psp_bootloader_load_soc_drv(psp); 1946 if (ret) { 1947 DRM_ERROR("PSP load soc drv failed!\n"); 1948 return ret; 1949 } 1950 } 1951 1952 if ((is_psp_fw_valid(psp->intf_drv)) && 1953 (psp->funcs->bootloader_load_intf_drv != NULL)) { 1954 ret = psp_bootloader_load_intf_drv(psp); 1955 if (ret) { 1956 DRM_ERROR("PSP load intf drv failed!\n"); 1957 return ret; 1958 } 1959 } 1960 1961 if ((is_psp_fw_valid(psp->dbg_drv)) && 1962 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 1963 ret = psp_bootloader_load_dbg_drv(psp); 1964 if (ret) { 1965 DRM_ERROR("PSP load dbg drv failed!\n"); 1966 return ret; 1967 } 1968 } 1969 1970 if ((is_psp_fw_valid(psp->sos)) && 1971 (psp->funcs->bootloader_load_sos != NULL)) { 1972 ret = psp_bootloader_load_sos(psp); 1973 if (ret) { 1974 DRM_ERROR("PSP load sos failed!\n"); 1975 return ret; 1976 } 1977 } 1978 } 1979 1980 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1981 if (ret) { 1982 DRM_ERROR("PSP create ring failed!\n"); 1983 return ret; 1984 } 1985 1986 ret = psp_tmr_init(psp); 1987 if (ret) { 1988 DRM_ERROR("PSP tmr init failed!\n"); 1989 return ret; 1990 } 1991 1992 /* 1993 * For ASICs with DF Cstate management centralized 1994 * to PMFW, TMR setup should be performed after PMFW 1995 * loaded and before other non-psp firmware loaded. 1996 */ 1997 if (psp->pmfw_centralized_cstate_management) { 1998 ret = psp_load_smu_fw(psp); 1999 if (ret) 2000 return ret; 2001 } 2002 2003 ret = psp_tmr_load(psp); 2004 if (ret) { 2005 DRM_ERROR("PSP load tmr failed!\n"); 2006 return ret; 2007 } 2008 2009 return 0; 2010 } 2011 2012 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2013 enum psp_gfx_fw_type *type) 2014 { 2015 switch (ucode->ucode_id) { 2016 case AMDGPU_UCODE_ID_SDMA0: 2017 *type = GFX_FW_TYPE_SDMA0; 2018 break; 2019 case AMDGPU_UCODE_ID_SDMA1: 2020 *type = GFX_FW_TYPE_SDMA1; 2021 break; 2022 case AMDGPU_UCODE_ID_SDMA2: 2023 *type = GFX_FW_TYPE_SDMA2; 2024 break; 2025 case AMDGPU_UCODE_ID_SDMA3: 2026 *type = GFX_FW_TYPE_SDMA3; 2027 break; 2028 case AMDGPU_UCODE_ID_SDMA4: 2029 *type = GFX_FW_TYPE_SDMA4; 2030 break; 2031 case AMDGPU_UCODE_ID_SDMA5: 2032 *type = GFX_FW_TYPE_SDMA5; 2033 break; 2034 case AMDGPU_UCODE_ID_SDMA6: 2035 *type = GFX_FW_TYPE_SDMA6; 2036 break; 2037 case AMDGPU_UCODE_ID_SDMA7: 2038 *type = GFX_FW_TYPE_SDMA7; 2039 break; 2040 case AMDGPU_UCODE_ID_CP_MES: 2041 *type = GFX_FW_TYPE_CP_MES; 2042 break; 2043 case AMDGPU_UCODE_ID_CP_MES_DATA: 2044 *type = GFX_FW_TYPE_MES_STACK; 2045 break; 2046 case AMDGPU_UCODE_ID_CP_CE: 2047 *type = GFX_FW_TYPE_CP_CE; 2048 break; 2049 case AMDGPU_UCODE_ID_CP_PFP: 2050 *type = GFX_FW_TYPE_CP_PFP; 2051 break; 2052 case AMDGPU_UCODE_ID_CP_ME: 2053 *type = GFX_FW_TYPE_CP_ME; 2054 break; 2055 case AMDGPU_UCODE_ID_CP_MEC1: 2056 *type = GFX_FW_TYPE_CP_MEC; 2057 break; 2058 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2059 *type = GFX_FW_TYPE_CP_MEC_ME1; 2060 break; 2061 case AMDGPU_UCODE_ID_CP_MEC2: 2062 *type = GFX_FW_TYPE_CP_MEC; 2063 break; 2064 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2065 *type = GFX_FW_TYPE_CP_MEC_ME2; 2066 break; 2067 case AMDGPU_UCODE_ID_RLC_G: 2068 *type = GFX_FW_TYPE_RLC_G; 2069 break; 2070 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2071 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2072 break; 2073 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2074 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2075 break; 2076 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2077 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2078 break; 2079 case AMDGPU_UCODE_ID_RLC_IRAM: 2080 *type = GFX_FW_TYPE_RLC_IRAM; 2081 break; 2082 case AMDGPU_UCODE_ID_RLC_DRAM: 2083 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2084 break; 2085 case AMDGPU_UCODE_ID_SMC: 2086 *type = GFX_FW_TYPE_SMU; 2087 break; 2088 case AMDGPU_UCODE_ID_UVD: 2089 *type = GFX_FW_TYPE_UVD; 2090 break; 2091 case AMDGPU_UCODE_ID_UVD1: 2092 *type = GFX_FW_TYPE_UVD1; 2093 break; 2094 case AMDGPU_UCODE_ID_VCE: 2095 *type = GFX_FW_TYPE_VCE; 2096 break; 2097 case AMDGPU_UCODE_ID_VCN: 2098 *type = GFX_FW_TYPE_VCN; 2099 break; 2100 case AMDGPU_UCODE_ID_VCN1: 2101 *type = GFX_FW_TYPE_VCN1; 2102 break; 2103 case AMDGPU_UCODE_ID_DMCU_ERAM: 2104 *type = GFX_FW_TYPE_DMCU_ERAM; 2105 break; 2106 case AMDGPU_UCODE_ID_DMCU_INTV: 2107 *type = GFX_FW_TYPE_DMCU_ISR; 2108 break; 2109 case AMDGPU_UCODE_ID_VCN0_RAM: 2110 *type = GFX_FW_TYPE_VCN0_RAM; 2111 break; 2112 case AMDGPU_UCODE_ID_VCN1_RAM: 2113 *type = GFX_FW_TYPE_VCN1_RAM; 2114 break; 2115 case AMDGPU_UCODE_ID_DMCUB: 2116 *type = GFX_FW_TYPE_DMUB; 2117 break; 2118 case AMDGPU_UCODE_ID_MAXIMUM: 2119 default: 2120 return -EINVAL; 2121 } 2122 2123 return 0; 2124 } 2125 2126 static void psp_print_fw_hdr(struct psp_context *psp, 2127 struct amdgpu_firmware_info *ucode) 2128 { 2129 struct amdgpu_device *adev = psp->adev; 2130 struct common_firmware_header *hdr; 2131 2132 switch (ucode->ucode_id) { 2133 case AMDGPU_UCODE_ID_SDMA0: 2134 case AMDGPU_UCODE_ID_SDMA1: 2135 case AMDGPU_UCODE_ID_SDMA2: 2136 case AMDGPU_UCODE_ID_SDMA3: 2137 case AMDGPU_UCODE_ID_SDMA4: 2138 case AMDGPU_UCODE_ID_SDMA5: 2139 case AMDGPU_UCODE_ID_SDMA6: 2140 case AMDGPU_UCODE_ID_SDMA7: 2141 hdr = (struct common_firmware_header *) 2142 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2143 amdgpu_ucode_print_sdma_hdr(hdr); 2144 break; 2145 case AMDGPU_UCODE_ID_CP_CE: 2146 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2147 amdgpu_ucode_print_gfx_hdr(hdr); 2148 break; 2149 case AMDGPU_UCODE_ID_CP_PFP: 2150 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2151 amdgpu_ucode_print_gfx_hdr(hdr); 2152 break; 2153 case AMDGPU_UCODE_ID_CP_ME: 2154 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2155 amdgpu_ucode_print_gfx_hdr(hdr); 2156 break; 2157 case AMDGPU_UCODE_ID_CP_MEC1: 2158 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2159 amdgpu_ucode_print_gfx_hdr(hdr); 2160 break; 2161 case AMDGPU_UCODE_ID_RLC_G: 2162 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2163 amdgpu_ucode_print_rlc_hdr(hdr); 2164 break; 2165 case AMDGPU_UCODE_ID_SMC: 2166 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2167 amdgpu_ucode_print_smc_hdr(hdr); 2168 break; 2169 default: 2170 break; 2171 } 2172 } 2173 2174 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2175 struct psp_gfx_cmd_resp *cmd) 2176 { 2177 int ret; 2178 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2179 2180 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2181 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2182 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2183 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2184 2185 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2186 if (ret) 2187 DRM_ERROR("Unknown firmware type\n"); 2188 2189 return ret; 2190 } 2191 2192 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2193 struct amdgpu_firmware_info *ucode) 2194 { 2195 int ret = 0; 2196 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2197 2198 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2199 if (!ret) { 2200 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2201 psp->fence_buf_mc_addr); 2202 } 2203 2204 release_psp_cmd_buf(psp); 2205 2206 return ret; 2207 } 2208 2209 static int psp_load_smu_fw(struct psp_context *psp) 2210 { 2211 int ret; 2212 struct amdgpu_device *adev = psp->adev; 2213 struct amdgpu_firmware_info *ucode = 2214 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2215 struct amdgpu_ras *ras = psp->ras_context.ras; 2216 2217 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2218 return 0; 2219 2220 if ((amdgpu_in_reset(adev) && 2221 ras && adev->ras_enabled && 2222 (adev->asic_type == CHIP_ARCTURUS || 2223 adev->asic_type == CHIP_VEGA20))) { 2224 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2225 if (ret) { 2226 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2227 } 2228 } 2229 2230 ret = psp_execute_non_psp_fw_load(psp, ucode); 2231 2232 if (ret) 2233 DRM_ERROR("PSP load smu failed!\n"); 2234 2235 return ret; 2236 } 2237 2238 static bool fw_load_skip_check(struct psp_context *psp, 2239 struct amdgpu_firmware_info *ucode) 2240 { 2241 if (!ucode->fw) 2242 return true; 2243 2244 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2245 (psp_smu_reload_quirk(psp) || 2246 psp->autoload_supported || 2247 psp->pmfw_centralized_cstate_management)) 2248 return true; 2249 2250 if (amdgpu_sriov_vf(psp->adev) && 2251 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2252 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2253 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2254 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2255 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2256 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2257 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2258 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2259 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2260 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2261 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2262 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2263 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2264 /*skip ucode loading in SRIOV VF */ 2265 return true; 2266 2267 if (psp->autoload_supported && 2268 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2269 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2270 /* skip mec JT when autoload is enabled */ 2271 return true; 2272 2273 return false; 2274 } 2275 2276 int psp_load_fw_list(struct psp_context *psp, 2277 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2278 { 2279 int ret = 0, i; 2280 struct amdgpu_firmware_info *ucode; 2281 2282 for (i = 0; i < ucode_count; ++i) { 2283 ucode = ucode_list[i]; 2284 psp_print_fw_hdr(psp, ucode); 2285 ret = psp_execute_non_psp_fw_load(psp, ucode); 2286 if (ret) 2287 return ret; 2288 } 2289 return ret; 2290 } 2291 2292 static int psp_load_non_psp_fw(struct psp_context *psp) 2293 { 2294 int i, ret; 2295 struct amdgpu_firmware_info *ucode; 2296 struct amdgpu_device *adev = psp->adev; 2297 2298 if (psp->autoload_supported && 2299 !psp->pmfw_centralized_cstate_management) { 2300 ret = psp_load_smu_fw(psp); 2301 if (ret) 2302 return ret; 2303 } 2304 2305 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2306 ucode = &adev->firmware.ucode[i]; 2307 2308 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2309 !fw_load_skip_check(psp, ucode)) { 2310 ret = psp_load_smu_fw(psp); 2311 if (ret) 2312 return ret; 2313 continue; 2314 } 2315 2316 if (fw_load_skip_check(psp, ucode)) 2317 continue; 2318 2319 if (psp->autoload_supported && 2320 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2321 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2322 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2323 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2324 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2325 /* PSP only receive one SDMA fw for sienna_cichlid, 2326 * as all four sdma fw are same */ 2327 continue; 2328 2329 psp_print_fw_hdr(psp, ucode); 2330 2331 ret = psp_execute_non_psp_fw_load(psp, ucode); 2332 if (ret) 2333 return ret; 2334 2335 /* Start rlc autoload after psp recieved all the gfx firmware */ 2336 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2337 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2338 ret = psp_rlc_autoload_start(psp); 2339 if (ret) { 2340 DRM_ERROR("Failed to start rlc autoload\n"); 2341 return ret; 2342 } 2343 } 2344 } 2345 2346 return 0; 2347 } 2348 2349 static int psp_load_fw(struct amdgpu_device *adev) 2350 { 2351 int ret; 2352 struct psp_context *psp = &adev->psp; 2353 2354 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2355 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2356 goto skip_memalloc; 2357 } 2358 2359 if (amdgpu_sriov_vf(adev)) { 2360 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2361 AMDGPU_GEM_DOMAIN_VRAM, 2362 &psp->fw_pri_bo, 2363 &psp->fw_pri_mc_addr, 2364 &psp->fw_pri_buf); 2365 } else { 2366 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2367 AMDGPU_GEM_DOMAIN_GTT, 2368 &psp->fw_pri_bo, 2369 &psp->fw_pri_mc_addr, 2370 &psp->fw_pri_buf); 2371 } 2372 2373 if (ret) 2374 goto failed; 2375 2376 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2377 AMDGPU_GEM_DOMAIN_VRAM, 2378 &psp->fence_buf_bo, 2379 &psp->fence_buf_mc_addr, 2380 &psp->fence_buf); 2381 if (ret) 2382 goto failed; 2383 2384 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2385 AMDGPU_GEM_DOMAIN_VRAM, 2386 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2387 (void **)&psp->cmd_buf_mem); 2388 if (ret) 2389 goto failed; 2390 2391 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2392 2393 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2394 if (ret) { 2395 DRM_ERROR("PSP ring init failed!\n"); 2396 goto failed; 2397 } 2398 2399 skip_memalloc: 2400 ret = psp_hw_start(psp); 2401 if (ret) 2402 goto failed; 2403 2404 ret = psp_load_non_psp_fw(psp); 2405 if (ret) 2406 goto failed; 2407 2408 ret = psp_asd_initialize(psp); 2409 if (ret) { 2410 DRM_ERROR("PSP load asd failed!\n"); 2411 return ret; 2412 } 2413 2414 ret = psp_rl_load(adev); 2415 if (ret) { 2416 DRM_ERROR("PSP load RL failed!\n"); 2417 return ret; 2418 } 2419 2420 if (psp->ta_fw) { 2421 ret = psp_ras_initialize(psp); 2422 if (ret) 2423 dev_err(psp->adev->dev, 2424 "RAS: Failed to initialize RAS\n"); 2425 2426 ret = psp_hdcp_initialize(psp); 2427 if (ret) 2428 dev_err(psp->adev->dev, 2429 "HDCP: Failed to initialize HDCP\n"); 2430 2431 ret = psp_dtm_initialize(psp); 2432 if (ret) 2433 dev_err(psp->adev->dev, 2434 "DTM: Failed to initialize DTM\n"); 2435 2436 ret = psp_rap_initialize(psp); 2437 if (ret) 2438 dev_err(psp->adev->dev, 2439 "RAP: Failed to initialize RAP\n"); 2440 2441 ret = psp_securedisplay_initialize(psp); 2442 if (ret) 2443 dev_err(psp->adev->dev, 2444 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2445 } 2446 2447 return 0; 2448 2449 failed: 2450 /* 2451 * all cleanup jobs (xgmi terminate, ras terminate, 2452 * ring destroy, cmd/fence/fw buffers destory, 2453 * psp->cmd destory) are delayed to psp_hw_fini 2454 */ 2455 return ret; 2456 } 2457 2458 static int psp_hw_init(void *handle) 2459 { 2460 int ret; 2461 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2462 2463 mutex_lock(&adev->firmware.mutex); 2464 /* 2465 * This sequence is just used on hw_init only once, no need on 2466 * resume. 2467 */ 2468 ret = amdgpu_ucode_init_bo(adev); 2469 if (ret) 2470 goto failed; 2471 2472 ret = psp_load_fw(adev); 2473 if (ret) { 2474 DRM_ERROR("PSP firmware loading failed\n"); 2475 goto failed; 2476 } 2477 2478 mutex_unlock(&adev->firmware.mutex); 2479 return 0; 2480 2481 failed: 2482 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2483 mutex_unlock(&adev->firmware.mutex); 2484 return -EINVAL; 2485 } 2486 2487 static int psp_hw_fini(void *handle) 2488 { 2489 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2490 struct psp_context *psp = &adev->psp; 2491 2492 if (psp->ta_fw) { 2493 psp_ras_terminate(psp); 2494 psp_securedisplay_terminate(psp); 2495 psp_rap_terminate(psp); 2496 psp_dtm_terminate(psp); 2497 psp_hdcp_terminate(psp); 2498 } 2499 2500 psp_asd_terminate(psp); 2501 2502 psp_tmr_terminate(psp); 2503 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2504 2505 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2506 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2507 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2508 &psp->fence_buf_mc_addr, &psp->fence_buf); 2509 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2510 (void **)&psp->cmd_buf_mem); 2511 2512 return 0; 2513 } 2514 2515 static int psp_suspend(void *handle) 2516 { 2517 int ret; 2518 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2519 struct psp_context *psp = &adev->psp; 2520 2521 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2522 psp->xgmi_context.context.initialized) { 2523 ret = psp_xgmi_terminate(psp); 2524 if (ret) { 2525 DRM_ERROR("Failed to terminate xgmi ta\n"); 2526 return ret; 2527 } 2528 } 2529 2530 if (psp->ta_fw) { 2531 ret = psp_ras_terminate(psp); 2532 if (ret) { 2533 DRM_ERROR("Failed to terminate ras ta\n"); 2534 return ret; 2535 } 2536 ret = psp_hdcp_terminate(psp); 2537 if (ret) { 2538 DRM_ERROR("Failed to terminate hdcp ta\n"); 2539 return ret; 2540 } 2541 ret = psp_dtm_terminate(psp); 2542 if (ret) { 2543 DRM_ERROR("Failed to terminate dtm ta\n"); 2544 return ret; 2545 } 2546 ret = psp_rap_terminate(psp); 2547 if (ret) { 2548 DRM_ERROR("Failed to terminate rap ta\n"); 2549 return ret; 2550 } 2551 ret = psp_securedisplay_terminate(psp); 2552 if (ret) { 2553 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2554 return ret; 2555 } 2556 } 2557 2558 ret = psp_asd_terminate(psp); 2559 if (ret) { 2560 DRM_ERROR("Failed to terminate asd\n"); 2561 return ret; 2562 } 2563 2564 ret = psp_tmr_terminate(psp); 2565 if (ret) { 2566 DRM_ERROR("Failed to terminate tmr\n"); 2567 return ret; 2568 } 2569 2570 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2571 if (ret) { 2572 DRM_ERROR("PSP ring stop failed\n"); 2573 return ret; 2574 } 2575 2576 return 0; 2577 } 2578 2579 static int psp_resume(void *handle) 2580 { 2581 int ret; 2582 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2583 struct psp_context *psp = &adev->psp; 2584 2585 DRM_INFO("PSP is resuming...\n"); 2586 2587 if (psp->mem_train_ctx.enable_mem_training) { 2588 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2589 if (ret) { 2590 DRM_ERROR("Failed to process memory training!\n"); 2591 return ret; 2592 } 2593 } 2594 2595 mutex_lock(&adev->firmware.mutex); 2596 2597 ret = psp_hw_start(psp); 2598 if (ret) 2599 goto failed; 2600 2601 ret = psp_load_non_psp_fw(psp); 2602 if (ret) 2603 goto failed; 2604 2605 ret = psp_asd_initialize(psp); 2606 if (ret) { 2607 DRM_ERROR("PSP load asd failed!\n"); 2608 goto failed; 2609 } 2610 2611 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2612 ret = psp_xgmi_initialize(psp, false, true); 2613 /* Warning the XGMI seesion initialize failure 2614 * Instead of stop driver initialization 2615 */ 2616 if (ret) 2617 dev_err(psp->adev->dev, 2618 "XGMI: Failed to initialize XGMI session\n"); 2619 } 2620 2621 if (psp->ta_fw) { 2622 ret = psp_ras_initialize(psp); 2623 if (ret) 2624 dev_err(psp->adev->dev, 2625 "RAS: Failed to initialize RAS\n"); 2626 2627 ret = psp_hdcp_initialize(psp); 2628 if (ret) 2629 dev_err(psp->adev->dev, 2630 "HDCP: Failed to initialize HDCP\n"); 2631 2632 ret = psp_dtm_initialize(psp); 2633 if (ret) 2634 dev_err(psp->adev->dev, 2635 "DTM: Failed to initialize DTM\n"); 2636 2637 ret = psp_rap_initialize(psp); 2638 if (ret) 2639 dev_err(psp->adev->dev, 2640 "RAP: Failed to initialize RAP\n"); 2641 2642 ret = psp_securedisplay_initialize(psp); 2643 if (ret) 2644 dev_err(psp->adev->dev, 2645 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2646 } 2647 2648 mutex_unlock(&adev->firmware.mutex); 2649 2650 return 0; 2651 2652 failed: 2653 DRM_ERROR("PSP resume failed\n"); 2654 mutex_unlock(&adev->firmware.mutex); 2655 return ret; 2656 } 2657 2658 int psp_gpu_reset(struct amdgpu_device *adev) 2659 { 2660 int ret; 2661 2662 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2663 return 0; 2664 2665 mutex_lock(&adev->psp.mutex); 2666 ret = psp_mode1_reset(&adev->psp); 2667 mutex_unlock(&adev->psp.mutex); 2668 2669 return ret; 2670 } 2671 2672 int psp_rlc_autoload_start(struct psp_context *psp) 2673 { 2674 int ret; 2675 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2676 2677 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2678 2679 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2680 psp->fence_buf_mc_addr); 2681 2682 release_psp_cmd_buf(psp); 2683 2684 return ret; 2685 } 2686 2687 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2688 uint64_t cmd_gpu_addr, int cmd_size) 2689 { 2690 struct amdgpu_firmware_info ucode = {0}; 2691 2692 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2693 AMDGPU_UCODE_ID_VCN0_RAM; 2694 ucode.mc_addr = cmd_gpu_addr; 2695 ucode.ucode_size = cmd_size; 2696 2697 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2698 } 2699 2700 int psp_ring_cmd_submit(struct psp_context *psp, 2701 uint64_t cmd_buf_mc_addr, 2702 uint64_t fence_mc_addr, 2703 int index) 2704 { 2705 unsigned int psp_write_ptr_reg = 0; 2706 struct psp_gfx_rb_frame *write_frame; 2707 struct psp_ring *ring = &psp->km_ring; 2708 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2709 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2710 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2711 struct amdgpu_device *adev = psp->adev; 2712 uint32_t ring_size_dw = ring->ring_size / 4; 2713 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2714 2715 /* KM (GPCOM) prepare write pointer */ 2716 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2717 2718 /* Update KM RB frame pointer to new frame */ 2719 /* write_frame ptr increments by size of rb_frame in bytes */ 2720 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2721 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2722 write_frame = ring_buffer_start; 2723 else 2724 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2725 /* Check invalid write_frame ptr address */ 2726 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2727 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2728 ring_buffer_start, ring_buffer_end, write_frame); 2729 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2730 return -EINVAL; 2731 } 2732 2733 /* Initialize KM RB frame */ 2734 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2735 2736 /* Update KM RB frame */ 2737 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2738 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2739 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2740 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2741 write_frame->fence_value = index; 2742 amdgpu_device_flush_hdp(adev, NULL); 2743 2744 /* Update the write Pointer in DWORDs */ 2745 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2746 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2747 return 0; 2748 } 2749 2750 int psp_init_asd_microcode(struct psp_context *psp, 2751 const char *chip_name) 2752 { 2753 struct amdgpu_device *adev = psp->adev; 2754 char fw_name[PSP_FW_NAME_LEN]; 2755 const struct psp_firmware_header_v1_0 *asd_hdr; 2756 int err = 0; 2757 2758 if (!chip_name) { 2759 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2760 return -EINVAL; 2761 } 2762 2763 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2764 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2765 if (err) 2766 goto out; 2767 2768 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2769 if (err) 2770 goto out; 2771 2772 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2773 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2774 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2775 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2776 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2777 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2778 return 0; 2779 out: 2780 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2781 release_firmware(adev->psp.asd_fw); 2782 adev->psp.asd_fw = NULL; 2783 return err; 2784 } 2785 2786 int psp_init_toc_microcode(struct psp_context *psp, 2787 const char *chip_name) 2788 { 2789 struct amdgpu_device *adev = psp->adev; 2790 char fw_name[PSP_FW_NAME_LEN]; 2791 const struct psp_firmware_header_v1_0 *toc_hdr; 2792 int err = 0; 2793 2794 if (!chip_name) { 2795 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2796 return -EINVAL; 2797 } 2798 2799 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2800 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2801 if (err) 2802 goto out; 2803 2804 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2805 if (err) 2806 goto out; 2807 2808 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2809 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2810 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2811 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2812 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2813 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2814 return 0; 2815 out: 2816 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2817 release_firmware(adev->psp.toc_fw); 2818 adev->psp.toc_fw = NULL; 2819 return err; 2820 } 2821 2822 static int parse_sos_bin_descriptor(struct psp_context *psp, 2823 const struct psp_fw_bin_desc *desc, 2824 const struct psp_firmware_header_v2_0 *sos_hdr) 2825 { 2826 uint8_t *ucode_start_addr = NULL; 2827 2828 if (!psp || !desc || !sos_hdr) 2829 return -EINVAL; 2830 2831 ucode_start_addr = (uint8_t *)sos_hdr + 2832 le32_to_cpu(desc->offset_bytes) + 2833 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2834 2835 switch (desc->fw_type) { 2836 case PSP_FW_TYPE_PSP_SOS: 2837 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2838 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2839 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2840 psp->sos.start_addr = ucode_start_addr; 2841 break; 2842 case PSP_FW_TYPE_PSP_SYS_DRV: 2843 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2844 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2845 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2846 psp->sys.start_addr = ucode_start_addr; 2847 break; 2848 case PSP_FW_TYPE_PSP_KDB: 2849 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2850 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2851 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2852 psp->kdb.start_addr = ucode_start_addr; 2853 break; 2854 case PSP_FW_TYPE_PSP_TOC: 2855 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2856 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2857 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 2858 psp->toc.start_addr = ucode_start_addr; 2859 break; 2860 case PSP_FW_TYPE_PSP_SPL: 2861 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 2862 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 2863 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 2864 psp->spl.start_addr = ucode_start_addr; 2865 break; 2866 case PSP_FW_TYPE_PSP_RL: 2867 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 2868 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 2869 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 2870 psp->rl.start_addr = ucode_start_addr; 2871 break; 2872 case PSP_FW_TYPE_PSP_SOC_DRV: 2873 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 2874 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 2875 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2876 psp->soc_drv.start_addr = ucode_start_addr; 2877 break; 2878 case PSP_FW_TYPE_PSP_INTF_DRV: 2879 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 2880 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 2881 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2882 psp->intf_drv.start_addr = ucode_start_addr; 2883 break; 2884 case PSP_FW_TYPE_PSP_DBG_DRV: 2885 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 2886 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 2887 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2888 psp->dbg_drv.start_addr = ucode_start_addr; 2889 break; 2890 default: 2891 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 2892 break; 2893 } 2894 2895 return 0; 2896 } 2897 2898 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 2899 { 2900 const struct psp_firmware_header_v1_0 *sos_hdr; 2901 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2902 uint8_t *ucode_array_start_addr; 2903 2904 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2905 ucode_array_start_addr = (uint8_t *)sos_hdr + 2906 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2907 2908 if (adev->gmc.xgmi.connected_to_cpu || (adev->asic_type != CHIP_ALDEBARAN)) { 2909 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 2910 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 2911 2912 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 2913 adev->psp.sys.start_addr = ucode_array_start_addr; 2914 2915 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 2916 adev->psp.sos.start_addr = ucode_array_start_addr + 2917 le32_to_cpu(sos_hdr->sos.offset_bytes); 2918 adev->psp.xgmi_context.supports_extended_data = false; 2919 } else { 2920 /* Load alternate PSP SOS FW */ 2921 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 2922 2923 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 2924 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 2925 2926 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 2927 adev->psp.sys.start_addr = ucode_array_start_addr + 2928 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 2929 2930 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 2931 adev->psp.sos.start_addr = ucode_array_start_addr + 2932 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 2933 adev->psp.xgmi_context.supports_extended_data = true; 2934 } 2935 2936 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 2937 dev_warn(adev->dev, "PSP SOS FW not available"); 2938 return -EINVAL; 2939 } 2940 2941 return 0; 2942 } 2943 2944 int psp_init_sos_microcode(struct psp_context *psp, 2945 const char *chip_name) 2946 { 2947 struct amdgpu_device *adev = psp->adev; 2948 char fw_name[PSP_FW_NAME_LEN]; 2949 const struct psp_firmware_header_v1_0 *sos_hdr; 2950 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 2951 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 2952 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2953 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 2954 int err = 0; 2955 uint8_t *ucode_array_start_addr; 2956 int fw_index = 0; 2957 2958 if (!chip_name) { 2959 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 2960 return -EINVAL; 2961 } 2962 2963 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 2964 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 2965 if (err) 2966 goto out; 2967 2968 err = amdgpu_ucode_validate(adev->psp.sos_fw); 2969 if (err) 2970 goto out; 2971 2972 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2973 ucode_array_start_addr = (uint8_t *)sos_hdr + 2974 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2975 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 2976 2977 switch (sos_hdr->header.header_version_major) { 2978 case 1: 2979 err = psp_init_sos_base_fw(adev); 2980 if (err) 2981 goto out; 2982 2983 if (sos_hdr->header.header_version_minor == 1) { 2984 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 2985 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 2986 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 2987 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 2988 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 2989 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 2990 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 2991 } 2992 if (sos_hdr->header.header_version_minor == 2) { 2993 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 2994 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 2995 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 2996 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 2997 } 2998 if (sos_hdr->header.header_version_minor == 3) { 2999 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3000 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3001 adev->psp.toc.start_addr = ucode_array_start_addr + 3002 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3003 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3004 adev->psp.kdb.start_addr = ucode_array_start_addr + 3005 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3006 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3007 adev->psp.spl.start_addr = ucode_array_start_addr + 3008 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3009 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3010 adev->psp.rl.start_addr = ucode_array_start_addr + 3011 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3012 } 3013 break; 3014 case 2: 3015 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3016 3017 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3018 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3019 err = -EINVAL; 3020 goto out; 3021 } 3022 3023 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3024 err = parse_sos_bin_descriptor(psp, 3025 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3026 sos_hdr_v2_0); 3027 if (err) 3028 goto out; 3029 } 3030 break; 3031 default: 3032 dev_err(adev->dev, 3033 "unsupported psp sos firmware\n"); 3034 err = -EINVAL; 3035 goto out; 3036 } 3037 3038 return 0; 3039 out: 3040 dev_err(adev->dev, 3041 "failed to init sos firmware\n"); 3042 release_firmware(adev->psp.sos_fw); 3043 adev->psp.sos_fw = NULL; 3044 3045 return err; 3046 } 3047 3048 static int parse_ta_bin_descriptor(struct psp_context *psp, 3049 const struct psp_fw_bin_desc *desc, 3050 const struct ta_firmware_header_v2_0 *ta_hdr) 3051 { 3052 uint8_t *ucode_start_addr = NULL; 3053 3054 if (!psp || !desc || !ta_hdr) 3055 return -EINVAL; 3056 3057 ucode_start_addr = (uint8_t *)ta_hdr + 3058 le32_to_cpu(desc->offset_bytes) + 3059 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3060 3061 switch (desc->fw_type) { 3062 case TA_FW_TYPE_PSP_ASD: 3063 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3064 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3065 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3066 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3067 break; 3068 case TA_FW_TYPE_PSP_XGMI: 3069 psp->xgmi_context.context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3070 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3071 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3072 break; 3073 case TA_FW_TYPE_PSP_RAS: 3074 psp->ras_context.context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3075 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3076 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3077 break; 3078 case TA_FW_TYPE_PSP_HDCP: 3079 psp->hdcp_context.context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3080 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3081 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3082 break; 3083 case TA_FW_TYPE_PSP_DTM: 3084 psp->dtm_context.context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3085 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3086 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3087 break; 3088 case TA_FW_TYPE_PSP_RAP: 3089 psp->rap_context.context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3090 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3091 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3092 break; 3093 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3094 psp->securedisplay_context.context.bin_desc.feature_version = 3095 le32_to_cpu(desc->fw_version); 3096 psp->securedisplay_context.context.bin_desc.size_bytes = 3097 le32_to_cpu(desc->size_bytes); 3098 psp->securedisplay_context.context.bin_desc.start_addr = 3099 ucode_start_addr; 3100 break; 3101 default: 3102 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3103 break; 3104 } 3105 3106 return 0; 3107 } 3108 3109 int psp_init_ta_microcode(struct psp_context *psp, 3110 const char *chip_name) 3111 { 3112 struct amdgpu_device *adev = psp->adev; 3113 char fw_name[PSP_FW_NAME_LEN]; 3114 const struct ta_firmware_header_v2_0 *ta_hdr; 3115 int err = 0; 3116 int ta_index = 0; 3117 3118 if (!chip_name) { 3119 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3120 return -EINVAL; 3121 } 3122 3123 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3124 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3125 if (err) 3126 goto out; 3127 3128 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3129 if (err) 3130 goto out; 3131 3132 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3133 3134 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3135 dev_err(adev->dev, "unsupported TA header version\n"); 3136 err = -EINVAL; 3137 goto out; 3138 } 3139 3140 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3141 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3142 err = -EINVAL; 3143 goto out; 3144 } 3145 3146 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3147 err = parse_ta_bin_descriptor(psp, 3148 &ta_hdr->ta_fw_bin[ta_index], 3149 ta_hdr); 3150 if (err) 3151 goto out; 3152 } 3153 3154 return 0; 3155 out: 3156 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3157 release_firmware(adev->psp.ta_fw); 3158 adev->psp.ta_fw = NULL; 3159 return err; 3160 } 3161 3162 static int psp_set_clockgating_state(void *handle, 3163 enum amd_clockgating_state state) 3164 { 3165 return 0; 3166 } 3167 3168 static int psp_set_powergating_state(void *handle, 3169 enum amd_powergating_state state) 3170 { 3171 return 0; 3172 } 3173 3174 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3175 struct device_attribute *attr, 3176 char *buf) 3177 { 3178 struct drm_device *ddev = dev_get_drvdata(dev); 3179 struct amdgpu_device *adev = drm_to_adev(ddev); 3180 uint32_t fw_ver; 3181 int ret; 3182 3183 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3184 DRM_INFO("PSP block is not ready yet."); 3185 return -EBUSY; 3186 } 3187 3188 mutex_lock(&adev->psp.mutex); 3189 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3190 mutex_unlock(&adev->psp.mutex); 3191 3192 if (ret) { 3193 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3194 return ret; 3195 } 3196 3197 return sysfs_emit(buf, "%x\n", fw_ver); 3198 } 3199 3200 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3201 struct device_attribute *attr, 3202 const char *buf, 3203 size_t count) 3204 { 3205 struct drm_device *ddev = dev_get_drvdata(dev); 3206 struct amdgpu_device *adev = drm_to_adev(ddev); 3207 int ret, idx; 3208 char fw_name[100]; 3209 const struct firmware *usbc_pd_fw; 3210 struct amdgpu_bo *fw_buf_bo = NULL; 3211 uint64_t fw_pri_mc_addr; 3212 void *fw_pri_cpu_addr; 3213 3214 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3215 DRM_INFO("PSP block is not ready yet."); 3216 return -EBUSY; 3217 } 3218 3219 if (!drm_dev_enter(ddev, &idx)) 3220 return -ENODEV; 3221 3222 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3223 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3224 if (ret) 3225 goto fail; 3226 3227 /* LFB address which is aligned to 1MB boundary per PSP request */ 3228 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3229 AMDGPU_GEM_DOMAIN_VRAM, 3230 &fw_buf_bo, 3231 &fw_pri_mc_addr, 3232 &fw_pri_cpu_addr); 3233 if (ret) 3234 goto rel_buf; 3235 3236 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3237 3238 mutex_lock(&adev->psp.mutex); 3239 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3240 mutex_unlock(&adev->psp.mutex); 3241 3242 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3243 3244 rel_buf: 3245 release_firmware(usbc_pd_fw); 3246 fail: 3247 if (ret) { 3248 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3249 count = ret; 3250 } 3251 3252 drm_dev_exit(idx); 3253 return count; 3254 } 3255 3256 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3257 { 3258 int idx; 3259 3260 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 3261 return; 3262 3263 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3264 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3265 3266 drm_dev_exit(idx); 3267 } 3268 3269 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3270 psp_usbc_pd_fw_sysfs_read, 3271 psp_usbc_pd_fw_sysfs_write); 3272 3273 int is_psp_fw_valid(struct psp_bin_desc bin) 3274 { 3275 return bin.size_bytes; 3276 } 3277 3278 const struct amd_ip_funcs psp_ip_funcs = { 3279 .name = "psp", 3280 .early_init = psp_early_init, 3281 .late_init = NULL, 3282 .sw_init = psp_sw_init, 3283 .sw_fini = psp_sw_fini, 3284 .hw_init = psp_hw_init, 3285 .hw_fini = psp_hw_fini, 3286 .suspend = psp_suspend, 3287 .resume = psp_resume, 3288 .is_idle = NULL, 3289 .check_soft_reset = NULL, 3290 .wait_for_idle = NULL, 3291 .soft_reset = NULL, 3292 .set_clockgating_state = psp_set_clockgating_state, 3293 .set_powergating_state = psp_set_powergating_state, 3294 }; 3295 3296 static int psp_sysfs_init(struct amdgpu_device *adev) 3297 { 3298 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3299 3300 if (ret) 3301 DRM_ERROR("Failed to create USBC PD FW control file!"); 3302 3303 return ret; 3304 } 3305 3306 static void psp_sysfs_fini(struct amdgpu_device *adev) 3307 { 3308 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3309 } 3310 3311 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3312 { 3313 .type = AMD_IP_BLOCK_TYPE_PSP, 3314 .major = 3, 3315 .minor = 1, 3316 .rev = 0, 3317 .funcs = &psp_ip_funcs, 3318 }; 3319 3320 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3321 { 3322 .type = AMD_IP_BLOCK_TYPE_PSP, 3323 .major = 10, 3324 .minor = 0, 3325 .rev = 0, 3326 .funcs = &psp_ip_funcs, 3327 }; 3328 3329 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3330 { 3331 .type = AMD_IP_BLOCK_TYPE_PSP, 3332 .major = 11, 3333 .minor = 0, 3334 .rev = 0, 3335 .funcs = &psp_ip_funcs, 3336 }; 3337 3338 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3339 .type = AMD_IP_BLOCK_TYPE_PSP, 3340 .major = 11, 3341 .minor = 0, 3342 .rev = 8, 3343 .funcs = &psp_ip_funcs, 3344 }; 3345 3346 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3347 { 3348 .type = AMD_IP_BLOCK_TYPE_PSP, 3349 .major = 12, 3350 .minor = 0, 3351 .rev = 0, 3352 .funcs = &psp_ip_funcs, 3353 }; 3354 3355 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3356 .type = AMD_IP_BLOCK_TYPE_PSP, 3357 .major = 13, 3358 .minor = 0, 3359 .rev = 0, 3360 .funcs = &psp_ip_funcs, 3361 }; 3362