1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 #include "psp_v10_0.h" 34 #include "psp_v11_0.h" 35 36 static void psp_set_funcs(struct amdgpu_device *adev); 37 38 static int psp_early_init(void *handle) 39 { 40 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 41 42 psp_set_funcs(adev); 43 44 return 0; 45 } 46 47 static int psp_sw_init(void *handle) 48 { 49 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 50 struct psp_context *psp = &adev->psp; 51 int ret; 52 53 switch (adev->asic_type) { 54 case CHIP_VEGA10: 55 case CHIP_VEGA12: 56 psp_v3_1_set_psp_funcs(psp); 57 break; 58 case CHIP_RAVEN: 59 psp_v10_0_set_psp_funcs(psp); 60 break; 61 case CHIP_VEGA20: 62 psp_v11_0_set_psp_funcs(psp); 63 break; 64 default: 65 return -EINVAL; 66 } 67 68 psp->adev = adev; 69 70 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 71 return 0; 72 73 ret = psp_init_microcode(psp); 74 if (ret) { 75 DRM_ERROR("Failed to load psp firmware!\n"); 76 return ret; 77 } 78 79 return 0; 80 } 81 82 static int psp_sw_fini(void *handle) 83 { 84 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 85 86 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 87 return 0; 88 89 release_firmware(adev->psp.sos_fw); 90 adev->psp.sos_fw = NULL; 91 release_firmware(adev->psp.asd_fw); 92 adev->psp.asd_fw = NULL; 93 release_firmware(adev->psp.ta_fw); 94 adev->psp.ta_fw = NULL; 95 return 0; 96 } 97 98 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 99 uint32_t reg_val, uint32_t mask, bool check_changed) 100 { 101 uint32_t val; 102 int i; 103 struct amdgpu_device *adev = psp->adev; 104 105 for (i = 0; i < adev->usec_timeout; i++) { 106 val = RREG32(reg_index); 107 if (check_changed) { 108 if (val != reg_val) 109 return 0; 110 } else { 111 if ((val & mask) == reg_val) 112 return 0; 113 } 114 udelay(1); 115 } 116 117 return -ETIME; 118 } 119 120 static int 121 psp_cmd_submit_buf(struct psp_context *psp, 122 struct amdgpu_firmware_info *ucode, 123 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 124 { 125 int ret; 126 int index; 127 128 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 129 130 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 131 132 index = atomic_inc_return(&psp->fence_value); 133 ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr, 134 fence_mc_addr, index); 135 if (ret) { 136 atomic_dec(&psp->fence_value); 137 return ret; 138 } 139 140 while (*((unsigned int *)psp->fence_buf) != index) 141 msleep(1); 142 143 /* the status field must be 0 after FW is loaded */ 144 if (ucode && psp->cmd_buf_mem->resp.status) { 145 DRM_ERROR("failed loading with status (%d) and ucode id (%d)\n", 146 psp->cmd_buf_mem->resp.status, ucode->ucode_id); 147 return -EINVAL; 148 } 149 150 if (ucode) { 151 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 152 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 153 } 154 155 return ret; 156 } 157 158 static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd, 159 uint64_t tmr_mc, uint32_t size) 160 { 161 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 162 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 163 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 164 cmd->cmd.cmd_setup_tmr.buf_size = size; 165 } 166 167 /* Set up Trusted Memory Region */ 168 static int psp_tmr_init(struct psp_context *psp) 169 { 170 int ret; 171 172 /* 173 * Allocate 3M memory aligned to 1M from Frame Buffer (local 174 * physical). 175 * 176 * Note: this memory need be reserved till the driver 177 * uninitializes. 178 */ 179 ret = amdgpu_bo_create_kernel(psp->adev, PSP_TMR_SIZE, 0x100000, 180 AMDGPU_GEM_DOMAIN_VRAM, 181 &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 182 183 return ret; 184 } 185 186 static int psp_tmr_load(struct psp_context *psp) 187 { 188 int ret; 189 struct psp_gfx_cmd_resp *cmd; 190 191 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 192 if (!cmd) 193 return -ENOMEM; 194 195 psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, PSP_TMR_SIZE); 196 DRM_INFO("reserve 0x%x from 0x%llx for PSP TMR SIZE\n", 197 PSP_TMR_SIZE, psp->tmr_mc_addr); 198 199 ret = psp_cmd_submit_buf(psp, NULL, cmd, 200 psp->fence_buf_mc_addr); 201 if (ret) 202 goto failed; 203 204 kfree(cmd); 205 206 return 0; 207 208 failed: 209 kfree(cmd); 210 return ret; 211 } 212 213 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd, 214 uint64_t asd_mc, uint64_t asd_mc_shared, 215 uint32_t size, uint32_t shared_size) 216 { 217 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 218 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 219 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 220 cmd->cmd.cmd_load_ta.app_len = size; 221 222 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared); 223 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared); 224 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 225 } 226 227 static int psp_asd_init(struct psp_context *psp) 228 { 229 int ret; 230 231 /* 232 * Allocate 16k memory aligned to 4k from Frame Buffer (local 233 * physical) for shared ASD <-> Driver 234 */ 235 ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE, 236 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 237 &psp->asd_shared_bo, 238 &psp->asd_shared_mc_addr, 239 &psp->asd_shared_buf); 240 241 return ret; 242 } 243 244 static int psp_asd_load(struct psp_context *psp) 245 { 246 int ret; 247 struct psp_gfx_cmd_resp *cmd; 248 249 /* If PSP version doesn't match ASD version, asd loading will be failed. 250 * add workaround to bypass it for sriov now. 251 * TODO: add version check to make it common 252 */ 253 if (amdgpu_sriov_vf(psp->adev)) 254 return 0; 255 256 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 257 if (!cmd) 258 return -ENOMEM; 259 260 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 261 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 262 263 psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr, 264 psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE); 265 266 ret = psp_cmd_submit_buf(psp, NULL, cmd, 267 psp->fence_buf_mc_addr); 268 269 kfree(cmd); 270 271 return ret; 272 } 273 274 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 275 uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared, 276 uint32_t xgmi_ta_size, uint32_t shared_size) 277 { 278 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 279 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc); 280 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc); 281 cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size; 282 283 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared); 284 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared); 285 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 286 } 287 288 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 289 { 290 int ret; 291 292 /* 293 * Allocate 16k memory aligned to 4k from Frame Buffer (local 294 * physical) for xgmi ta <-> Driver 295 */ 296 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 297 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 298 &psp->xgmi_context.xgmi_shared_bo, 299 &psp->xgmi_context.xgmi_shared_mc_addr, 300 &psp->xgmi_context.xgmi_shared_buf); 301 302 return ret; 303 } 304 305 static int psp_xgmi_load(struct psp_context *psp) 306 { 307 int ret; 308 struct psp_gfx_cmd_resp *cmd; 309 310 /* 311 * TODO: bypass the loading in sriov for now 312 */ 313 if (amdgpu_sriov_vf(psp->adev)) 314 return 0; 315 316 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 317 if (!cmd) 318 return -ENOMEM; 319 320 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 321 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 322 323 psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 324 psp->xgmi_context.xgmi_shared_mc_addr, 325 psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE); 326 327 ret = psp_cmd_submit_buf(psp, NULL, cmd, 328 psp->fence_buf_mc_addr); 329 330 if (!ret) { 331 psp->xgmi_context.initialized = 1; 332 psp->xgmi_context.session_id = cmd->resp.session_id; 333 } 334 335 kfree(cmd); 336 337 return ret; 338 } 339 340 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 341 uint32_t xgmi_session_id) 342 { 343 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 344 cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id; 345 } 346 347 static int psp_xgmi_unload(struct psp_context *psp) 348 { 349 int ret; 350 struct psp_gfx_cmd_resp *cmd; 351 352 /* 353 * TODO: bypass the unloading in sriov for now 354 */ 355 if (amdgpu_sriov_vf(psp->adev)) 356 return 0; 357 358 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 359 if (!cmd) 360 return -ENOMEM; 361 362 psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 363 364 ret = psp_cmd_submit_buf(psp, NULL, cmd, 365 psp->fence_buf_mc_addr); 366 367 kfree(cmd); 368 369 return ret; 370 } 371 372 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 373 uint32_t ta_cmd_id, 374 uint32_t xgmi_session_id) 375 { 376 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 377 cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id; 378 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 379 /* Note: cmd_invoke_cmd.buf is not used for now */ 380 } 381 382 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 383 { 384 int ret; 385 struct psp_gfx_cmd_resp *cmd; 386 387 /* 388 * TODO: bypass the loading in sriov for now 389 */ 390 if (amdgpu_sriov_vf(psp->adev)) 391 return 0; 392 393 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 394 if (!cmd) 395 return -ENOMEM; 396 397 psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id, 398 psp->xgmi_context.session_id); 399 400 ret = psp_cmd_submit_buf(psp, NULL, cmd, 401 psp->fence_buf_mc_addr); 402 403 kfree(cmd); 404 405 return ret; 406 } 407 408 static int psp_xgmi_terminate(struct psp_context *psp) 409 { 410 int ret; 411 412 if (!psp->xgmi_context.initialized) 413 return 0; 414 415 ret = psp_xgmi_unload(psp); 416 if (ret) 417 return ret; 418 419 psp->xgmi_context.initialized = 0; 420 421 /* free xgmi shared memory */ 422 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 423 &psp->xgmi_context.xgmi_shared_mc_addr, 424 &psp->xgmi_context.xgmi_shared_buf); 425 426 return 0; 427 } 428 429 static int psp_xgmi_initialize(struct psp_context *psp) 430 { 431 struct ta_xgmi_shared_memory *xgmi_cmd; 432 int ret; 433 434 if (!psp->xgmi_context.initialized) { 435 ret = psp_xgmi_init_shared_buf(psp); 436 if (ret) 437 return ret; 438 } 439 440 /* Load XGMI TA */ 441 ret = psp_xgmi_load(psp); 442 if (ret) 443 return ret; 444 445 /* Initialize XGMI session */ 446 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 447 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 448 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 449 450 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 451 452 return ret; 453 } 454 455 static int psp_hw_start(struct psp_context *psp) 456 { 457 struct amdgpu_device *adev = psp->adev; 458 int ret; 459 460 if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) { 461 ret = psp_bootloader_load_sysdrv(psp); 462 if (ret) 463 return ret; 464 465 ret = psp_bootloader_load_sos(psp); 466 if (ret) 467 return ret; 468 } 469 470 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 471 if (ret) 472 return ret; 473 474 ret = psp_tmr_load(psp); 475 if (ret) 476 return ret; 477 478 ret = psp_asd_load(psp); 479 if (ret) 480 return ret; 481 482 if (adev->gmc.xgmi.num_physical_nodes > 1) { 483 ret = psp_xgmi_initialize(psp); 484 /* Warning the XGMI seesion initialize failure 485 * Instead of stop driver initialization 486 */ 487 if (ret) 488 dev_err(psp->adev->dev, 489 "XGMI: Failed to initialize XGMI session\n"); 490 } 491 return 0; 492 } 493 494 static int psp_np_fw_load(struct psp_context *psp) 495 { 496 int i, ret; 497 struct amdgpu_firmware_info *ucode; 498 struct amdgpu_device* adev = psp->adev; 499 500 for (i = 0; i < adev->firmware.max_ucodes; i++) { 501 ucode = &adev->firmware.ucode[i]; 502 if (!ucode->fw) 503 continue; 504 505 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 506 psp_smu_reload_quirk(psp)) 507 continue; 508 if (amdgpu_sriov_vf(adev) && 509 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 510 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 511 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) 512 /*skip ucode loading in SRIOV VF */ 513 continue; 514 515 ret = psp_prep_cmd_buf(ucode, psp->cmd); 516 if (ret) 517 return ret; 518 519 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 520 psp->fence_buf_mc_addr); 521 if (ret) 522 return ret; 523 524 #if 0 525 /* check if firmware loaded sucessfully */ 526 if (!amdgpu_psp_check_fw_loading_status(adev, i)) 527 return -EINVAL; 528 #endif 529 } 530 531 return 0; 532 } 533 534 static int psp_load_fw(struct amdgpu_device *adev) 535 { 536 int ret; 537 struct psp_context *psp = &adev->psp; 538 539 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset != 0) 540 goto skip_memalloc; 541 542 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 543 if (!psp->cmd) 544 return -ENOMEM; 545 546 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 547 AMDGPU_GEM_DOMAIN_GTT, 548 &psp->fw_pri_bo, 549 &psp->fw_pri_mc_addr, 550 &psp->fw_pri_buf); 551 if (ret) 552 goto failed; 553 554 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 555 AMDGPU_GEM_DOMAIN_VRAM, 556 &psp->fence_buf_bo, 557 &psp->fence_buf_mc_addr, 558 &psp->fence_buf); 559 if (ret) 560 goto failed_mem2; 561 562 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 563 AMDGPU_GEM_DOMAIN_VRAM, 564 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 565 (void **)&psp->cmd_buf_mem); 566 if (ret) 567 goto failed_mem1; 568 569 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 570 571 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 572 if (ret) 573 goto failed_mem; 574 575 ret = psp_tmr_init(psp); 576 if (ret) 577 goto failed_mem; 578 579 ret = psp_asd_init(psp); 580 if (ret) 581 goto failed_mem; 582 583 skip_memalloc: 584 ret = psp_hw_start(psp); 585 if (ret) 586 goto failed_mem; 587 588 ret = psp_np_fw_load(psp); 589 if (ret) 590 goto failed_mem; 591 592 return 0; 593 594 failed_mem: 595 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, 596 &psp->cmd_buf_mc_addr, 597 (void **)&psp->cmd_buf_mem); 598 failed_mem1: 599 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 600 &psp->fence_buf_mc_addr, &psp->fence_buf); 601 failed_mem2: 602 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 603 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 604 failed: 605 kfree(psp->cmd); 606 psp->cmd = NULL; 607 return ret; 608 } 609 610 static int psp_hw_init(void *handle) 611 { 612 int ret; 613 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 614 615 616 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 617 return 0; 618 619 mutex_lock(&adev->firmware.mutex); 620 /* 621 * This sequence is just used on hw_init only once, no need on 622 * resume. 623 */ 624 ret = amdgpu_ucode_init_bo(adev); 625 if (ret) 626 goto failed; 627 628 ret = psp_load_fw(adev); 629 if (ret) { 630 DRM_ERROR("PSP firmware loading failed\n"); 631 goto failed; 632 } 633 634 mutex_unlock(&adev->firmware.mutex); 635 return 0; 636 637 failed: 638 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 639 mutex_unlock(&adev->firmware.mutex); 640 return -EINVAL; 641 } 642 643 static int psp_hw_fini(void *handle) 644 { 645 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 646 struct psp_context *psp = &adev->psp; 647 648 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 649 return 0; 650 651 if (adev->gmc.xgmi.num_physical_nodes > 1 && 652 psp->xgmi_context.initialized == 1) 653 psp_xgmi_terminate(psp); 654 655 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 656 657 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 658 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 659 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 660 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 661 &psp->fence_buf_mc_addr, &psp->fence_buf); 662 amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr, 663 &psp->asd_shared_buf); 664 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 665 (void **)&psp->cmd_buf_mem); 666 667 kfree(psp->cmd); 668 psp->cmd = NULL; 669 670 return 0; 671 } 672 673 static int psp_suspend(void *handle) 674 { 675 int ret; 676 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 677 struct psp_context *psp = &adev->psp; 678 679 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 680 return 0; 681 682 if (adev->gmc.xgmi.num_physical_nodes > 1 && 683 psp->xgmi_context.initialized == 1) { 684 ret = psp_xgmi_terminate(psp); 685 if (ret) { 686 DRM_ERROR("Failed to terminate xgmi ta\n"); 687 return ret; 688 } 689 } 690 691 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 692 if (ret) { 693 DRM_ERROR("PSP ring stop failed\n"); 694 return ret; 695 } 696 697 return 0; 698 } 699 700 static int psp_resume(void *handle) 701 { 702 int ret; 703 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 704 struct psp_context *psp = &adev->psp; 705 706 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 707 return 0; 708 709 DRM_INFO("PSP is resuming...\n"); 710 711 mutex_lock(&adev->firmware.mutex); 712 713 ret = psp_hw_start(psp); 714 if (ret) 715 goto failed; 716 717 ret = psp_np_fw_load(psp); 718 if (ret) 719 goto failed; 720 721 mutex_unlock(&adev->firmware.mutex); 722 723 return 0; 724 725 failed: 726 DRM_ERROR("PSP resume failed\n"); 727 mutex_unlock(&adev->firmware.mutex); 728 return ret; 729 } 730 731 int psp_gpu_reset(struct amdgpu_device *adev) 732 { 733 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 734 return 0; 735 736 return psp_mode1_reset(&adev->psp); 737 } 738 739 static bool psp_check_fw_loading_status(struct amdgpu_device *adev, 740 enum AMDGPU_UCODE_ID ucode_type) 741 { 742 struct amdgpu_firmware_info *ucode = NULL; 743 744 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 745 DRM_INFO("firmware is not loaded by PSP\n"); 746 return true; 747 } 748 749 if (!adev->firmware.fw_size) 750 return false; 751 752 ucode = &adev->firmware.ucode[ucode_type]; 753 if (!ucode->fw || !ucode->ucode_size) 754 return false; 755 756 return psp_compare_sram_data(&adev->psp, ucode, ucode_type); 757 } 758 759 static int psp_set_clockgating_state(void *handle, 760 enum amd_clockgating_state state) 761 { 762 return 0; 763 } 764 765 static int psp_set_powergating_state(void *handle, 766 enum amd_powergating_state state) 767 { 768 return 0; 769 } 770 771 const struct amd_ip_funcs psp_ip_funcs = { 772 .name = "psp", 773 .early_init = psp_early_init, 774 .late_init = NULL, 775 .sw_init = psp_sw_init, 776 .sw_fini = psp_sw_fini, 777 .hw_init = psp_hw_init, 778 .hw_fini = psp_hw_fini, 779 .suspend = psp_suspend, 780 .resume = psp_resume, 781 .is_idle = NULL, 782 .check_soft_reset = NULL, 783 .wait_for_idle = NULL, 784 .soft_reset = NULL, 785 .set_clockgating_state = psp_set_clockgating_state, 786 .set_powergating_state = psp_set_powergating_state, 787 }; 788 789 static const struct amdgpu_psp_funcs psp_funcs = { 790 .check_fw_loading_status = psp_check_fw_loading_status, 791 }; 792 793 static void psp_set_funcs(struct amdgpu_device *adev) 794 { 795 if (NULL == adev->firmware.funcs) 796 adev->firmware.funcs = &psp_funcs; 797 } 798 799 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 800 { 801 .type = AMD_IP_BLOCK_TYPE_PSP, 802 .major = 3, 803 .minor = 1, 804 .rev = 0, 805 .funcs = &psp_ip_funcs, 806 }; 807 808 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 809 { 810 .type = AMD_IP_BLOCK_TYPE_PSP, 811 .major = 10, 812 .minor = 0, 813 .rev = 0, 814 .funcs = &psp_ip_funcs, 815 }; 816 817 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 818 { 819 .type = AMD_IP_BLOCK_TYPE_PSP, 820 .major = 11, 821 .minor = 0, 822 .rev = 0, 823 .funcs = &psp_ip_funcs, 824 }; 825