1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 41 #include "amdgpu_ras.h" 42 #include "amdgpu_securedisplay.h" 43 #include "amdgpu_atomfirmware.h" 44 45 static int psp_sysfs_init(struct amdgpu_device *adev); 46 static void psp_sysfs_fini(struct amdgpu_device *adev); 47 48 static int psp_load_smu_fw(struct psp_context *psp); 49 static int psp_ta_unload(struct psp_context *psp, struct ta_context *context); 50 static int psp_ta_load(struct psp_context *psp, struct ta_context *context); 51 static int psp_rap_terminate(struct psp_context *psp); 52 static int psp_securedisplay_terminate(struct psp_context *psp); 53 54 /* 55 * Due to DF Cstate management centralized to PMFW, the firmware 56 * loading sequence will be updated as below: 57 * - Load KDB 58 * - Load SYS_DRV 59 * - Load tOS 60 * - Load PMFW 61 * - Setup TMR 62 * - Load other non-psp fw 63 * - Load ASD 64 * - Load XGMI/RAS/HDCP/DTM TA if any 65 * 66 * This new sequence is required for 67 * - Arcturus and onwards 68 * - Navi12 and onwards 69 */ 70 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 71 { 72 struct amdgpu_device *adev = psp->adev; 73 74 if (amdgpu_sriov_vf(adev)) { 75 psp->pmfw_centralized_cstate_management = false; 76 return; 77 } 78 79 switch (adev->ip_versions[MP0_HWIP][0]) { 80 case IP_VERSION(11, 0, 4): 81 case IP_VERSION(11, 0, 7): 82 case IP_VERSION(11, 0, 9): 83 case IP_VERSION(11, 0, 11): 84 case IP_VERSION(11, 0, 12): 85 case IP_VERSION(11, 0, 13): 86 case IP_VERSION(13, 0, 2): 87 psp->pmfw_centralized_cstate_management = true; 88 break; 89 default: 90 psp->pmfw_centralized_cstate_management = false; 91 break; 92 } 93 } 94 95 static int psp_early_init(void *handle) 96 { 97 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 98 struct psp_context *psp = &adev->psp; 99 100 switch (adev->ip_versions[MP0_HWIP][0]) { 101 case IP_VERSION(9, 0, 0): 102 psp_v3_1_set_psp_funcs(psp); 103 psp->autoload_supported = false; 104 break; 105 case IP_VERSION(10, 0, 0): 106 case IP_VERSION(10, 0, 1): 107 psp_v10_0_set_psp_funcs(psp); 108 psp->autoload_supported = false; 109 break; 110 case IP_VERSION(11, 0, 2): 111 case IP_VERSION(11, 0, 4): 112 psp_v11_0_set_psp_funcs(psp); 113 psp->autoload_supported = false; 114 break; 115 case IP_VERSION(11, 0, 0): 116 case IP_VERSION(11, 0, 5): 117 case IP_VERSION(11, 0, 9): 118 case IP_VERSION(11, 0, 7): 119 case IP_VERSION(11, 0, 11): 120 case IP_VERSION(11, 5, 0): 121 case IP_VERSION(11, 0, 12): 122 case IP_VERSION(11, 0, 13): 123 psp_v11_0_set_psp_funcs(psp); 124 psp->autoload_supported = true; 125 break; 126 case IP_VERSION(11, 0, 3): 127 case IP_VERSION(12, 0, 1): 128 psp_v12_0_set_psp_funcs(psp); 129 break; 130 case IP_VERSION(13, 0, 2): 131 psp_v13_0_set_psp_funcs(psp); 132 break; 133 case IP_VERSION(13, 0, 1): 134 case IP_VERSION(13, 0, 3): 135 psp_v13_0_set_psp_funcs(psp); 136 psp->autoload_supported = true; 137 break; 138 case IP_VERSION(11, 0, 8): 139 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 140 psp_v11_0_8_set_psp_funcs(psp); 141 psp->autoload_supported = false; 142 } 143 break; 144 default: 145 return -EINVAL; 146 } 147 148 psp->adev = adev; 149 150 psp_check_pmfw_centralized_cstate_management(psp); 151 152 return 0; 153 } 154 155 static void psp_memory_training_fini(struct psp_context *psp) 156 { 157 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 158 159 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 160 kfree(ctx->sys_cache); 161 ctx->sys_cache = NULL; 162 } 163 164 static int psp_memory_training_init(struct psp_context *psp) 165 { 166 int ret; 167 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 168 169 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 170 DRM_DEBUG("memory training is not supported!\n"); 171 return 0; 172 } 173 174 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 175 if (ctx->sys_cache == NULL) { 176 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 177 ret = -ENOMEM; 178 goto Err_out; 179 } 180 181 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 182 ctx->train_data_size, 183 ctx->p2c_train_data_offset, 184 ctx->c2p_train_data_offset); 185 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 186 return 0; 187 188 Err_out: 189 psp_memory_training_fini(psp); 190 return ret; 191 } 192 193 /* 194 * Helper funciton to query psp runtime database entry 195 * 196 * @adev: amdgpu_device pointer 197 * @entry_type: the type of psp runtime database entry 198 * @db_entry: runtime database entry pointer 199 * 200 * Return false if runtime database doesn't exit or entry is invalid 201 * or true if the specific database entry is found, and copy to @db_entry 202 */ 203 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 204 enum psp_runtime_entry_type entry_type, 205 void *db_entry) 206 { 207 uint64_t db_header_pos, db_dir_pos; 208 struct psp_runtime_data_header db_header = {0}; 209 struct psp_runtime_data_directory db_dir = {0}; 210 bool ret = false; 211 int i; 212 213 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 214 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 215 216 /* read runtime db header from vram */ 217 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 218 sizeof(struct psp_runtime_data_header), false); 219 220 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 221 /* runtime db doesn't exist, exit */ 222 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 223 return false; 224 } 225 226 /* read runtime database entry from vram */ 227 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 228 sizeof(struct psp_runtime_data_directory), false); 229 230 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 231 /* invalid db entry count, exit */ 232 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 233 return false; 234 } 235 236 /* look up for requested entry type */ 237 for (i = 0; i < db_dir.entry_count && !ret; i++) { 238 if (db_dir.entry_list[i].entry_type == entry_type) { 239 switch (entry_type) { 240 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 241 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 242 /* invalid db entry size */ 243 dev_warn(adev->dev, "Invalid PSP runtime database entry size\n"); 244 return false; 245 } 246 /* read runtime database entry */ 247 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 248 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 249 ret = true; 250 break; 251 default: 252 ret = false; 253 break; 254 } 255 } 256 } 257 258 return ret; 259 } 260 261 static int psp_sw_init(void *handle) 262 { 263 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 264 struct psp_context *psp = &adev->psp; 265 int ret; 266 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 267 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 268 269 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 270 if (!psp->cmd) { 271 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 272 ret = -ENOMEM; 273 } 274 275 if (!amdgpu_sriov_vf(adev)) { 276 ret = psp_init_microcode(psp); 277 if (ret) { 278 DRM_ERROR("Failed to load psp firmware!\n"); 279 return ret; 280 } 281 } else if (amdgpu_sriov_vf(adev) && 282 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2)) { 283 ret = psp_init_ta_microcode(psp, "aldebaran"); 284 if (ret) { 285 DRM_ERROR("Failed to initialize ta microcode!\n"); 286 return ret; 287 } 288 } 289 290 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 291 if (psp_get_runtime_db_entry(adev, 292 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 293 &boot_cfg_entry)) { 294 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 295 if ((psp->boot_cfg_bitmask) & 296 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 297 /* If psp runtime database exists, then 298 * only enable two stage memory training 299 * when TWO_STAGE_DRAM_TRAINING bit is set 300 * in runtime database */ 301 mem_training_ctx->enable_mem_training = true; 302 } 303 304 } else { 305 /* If psp runtime database doesn't exist or 306 * is invalid, force enable two stage memory 307 * training */ 308 mem_training_ctx->enable_mem_training = true; 309 } 310 311 if (mem_training_ctx->enable_mem_training) { 312 ret = psp_memory_training_init(psp); 313 if (ret) { 314 DRM_ERROR("Failed to initialize memory training!\n"); 315 return ret; 316 } 317 318 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 319 if (ret) { 320 DRM_ERROR("Failed to process memory training!\n"); 321 return ret; 322 } 323 } 324 325 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 326 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 327 ret= psp_sysfs_init(adev); 328 if (ret) { 329 return ret; 330 } 331 } 332 333 return 0; 334 } 335 336 static int psp_sw_fini(void *handle) 337 { 338 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 339 struct psp_context *psp = &adev->psp; 340 struct psp_gfx_cmd_resp *cmd = psp->cmd; 341 342 psp_memory_training_fini(psp); 343 if (psp->sos_fw) { 344 release_firmware(psp->sos_fw); 345 psp->sos_fw = NULL; 346 } 347 if (psp->asd_fw) { 348 release_firmware(psp->asd_fw); 349 psp->asd_fw = NULL; 350 } 351 if (psp->ta_fw) { 352 release_firmware(psp->ta_fw); 353 psp->ta_fw = NULL; 354 } 355 356 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 357 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 358 psp_sysfs_fini(adev); 359 360 kfree(cmd); 361 cmd = NULL; 362 363 return 0; 364 } 365 366 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 367 uint32_t reg_val, uint32_t mask, bool check_changed) 368 { 369 uint32_t val; 370 int i; 371 struct amdgpu_device *adev = psp->adev; 372 373 if (psp->adev->no_hw_access) 374 return 0; 375 376 for (i = 0; i < adev->usec_timeout; i++) { 377 val = RREG32(reg_index); 378 if (check_changed) { 379 if (val != reg_val) 380 return 0; 381 } else { 382 if ((val & mask) == reg_val) 383 return 0; 384 } 385 udelay(1); 386 } 387 388 return -ETIME; 389 } 390 391 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 392 { 393 switch (cmd_id) { 394 case GFX_CMD_ID_LOAD_TA: 395 return "LOAD_TA"; 396 case GFX_CMD_ID_UNLOAD_TA: 397 return "UNLOAD_TA"; 398 case GFX_CMD_ID_INVOKE_CMD: 399 return "INVOKE_CMD"; 400 case GFX_CMD_ID_LOAD_ASD: 401 return "LOAD_ASD"; 402 case GFX_CMD_ID_SETUP_TMR: 403 return "SETUP_TMR"; 404 case GFX_CMD_ID_LOAD_IP_FW: 405 return "LOAD_IP_FW"; 406 case GFX_CMD_ID_DESTROY_TMR: 407 return "DESTROY_TMR"; 408 case GFX_CMD_ID_SAVE_RESTORE: 409 return "SAVE_RESTORE_IP_FW"; 410 case GFX_CMD_ID_SETUP_VMR: 411 return "SETUP_VMR"; 412 case GFX_CMD_ID_DESTROY_VMR: 413 return "DESTROY_VMR"; 414 case GFX_CMD_ID_PROG_REG: 415 return "PROG_REG"; 416 case GFX_CMD_ID_GET_FW_ATTESTATION: 417 return "GET_FW_ATTESTATION"; 418 case GFX_CMD_ID_LOAD_TOC: 419 return "ID_LOAD_TOC"; 420 case GFX_CMD_ID_AUTOLOAD_RLC: 421 return "AUTOLOAD_RLC"; 422 case GFX_CMD_ID_BOOT_CFG: 423 return "BOOT_CFG"; 424 default: 425 return "UNKNOWN CMD"; 426 } 427 } 428 429 static int 430 psp_cmd_submit_buf(struct psp_context *psp, 431 struct amdgpu_firmware_info *ucode, 432 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 433 { 434 int ret; 435 int index, idx; 436 int timeout = 20000; 437 bool ras_intr = false; 438 bool skip_unsupport = false; 439 440 if (psp->adev->no_hw_access) 441 return 0; 442 443 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 444 return 0; 445 446 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 447 448 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 449 450 index = atomic_inc_return(&psp->fence_value); 451 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 452 if (ret) { 453 atomic_dec(&psp->fence_value); 454 goto exit; 455 } 456 457 amdgpu_device_invalidate_hdp(psp->adev, NULL); 458 while (*((unsigned int *)psp->fence_buf) != index) { 459 if (--timeout == 0) 460 break; 461 /* 462 * Shouldn't wait for timeout when err_event_athub occurs, 463 * because gpu reset thread triggered and lock resource should 464 * be released for psp resume sequence. 465 */ 466 ras_intr = amdgpu_ras_intr_triggered(); 467 if (ras_intr) 468 break; 469 usleep_range(10, 100); 470 amdgpu_device_invalidate_hdp(psp->adev, NULL); 471 } 472 473 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 474 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 475 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 476 477 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 478 479 /* In some cases, psp response status is not 0 even there is no 480 * problem while the command is submitted. Some version of PSP FW 481 * doesn't write 0 to that field. 482 * So here we would like to only print a warning instead of an error 483 * during psp initialization to avoid breaking hw_init and it doesn't 484 * return -EINVAL. 485 */ 486 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 487 if (ucode) 488 DRM_WARN("failed to load ucode %s(0x%X) ", 489 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 490 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 491 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 492 psp->cmd_buf_mem->resp.status); 493 if (!timeout) { 494 ret = -EINVAL; 495 goto exit; 496 } 497 } 498 499 if (ucode) { 500 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 501 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 502 } 503 504 exit: 505 drm_dev_exit(idx); 506 return ret; 507 } 508 509 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 510 { 511 struct psp_gfx_cmd_resp *cmd = psp->cmd; 512 513 mutex_lock(&psp->mutex); 514 515 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 516 517 return cmd; 518 } 519 520 void release_psp_cmd_buf(struct psp_context *psp) 521 { 522 mutex_unlock(&psp->mutex); 523 } 524 525 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 526 struct psp_gfx_cmd_resp *cmd, 527 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 528 { 529 struct amdgpu_device *adev = psp->adev; 530 uint32_t size = amdgpu_bo_size(tmr_bo); 531 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 532 533 if (amdgpu_sriov_vf(psp->adev)) 534 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 535 else 536 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 537 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 538 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 539 cmd->cmd.cmd_setup_tmr.buf_size = size; 540 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 541 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 542 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 543 } 544 545 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 546 uint64_t pri_buf_mc, uint32_t size) 547 { 548 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 549 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 550 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 551 cmd->cmd.cmd_load_toc.toc_size = size; 552 } 553 554 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 555 static int psp_load_toc(struct psp_context *psp, 556 uint32_t *tmr_size) 557 { 558 int ret; 559 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 560 561 /* Copy toc to psp firmware private buffer */ 562 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 563 564 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 565 566 ret = psp_cmd_submit_buf(psp, NULL, cmd, 567 psp->fence_buf_mc_addr); 568 if (!ret) 569 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 570 571 release_psp_cmd_buf(psp); 572 573 return ret; 574 } 575 576 /* Set up Trusted Memory Region */ 577 static int psp_tmr_init(struct psp_context *psp) 578 { 579 int ret; 580 int tmr_size; 581 void *tmr_buf; 582 void **pptr; 583 584 /* 585 * According to HW engineer, they prefer the TMR address be "naturally 586 * aligned" , e.g. the start address be an integer divide of TMR size. 587 * 588 * Note: this memory need be reserved till the driver 589 * uninitializes. 590 */ 591 tmr_size = PSP_TMR_SIZE(psp->adev); 592 593 /* For ASICs support RLC autoload, psp will parse the toc 594 * and calculate the total size of TMR needed */ 595 if (!amdgpu_sriov_vf(psp->adev) && 596 psp->toc.start_addr && 597 psp->toc.size_bytes && 598 psp->fw_pri_buf) { 599 ret = psp_load_toc(psp, &tmr_size); 600 if (ret) { 601 DRM_ERROR("Failed to load toc\n"); 602 return ret; 603 } 604 } 605 606 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 607 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 608 AMDGPU_GEM_DOMAIN_VRAM, 609 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 610 611 return ret; 612 } 613 614 static bool psp_skip_tmr(struct psp_context *psp) 615 { 616 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 617 case IP_VERSION(11, 0, 9): 618 case IP_VERSION(11, 0, 7): 619 case IP_VERSION(13, 0, 2): 620 return true; 621 default: 622 return false; 623 } 624 } 625 626 static int psp_tmr_load(struct psp_context *psp) 627 { 628 int ret; 629 struct psp_gfx_cmd_resp *cmd; 630 631 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 632 * Already set up by host driver. 633 */ 634 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 635 return 0; 636 637 cmd = acquire_psp_cmd_buf(psp); 638 639 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 640 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 641 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 642 643 ret = psp_cmd_submit_buf(psp, NULL, cmd, 644 psp->fence_buf_mc_addr); 645 646 release_psp_cmd_buf(psp); 647 648 return ret; 649 } 650 651 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 652 struct psp_gfx_cmd_resp *cmd) 653 { 654 if (amdgpu_sriov_vf(psp->adev)) 655 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 656 else 657 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 658 } 659 660 static int psp_tmr_unload(struct psp_context *psp) 661 { 662 int ret; 663 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 664 665 psp_prep_tmr_unload_cmd_buf(psp, cmd); 666 DRM_INFO("free PSP TMR buffer\n"); 667 668 ret = psp_cmd_submit_buf(psp, NULL, cmd, 669 psp->fence_buf_mc_addr); 670 671 release_psp_cmd_buf(psp); 672 673 return ret; 674 } 675 676 static int psp_tmr_terminate(struct psp_context *psp) 677 { 678 int ret; 679 void *tmr_buf; 680 void **pptr; 681 682 ret = psp_tmr_unload(psp); 683 if (ret) 684 return ret; 685 686 /* free TMR memory buffer */ 687 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 688 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 689 690 return 0; 691 } 692 693 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 694 uint64_t *output_ptr) 695 { 696 int ret; 697 struct psp_gfx_cmd_resp *cmd; 698 699 if (!output_ptr) 700 return -EINVAL; 701 702 if (amdgpu_sriov_vf(psp->adev)) 703 return 0; 704 705 cmd = acquire_psp_cmd_buf(psp); 706 707 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 708 709 ret = psp_cmd_submit_buf(psp, NULL, cmd, 710 psp->fence_buf_mc_addr); 711 712 if (!ret) { 713 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 714 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 715 } 716 717 release_psp_cmd_buf(psp); 718 719 return ret; 720 } 721 722 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 723 { 724 struct psp_context *psp = &adev->psp; 725 struct psp_gfx_cmd_resp *cmd; 726 int ret; 727 728 if (amdgpu_sriov_vf(adev)) 729 return 0; 730 731 cmd = acquire_psp_cmd_buf(psp); 732 733 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 734 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 735 736 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 737 if (!ret) { 738 *boot_cfg = 739 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 740 } 741 742 release_psp_cmd_buf(psp); 743 744 return ret; 745 } 746 747 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 748 { 749 int ret; 750 struct psp_context *psp = &adev->psp; 751 struct psp_gfx_cmd_resp *cmd; 752 753 if (amdgpu_sriov_vf(adev)) 754 return 0; 755 756 cmd = acquire_psp_cmd_buf(psp); 757 758 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 759 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 760 cmd->cmd.boot_cfg.boot_config = boot_cfg; 761 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 762 763 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 764 765 release_psp_cmd_buf(psp); 766 767 return ret; 768 } 769 770 static int psp_rl_load(struct amdgpu_device *adev) 771 { 772 int ret; 773 struct psp_context *psp = &adev->psp; 774 struct psp_gfx_cmd_resp *cmd; 775 776 if (!is_psp_fw_valid(psp->rl)) 777 return 0; 778 779 cmd = acquire_psp_cmd_buf(psp); 780 781 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 782 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 783 784 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 785 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 786 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 787 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 788 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 789 790 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 791 792 release_psp_cmd_buf(psp); 793 794 return ret; 795 } 796 797 static int psp_asd_load(struct psp_context *psp) 798 { 799 return psp_ta_load(psp, &psp->asd_context); 800 } 801 802 static int psp_asd_initialize(struct psp_context *psp) 803 { 804 int ret; 805 806 /* If PSP version doesn't match ASD version, asd loading will be failed. 807 * add workaround to bypass it for sriov now. 808 * TODO: add version check to make it common 809 */ 810 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 811 return 0; 812 813 psp->asd_context.mem_context.shared_mc_addr = 0; 814 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 815 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 816 817 ret = psp_asd_load(psp); 818 if (!ret) 819 psp->asd_context.initialized = true; 820 821 return ret; 822 } 823 824 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 825 uint32_t session_id) 826 { 827 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 828 cmd->cmd.cmd_unload_ta.session_id = session_id; 829 } 830 831 static int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 832 { 833 int ret; 834 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 835 836 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 837 838 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 839 840 release_psp_cmd_buf(psp); 841 842 return ret; 843 } 844 845 static int psp_asd_unload(struct psp_context *psp) 846 { 847 return psp_ta_unload(psp, &psp->asd_context); 848 } 849 850 static int psp_asd_terminate(struct psp_context *psp) 851 { 852 int ret; 853 854 if (amdgpu_sriov_vf(psp->adev)) 855 return 0; 856 857 if (!psp->asd_context.initialized) 858 return 0; 859 860 ret = psp_asd_unload(psp); 861 862 if (!ret) 863 psp->asd_context.initialized = false; 864 865 return ret; 866 } 867 868 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 869 uint32_t id, uint32_t value) 870 { 871 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 872 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 873 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 874 } 875 876 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 877 uint32_t value) 878 { 879 struct psp_gfx_cmd_resp *cmd; 880 int ret = 0; 881 882 if (reg >= PSP_REG_LAST) 883 return -EINVAL; 884 885 cmd = acquire_psp_cmd_buf(psp); 886 887 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 888 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 889 if (ret) 890 DRM_ERROR("PSP failed to program reg id %d", reg); 891 892 release_psp_cmd_buf(psp); 893 894 return ret; 895 } 896 897 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 898 uint64_t ta_bin_mc, 899 struct ta_context *context) 900 { 901 cmd->cmd_id = context->ta_load_type; 902 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 903 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 904 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 905 906 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 907 lower_32_bits(context->mem_context.shared_mc_addr); 908 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 909 upper_32_bits(context->mem_context.shared_mc_addr); 910 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 911 } 912 913 static int psp_ta_init_shared_buf(struct psp_context *psp, 914 struct ta_mem_context *mem_ctx) 915 { 916 int ret; 917 918 /* 919 * Allocate 16k memory aligned to 4k from Frame Buffer (local 920 * physical) for ta to host memory 921 */ 922 ret = amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 923 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 924 &mem_ctx->shared_bo, 925 &mem_ctx->shared_mc_addr, 926 &mem_ctx->shared_buf); 927 928 return ret; 929 } 930 931 static void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 932 { 933 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 934 &mem_ctx->shared_buf); 935 } 936 937 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 938 { 939 return psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 940 } 941 942 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 943 uint32_t ta_cmd_id, 944 uint32_t session_id) 945 { 946 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 947 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 948 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 949 } 950 951 static int psp_ta_invoke(struct psp_context *psp, 952 uint32_t ta_cmd_id, 953 struct ta_context *context) 954 { 955 int ret; 956 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 957 958 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 959 960 ret = psp_cmd_submit_buf(psp, NULL, cmd, 961 psp->fence_buf_mc_addr); 962 963 release_psp_cmd_buf(psp); 964 965 return ret; 966 } 967 968 static int psp_ta_load(struct psp_context *psp, struct ta_context *context) 969 { 970 int ret; 971 struct psp_gfx_cmd_resp *cmd; 972 973 cmd = acquire_psp_cmd_buf(psp); 974 975 psp_copy_fw(psp, context->bin_desc.start_addr, 976 context->bin_desc.size_bytes); 977 978 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 979 980 ret = psp_cmd_submit_buf(psp, NULL, cmd, 981 psp->fence_buf_mc_addr); 982 983 if (!ret) { 984 context->session_id = cmd->resp.session_id; 985 } 986 987 release_psp_cmd_buf(psp); 988 989 return ret; 990 } 991 992 static int psp_xgmi_load(struct psp_context *psp) 993 { 994 return psp_ta_load(psp, &psp->xgmi_context.context); 995 } 996 997 static int psp_xgmi_unload(struct psp_context *psp) 998 { 999 return psp_ta_unload(psp, &psp->xgmi_context.context); 1000 } 1001 1002 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1003 { 1004 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1005 } 1006 1007 int psp_xgmi_terminate(struct psp_context *psp) 1008 { 1009 int ret; 1010 struct amdgpu_device *adev = psp->adev; 1011 1012 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1013 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1014 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1015 adev->gmc.xgmi.connected_to_cpu)) 1016 return 0; 1017 1018 if (!psp->xgmi_context.context.initialized) 1019 return 0; 1020 1021 ret = psp_xgmi_unload(psp); 1022 if (ret) 1023 return ret; 1024 1025 psp->xgmi_context.context.initialized = false; 1026 1027 /* free xgmi shared memory */ 1028 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 1029 1030 return 0; 1031 } 1032 1033 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1034 { 1035 struct ta_xgmi_shared_memory *xgmi_cmd; 1036 int ret; 1037 1038 if (!psp->ta_fw || 1039 !psp->xgmi_context.context.bin_desc.size_bytes || 1040 !psp->xgmi_context.context.bin_desc.start_addr) 1041 return -ENOENT; 1042 1043 if (!load_ta) 1044 goto invoke; 1045 1046 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1047 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1048 1049 if (!psp->xgmi_context.context.initialized) { 1050 ret = psp_xgmi_init_shared_buf(psp); 1051 if (ret) 1052 return ret; 1053 } 1054 1055 /* Load XGMI TA */ 1056 ret = psp_xgmi_load(psp); 1057 if (!ret) 1058 psp->xgmi_context.context.initialized = true; 1059 else 1060 return ret; 1061 1062 invoke: 1063 /* Initialize XGMI session */ 1064 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1065 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1066 xgmi_cmd->flag_extend_link_record = set_extended_data; 1067 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1068 1069 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1070 1071 return ret; 1072 } 1073 1074 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1075 { 1076 struct ta_xgmi_shared_memory *xgmi_cmd; 1077 int ret; 1078 1079 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1080 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1081 1082 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1083 1084 /* Invoke xgmi ta to get hive id */ 1085 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1086 if (ret) 1087 return ret; 1088 1089 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1090 1091 return 0; 1092 } 1093 1094 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1095 { 1096 struct ta_xgmi_shared_memory *xgmi_cmd; 1097 int ret; 1098 1099 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1100 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1101 1102 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1103 1104 /* Invoke xgmi ta to get the node id */ 1105 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1106 if (ret) 1107 return ret; 1108 1109 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1110 1111 return 0; 1112 } 1113 1114 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1115 { 1116 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1117 psp->xgmi_context.context.bin_desc.feature_version >= 0x2000000b; 1118 } 1119 1120 /* 1121 * Chips that support extended topology information require the driver to 1122 * reflect topology information in the opposite direction. This is 1123 * because the TA has already exceeded its link record limit and if the 1124 * TA holds bi-directional information, the driver would have to do 1125 * multiple fetches instead of just two. 1126 */ 1127 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1128 struct psp_xgmi_node_info node_info) 1129 { 1130 struct amdgpu_device *mirror_adev; 1131 struct amdgpu_hive_info *hive; 1132 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1133 uint64_t dst_node_id = node_info.node_id; 1134 uint8_t dst_num_hops = node_info.num_hops; 1135 uint8_t dst_num_links = node_info.num_links; 1136 1137 hive = amdgpu_get_xgmi_hive(psp->adev); 1138 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1139 struct psp_xgmi_topology_info *mirror_top_info; 1140 int j; 1141 1142 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1143 continue; 1144 1145 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1146 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1147 if (mirror_top_info->nodes[j].node_id != src_node_id) 1148 continue; 1149 1150 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1151 /* 1152 * prevent 0 num_links value re-reflection since reflection 1153 * criteria is based on num_hops (direct or indirect). 1154 * 1155 */ 1156 if (dst_num_links) 1157 mirror_top_info->nodes[j].num_links = dst_num_links; 1158 1159 break; 1160 } 1161 1162 break; 1163 } 1164 } 1165 1166 int psp_xgmi_get_topology_info(struct psp_context *psp, 1167 int number_devices, 1168 struct psp_xgmi_topology_info *topology, 1169 bool get_extended_data) 1170 { 1171 struct ta_xgmi_shared_memory *xgmi_cmd; 1172 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1173 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1174 int i; 1175 int ret; 1176 1177 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1178 return -EINVAL; 1179 1180 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1181 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1182 xgmi_cmd->flag_extend_link_record = get_extended_data; 1183 1184 /* Fill in the shared memory with topology information as input */ 1185 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1186 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1187 topology_info_input->num_nodes = number_devices; 1188 1189 for (i = 0; i < topology_info_input->num_nodes; i++) { 1190 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1191 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1192 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1193 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1194 } 1195 1196 /* Invoke xgmi ta to get the topology information */ 1197 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1198 if (ret) 1199 return ret; 1200 1201 /* Read the output topology information from the shared memory */ 1202 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1203 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1204 for (i = 0; i < topology->num_nodes; i++) { 1205 /* extended data will either be 0 or equal to non-extended data */ 1206 if (topology_info_output->nodes[i].num_hops) 1207 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1208 1209 /* non-extended data gets everything here so no need to update */ 1210 if (!get_extended_data) { 1211 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1212 topology->nodes[i].is_sharing_enabled = 1213 topology_info_output->nodes[i].is_sharing_enabled; 1214 topology->nodes[i].sdma_engine = 1215 topology_info_output->nodes[i].sdma_engine; 1216 } 1217 1218 } 1219 1220 /* Invoke xgmi ta again to get the link information */ 1221 if (psp_xgmi_peer_link_info_supported(psp)) { 1222 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1223 1224 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1225 1226 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1227 1228 if (ret) 1229 return ret; 1230 1231 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1232 for (i = 0; i < topology->num_nodes; i++) { 1233 /* accumulate num_links on extended data */ 1234 topology->nodes[i].num_links = get_extended_data ? 1235 topology->nodes[i].num_links + 1236 link_info_output->nodes[i].num_links : 1237 link_info_output->nodes[i].num_links; 1238 1239 /* reflect the topology information for bi-directionality */ 1240 if (psp->xgmi_context.supports_extended_data && 1241 get_extended_data && topology->nodes[i].num_hops) 1242 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1243 } 1244 } 1245 1246 return 0; 1247 } 1248 1249 int psp_xgmi_set_topology_info(struct psp_context *psp, 1250 int number_devices, 1251 struct psp_xgmi_topology_info *topology) 1252 { 1253 struct ta_xgmi_shared_memory *xgmi_cmd; 1254 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1255 int i; 1256 1257 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1258 return -EINVAL; 1259 1260 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1261 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1262 1263 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1264 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1265 topology_info_input->num_nodes = number_devices; 1266 1267 for (i = 0; i < topology_info_input->num_nodes; i++) { 1268 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1269 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1270 topology_info_input->nodes[i].is_sharing_enabled = 1; 1271 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1272 } 1273 1274 /* Invoke xgmi ta to set topology information */ 1275 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1276 } 1277 1278 // ras begin 1279 static int psp_ras_init_shared_buf(struct psp_context *psp) 1280 { 1281 return psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1282 } 1283 1284 static int psp_ras_load(struct psp_context *psp) 1285 { 1286 return psp_ta_load(psp, &psp->ras_context.context); 1287 } 1288 1289 static int psp_ras_unload(struct psp_context *psp) 1290 { 1291 return psp_ta_unload(psp, &psp->ras_context.context); 1292 } 1293 1294 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1295 { 1296 struct ta_ras_shared_memory *ras_cmd; 1297 int ret; 1298 1299 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1300 1301 /* 1302 * TODO: bypass the loading in sriov for now 1303 */ 1304 if (amdgpu_sriov_vf(psp->adev)) 1305 return 0; 1306 1307 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1308 1309 if (amdgpu_ras_intr_triggered()) 1310 return ret; 1311 1312 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1313 { 1314 DRM_WARN("RAS: Unsupported Interface"); 1315 return -EINVAL; 1316 } 1317 1318 if (!ret) { 1319 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1320 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1321 1322 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1323 } 1324 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1325 dev_warn(psp->adev->dev, 1326 "RAS internal register access blocked\n"); 1327 1328 if (ras_cmd->ras_status == TA_RAS_STATUS__ERROR_UNSUPPORTED_IP) 1329 dev_warn(psp->adev->dev, "RAS WARNING: cmd failed due to unsupported ip\n"); 1330 else if (ras_cmd->ras_status) 1331 dev_warn(psp->adev->dev, "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1332 } 1333 1334 return ret; 1335 } 1336 1337 int psp_ras_enable_features(struct psp_context *psp, 1338 union ta_ras_cmd_input *info, bool enable) 1339 { 1340 struct ta_ras_shared_memory *ras_cmd; 1341 int ret; 1342 1343 if (!psp->ras_context.context.initialized) 1344 return -EINVAL; 1345 1346 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1347 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1348 1349 if (enable) 1350 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1351 else 1352 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1353 1354 ras_cmd->ras_in_message = *info; 1355 1356 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1357 if (ret) 1358 return -EINVAL; 1359 1360 return 0; 1361 } 1362 1363 static int psp_ras_terminate(struct psp_context *psp) 1364 { 1365 int ret; 1366 1367 /* 1368 * TODO: bypass the terminate in sriov for now 1369 */ 1370 if (amdgpu_sriov_vf(psp->adev)) 1371 return 0; 1372 1373 if (!psp->ras_context.context.initialized) 1374 return 0; 1375 1376 ret = psp_ras_unload(psp); 1377 if (ret) 1378 return ret; 1379 1380 psp->ras_context.context.initialized = false; 1381 1382 /* free ras shared memory */ 1383 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 1384 1385 return 0; 1386 } 1387 1388 static int psp_ras_initialize(struct psp_context *psp) 1389 { 1390 int ret; 1391 uint32_t boot_cfg = 0xFF; 1392 struct amdgpu_device *adev = psp->adev; 1393 struct ta_ras_shared_memory *ras_cmd; 1394 1395 /* 1396 * TODO: bypass the initialize in sriov for now 1397 */ 1398 if (amdgpu_sriov_vf(adev)) 1399 return 0; 1400 1401 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1402 !adev->psp.ras_context.context.bin_desc.start_addr) { 1403 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1404 return 0; 1405 } 1406 1407 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1408 /* query GECC enablement status from boot config 1409 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1410 */ 1411 ret = psp_boot_config_get(adev, &boot_cfg); 1412 if (ret) 1413 dev_warn(adev->dev, "PSP get boot config failed\n"); 1414 1415 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1416 if (!boot_cfg) { 1417 dev_info(adev->dev, "GECC is disabled\n"); 1418 } else { 1419 /* disable GECC in next boot cycle if ras is 1420 * disabled by module parameter amdgpu_ras_enable 1421 * and/or amdgpu_ras_mask, or boot_config_get call 1422 * is failed 1423 */ 1424 ret = psp_boot_config_set(adev, 0); 1425 if (ret) 1426 dev_warn(adev->dev, "PSP set boot config failed\n"); 1427 else 1428 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1429 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1430 } 1431 } else { 1432 if (1 == boot_cfg) { 1433 dev_info(adev->dev, "GECC is enabled\n"); 1434 } else { 1435 /* enable GECC in next boot cycle if it is disabled 1436 * in boot config, or force enable GECC if failed to 1437 * get boot configuration 1438 */ 1439 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1440 if (ret) 1441 dev_warn(adev->dev, "PSP set boot config failed\n"); 1442 else 1443 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1444 } 1445 } 1446 } 1447 1448 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1449 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1450 1451 if (!psp->ras_context.context.initialized) { 1452 ret = psp_ras_init_shared_buf(psp); 1453 if (ret) 1454 return ret; 1455 } 1456 1457 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1458 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1459 1460 if (amdgpu_ras_is_poison_mode_supported(adev)) 1461 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1462 if (!adev->gmc.xgmi.connected_to_cpu) 1463 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1464 1465 ret = psp_ras_load(psp); 1466 1467 if (!ret && !ras_cmd->ras_status) 1468 psp->ras_context.context.initialized = true; 1469 else { 1470 if (ras_cmd->ras_status) 1471 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1472 amdgpu_ras_fini(psp->adev); 1473 } 1474 1475 return ret; 1476 } 1477 1478 int psp_ras_trigger_error(struct psp_context *psp, 1479 struct ta_ras_trigger_error_input *info) 1480 { 1481 struct ta_ras_shared_memory *ras_cmd; 1482 int ret; 1483 1484 if (!psp->ras_context.context.initialized) 1485 return -EINVAL; 1486 1487 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1488 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1489 1490 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1491 ras_cmd->ras_in_message.trigger_error = *info; 1492 1493 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1494 if (ret) 1495 return -EINVAL; 1496 1497 /* If err_event_athub occurs error inject was successful, however 1498 return status from TA is no long reliable */ 1499 if (amdgpu_ras_intr_triggered()) 1500 return 0; 1501 1502 if (ras_cmd->ras_status) 1503 return -EINVAL; 1504 1505 return 0; 1506 } 1507 // ras end 1508 1509 // HDCP start 1510 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1511 { 1512 return psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1513 } 1514 1515 static int psp_hdcp_load(struct psp_context *psp) 1516 { 1517 return psp_ta_load(psp, &psp->hdcp_context.context); 1518 } 1519 1520 static int psp_hdcp_initialize(struct psp_context *psp) 1521 { 1522 int ret; 1523 1524 /* 1525 * TODO: bypass the initialize in sriov for now 1526 */ 1527 if (amdgpu_sriov_vf(psp->adev)) 1528 return 0; 1529 1530 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1531 !psp->hdcp_context.context.bin_desc.start_addr) { 1532 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1533 return 0; 1534 } 1535 1536 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1537 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1538 1539 if (!psp->hdcp_context.context.initialized) { 1540 ret = psp_hdcp_init_shared_buf(psp); 1541 if (ret) 1542 return ret; 1543 } 1544 1545 ret = psp_hdcp_load(psp); 1546 if (!ret) { 1547 psp->hdcp_context.context.initialized = true; 1548 mutex_init(&psp->hdcp_context.mutex); 1549 } 1550 1551 return ret; 1552 } 1553 1554 static int psp_hdcp_unload(struct psp_context *psp) 1555 { 1556 return psp_ta_unload(psp, &psp->hdcp_context.context); 1557 } 1558 1559 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1560 { 1561 /* 1562 * TODO: bypass the loading in sriov for now 1563 */ 1564 if (amdgpu_sriov_vf(psp->adev)) 1565 return 0; 1566 1567 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1568 } 1569 1570 static int psp_hdcp_terminate(struct psp_context *psp) 1571 { 1572 int ret; 1573 1574 /* 1575 * TODO: bypass the terminate in sriov for now 1576 */ 1577 if (amdgpu_sriov_vf(psp->adev)) 1578 return 0; 1579 1580 if (!psp->hdcp_context.context.initialized) { 1581 if (psp->hdcp_context.context.mem_context.shared_buf) 1582 goto out; 1583 else 1584 return 0; 1585 } 1586 1587 ret = psp_hdcp_unload(psp); 1588 if (ret) 1589 return ret; 1590 1591 psp->hdcp_context.context.initialized = false; 1592 1593 out: 1594 /* free hdcp shared memory */ 1595 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 1596 1597 return 0; 1598 } 1599 // HDCP end 1600 1601 // DTM start 1602 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1603 { 1604 return psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1605 } 1606 1607 static int psp_dtm_load(struct psp_context *psp) 1608 { 1609 return psp_ta_load(psp, &psp->dtm_context.context); 1610 } 1611 1612 static int psp_dtm_initialize(struct psp_context *psp) 1613 { 1614 int ret; 1615 1616 /* 1617 * TODO: bypass the initialize in sriov for now 1618 */ 1619 if (amdgpu_sriov_vf(psp->adev)) 1620 return 0; 1621 1622 if (!psp->dtm_context.context.bin_desc.size_bytes || 1623 !psp->dtm_context.context.bin_desc.start_addr) { 1624 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1625 return 0; 1626 } 1627 1628 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1629 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1630 1631 if (!psp->dtm_context.context.initialized) { 1632 ret = psp_dtm_init_shared_buf(psp); 1633 if (ret) 1634 return ret; 1635 } 1636 1637 ret = psp_dtm_load(psp); 1638 if (!ret) { 1639 psp->dtm_context.context.initialized = true; 1640 mutex_init(&psp->dtm_context.mutex); 1641 } 1642 1643 return ret; 1644 } 1645 1646 static int psp_dtm_unload(struct psp_context *psp) 1647 { 1648 return psp_ta_unload(psp, &psp->dtm_context.context); 1649 } 1650 1651 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1652 { 1653 /* 1654 * TODO: bypass the loading in sriov for now 1655 */ 1656 if (amdgpu_sriov_vf(psp->adev)) 1657 return 0; 1658 1659 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1660 } 1661 1662 static int psp_dtm_terminate(struct psp_context *psp) 1663 { 1664 int ret; 1665 1666 /* 1667 * TODO: bypass the terminate in sriov for now 1668 */ 1669 if (amdgpu_sriov_vf(psp->adev)) 1670 return 0; 1671 1672 if (!psp->dtm_context.context.initialized) { 1673 if (psp->dtm_context.context.mem_context.shared_buf) 1674 goto out; 1675 else 1676 return 0; 1677 } 1678 1679 ret = psp_dtm_unload(psp); 1680 if (ret) 1681 return ret; 1682 1683 psp->dtm_context.context.initialized = false; 1684 1685 out: 1686 /* free dtm shared memory */ 1687 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 1688 1689 return 0; 1690 } 1691 // DTM end 1692 1693 // RAP start 1694 static int psp_rap_init_shared_buf(struct psp_context *psp) 1695 { 1696 return psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1697 } 1698 1699 static int psp_rap_load(struct psp_context *psp) 1700 { 1701 return psp_ta_load(psp, &psp->rap_context.context); 1702 } 1703 1704 static int psp_rap_unload(struct psp_context *psp) 1705 { 1706 return psp_ta_unload(psp, &psp->rap_context.context); 1707 } 1708 1709 static int psp_rap_initialize(struct psp_context *psp) 1710 { 1711 int ret; 1712 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1713 1714 /* 1715 * TODO: bypass the initialize in sriov for now 1716 */ 1717 if (amdgpu_sriov_vf(psp->adev)) 1718 return 0; 1719 1720 if (!psp->rap_context.context.bin_desc.size_bytes || 1721 !psp->rap_context.context.bin_desc.start_addr) { 1722 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1723 return 0; 1724 } 1725 1726 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1727 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1728 1729 if (!psp->rap_context.context.initialized) { 1730 ret = psp_rap_init_shared_buf(psp); 1731 if (ret) 1732 return ret; 1733 } 1734 1735 ret = psp_rap_load(psp); 1736 if (!ret) { 1737 psp->rap_context.context.initialized = true; 1738 mutex_init(&psp->rap_context.mutex); 1739 } else 1740 return ret; 1741 1742 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1743 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1744 psp_rap_terminate(psp); 1745 1746 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1747 ret, status); 1748 1749 return ret; 1750 } 1751 1752 return 0; 1753 } 1754 1755 static int psp_rap_terminate(struct psp_context *psp) 1756 { 1757 int ret; 1758 1759 if (!psp->rap_context.context.initialized) 1760 return 0; 1761 1762 ret = psp_rap_unload(psp); 1763 1764 psp->rap_context.context.initialized = false; 1765 1766 /* free rap shared memory */ 1767 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1768 1769 return ret; 1770 } 1771 1772 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1773 { 1774 struct ta_rap_shared_memory *rap_cmd; 1775 int ret = 0; 1776 1777 if (!psp->rap_context.context.initialized) 1778 return 0; 1779 1780 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1781 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1782 return -EINVAL; 1783 1784 mutex_lock(&psp->rap_context.mutex); 1785 1786 rap_cmd = (struct ta_rap_shared_memory *) 1787 psp->rap_context.context.mem_context.shared_buf; 1788 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1789 1790 rap_cmd->cmd_id = ta_cmd_id; 1791 rap_cmd->validation_method_id = METHOD_A; 1792 1793 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1794 if (ret) 1795 goto out_unlock; 1796 1797 if (status) 1798 *status = rap_cmd->rap_status; 1799 1800 out_unlock: 1801 mutex_unlock(&psp->rap_context.mutex); 1802 1803 return ret; 1804 } 1805 // RAP end 1806 1807 /* securedisplay start */ 1808 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1809 { 1810 return psp_ta_init_shared_buf( 1811 psp, &psp->securedisplay_context.context.mem_context); 1812 } 1813 1814 static int psp_securedisplay_load(struct psp_context *psp) 1815 { 1816 return psp_ta_load(psp, &psp->securedisplay_context.context); 1817 } 1818 1819 static int psp_securedisplay_unload(struct psp_context *psp) 1820 { 1821 return psp_ta_unload(psp, &psp->securedisplay_context.context); 1822 } 1823 1824 static int psp_securedisplay_initialize(struct psp_context *psp) 1825 { 1826 int ret; 1827 struct securedisplay_cmd *securedisplay_cmd; 1828 1829 /* 1830 * TODO: bypass the initialize in sriov for now 1831 */ 1832 if (amdgpu_sriov_vf(psp->adev)) 1833 return 0; 1834 1835 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1836 !psp->securedisplay_context.context.bin_desc.start_addr) { 1837 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1838 return 0; 1839 } 1840 1841 psp->securedisplay_context.context.mem_context.shared_mem_size = 1842 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1843 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1844 1845 if (!psp->securedisplay_context.context.initialized) { 1846 ret = psp_securedisplay_init_shared_buf(psp); 1847 if (ret) 1848 return ret; 1849 } 1850 1851 ret = psp_securedisplay_load(psp); 1852 if (!ret) { 1853 psp->securedisplay_context.context.initialized = true; 1854 mutex_init(&psp->securedisplay_context.mutex); 1855 } else 1856 return ret; 1857 1858 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1859 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1860 1861 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1862 if (ret) { 1863 psp_securedisplay_terminate(psp); 1864 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1865 return -EINVAL; 1866 } 1867 1868 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1869 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1870 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1871 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1872 } 1873 1874 return 0; 1875 } 1876 1877 static int psp_securedisplay_terminate(struct psp_context *psp) 1878 { 1879 int ret; 1880 1881 /* 1882 * TODO:bypass the terminate in sriov for now 1883 */ 1884 if (amdgpu_sriov_vf(psp->adev)) 1885 return 0; 1886 1887 if (!psp->securedisplay_context.context.initialized) 1888 return 0; 1889 1890 ret = psp_securedisplay_unload(psp); 1891 if (ret) 1892 return ret; 1893 1894 psp->securedisplay_context.context.initialized = false; 1895 1896 /* free securedisplay shared memory */ 1897 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1898 1899 return ret; 1900 } 1901 1902 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1903 { 1904 int ret; 1905 1906 if (!psp->securedisplay_context.context.initialized) 1907 return -EINVAL; 1908 1909 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1910 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1911 return -EINVAL; 1912 1913 mutex_lock(&psp->securedisplay_context.mutex); 1914 1915 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1916 1917 mutex_unlock(&psp->securedisplay_context.mutex); 1918 1919 return ret; 1920 } 1921 /* SECUREDISPLAY end */ 1922 1923 static int psp_hw_start(struct psp_context *psp) 1924 { 1925 struct amdgpu_device *adev = psp->adev; 1926 int ret; 1927 1928 if (!amdgpu_sriov_vf(adev)) { 1929 if ((is_psp_fw_valid(psp->kdb)) && 1930 (psp->funcs->bootloader_load_kdb != NULL)) { 1931 ret = psp_bootloader_load_kdb(psp); 1932 if (ret) { 1933 DRM_ERROR("PSP load kdb failed!\n"); 1934 return ret; 1935 } 1936 } 1937 1938 if ((is_psp_fw_valid(psp->spl)) && 1939 (psp->funcs->bootloader_load_spl != NULL)) { 1940 ret = psp_bootloader_load_spl(psp); 1941 if (ret) { 1942 DRM_ERROR("PSP load spl failed!\n"); 1943 return ret; 1944 } 1945 } 1946 1947 if ((is_psp_fw_valid(psp->sys)) && 1948 (psp->funcs->bootloader_load_sysdrv != NULL)) { 1949 ret = psp_bootloader_load_sysdrv(psp); 1950 if (ret) { 1951 DRM_ERROR("PSP load sys drv failed!\n"); 1952 return ret; 1953 } 1954 } 1955 1956 if ((is_psp_fw_valid(psp->soc_drv)) && 1957 (psp->funcs->bootloader_load_soc_drv != NULL)) { 1958 ret = psp_bootloader_load_soc_drv(psp); 1959 if (ret) { 1960 DRM_ERROR("PSP load soc drv failed!\n"); 1961 return ret; 1962 } 1963 } 1964 1965 if ((is_psp_fw_valid(psp->intf_drv)) && 1966 (psp->funcs->bootloader_load_intf_drv != NULL)) { 1967 ret = psp_bootloader_load_intf_drv(psp); 1968 if (ret) { 1969 DRM_ERROR("PSP load intf drv failed!\n"); 1970 return ret; 1971 } 1972 } 1973 1974 if ((is_psp_fw_valid(psp->dbg_drv)) && 1975 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 1976 ret = psp_bootloader_load_dbg_drv(psp); 1977 if (ret) { 1978 DRM_ERROR("PSP load dbg drv failed!\n"); 1979 return ret; 1980 } 1981 } 1982 1983 if ((is_psp_fw_valid(psp->sos)) && 1984 (psp->funcs->bootloader_load_sos != NULL)) { 1985 ret = psp_bootloader_load_sos(psp); 1986 if (ret) { 1987 DRM_ERROR("PSP load sos failed!\n"); 1988 return ret; 1989 } 1990 } 1991 } 1992 1993 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1994 if (ret) { 1995 DRM_ERROR("PSP create ring failed!\n"); 1996 return ret; 1997 } 1998 1999 ret = psp_tmr_init(psp); 2000 if (ret) { 2001 DRM_ERROR("PSP tmr init failed!\n"); 2002 return ret; 2003 } 2004 2005 /* 2006 * For ASICs with DF Cstate management centralized 2007 * to PMFW, TMR setup should be performed after PMFW 2008 * loaded and before other non-psp firmware loaded. 2009 */ 2010 if (psp->pmfw_centralized_cstate_management) { 2011 ret = psp_load_smu_fw(psp); 2012 if (ret) 2013 return ret; 2014 } 2015 2016 ret = psp_tmr_load(psp); 2017 if (ret) { 2018 DRM_ERROR("PSP load tmr failed!\n"); 2019 return ret; 2020 } 2021 2022 return 0; 2023 } 2024 2025 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2026 enum psp_gfx_fw_type *type) 2027 { 2028 switch (ucode->ucode_id) { 2029 case AMDGPU_UCODE_ID_SDMA0: 2030 *type = GFX_FW_TYPE_SDMA0; 2031 break; 2032 case AMDGPU_UCODE_ID_SDMA1: 2033 *type = GFX_FW_TYPE_SDMA1; 2034 break; 2035 case AMDGPU_UCODE_ID_SDMA2: 2036 *type = GFX_FW_TYPE_SDMA2; 2037 break; 2038 case AMDGPU_UCODE_ID_SDMA3: 2039 *type = GFX_FW_TYPE_SDMA3; 2040 break; 2041 case AMDGPU_UCODE_ID_SDMA4: 2042 *type = GFX_FW_TYPE_SDMA4; 2043 break; 2044 case AMDGPU_UCODE_ID_SDMA5: 2045 *type = GFX_FW_TYPE_SDMA5; 2046 break; 2047 case AMDGPU_UCODE_ID_SDMA6: 2048 *type = GFX_FW_TYPE_SDMA6; 2049 break; 2050 case AMDGPU_UCODE_ID_SDMA7: 2051 *type = GFX_FW_TYPE_SDMA7; 2052 break; 2053 case AMDGPU_UCODE_ID_CP_MES: 2054 *type = GFX_FW_TYPE_CP_MES; 2055 break; 2056 case AMDGPU_UCODE_ID_CP_MES_DATA: 2057 *type = GFX_FW_TYPE_MES_STACK; 2058 break; 2059 case AMDGPU_UCODE_ID_CP_CE: 2060 *type = GFX_FW_TYPE_CP_CE; 2061 break; 2062 case AMDGPU_UCODE_ID_CP_PFP: 2063 *type = GFX_FW_TYPE_CP_PFP; 2064 break; 2065 case AMDGPU_UCODE_ID_CP_ME: 2066 *type = GFX_FW_TYPE_CP_ME; 2067 break; 2068 case AMDGPU_UCODE_ID_CP_MEC1: 2069 *type = GFX_FW_TYPE_CP_MEC; 2070 break; 2071 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2072 *type = GFX_FW_TYPE_CP_MEC_ME1; 2073 break; 2074 case AMDGPU_UCODE_ID_CP_MEC2: 2075 *type = GFX_FW_TYPE_CP_MEC; 2076 break; 2077 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2078 *type = GFX_FW_TYPE_CP_MEC_ME2; 2079 break; 2080 case AMDGPU_UCODE_ID_RLC_G: 2081 *type = GFX_FW_TYPE_RLC_G; 2082 break; 2083 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2084 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2085 break; 2086 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2087 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2088 break; 2089 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2090 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2091 break; 2092 case AMDGPU_UCODE_ID_RLC_IRAM: 2093 *type = GFX_FW_TYPE_RLC_IRAM; 2094 break; 2095 case AMDGPU_UCODE_ID_RLC_DRAM: 2096 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2097 break; 2098 case AMDGPU_UCODE_ID_SMC: 2099 *type = GFX_FW_TYPE_SMU; 2100 break; 2101 case AMDGPU_UCODE_ID_UVD: 2102 *type = GFX_FW_TYPE_UVD; 2103 break; 2104 case AMDGPU_UCODE_ID_UVD1: 2105 *type = GFX_FW_TYPE_UVD1; 2106 break; 2107 case AMDGPU_UCODE_ID_VCE: 2108 *type = GFX_FW_TYPE_VCE; 2109 break; 2110 case AMDGPU_UCODE_ID_VCN: 2111 *type = GFX_FW_TYPE_VCN; 2112 break; 2113 case AMDGPU_UCODE_ID_VCN1: 2114 *type = GFX_FW_TYPE_VCN1; 2115 break; 2116 case AMDGPU_UCODE_ID_DMCU_ERAM: 2117 *type = GFX_FW_TYPE_DMCU_ERAM; 2118 break; 2119 case AMDGPU_UCODE_ID_DMCU_INTV: 2120 *type = GFX_FW_TYPE_DMCU_ISR; 2121 break; 2122 case AMDGPU_UCODE_ID_VCN0_RAM: 2123 *type = GFX_FW_TYPE_VCN0_RAM; 2124 break; 2125 case AMDGPU_UCODE_ID_VCN1_RAM: 2126 *type = GFX_FW_TYPE_VCN1_RAM; 2127 break; 2128 case AMDGPU_UCODE_ID_DMCUB: 2129 *type = GFX_FW_TYPE_DMUB; 2130 break; 2131 case AMDGPU_UCODE_ID_MAXIMUM: 2132 default: 2133 return -EINVAL; 2134 } 2135 2136 return 0; 2137 } 2138 2139 static void psp_print_fw_hdr(struct psp_context *psp, 2140 struct amdgpu_firmware_info *ucode) 2141 { 2142 struct amdgpu_device *adev = psp->adev; 2143 struct common_firmware_header *hdr; 2144 2145 switch (ucode->ucode_id) { 2146 case AMDGPU_UCODE_ID_SDMA0: 2147 case AMDGPU_UCODE_ID_SDMA1: 2148 case AMDGPU_UCODE_ID_SDMA2: 2149 case AMDGPU_UCODE_ID_SDMA3: 2150 case AMDGPU_UCODE_ID_SDMA4: 2151 case AMDGPU_UCODE_ID_SDMA5: 2152 case AMDGPU_UCODE_ID_SDMA6: 2153 case AMDGPU_UCODE_ID_SDMA7: 2154 hdr = (struct common_firmware_header *) 2155 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2156 amdgpu_ucode_print_sdma_hdr(hdr); 2157 break; 2158 case AMDGPU_UCODE_ID_CP_CE: 2159 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2160 amdgpu_ucode_print_gfx_hdr(hdr); 2161 break; 2162 case AMDGPU_UCODE_ID_CP_PFP: 2163 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2164 amdgpu_ucode_print_gfx_hdr(hdr); 2165 break; 2166 case AMDGPU_UCODE_ID_CP_ME: 2167 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2168 amdgpu_ucode_print_gfx_hdr(hdr); 2169 break; 2170 case AMDGPU_UCODE_ID_CP_MEC1: 2171 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2172 amdgpu_ucode_print_gfx_hdr(hdr); 2173 break; 2174 case AMDGPU_UCODE_ID_RLC_G: 2175 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2176 amdgpu_ucode_print_rlc_hdr(hdr); 2177 break; 2178 case AMDGPU_UCODE_ID_SMC: 2179 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2180 amdgpu_ucode_print_smc_hdr(hdr); 2181 break; 2182 default: 2183 break; 2184 } 2185 } 2186 2187 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2188 struct psp_gfx_cmd_resp *cmd) 2189 { 2190 int ret; 2191 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2192 2193 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2194 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2195 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2196 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2197 2198 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2199 if (ret) 2200 DRM_ERROR("Unknown firmware type\n"); 2201 2202 return ret; 2203 } 2204 2205 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2206 struct amdgpu_firmware_info *ucode) 2207 { 2208 int ret = 0; 2209 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2210 2211 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2212 if (!ret) { 2213 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2214 psp->fence_buf_mc_addr); 2215 } 2216 2217 release_psp_cmd_buf(psp); 2218 2219 return ret; 2220 } 2221 2222 static int psp_load_smu_fw(struct psp_context *psp) 2223 { 2224 int ret; 2225 struct amdgpu_device *adev = psp->adev; 2226 struct amdgpu_firmware_info *ucode = 2227 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2228 struct amdgpu_ras *ras = psp->ras_context.ras; 2229 2230 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2231 return 0; 2232 2233 if ((amdgpu_in_reset(adev) && 2234 ras && adev->ras_enabled && 2235 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2236 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2237 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2238 if (ret) { 2239 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2240 } 2241 } 2242 2243 ret = psp_execute_non_psp_fw_load(psp, ucode); 2244 2245 if (ret) 2246 DRM_ERROR("PSP load smu failed!\n"); 2247 2248 return ret; 2249 } 2250 2251 static bool fw_load_skip_check(struct psp_context *psp, 2252 struct amdgpu_firmware_info *ucode) 2253 { 2254 if (!ucode->fw) 2255 return true; 2256 2257 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2258 (psp_smu_reload_quirk(psp) || 2259 psp->autoload_supported || 2260 psp->pmfw_centralized_cstate_management)) 2261 return true; 2262 2263 if (amdgpu_sriov_vf(psp->adev) && 2264 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2265 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2266 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2267 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2268 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2269 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2270 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2271 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2272 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2273 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2274 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2275 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2276 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2277 /*skip ucode loading in SRIOV VF */ 2278 return true; 2279 2280 if (psp->autoload_supported && 2281 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2282 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2283 /* skip mec JT when autoload is enabled */ 2284 return true; 2285 2286 return false; 2287 } 2288 2289 int psp_load_fw_list(struct psp_context *psp, 2290 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2291 { 2292 int ret = 0, i; 2293 struct amdgpu_firmware_info *ucode; 2294 2295 for (i = 0; i < ucode_count; ++i) { 2296 ucode = ucode_list[i]; 2297 psp_print_fw_hdr(psp, ucode); 2298 ret = psp_execute_non_psp_fw_load(psp, ucode); 2299 if (ret) 2300 return ret; 2301 } 2302 return ret; 2303 } 2304 2305 static int psp_load_non_psp_fw(struct psp_context *psp) 2306 { 2307 int i, ret; 2308 struct amdgpu_firmware_info *ucode; 2309 struct amdgpu_device *adev = psp->adev; 2310 2311 if (psp->autoload_supported && 2312 !psp->pmfw_centralized_cstate_management) { 2313 ret = psp_load_smu_fw(psp); 2314 if (ret) 2315 return ret; 2316 } 2317 2318 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2319 ucode = &adev->firmware.ucode[i]; 2320 2321 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2322 !fw_load_skip_check(psp, ucode)) { 2323 ret = psp_load_smu_fw(psp); 2324 if (ret) 2325 return ret; 2326 continue; 2327 } 2328 2329 if (fw_load_skip_check(psp, ucode)) 2330 continue; 2331 2332 if (psp->autoload_supported && 2333 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2334 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2335 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2336 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2337 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2338 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2339 /* PSP only receive one SDMA fw for sienna_cichlid, 2340 * as all four sdma fw are same */ 2341 continue; 2342 2343 psp_print_fw_hdr(psp, ucode); 2344 2345 ret = psp_execute_non_psp_fw_load(psp, ucode); 2346 if (ret) 2347 return ret; 2348 2349 /* Start rlc autoload after psp recieved all the gfx firmware */ 2350 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2351 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2352 ret = psp_rlc_autoload_start(psp); 2353 if (ret) { 2354 DRM_ERROR("Failed to start rlc autoload\n"); 2355 return ret; 2356 } 2357 } 2358 } 2359 2360 return 0; 2361 } 2362 2363 static int psp_load_fw(struct amdgpu_device *adev) 2364 { 2365 int ret; 2366 struct psp_context *psp = &adev->psp; 2367 2368 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2369 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2370 goto skip_memalloc; 2371 } 2372 2373 if (amdgpu_sriov_vf(adev)) { 2374 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2375 AMDGPU_GEM_DOMAIN_VRAM, 2376 &psp->fw_pri_bo, 2377 &psp->fw_pri_mc_addr, 2378 &psp->fw_pri_buf); 2379 } else { 2380 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2381 AMDGPU_GEM_DOMAIN_GTT, 2382 &psp->fw_pri_bo, 2383 &psp->fw_pri_mc_addr, 2384 &psp->fw_pri_buf); 2385 } 2386 2387 if (ret) 2388 goto failed; 2389 2390 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2391 AMDGPU_GEM_DOMAIN_VRAM, 2392 &psp->fence_buf_bo, 2393 &psp->fence_buf_mc_addr, 2394 &psp->fence_buf); 2395 if (ret) 2396 goto failed; 2397 2398 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2399 AMDGPU_GEM_DOMAIN_VRAM, 2400 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2401 (void **)&psp->cmd_buf_mem); 2402 if (ret) 2403 goto failed; 2404 2405 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2406 2407 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2408 if (ret) { 2409 DRM_ERROR("PSP ring init failed!\n"); 2410 goto failed; 2411 } 2412 2413 skip_memalloc: 2414 ret = psp_hw_start(psp); 2415 if (ret) 2416 goto failed; 2417 2418 ret = psp_load_non_psp_fw(psp); 2419 if (ret) 2420 goto failed; 2421 2422 ret = psp_asd_initialize(psp); 2423 if (ret) { 2424 DRM_ERROR("PSP load asd failed!\n"); 2425 return ret; 2426 } 2427 2428 ret = psp_rl_load(adev); 2429 if (ret) { 2430 DRM_ERROR("PSP load RL failed!\n"); 2431 return ret; 2432 } 2433 2434 if (psp->ta_fw) { 2435 ret = psp_ras_initialize(psp); 2436 if (ret) 2437 dev_err(psp->adev->dev, 2438 "RAS: Failed to initialize RAS\n"); 2439 2440 ret = psp_hdcp_initialize(psp); 2441 if (ret) 2442 dev_err(psp->adev->dev, 2443 "HDCP: Failed to initialize HDCP\n"); 2444 2445 ret = psp_dtm_initialize(psp); 2446 if (ret) 2447 dev_err(psp->adev->dev, 2448 "DTM: Failed to initialize DTM\n"); 2449 2450 ret = psp_rap_initialize(psp); 2451 if (ret) 2452 dev_err(psp->adev->dev, 2453 "RAP: Failed to initialize RAP\n"); 2454 2455 ret = psp_securedisplay_initialize(psp); 2456 if (ret) 2457 dev_err(psp->adev->dev, 2458 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2459 } 2460 2461 return 0; 2462 2463 failed: 2464 /* 2465 * all cleanup jobs (xgmi terminate, ras terminate, 2466 * ring destroy, cmd/fence/fw buffers destory, 2467 * psp->cmd destory) are delayed to psp_hw_fini 2468 */ 2469 return ret; 2470 } 2471 2472 static int psp_hw_init(void *handle) 2473 { 2474 int ret; 2475 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2476 2477 mutex_lock(&adev->firmware.mutex); 2478 /* 2479 * This sequence is just used on hw_init only once, no need on 2480 * resume. 2481 */ 2482 ret = amdgpu_ucode_init_bo(adev); 2483 if (ret) 2484 goto failed; 2485 2486 ret = psp_load_fw(adev); 2487 if (ret) { 2488 DRM_ERROR("PSP firmware loading failed\n"); 2489 goto failed; 2490 } 2491 2492 mutex_unlock(&adev->firmware.mutex); 2493 return 0; 2494 2495 failed: 2496 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2497 mutex_unlock(&adev->firmware.mutex); 2498 return -EINVAL; 2499 } 2500 2501 static int psp_hw_fini(void *handle) 2502 { 2503 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2504 struct psp_context *psp = &adev->psp; 2505 2506 if (psp->ta_fw) { 2507 psp_ras_terminate(psp); 2508 psp_securedisplay_terminate(psp); 2509 psp_rap_terminate(psp); 2510 psp_dtm_terminate(psp); 2511 psp_hdcp_terminate(psp); 2512 } 2513 2514 psp_asd_terminate(psp); 2515 2516 psp_tmr_terminate(psp); 2517 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2518 2519 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2520 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2521 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2522 &psp->fence_buf_mc_addr, &psp->fence_buf); 2523 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2524 (void **)&psp->cmd_buf_mem); 2525 2526 return 0; 2527 } 2528 2529 static int psp_suspend(void *handle) 2530 { 2531 int ret; 2532 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2533 struct psp_context *psp = &adev->psp; 2534 2535 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2536 psp->xgmi_context.context.initialized) { 2537 ret = psp_xgmi_terminate(psp); 2538 if (ret) { 2539 DRM_ERROR("Failed to terminate xgmi ta\n"); 2540 return ret; 2541 } 2542 } 2543 2544 if (psp->ta_fw) { 2545 ret = psp_ras_terminate(psp); 2546 if (ret) { 2547 DRM_ERROR("Failed to terminate ras ta\n"); 2548 return ret; 2549 } 2550 ret = psp_hdcp_terminate(psp); 2551 if (ret) { 2552 DRM_ERROR("Failed to terminate hdcp ta\n"); 2553 return ret; 2554 } 2555 ret = psp_dtm_terminate(psp); 2556 if (ret) { 2557 DRM_ERROR("Failed to terminate dtm ta\n"); 2558 return ret; 2559 } 2560 ret = psp_rap_terminate(psp); 2561 if (ret) { 2562 DRM_ERROR("Failed to terminate rap ta\n"); 2563 return ret; 2564 } 2565 ret = psp_securedisplay_terminate(psp); 2566 if (ret) { 2567 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2568 return ret; 2569 } 2570 } 2571 2572 ret = psp_asd_terminate(psp); 2573 if (ret) { 2574 DRM_ERROR("Failed to terminate asd\n"); 2575 return ret; 2576 } 2577 2578 ret = psp_tmr_terminate(psp); 2579 if (ret) { 2580 DRM_ERROR("Failed to terminate tmr\n"); 2581 return ret; 2582 } 2583 2584 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2585 if (ret) { 2586 DRM_ERROR("PSP ring stop failed\n"); 2587 return ret; 2588 } 2589 2590 return 0; 2591 } 2592 2593 static int psp_resume(void *handle) 2594 { 2595 int ret; 2596 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2597 struct psp_context *psp = &adev->psp; 2598 2599 DRM_INFO("PSP is resuming...\n"); 2600 2601 if (psp->mem_train_ctx.enable_mem_training) { 2602 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2603 if (ret) { 2604 DRM_ERROR("Failed to process memory training!\n"); 2605 return ret; 2606 } 2607 } 2608 2609 mutex_lock(&adev->firmware.mutex); 2610 2611 ret = psp_hw_start(psp); 2612 if (ret) 2613 goto failed; 2614 2615 ret = psp_load_non_psp_fw(psp); 2616 if (ret) 2617 goto failed; 2618 2619 ret = psp_asd_initialize(psp); 2620 if (ret) { 2621 DRM_ERROR("PSP load asd failed!\n"); 2622 goto failed; 2623 } 2624 2625 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2626 ret = psp_xgmi_initialize(psp, false, true); 2627 /* Warning the XGMI seesion initialize failure 2628 * Instead of stop driver initialization 2629 */ 2630 if (ret) 2631 dev_err(psp->adev->dev, 2632 "XGMI: Failed to initialize XGMI session\n"); 2633 } 2634 2635 if (psp->ta_fw) { 2636 ret = psp_ras_initialize(psp); 2637 if (ret) 2638 dev_err(psp->adev->dev, 2639 "RAS: Failed to initialize RAS\n"); 2640 2641 ret = psp_hdcp_initialize(psp); 2642 if (ret) 2643 dev_err(psp->adev->dev, 2644 "HDCP: Failed to initialize HDCP\n"); 2645 2646 ret = psp_dtm_initialize(psp); 2647 if (ret) 2648 dev_err(psp->adev->dev, 2649 "DTM: Failed to initialize DTM\n"); 2650 2651 ret = psp_rap_initialize(psp); 2652 if (ret) 2653 dev_err(psp->adev->dev, 2654 "RAP: Failed to initialize RAP\n"); 2655 2656 ret = psp_securedisplay_initialize(psp); 2657 if (ret) 2658 dev_err(psp->adev->dev, 2659 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2660 } 2661 2662 mutex_unlock(&adev->firmware.mutex); 2663 2664 return 0; 2665 2666 failed: 2667 DRM_ERROR("PSP resume failed\n"); 2668 mutex_unlock(&adev->firmware.mutex); 2669 return ret; 2670 } 2671 2672 int psp_gpu_reset(struct amdgpu_device *adev) 2673 { 2674 int ret; 2675 2676 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2677 return 0; 2678 2679 mutex_lock(&adev->psp.mutex); 2680 ret = psp_mode1_reset(&adev->psp); 2681 mutex_unlock(&adev->psp.mutex); 2682 2683 return ret; 2684 } 2685 2686 int psp_rlc_autoload_start(struct psp_context *psp) 2687 { 2688 int ret; 2689 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2690 2691 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2692 2693 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2694 psp->fence_buf_mc_addr); 2695 2696 release_psp_cmd_buf(psp); 2697 2698 return ret; 2699 } 2700 2701 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2702 uint64_t cmd_gpu_addr, int cmd_size) 2703 { 2704 struct amdgpu_firmware_info ucode = {0}; 2705 2706 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2707 AMDGPU_UCODE_ID_VCN0_RAM; 2708 ucode.mc_addr = cmd_gpu_addr; 2709 ucode.ucode_size = cmd_size; 2710 2711 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2712 } 2713 2714 int psp_ring_cmd_submit(struct psp_context *psp, 2715 uint64_t cmd_buf_mc_addr, 2716 uint64_t fence_mc_addr, 2717 int index) 2718 { 2719 unsigned int psp_write_ptr_reg = 0; 2720 struct psp_gfx_rb_frame *write_frame; 2721 struct psp_ring *ring = &psp->km_ring; 2722 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2723 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2724 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2725 struct amdgpu_device *adev = psp->adev; 2726 uint32_t ring_size_dw = ring->ring_size / 4; 2727 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2728 2729 /* KM (GPCOM) prepare write pointer */ 2730 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2731 2732 /* Update KM RB frame pointer to new frame */ 2733 /* write_frame ptr increments by size of rb_frame in bytes */ 2734 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2735 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2736 write_frame = ring_buffer_start; 2737 else 2738 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2739 /* Check invalid write_frame ptr address */ 2740 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2741 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2742 ring_buffer_start, ring_buffer_end, write_frame); 2743 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2744 return -EINVAL; 2745 } 2746 2747 /* Initialize KM RB frame */ 2748 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2749 2750 /* Update KM RB frame */ 2751 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2752 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2753 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2754 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2755 write_frame->fence_value = index; 2756 amdgpu_device_flush_hdp(adev, NULL); 2757 2758 /* Update the write Pointer in DWORDs */ 2759 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2760 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2761 return 0; 2762 } 2763 2764 int psp_init_asd_microcode(struct psp_context *psp, 2765 const char *chip_name) 2766 { 2767 struct amdgpu_device *adev = psp->adev; 2768 char fw_name[PSP_FW_NAME_LEN]; 2769 const struct psp_firmware_header_v1_0 *asd_hdr; 2770 int err = 0; 2771 2772 if (!chip_name) { 2773 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2774 return -EINVAL; 2775 } 2776 2777 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2778 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2779 if (err) 2780 goto out; 2781 2782 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2783 if (err) 2784 goto out; 2785 2786 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2787 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2788 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2789 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2790 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2791 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2792 return 0; 2793 out: 2794 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2795 release_firmware(adev->psp.asd_fw); 2796 adev->psp.asd_fw = NULL; 2797 return err; 2798 } 2799 2800 int psp_init_toc_microcode(struct psp_context *psp, 2801 const char *chip_name) 2802 { 2803 struct amdgpu_device *adev = psp->adev; 2804 char fw_name[PSP_FW_NAME_LEN]; 2805 const struct psp_firmware_header_v1_0 *toc_hdr; 2806 int err = 0; 2807 2808 if (!chip_name) { 2809 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2810 return -EINVAL; 2811 } 2812 2813 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2814 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2815 if (err) 2816 goto out; 2817 2818 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2819 if (err) 2820 goto out; 2821 2822 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2823 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2824 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2825 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2826 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2827 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2828 return 0; 2829 out: 2830 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2831 release_firmware(adev->psp.toc_fw); 2832 adev->psp.toc_fw = NULL; 2833 return err; 2834 } 2835 2836 static int parse_sos_bin_descriptor(struct psp_context *psp, 2837 const struct psp_fw_bin_desc *desc, 2838 const struct psp_firmware_header_v2_0 *sos_hdr) 2839 { 2840 uint8_t *ucode_start_addr = NULL; 2841 2842 if (!psp || !desc || !sos_hdr) 2843 return -EINVAL; 2844 2845 ucode_start_addr = (uint8_t *)sos_hdr + 2846 le32_to_cpu(desc->offset_bytes) + 2847 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2848 2849 switch (desc->fw_type) { 2850 case PSP_FW_TYPE_PSP_SOS: 2851 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2852 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2853 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2854 psp->sos.start_addr = ucode_start_addr; 2855 break; 2856 case PSP_FW_TYPE_PSP_SYS_DRV: 2857 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2858 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2859 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2860 psp->sys.start_addr = ucode_start_addr; 2861 break; 2862 case PSP_FW_TYPE_PSP_KDB: 2863 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2864 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2865 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2866 psp->kdb.start_addr = ucode_start_addr; 2867 break; 2868 case PSP_FW_TYPE_PSP_TOC: 2869 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2870 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2871 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 2872 psp->toc.start_addr = ucode_start_addr; 2873 break; 2874 case PSP_FW_TYPE_PSP_SPL: 2875 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 2876 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 2877 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 2878 psp->spl.start_addr = ucode_start_addr; 2879 break; 2880 case PSP_FW_TYPE_PSP_RL: 2881 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 2882 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 2883 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 2884 psp->rl.start_addr = ucode_start_addr; 2885 break; 2886 case PSP_FW_TYPE_PSP_SOC_DRV: 2887 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 2888 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 2889 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2890 psp->soc_drv.start_addr = ucode_start_addr; 2891 break; 2892 case PSP_FW_TYPE_PSP_INTF_DRV: 2893 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 2894 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 2895 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2896 psp->intf_drv.start_addr = ucode_start_addr; 2897 break; 2898 case PSP_FW_TYPE_PSP_DBG_DRV: 2899 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 2900 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 2901 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2902 psp->dbg_drv.start_addr = ucode_start_addr; 2903 break; 2904 default: 2905 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 2906 break; 2907 } 2908 2909 return 0; 2910 } 2911 2912 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 2913 { 2914 const struct psp_firmware_header_v1_0 *sos_hdr; 2915 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2916 uint8_t *ucode_array_start_addr; 2917 2918 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2919 ucode_array_start_addr = (uint8_t *)sos_hdr + 2920 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2921 2922 if (adev->gmc.xgmi.connected_to_cpu || 2923 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 2924 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 2925 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 2926 2927 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 2928 adev->psp.sys.start_addr = ucode_array_start_addr; 2929 2930 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 2931 adev->psp.sos.start_addr = ucode_array_start_addr + 2932 le32_to_cpu(sos_hdr->sos.offset_bytes); 2933 adev->psp.xgmi_context.supports_extended_data = false; 2934 } else { 2935 /* Load alternate PSP SOS FW */ 2936 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 2937 2938 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 2939 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 2940 2941 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 2942 adev->psp.sys.start_addr = ucode_array_start_addr + 2943 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 2944 2945 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 2946 adev->psp.sos.start_addr = ucode_array_start_addr + 2947 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 2948 adev->psp.xgmi_context.supports_extended_data = true; 2949 } 2950 2951 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 2952 dev_warn(adev->dev, "PSP SOS FW not available"); 2953 return -EINVAL; 2954 } 2955 2956 return 0; 2957 } 2958 2959 int psp_init_sos_microcode(struct psp_context *psp, 2960 const char *chip_name) 2961 { 2962 struct amdgpu_device *adev = psp->adev; 2963 char fw_name[PSP_FW_NAME_LEN]; 2964 const struct psp_firmware_header_v1_0 *sos_hdr; 2965 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 2966 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 2967 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2968 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 2969 int err = 0; 2970 uint8_t *ucode_array_start_addr; 2971 int fw_index = 0; 2972 2973 if (!chip_name) { 2974 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 2975 return -EINVAL; 2976 } 2977 2978 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 2979 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 2980 if (err) 2981 goto out; 2982 2983 err = amdgpu_ucode_validate(adev->psp.sos_fw); 2984 if (err) 2985 goto out; 2986 2987 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2988 ucode_array_start_addr = (uint8_t *)sos_hdr + 2989 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2990 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 2991 2992 switch (sos_hdr->header.header_version_major) { 2993 case 1: 2994 err = psp_init_sos_base_fw(adev); 2995 if (err) 2996 goto out; 2997 2998 if (sos_hdr->header.header_version_minor == 1) { 2999 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3000 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3001 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3002 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3003 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3004 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3005 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3006 } 3007 if (sos_hdr->header.header_version_minor == 2) { 3008 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3009 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3010 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3011 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3012 } 3013 if (sos_hdr->header.header_version_minor == 3) { 3014 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3015 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3016 adev->psp.toc.start_addr = ucode_array_start_addr + 3017 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3018 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3019 adev->psp.kdb.start_addr = ucode_array_start_addr + 3020 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3021 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3022 adev->psp.spl.start_addr = ucode_array_start_addr + 3023 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3024 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3025 adev->psp.rl.start_addr = ucode_array_start_addr + 3026 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3027 } 3028 break; 3029 case 2: 3030 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3031 3032 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3033 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3034 err = -EINVAL; 3035 goto out; 3036 } 3037 3038 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3039 err = parse_sos_bin_descriptor(psp, 3040 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3041 sos_hdr_v2_0); 3042 if (err) 3043 goto out; 3044 } 3045 break; 3046 default: 3047 dev_err(adev->dev, 3048 "unsupported psp sos firmware\n"); 3049 err = -EINVAL; 3050 goto out; 3051 } 3052 3053 return 0; 3054 out: 3055 dev_err(adev->dev, 3056 "failed to init sos firmware\n"); 3057 release_firmware(adev->psp.sos_fw); 3058 adev->psp.sos_fw = NULL; 3059 3060 return err; 3061 } 3062 3063 static int parse_ta_bin_descriptor(struct psp_context *psp, 3064 const struct psp_fw_bin_desc *desc, 3065 const struct ta_firmware_header_v2_0 *ta_hdr) 3066 { 3067 uint8_t *ucode_start_addr = NULL; 3068 3069 if (!psp || !desc || !ta_hdr) 3070 return -EINVAL; 3071 3072 ucode_start_addr = (uint8_t *)ta_hdr + 3073 le32_to_cpu(desc->offset_bytes) + 3074 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3075 3076 switch (desc->fw_type) { 3077 case TA_FW_TYPE_PSP_ASD: 3078 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3079 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3080 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3081 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3082 break; 3083 case TA_FW_TYPE_PSP_XGMI: 3084 psp->xgmi_context.context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3085 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3086 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3087 break; 3088 case TA_FW_TYPE_PSP_RAS: 3089 psp->ras_context.context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3090 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3091 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3092 break; 3093 case TA_FW_TYPE_PSP_HDCP: 3094 psp->hdcp_context.context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3095 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3096 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3097 break; 3098 case TA_FW_TYPE_PSP_DTM: 3099 psp->dtm_context.context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3100 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3101 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3102 break; 3103 case TA_FW_TYPE_PSP_RAP: 3104 psp->rap_context.context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3105 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3106 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3107 break; 3108 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3109 psp->securedisplay_context.context.bin_desc.feature_version = 3110 le32_to_cpu(desc->fw_version); 3111 psp->securedisplay_context.context.bin_desc.size_bytes = 3112 le32_to_cpu(desc->size_bytes); 3113 psp->securedisplay_context.context.bin_desc.start_addr = 3114 ucode_start_addr; 3115 break; 3116 default: 3117 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3118 break; 3119 } 3120 3121 return 0; 3122 } 3123 3124 int psp_init_ta_microcode(struct psp_context *psp, 3125 const char *chip_name) 3126 { 3127 struct amdgpu_device *adev = psp->adev; 3128 char fw_name[PSP_FW_NAME_LEN]; 3129 const struct ta_firmware_header_v2_0 *ta_hdr; 3130 int err = 0; 3131 int ta_index = 0; 3132 3133 if (!chip_name) { 3134 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3135 return -EINVAL; 3136 } 3137 3138 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3139 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3140 if (err) 3141 goto out; 3142 3143 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3144 if (err) 3145 goto out; 3146 3147 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3148 3149 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3150 dev_err(adev->dev, "unsupported TA header version\n"); 3151 err = -EINVAL; 3152 goto out; 3153 } 3154 3155 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3156 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3157 err = -EINVAL; 3158 goto out; 3159 } 3160 3161 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3162 err = parse_ta_bin_descriptor(psp, 3163 &ta_hdr->ta_fw_bin[ta_index], 3164 ta_hdr); 3165 if (err) 3166 goto out; 3167 } 3168 3169 return 0; 3170 out: 3171 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3172 release_firmware(adev->psp.ta_fw); 3173 adev->psp.ta_fw = NULL; 3174 return err; 3175 } 3176 3177 static int psp_set_clockgating_state(void *handle, 3178 enum amd_clockgating_state state) 3179 { 3180 return 0; 3181 } 3182 3183 static int psp_set_powergating_state(void *handle, 3184 enum amd_powergating_state state) 3185 { 3186 return 0; 3187 } 3188 3189 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3190 struct device_attribute *attr, 3191 char *buf) 3192 { 3193 struct drm_device *ddev = dev_get_drvdata(dev); 3194 struct amdgpu_device *adev = drm_to_adev(ddev); 3195 uint32_t fw_ver; 3196 int ret; 3197 3198 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3199 DRM_INFO("PSP block is not ready yet."); 3200 return -EBUSY; 3201 } 3202 3203 mutex_lock(&adev->psp.mutex); 3204 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3205 mutex_unlock(&adev->psp.mutex); 3206 3207 if (ret) { 3208 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3209 return ret; 3210 } 3211 3212 return sysfs_emit(buf, "%x\n", fw_ver); 3213 } 3214 3215 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3216 struct device_attribute *attr, 3217 const char *buf, 3218 size_t count) 3219 { 3220 struct drm_device *ddev = dev_get_drvdata(dev); 3221 struct amdgpu_device *adev = drm_to_adev(ddev); 3222 int ret, idx; 3223 char fw_name[100]; 3224 const struct firmware *usbc_pd_fw; 3225 struct amdgpu_bo *fw_buf_bo = NULL; 3226 uint64_t fw_pri_mc_addr; 3227 void *fw_pri_cpu_addr; 3228 3229 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3230 DRM_INFO("PSP block is not ready yet."); 3231 return -EBUSY; 3232 } 3233 3234 if (!drm_dev_enter(ddev, &idx)) 3235 return -ENODEV; 3236 3237 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3238 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3239 if (ret) 3240 goto fail; 3241 3242 /* LFB address which is aligned to 1MB boundary per PSP request */ 3243 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3244 AMDGPU_GEM_DOMAIN_VRAM, 3245 &fw_buf_bo, 3246 &fw_pri_mc_addr, 3247 &fw_pri_cpu_addr); 3248 if (ret) 3249 goto rel_buf; 3250 3251 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3252 3253 mutex_lock(&adev->psp.mutex); 3254 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3255 mutex_unlock(&adev->psp.mutex); 3256 3257 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3258 3259 rel_buf: 3260 release_firmware(usbc_pd_fw); 3261 fail: 3262 if (ret) { 3263 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3264 count = ret; 3265 } 3266 3267 drm_dev_exit(idx); 3268 return count; 3269 } 3270 3271 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3272 { 3273 int idx; 3274 3275 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3276 return; 3277 3278 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3279 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3280 3281 drm_dev_exit(idx); 3282 } 3283 3284 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3285 psp_usbc_pd_fw_sysfs_read, 3286 psp_usbc_pd_fw_sysfs_write); 3287 3288 int is_psp_fw_valid(struct psp_bin_desc bin) 3289 { 3290 return bin.size_bytes; 3291 } 3292 3293 const struct amd_ip_funcs psp_ip_funcs = { 3294 .name = "psp", 3295 .early_init = psp_early_init, 3296 .late_init = NULL, 3297 .sw_init = psp_sw_init, 3298 .sw_fini = psp_sw_fini, 3299 .hw_init = psp_hw_init, 3300 .hw_fini = psp_hw_fini, 3301 .suspend = psp_suspend, 3302 .resume = psp_resume, 3303 .is_idle = NULL, 3304 .check_soft_reset = NULL, 3305 .wait_for_idle = NULL, 3306 .soft_reset = NULL, 3307 .set_clockgating_state = psp_set_clockgating_state, 3308 .set_powergating_state = psp_set_powergating_state, 3309 }; 3310 3311 static int psp_sysfs_init(struct amdgpu_device *adev) 3312 { 3313 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3314 3315 if (ret) 3316 DRM_ERROR("Failed to create USBC PD FW control file!"); 3317 3318 return ret; 3319 } 3320 3321 static void psp_sysfs_fini(struct amdgpu_device *adev) 3322 { 3323 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3324 } 3325 3326 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3327 { 3328 .type = AMD_IP_BLOCK_TYPE_PSP, 3329 .major = 3, 3330 .minor = 1, 3331 .rev = 0, 3332 .funcs = &psp_ip_funcs, 3333 }; 3334 3335 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3336 { 3337 .type = AMD_IP_BLOCK_TYPE_PSP, 3338 .major = 10, 3339 .minor = 0, 3340 .rev = 0, 3341 .funcs = &psp_ip_funcs, 3342 }; 3343 3344 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3345 { 3346 .type = AMD_IP_BLOCK_TYPE_PSP, 3347 .major = 11, 3348 .minor = 0, 3349 .rev = 0, 3350 .funcs = &psp_ip_funcs, 3351 }; 3352 3353 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3354 .type = AMD_IP_BLOCK_TYPE_PSP, 3355 .major = 11, 3356 .minor = 0, 3357 .rev = 8, 3358 .funcs = &psp_ip_funcs, 3359 }; 3360 3361 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3362 { 3363 .type = AMD_IP_BLOCK_TYPE_PSP, 3364 .major = 12, 3365 .minor = 0, 3366 .rev = 0, 3367 .funcs = &psp_ip_funcs, 3368 }; 3369 3370 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3371 .type = AMD_IP_BLOCK_TYPE_PSP, 3372 .major = 13, 3373 .minor = 0, 3374 .rev = 0, 3375 .funcs = &psp_ip_funcs, 3376 }; 3377