1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 #include "psp_v10_0.h" 34 #include "psp_v11_0.h" 35 36 static void psp_set_funcs(struct amdgpu_device *adev); 37 38 static int psp_early_init(void *handle) 39 { 40 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 41 struct psp_context *psp = &adev->psp; 42 43 psp_set_funcs(adev); 44 45 switch (adev->asic_type) { 46 case CHIP_VEGA10: 47 case CHIP_VEGA12: 48 psp_v3_1_set_psp_funcs(psp); 49 psp->autoload_supported = false; 50 break; 51 case CHIP_RAVEN: 52 psp_v10_0_set_psp_funcs(psp); 53 psp->autoload_supported = false; 54 break; 55 case CHIP_VEGA20: 56 psp_v11_0_set_psp_funcs(psp); 57 psp->autoload_supported = false; 58 break; 59 case CHIP_NAVI10: 60 psp_v11_0_set_psp_funcs(psp); 61 psp->autoload_supported = true; 62 break; 63 default: 64 return -EINVAL; 65 } 66 67 psp->adev = adev; 68 69 return 0; 70 } 71 72 static int psp_sw_init(void *handle) 73 { 74 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 75 struct psp_context *psp = &adev->psp; 76 int ret; 77 78 ret = psp_init_microcode(psp); 79 if (ret) { 80 DRM_ERROR("Failed to load psp firmware!\n"); 81 return ret; 82 } 83 84 return 0; 85 } 86 87 static int psp_sw_fini(void *handle) 88 { 89 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 90 91 release_firmware(adev->psp.sos_fw); 92 adev->psp.sos_fw = NULL; 93 release_firmware(adev->psp.asd_fw); 94 adev->psp.asd_fw = NULL; 95 if (adev->psp.ta_fw) { 96 release_firmware(adev->psp.ta_fw); 97 adev->psp.ta_fw = NULL; 98 } 99 return 0; 100 } 101 102 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 103 uint32_t reg_val, uint32_t mask, bool check_changed) 104 { 105 uint32_t val; 106 int i; 107 struct amdgpu_device *adev = psp->adev; 108 109 for (i = 0; i < adev->usec_timeout; i++) { 110 val = RREG32(reg_index); 111 if (check_changed) { 112 if (val != reg_val) 113 return 0; 114 } else { 115 if ((val & mask) == reg_val) 116 return 0; 117 } 118 udelay(1); 119 } 120 121 return -ETIME; 122 } 123 124 static int 125 psp_cmd_submit_buf(struct psp_context *psp, 126 struct amdgpu_firmware_info *ucode, 127 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 128 { 129 int ret; 130 int index; 131 int timeout = 2000; 132 133 mutex_lock(&psp->mutex); 134 135 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 136 137 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 138 139 index = atomic_inc_return(&psp->fence_value); 140 ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr, 141 fence_mc_addr, index); 142 if (ret) { 143 atomic_dec(&psp->fence_value); 144 mutex_unlock(&psp->mutex); 145 return ret; 146 } 147 148 while (*((unsigned int *)psp->fence_buf) != index) { 149 if (--timeout == 0) 150 break; 151 msleep(1); 152 } 153 154 /* In some cases, psp response status is not 0 even there is no 155 * problem while the command is submitted. Some version of PSP FW 156 * doesn't write 0 to that field. 157 * So here we would like to only print a warning instead of an error 158 * during psp initialization to avoid breaking hw_init and it doesn't 159 * return -EINVAL. 160 */ 161 if (psp->cmd_buf_mem->resp.status || !timeout) { 162 if (ucode) 163 DRM_WARN("failed to load ucode id (%d) ", 164 ucode->ucode_id); 165 DRM_WARN("psp command failed and response status is (%d)\n", 166 psp->cmd_buf_mem->resp.status); 167 if (!timeout) { 168 mutex_unlock(&psp->mutex); 169 return -EINVAL; 170 } 171 } 172 173 /* get xGMI session id from response buffer */ 174 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id; 175 176 if (ucode) { 177 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 178 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 179 } 180 mutex_unlock(&psp->mutex); 181 182 return ret; 183 } 184 185 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 186 struct psp_gfx_cmd_resp *cmd, 187 uint64_t tmr_mc, uint32_t size) 188 { 189 if (psp_support_vmr_ring(psp)) 190 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 191 else 192 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 193 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 194 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 195 cmd->cmd.cmd_setup_tmr.buf_size = size; 196 } 197 198 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 199 uint64_t pri_buf_mc, uint32_t size) 200 { 201 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 202 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 203 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 204 cmd->cmd.cmd_load_toc.toc_size = size; 205 } 206 207 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 208 static int psp_load_toc(struct psp_context *psp, 209 uint32_t *tmr_size) 210 { 211 int ret; 212 struct psp_gfx_cmd_resp *cmd; 213 214 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 215 if (!cmd) 216 return -ENOMEM; 217 /* Copy toc to psp firmware private buffer */ 218 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 219 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size); 220 221 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 222 223 ret = psp_cmd_submit_buf(psp, NULL, cmd, 224 psp->fence_buf_mc_addr); 225 if (!ret) 226 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 227 kfree(cmd); 228 return ret; 229 } 230 231 /* Set up Trusted Memory Region */ 232 static int psp_tmr_init(struct psp_context *psp) 233 { 234 int ret; 235 int tmr_size; 236 237 /* 238 * According to HW engineer, they prefer the TMR address be "naturally 239 * aligned" , e.g. the start address be an integer divide of TMR size. 240 * 241 * Note: this memory need be reserved till the driver 242 * uninitializes. 243 */ 244 tmr_size = PSP_TMR_SIZE; 245 246 /* For ASICs support RLC autoload, psp will parse the toc 247 * and calculate the total size of TMR needed */ 248 if (psp->toc_start_addr && 249 psp->toc_bin_size && 250 psp->fw_pri_buf) { 251 ret = psp_load_toc(psp, &tmr_size); 252 if (ret) { 253 DRM_ERROR("Failed to load toc\n"); 254 return ret; 255 } 256 } 257 258 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE, 259 AMDGPU_GEM_DOMAIN_VRAM, 260 &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 261 262 return ret; 263 } 264 265 static int psp_tmr_load(struct psp_context *psp) 266 { 267 int ret; 268 struct psp_gfx_cmd_resp *cmd; 269 270 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 271 if (!cmd) 272 return -ENOMEM; 273 274 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, 275 amdgpu_bo_size(psp->tmr_bo)); 276 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 277 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 278 279 ret = psp_cmd_submit_buf(psp, NULL, cmd, 280 psp->fence_buf_mc_addr); 281 if (ret) 282 goto failed; 283 284 kfree(cmd); 285 286 return 0; 287 288 failed: 289 kfree(cmd); 290 return ret; 291 } 292 293 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd, 294 uint64_t asd_mc, uint64_t asd_mc_shared, 295 uint32_t size, uint32_t shared_size) 296 { 297 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 298 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 299 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 300 cmd->cmd.cmd_load_ta.app_len = size; 301 302 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared); 303 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared); 304 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 305 } 306 307 static int psp_asd_init(struct psp_context *psp) 308 { 309 int ret; 310 311 /* 312 * Allocate 16k memory aligned to 4k from Frame Buffer (local 313 * physical) for shared ASD <-> Driver 314 */ 315 ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE, 316 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 317 &psp->asd_shared_bo, 318 &psp->asd_shared_mc_addr, 319 &psp->asd_shared_buf); 320 321 return ret; 322 } 323 324 static int psp_asd_load(struct psp_context *psp) 325 { 326 int ret; 327 struct psp_gfx_cmd_resp *cmd; 328 329 /* If PSP version doesn't match ASD version, asd loading will be failed. 330 * add workaround to bypass it for sriov now. 331 * TODO: add version check to make it common 332 */ 333 if (amdgpu_sriov_vf(psp->adev)) 334 return 0; 335 336 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 337 if (!cmd) 338 return -ENOMEM; 339 340 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 341 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 342 343 psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr, 344 psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE); 345 346 ret = psp_cmd_submit_buf(psp, NULL, cmd, 347 psp->fence_buf_mc_addr); 348 349 kfree(cmd); 350 351 return ret; 352 } 353 354 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 355 uint32_t id, uint32_t value) 356 { 357 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 358 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 359 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 360 } 361 362 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 363 uint32_t value) 364 { 365 struct psp_gfx_cmd_resp *cmd = NULL; 366 int ret = 0; 367 368 if (reg >= PSP_REG_LAST) 369 return -EINVAL; 370 371 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 372 if (!cmd) 373 return -ENOMEM; 374 375 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 376 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 377 378 kfree(cmd); 379 return ret; 380 } 381 382 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 383 uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared, 384 uint32_t xgmi_ta_size, uint32_t shared_size) 385 { 386 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 387 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc); 388 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc); 389 cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size; 390 391 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared); 392 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared); 393 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 394 } 395 396 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 397 { 398 int ret; 399 400 /* 401 * Allocate 16k memory aligned to 4k from Frame Buffer (local 402 * physical) for xgmi ta <-> Driver 403 */ 404 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 405 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 406 &psp->xgmi_context.xgmi_shared_bo, 407 &psp->xgmi_context.xgmi_shared_mc_addr, 408 &psp->xgmi_context.xgmi_shared_buf); 409 410 return ret; 411 } 412 413 static int psp_xgmi_load(struct psp_context *psp) 414 { 415 int ret; 416 struct psp_gfx_cmd_resp *cmd; 417 418 /* 419 * TODO: bypass the loading in sriov for now 420 */ 421 if (amdgpu_sriov_vf(psp->adev)) 422 return 0; 423 424 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 425 if (!cmd) 426 return -ENOMEM; 427 428 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 429 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 430 431 psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 432 psp->xgmi_context.xgmi_shared_mc_addr, 433 psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE); 434 435 ret = psp_cmd_submit_buf(psp, NULL, cmd, 436 psp->fence_buf_mc_addr); 437 438 if (!ret) { 439 psp->xgmi_context.initialized = 1; 440 psp->xgmi_context.session_id = cmd->resp.session_id; 441 } 442 443 kfree(cmd); 444 445 return ret; 446 } 447 448 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 449 uint32_t xgmi_session_id) 450 { 451 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 452 cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id; 453 } 454 455 static int psp_xgmi_unload(struct psp_context *psp) 456 { 457 int ret; 458 struct psp_gfx_cmd_resp *cmd; 459 460 /* 461 * TODO: bypass the unloading in sriov for now 462 */ 463 if (amdgpu_sriov_vf(psp->adev)) 464 return 0; 465 466 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 467 if (!cmd) 468 return -ENOMEM; 469 470 psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 471 472 ret = psp_cmd_submit_buf(psp, NULL, cmd, 473 psp->fence_buf_mc_addr); 474 475 kfree(cmd); 476 477 return ret; 478 } 479 480 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 481 uint32_t ta_cmd_id, 482 uint32_t xgmi_session_id) 483 { 484 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 485 cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id; 486 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 487 /* Note: cmd_invoke_cmd.buf is not used for now */ 488 } 489 490 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 491 { 492 int ret; 493 struct psp_gfx_cmd_resp *cmd; 494 495 /* 496 * TODO: bypass the loading in sriov for now 497 */ 498 if (amdgpu_sriov_vf(psp->adev)) 499 return 0; 500 501 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 502 if (!cmd) 503 return -ENOMEM; 504 505 psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id, 506 psp->xgmi_context.session_id); 507 508 ret = psp_cmd_submit_buf(psp, NULL, cmd, 509 psp->fence_buf_mc_addr); 510 511 kfree(cmd); 512 513 return ret; 514 } 515 516 static int psp_xgmi_terminate(struct psp_context *psp) 517 { 518 int ret; 519 520 if (!psp->xgmi_context.initialized) 521 return 0; 522 523 ret = psp_xgmi_unload(psp); 524 if (ret) 525 return ret; 526 527 psp->xgmi_context.initialized = 0; 528 529 /* free xgmi shared memory */ 530 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 531 &psp->xgmi_context.xgmi_shared_mc_addr, 532 &psp->xgmi_context.xgmi_shared_buf); 533 534 return 0; 535 } 536 537 static int psp_xgmi_initialize(struct psp_context *psp) 538 { 539 struct ta_xgmi_shared_memory *xgmi_cmd; 540 int ret; 541 542 if (!psp->adev->psp.ta_fw) 543 return -ENOENT; 544 545 if (!psp->xgmi_context.initialized) { 546 ret = psp_xgmi_init_shared_buf(psp); 547 if (ret) 548 return ret; 549 } 550 551 /* Load XGMI TA */ 552 ret = psp_xgmi_load(psp); 553 if (ret) 554 return ret; 555 556 /* Initialize XGMI session */ 557 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 558 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 559 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 560 561 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 562 563 return ret; 564 } 565 566 // ras begin 567 static void psp_prep_ras_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 568 uint64_t ras_ta_mc, uint64_t ras_mc_shared, 569 uint32_t ras_ta_size, uint32_t shared_size) 570 { 571 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 572 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ras_ta_mc); 573 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ras_ta_mc); 574 cmd->cmd.cmd_load_ta.app_len = ras_ta_size; 575 576 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ras_mc_shared); 577 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ras_mc_shared); 578 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 579 } 580 581 static int psp_ras_init_shared_buf(struct psp_context *psp) 582 { 583 int ret; 584 585 /* 586 * Allocate 16k memory aligned to 4k from Frame Buffer (local 587 * physical) for ras ta <-> Driver 588 */ 589 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 590 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 591 &psp->ras.ras_shared_bo, 592 &psp->ras.ras_shared_mc_addr, 593 &psp->ras.ras_shared_buf); 594 595 return ret; 596 } 597 598 static int psp_ras_load(struct psp_context *psp) 599 { 600 int ret; 601 struct psp_gfx_cmd_resp *cmd; 602 603 /* 604 * TODO: bypass the loading in sriov for now 605 */ 606 if (amdgpu_sriov_vf(psp->adev)) 607 return 0; 608 609 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 610 if (!cmd) 611 return -ENOMEM; 612 613 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 614 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 615 616 psp_prep_ras_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 617 psp->ras.ras_shared_mc_addr, 618 psp->ta_ras_ucode_size, PSP_RAS_SHARED_MEM_SIZE); 619 620 ret = psp_cmd_submit_buf(psp, NULL, cmd, 621 psp->fence_buf_mc_addr); 622 623 if (!ret) { 624 psp->ras.ras_initialized = 1; 625 psp->ras.session_id = cmd->resp.session_id; 626 } 627 628 kfree(cmd); 629 630 return ret; 631 } 632 633 static void psp_prep_ras_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 634 uint32_t ras_session_id) 635 { 636 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 637 cmd->cmd.cmd_unload_ta.session_id = ras_session_id; 638 } 639 640 static int psp_ras_unload(struct psp_context *psp) 641 { 642 int ret; 643 struct psp_gfx_cmd_resp *cmd; 644 645 /* 646 * TODO: bypass the unloading in sriov for now 647 */ 648 if (amdgpu_sriov_vf(psp->adev)) 649 return 0; 650 651 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 652 if (!cmd) 653 return -ENOMEM; 654 655 psp_prep_ras_ta_unload_cmd_buf(cmd, psp->ras.session_id); 656 657 ret = psp_cmd_submit_buf(psp, NULL, cmd, 658 psp->fence_buf_mc_addr); 659 660 kfree(cmd); 661 662 return ret; 663 } 664 665 static void psp_prep_ras_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 666 uint32_t ta_cmd_id, 667 uint32_t ras_session_id) 668 { 669 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 670 cmd->cmd.cmd_invoke_cmd.session_id = ras_session_id; 671 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 672 /* Note: cmd_invoke_cmd.buf is not used for now */ 673 } 674 675 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 676 { 677 int ret; 678 struct psp_gfx_cmd_resp *cmd; 679 680 /* 681 * TODO: bypass the loading in sriov for now 682 */ 683 if (amdgpu_sriov_vf(psp->adev)) 684 return 0; 685 686 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 687 if (!cmd) 688 return -ENOMEM; 689 690 psp_prep_ras_ta_invoke_cmd_buf(cmd, ta_cmd_id, 691 psp->ras.session_id); 692 693 ret = psp_cmd_submit_buf(psp, NULL, cmd, 694 psp->fence_buf_mc_addr); 695 696 kfree(cmd); 697 698 return ret; 699 } 700 701 int psp_ras_enable_features(struct psp_context *psp, 702 union ta_ras_cmd_input *info, bool enable) 703 { 704 struct ta_ras_shared_memory *ras_cmd; 705 int ret; 706 707 if (!psp->ras.ras_initialized) 708 return -EINVAL; 709 710 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 711 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 712 713 if (enable) 714 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 715 else 716 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 717 718 ras_cmd->ras_in_message = *info; 719 720 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 721 if (ret) 722 return -EINVAL; 723 724 return ras_cmd->ras_status; 725 } 726 727 static int psp_ras_terminate(struct psp_context *psp) 728 { 729 int ret; 730 731 if (!psp->ras.ras_initialized) 732 return 0; 733 734 ret = psp_ras_unload(psp); 735 if (ret) 736 return ret; 737 738 psp->ras.ras_initialized = 0; 739 740 /* free ras shared memory */ 741 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 742 &psp->ras.ras_shared_mc_addr, 743 &psp->ras.ras_shared_buf); 744 745 return 0; 746 } 747 748 static int psp_ras_initialize(struct psp_context *psp) 749 { 750 int ret; 751 752 if (!psp->ras.ras_initialized) { 753 ret = psp_ras_init_shared_buf(psp); 754 if (ret) 755 return ret; 756 } 757 758 ret = psp_ras_load(psp); 759 if (ret) 760 return ret; 761 762 return 0; 763 } 764 // ras end 765 766 static int psp_hw_start(struct psp_context *psp) 767 { 768 struct amdgpu_device *adev = psp->adev; 769 int ret; 770 771 if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) { 772 if (psp->kdb_bin_size && 773 (psp->funcs->bootloader_load_kdb != NULL)) { 774 ret = psp_bootloader_load_kdb(psp); 775 if (ret) { 776 DRM_ERROR("PSP load kdb failed!\n"); 777 return ret; 778 } 779 } 780 781 ret = psp_bootloader_load_sysdrv(psp); 782 if (ret) { 783 DRM_ERROR("PSP load sysdrv failed!\n"); 784 return ret; 785 } 786 787 ret = psp_bootloader_load_sos(psp); 788 if (ret) { 789 DRM_ERROR("PSP load sos failed!\n"); 790 return ret; 791 } 792 } 793 794 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 795 if (ret) { 796 DRM_ERROR("PSP create ring failed!\n"); 797 return ret; 798 } 799 800 ret = psp_tmr_init(psp); 801 if (ret) { 802 DRM_ERROR("PSP tmr init failed!\n"); 803 return ret; 804 } 805 806 ret = psp_tmr_load(psp); 807 if (ret) { 808 DRM_ERROR("PSP load tmr failed!\n"); 809 return ret; 810 } 811 812 ret = psp_asd_init(psp); 813 if (ret) { 814 DRM_ERROR("PSP asd init failed!\n"); 815 return ret; 816 } 817 818 ret = psp_asd_load(psp); 819 if (ret) { 820 DRM_ERROR("PSP load asd failed!\n"); 821 return ret; 822 } 823 824 if (adev->gmc.xgmi.num_physical_nodes > 1) { 825 ret = psp_xgmi_initialize(psp); 826 /* Warning the XGMI seesion initialize failure 827 * Instead of stop driver initialization 828 */ 829 if (ret) 830 dev_err(psp->adev->dev, 831 "XGMI: Failed to initialize XGMI session\n"); 832 } 833 834 835 if (psp->adev->psp.ta_fw) { 836 ret = psp_ras_initialize(psp); 837 if (ret) 838 dev_err(psp->adev->dev, 839 "RAS: Failed to initialize RAS\n"); 840 } 841 842 return 0; 843 } 844 845 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 846 enum psp_gfx_fw_type *type) 847 { 848 switch (ucode->ucode_id) { 849 case AMDGPU_UCODE_ID_SDMA0: 850 *type = GFX_FW_TYPE_SDMA0; 851 break; 852 case AMDGPU_UCODE_ID_SDMA1: 853 *type = GFX_FW_TYPE_SDMA1; 854 break; 855 case AMDGPU_UCODE_ID_CP_CE: 856 *type = GFX_FW_TYPE_CP_CE; 857 break; 858 case AMDGPU_UCODE_ID_CP_PFP: 859 *type = GFX_FW_TYPE_CP_PFP; 860 break; 861 case AMDGPU_UCODE_ID_CP_ME: 862 *type = GFX_FW_TYPE_CP_ME; 863 break; 864 case AMDGPU_UCODE_ID_CP_MEC1: 865 *type = GFX_FW_TYPE_CP_MEC; 866 break; 867 case AMDGPU_UCODE_ID_CP_MEC1_JT: 868 *type = GFX_FW_TYPE_CP_MEC_ME1; 869 break; 870 case AMDGPU_UCODE_ID_CP_MEC2: 871 *type = GFX_FW_TYPE_CP_MEC; 872 break; 873 case AMDGPU_UCODE_ID_CP_MEC2_JT: 874 *type = GFX_FW_TYPE_CP_MEC_ME2; 875 break; 876 case AMDGPU_UCODE_ID_RLC_G: 877 *type = GFX_FW_TYPE_RLC_G; 878 break; 879 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 880 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 881 break; 882 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 883 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 884 break; 885 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 886 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 887 break; 888 case AMDGPU_UCODE_ID_SMC: 889 *type = GFX_FW_TYPE_SMU; 890 break; 891 case AMDGPU_UCODE_ID_UVD: 892 *type = GFX_FW_TYPE_UVD; 893 break; 894 case AMDGPU_UCODE_ID_UVD1: 895 *type = GFX_FW_TYPE_UVD1; 896 break; 897 case AMDGPU_UCODE_ID_VCE: 898 *type = GFX_FW_TYPE_VCE; 899 break; 900 case AMDGPU_UCODE_ID_VCN: 901 *type = GFX_FW_TYPE_VCN; 902 break; 903 case AMDGPU_UCODE_ID_DMCU_ERAM: 904 *type = GFX_FW_TYPE_DMCU_ERAM; 905 break; 906 case AMDGPU_UCODE_ID_DMCU_INTV: 907 *type = GFX_FW_TYPE_DMCU_ISR; 908 break; 909 case AMDGPU_UCODE_ID_VCN0_RAM: 910 *type = GFX_FW_TYPE_VCN0_RAM; 911 break; 912 case AMDGPU_UCODE_ID_VCN1_RAM: 913 *type = GFX_FW_TYPE_VCN1_RAM; 914 break; 915 case AMDGPU_UCODE_ID_MAXIMUM: 916 default: 917 return -EINVAL; 918 } 919 920 return 0; 921 } 922 923 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 924 struct psp_gfx_cmd_resp *cmd) 925 { 926 int ret; 927 uint64_t fw_mem_mc_addr = ucode->mc_addr; 928 929 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 930 931 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 932 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 933 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 934 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 935 936 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 937 if (ret) 938 DRM_ERROR("Unknown firmware type\n"); 939 940 return ret; 941 } 942 943 static int psp_execute_np_fw_load(struct psp_context *psp, 944 struct amdgpu_firmware_info *ucode) 945 { 946 int ret = 0; 947 948 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 949 if (ret) 950 return ret; 951 952 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 953 psp->fence_buf_mc_addr); 954 955 return ret; 956 } 957 958 static int psp_np_fw_load(struct psp_context *psp) 959 { 960 int i, ret; 961 struct amdgpu_firmware_info *ucode; 962 struct amdgpu_device* adev = psp->adev; 963 964 if (psp->autoload_supported) { 965 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 966 if (!ucode->fw) 967 goto out; 968 969 ret = psp_execute_np_fw_load(psp, ucode); 970 if (ret) 971 return ret; 972 } 973 974 out: 975 for (i = 0; i < adev->firmware.max_ucodes; i++) { 976 ucode = &adev->firmware.ucode[i]; 977 if (!ucode->fw) 978 continue; 979 980 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 981 (psp_smu_reload_quirk(psp) || psp->autoload_supported)) 982 continue; 983 if (amdgpu_sriov_vf(adev) && 984 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 985 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 986 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) 987 /*skip ucode loading in SRIOV VF */ 988 continue; 989 if (psp->autoload_supported && 990 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 991 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 992 /* skip mec JT when autoload is enabled */ 993 continue; 994 995 ret = psp_execute_np_fw_load(psp, ucode); 996 if (ret) 997 return ret; 998 999 /* Start rlc autoload after psp recieved all the gfx firmware */ 1000 if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) { 1001 ret = psp_rlc_autoload(psp); 1002 if (ret) { 1003 DRM_ERROR("Failed to start rlc autoload\n"); 1004 return ret; 1005 } 1006 } 1007 #if 0 1008 /* check if firmware loaded sucessfully */ 1009 if (!amdgpu_psp_check_fw_loading_status(adev, i)) 1010 return -EINVAL; 1011 #endif 1012 } 1013 1014 return 0; 1015 } 1016 1017 static int psp_load_fw(struct amdgpu_device *adev) 1018 { 1019 int ret; 1020 struct psp_context *psp = &adev->psp; 1021 1022 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) { 1023 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 1024 goto skip_memalloc; 1025 } 1026 1027 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1028 if (!psp->cmd) 1029 return -ENOMEM; 1030 1031 /* this fw pri bo is not used under SRIOV */ 1032 if (!amdgpu_sriov_vf(psp->adev)) { 1033 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 1034 AMDGPU_GEM_DOMAIN_GTT, 1035 &psp->fw_pri_bo, 1036 &psp->fw_pri_mc_addr, 1037 &psp->fw_pri_buf); 1038 if (ret) 1039 goto failed; 1040 } 1041 1042 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 1043 AMDGPU_GEM_DOMAIN_VRAM, 1044 &psp->fence_buf_bo, 1045 &psp->fence_buf_mc_addr, 1046 &psp->fence_buf); 1047 if (ret) 1048 goto failed; 1049 1050 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 1051 AMDGPU_GEM_DOMAIN_VRAM, 1052 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 1053 (void **)&psp->cmd_buf_mem); 1054 if (ret) 1055 goto failed; 1056 1057 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 1058 1059 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 1060 if (ret) { 1061 DRM_ERROR("PSP ring init failed!\n"); 1062 goto failed; 1063 } 1064 1065 skip_memalloc: 1066 ret = psp_hw_start(psp); 1067 if (ret) 1068 goto failed; 1069 1070 ret = psp_np_fw_load(psp); 1071 if (ret) 1072 goto failed; 1073 1074 return 0; 1075 1076 failed: 1077 /* 1078 * all cleanup jobs (xgmi terminate, ras terminate, 1079 * ring destroy, cmd/fence/fw buffers destory, 1080 * psp->cmd destory) are delayed to psp_hw_fini 1081 */ 1082 return ret; 1083 } 1084 1085 static int psp_hw_init(void *handle) 1086 { 1087 int ret; 1088 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1089 1090 mutex_lock(&adev->firmware.mutex); 1091 /* 1092 * This sequence is just used on hw_init only once, no need on 1093 * resume. 1094 */ 1095 ret = amdgpu_ucode_init_bo(adev); 1096 if (ret) 1097 goto failed; 1098 1099 ret = psp_load_fw(adev); 1100 if (ret) { 1101 DRM_ERROR("PSP firmware loading failed\n"); 1102 goto failed; 1103 } 1104 1105 mutex_unlock(&adev->firmware.mutex); 1106 return 0; 1107 1108 failed: 1109 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 1110 mutex_unlock(&adev->firmware.mutex); 1111 return -EINVAL; 1112 } 1113 1114 static int psp_hw_fini(void *handle) 1115 { 1116 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1117 struct psp_context *psp = &adev->psp; 1118 1119 if (adev->gmc.xgmi.num_physical_nodes > 1 && 1120 psp->xgmi_context.initialized == 1) 1121 psp_xgmi_terminate(psp); 1122 1123 if (psp->adev->psp.ta_fw) 1124 psp_ras_terminate(psp); 1125 1126 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 1127 1128 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 1129 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 1130 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 1131 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 1132 &psp->fence_buf_mc_addr, &psp->fence_buf); 1133 amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr, 1134 &psp->asd_shared_buf); 1135 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 1136 (void **)&psp->cmd_buf_mem); 1137 1138 kfree(psp->cmd); 1139 psp->cmd = NULL; 1140 1141 return 0; 1142 } 1143 1144 static int psp_suspend(void *handle) 1145 { 1146 int ret; 1147 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1148 struct psp_context *psp = &adev->psp; 1149 1150 if (adev->gmc.xgmi.num_physical_nodes > 1 && 1151 psp->xgmi_context.initialized == 1) { 1152 ret = psp_xgmi_terminate(psp); 1153 if (ret) { 1154 DRM_ERROR("Failed to terminate xgmi ta\n"); 1155 return ret; 1156 } 1157 } 1158 1159 if (psp->adev->psp.ta_fw) { 1160 ret = psp_ras_terminate(psp); 1161 if (ret) { 1162 DRM_ERROR("Failed to terminate ras ta\n"); 1163 return ret; 1164 } 1165 } 1166 1167 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 1168 if (ret) { 1169 DRM_ERROR("PSP ring stop failed\n"); 1170 return ret; 1171 } 1172 1173 return 0; 1174 } 1175 1176 static int psp_resume(void *handle) 1177 { 1178 int ret; 1179 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1180 struct psp_context *psp = &adev->psp; 1181 1182 DRM_INFO("PSP is resuming...\n"); 1183 1184 mutex_lock(&adev->firmware.mutex); 1185 1186 ret = psp_hw_start(psp); 1187 if (ret) 1188 goto failed; 1189 1190 ret = psp_np_fw_load(psp); 1191 if (ret) 1192 goto failed; 1193 1194 mutex_unlock(&adev->firmware.mutex); 1195 1196 return 0; 1197 1198 failed: 1199 DRM_ERROR("PSP resume failed\n"); 1200 mutex_unlock(&adev->firmware.mutex); 1201 return ret; 1202 } 1203 1204 int psp_gpu_reset(struct amdgpu_device *adev) 1205 { 1206 int ret; 1207 1208 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 1209 return 0; 1210 1211 mutex_lock(&adev->psp.mutex); 1212 ret = psp_mode1_reset(&adev->psp); 1213 mutex_unlock(&adev->psp.mutex); 1214 1215 return ret; 1216 } 1217 1218 int psp_rlc_autoload_start(struct psp_context *psp) 1219 { 1220 int ret; 1221 struct psp_gfx_cmd_resp *cmd; 1222 1223 if (amdgpu_sriov_vf(psp->adev)) 1224 return 0; 1225 1226 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1227 if (!cmd) 1228 return -ENOMEM; 1229 1230 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 1231 1232 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1233 psp->fence_buf_mc_addr); 1234 kfree(cmd); 1235 return ret; 1236 } 1237 1238 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 1239 uint64_t cmd_gpu_addr, int cmd_size) 1240 { 1241 struct amdgpu_firmware_info ucode = {0}; 1242 1243 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 1244 AMDGPU_UCODE_ID_VCN0_RAM; 1245 ucode.mc_addr = cmd_gpu_addr; 1246 ucode.ucode_size = cmd_size; 1247 1248 return psp_execute_np_fw_load(&adev->psp, &ucode); 1249 } 1250 1251 static bool psp_check_fw_loading_status(struct amdgpu_device *adev, 1252 enum AMDGPU_UCODE_ID ucode_type) 1253 { 1254 struct amdgpu_firmware_info *ucode = NULL; 1255 1256 if (!adev->firmware.fw_size) 1257 return false; 1258 1259 ucode = &adev->firmware.ucode[ucode_type]; 1260 if (!ucode->fw || !ucode->ucode_size) 1261 return false; 1262 1263 return psp_compare_sram_data(&adev->psp, ucode, ucode_type); 1264 } 1265 1266 static int psp_set_clockgating_state(void *handle, 1267 enum amd_clockgating_state state) 1268 { 1269 return 0; 1270 } 1271 1272 static int psp_set_powergating_state(void *handle, 1273 enum amd_powergating_state state) 1274 { 1275 return 0; 1276 } 1277 1278 const struct amd_ip_funcs psp_ip_funcs = { 1279 .name = "psp", 1280 .early_init = psp_early_init, 1281 .late_init = NULL, 1282 .sw_init = psp_sw_init, 1283 .sw_fini = psp_sw_fini, 1284 .hw_init = psp_hw_init, 1285 .hw_fini = psp_hw_fini, 1286 .suspend = psp_suspend, 1287 .resume = psp_resume, 1288 .is_idle = NULL, 1289 .check_soft_reset = NULL, 1290 .wait_for_idle = NULL, 1291 .soft_reset = NULL, 1292 .set_clockgating_state = psp_set_clockgating_state, 1293 .set_powergating_state = psp_set_powergating_state, 1294 }; 1295 1296 static const struct amdgpu_psp_funcs psp_funcs = { 1297 .check_fw_loading_status = psp_check_fw_loading_status, 1298 }; 1299 1300 static void psp_set_funcs(struct amdgpu_device *adev) 1301 { 1302 if (NULL == adev->firmware.funcs) 1303 adev->firmware.funcs = &psp_funcs; 1304 } 1305 1306 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 1307 { 1308 .type = AMD_IP_BLOCK_TYPE_PSP, 1309 .major = 3, 1310 .minor = 1, 1311 .rev = 0, 1312 .funcs = &psp_ip_funcs, 1313 }; 1314 1315 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 1316 { 1317 .type = AMD_IP_BLOCK_TYPE_PSP, 1318 .major = 10, 1319 .minor = 0, 1320 .rev = 0, 1321 .funcs = &psp_ip_funcs, 1322 }; 1323 1324 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 1325 { 1326 .type = AMD_IP_BLOCK_TYPE_PSP, 1327 .major = 11, 1328 .minor = 0, 1329 .rev = 0, 1330 .funcs = &psp_ip_funcs, 1331 }; 1332