1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 42 #include "amdgpu_ras.h" 43 #include "amdgpu_securedisplay.h" 44 #include "amdgpu_atomfirmware.h" 45 46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 47 48 static int psp_sysfs_init(struct amdgpu_device *adev); 49 static void psp_sysfs_fini(struct amdgpu_device *adev); 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 /* 56 * Due to DF Cstate management centralized to PMFW, the firmware 57 * loading sequence will be updated as below: 58 * - Load KDB 59 * - Load SYS_DRV 60 * - Load tOS 61 * - Load PMFW 62 * - Setup TMR 63 * - Load other non-psp fw 64 * - Load ASD 65 * - Load XGMI/RAS/HDCP/DTM TA if any 66 * 67 * This new sequence is required for 68 * - Arcturus and onwards 69 */ 70 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 71 { 72 struct amdgpu_device *adev = psp->adev; 73 74 if (amdgpu_sriov_vf(adev)) { 75 psp->pmfw_centralized_cstate_management = false; 76 return; 77 } 78 79 switch (adev->ip_versions[MP0_HWIP][0]) { 80 case IP_VERSION(11, 0, 0): 81 case IP_VERSION(11, 0, 4): 82 case IP_VERSION(11, 0, 5): 83 case IP_VERSION(11, 0, 7): 84 case IP_VERSION(11, 0, 9): 85 case IP_VERSION(11, 0, 11): 86 case IP_VERSION(11, 0, 12): 87 case IP_VERSION(11, 0, 13): 88 case IP_VERSION(13, 0, 0): 89 case IP_VERSION(13, 0, 2): 90 case IP_VERSION(13, 0, 7): 91 psp->pmfw_centralized_cstate_management = true; 92 break; 93 default: 94 psp->pmfw_centralized_cstate_management = false; 95 break; 96 } 97 } 98 99 static int psp_early_init(void *handle) 100 { 101 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 102 struct psp_context *psp = &adev->psp; 103 104 switch (adev->ip_versions[MP0_HWIP][0]) { 105 case IP_VERSION(9, 0, 0): 106 psp_v3_1_set_psp_funcs(psp); 107 psp->autoload_supported = false; 108 break; 109 case IP_VERSION(10, 0, 0): 110 case IP_VERSION(10, 0, 1): 111 psp_v10_0_set_psp_funcs(psp); 112 psp->autoload_supported = false; 113 break; 114 case IP_VERSION(11, 0, 2): 115 case IP_VERSION(11, 0, 4): 116 psp_v11_0_set_psp_funcs(psp); 117 psp->autoload_supported = false; 118 break; 119 case IP_VERSION(11, 0, 0): 120 case IP_VERSION(11, 0, 5): 121 case IP_VERSION(11, 0, 9): 122 case IP_VERSION(11, 0, 7): 123 case IP_VERSION(11, 0, 11): 124 case IP_VERSION(11, 5, 0): 125 case IP_VERSION(11, 0, 12): 126 case IP_VERSION(11, 0, 13): 127 psp_v11_0_set_psp_funcs(psp); 128 psp->autoload_supported = true; 129 break; 130 case IP_VERSION(11, 0, 3): 131 case IP_VERSION(12, 0, 1): 132 psp_v12_0_set_psp_funcs(psp); 133 break; 134 case IP_VERSION(13, 0, 2): 135 psp_v13_0_set_psp_funcs(psp); 136 break; 137 case IP_VERSION(13, 0, 1): 138 case IP_VERSION(13, 0, 3): 139 case IP_VERSION(13, 0, 5): 140 case IP_VERSION(13, 0, 8): 141 psp_v13_0_set_psp_funcs(psp); 142 psp->autoload_supported = true; 143 break; 144 case IP_VERSION(11, 0, 8): 145 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 146 psp_v11_0_8_set_psp_funcs(psp); 147 psp->autoload_supported = false; 148 } 149 break; 150 case IP_VERSION(13, 0, 0): 151 case IP_VERSION(13, 0, 7): 152 psp_v13_0_set_psp_funcs(psp); 153 psp->autoload_supported = true; 154 break; 155 case IP_VERSION(13, 0, 4): 156 psp_v13_0_4_set_psp_funcs(psp); 157 psp->autoload_supported = true; 158 break; 159 default: 160 return -EINVAL; 161 } 162 163 psp->adev = adev; 164 165 psp_check_pmfw_centralized_cstate_management(psp); 166 167 return 0; 168 } 169 170 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 171 { 172 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 173 &mem_ctx->shared_buf); 174 } 175 176 static void psp_free_shared_bufs(struct psp_context *psp) 177 { 178 void *tmr_buf; 179 void **pptr; 180 181 /* free TMR memory buffer */ 182 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 183 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 184 185 /* free xgmi shared memory */ 186 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 187 188 /* free ras shared memory */ 189 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 190 191 /* free hdcp shared memory */ 192 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 193 194 /* free dtm shared memory */ 195 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 196 197 /* free rap shared memory */ 198 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 199 200 /* free securedisplay shared memory */ 201 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 202 203 204 } 205 206 static void psp_memory_training_fini(struct psp_context *psp) 207 { 208 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 209 210 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 211 kfree(ctx->sys_cache); 212 ctx->sys_cache = NULL; 213 } 214 215 static int psp_memory_training_init(struct psp_context *psp) 216 { 217 int ret; 218 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 219 220 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 221 DRM_DEBUG("memory training is not supported!\n"); 222 return 0; 223 } 224 225 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 226 if (ctx->sys_cache == NULL) { 227 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 228 ret = -ENOMEM; 229 goto Err_out; 230 } 231 232 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 233 ctx->train_data_size, 234 ctx->p2c_train_data_offset, 235 ctx->c2p_train_data_offset); 236 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 237 return 0; 238 239 Err_out: 240 psp_memory_training_fini(psp); 241 return ret; 242 } 243 244 /* 245 * Helper funciton to query psp runtime database entry 246 * 247 * @adev: amdgpu_device pointer 248 * @entry_type: the type of psp runtime database entry 249 * @db_entry: runtime database entry pointer 250 * 251 * Return false if runtime database doesn't exit or entry is invalid 252 * or true if the specific database entry is found, and copy to @db_entry 253 */ 254 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 255 enum psp_runtime_entry_type entry_type, 256 void *db_entry) 257 { 258 uint64_t db_header_pos, db_dir_pos; 259 struct psp_runtime_data_header db_header = {0}; 260 struct psp_runtime_data_directory db_dir = {0}; 261 bool ret = false; 262 int i; 263 264 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 265 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 266 267 /* read runtime db header from vram */ 268 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 269 sizeof(struct psp_runtime_data_header), false); 270 271 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 272 /* runtime db doesn't exist, exit */ 273 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 274 return false; 275 } 276 277 /* read runtime database entry from vram */ 278 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 279 sizeof(struct psp_runtime_data_directory), false); 280 281 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 282 /* invalid db entry count, exit */ 283 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 284 return false; 285 } 286 287 /* look up for requested entry type */ 288 for (i = 0; i < db_dir.entry_count && !ret; i++) { 289 if (db_dir.entry_list[i].entry_type == entry_type) { 290 switch (entry_type) { 291 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 292 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 293 /* invalid db entry size */ 294 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 295 return false; 296 } 297 /* read runtime database entry */ 298 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 299 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 300 ret = true; 301 break; 302 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 303 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 304 /* invalid db entry size */ 305 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 306 return false; 307 } 308 /* read runtime database entry */ 309 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 310 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 311 ret = true; 312 break; 313 default: 314 ret = false; 315 break; 316 } 317 } 318 } 319 320 return ret; 321 } 322 323 static int psp_init_sriov_microcode(struct psp_context *psp) 324 { 325 struct amdgpu_device *adev = psp->adev; 326 int ret = 0; 327 328 switch (adev->ip_versions[MP0_HWIP][0]) { 329 case IP_VERSION(9, 0, 0): 330 ret = psp_init_cap_microcode(psp, "vega10"); 331 break; 332 case IP_VERSION(11, 0, 9): 333 ret = psp_init_cap_microcode(psp, "navi12"); 334 break; 335 case IP_VERSION(11, 0, 7): 336 ret = psp_init_cap_microcode(psp, "sienna_cichlid"); 337 break; 338 case IP_VERSION(13, 0, 2): 339 ret = psp_init_cap_microcode(psp, "aldebaran"); 340 ret &= psp_init_ta_microcode(psp, "aldebaran"); 341 break; 342 default: 343 BUG(); 344 break; 345 } 346 347 return ret; 348 } 349 350 static int psp_sw_init(void *handle) 351 { 352 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 353 struct psp_context *psp = &adev->psp; 354 int ret; 355 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 356 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 357 struct psp_runtime_scpm_entry scpm_entry; 358 359 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 360 if (!psp->cmd) { 361 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 362 ret = -ENOMEM; 363 } 364 365 if (amdgpu_sriov_vf(adev)) 366 ret = psp_init_sriov_microcode(psp); 367 else 368 ret = psp_init_microcode(psp); 369 if (ret) { 370 DRM_ERROR("Failed to load psp firmware!\n"); 371 return ret; 372 } 373 374 adev->psp.xgmi_context.supports_extended_data = 375 !adev->gmc.xgmi.connected_to_cpu && 376 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 377 378 memset(&scpm_entry, 0, sizeof(scpm_entry)); 379 if ((psp_get_runtime_db_entry(adev, 380 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 381 &scpm_entry)) && 382 (SCPM_DISABLE != scpm_entry.scpm_status)) { 383 adev->scpm_enabled = true; 384 adev->scpm_status = scpm_entry.scpm_status; 385 } else { 386 adev->scpm_enabled = false; 387 adev->scpm_status = SCPM_DISABLE; 388 } 389 390 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 391 392 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 393 if (psp_get_runtime_db_entry(adev, 394 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 395 &boot_cfg_entry)) { 396 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 397 if ((psp->boot_cfg_bitmask) & 398 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 399 /* If psp runtime database exists, then 400 * only enable two stage memory training 401 * when TWO_STAGE_DRAM_TRAINING bit is set 402 * in runtime database */ 403 mem_training_ctx->enable_mem_training = true; 404 } 405 406 } else { 407 /* If psp runtime database doesn't exist or 408 * is invalid, force enable two stage memory 409 * training */ 410 mem_training_ctx->enable_mem_training = true; 411 } 412 413 if (mem_training_ctx->enable_mem_training) { 414 ret = psp_memory_training_init(psp); 415 if (ret) { 416 DRM_ERROR("Failed to initialize memory training!\n"); 417 return ret; 418 } 419 420 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 421 if (ret) { 422 DRM_ERROR("Failed to process memory training!\n"); 423 return ret; 424 } 425 } 426 427 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 428 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 429 ret= psp_sysfs_init(adev); 430 if (ret) { 431 return ret; 432 } 433 } 434 435 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 436 amdgpu_sriov_vf(adev) ? 437 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 438 &psp->fw_pri_bo, 439 &psp->fw_pri_mc_addr, 440 &psp->fw_pri_buf); 441 if (ret) 442 return ret; 443 444 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 445 AMDGPU_GEM_DOMAIN_VRAM, 446 &psp->fence_buf_bo, 447 &psp->fence_buf_mc_addr, 448 &psp->fence_buf); 449 if (ret) 450 goto failed1; 451 452 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 453 AMDGPU_GEM_DOMAIN_VRAM, 454 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 455 (void **)&psp->cmd_buf_mem); 456 if (ret) 457 goto failed2; 458 459 return 0; 460 461 failed2: 462 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 463 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 464 failed1: 465 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 466 &psp->fence_buf_mc_addr, &psp->fence_buf); 467 return ret; 468 } 469 470 static int psp_sw_fini(void *handle) 471 { 472 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 473 struct psp_context *psp = &adev->psp; 474 struct psp_gfx_cmd_resp *cmd = psp->cmd; 475 476 psp_memory_training_fini(psp); 477 if (psp->sos_fw) { 478 release_firmware(psp->sos_fw); 479 psp->sos_fw = NULL; 480 } 481 if (psp->asd_fw) { 482 release_firmware(psp->asd_fw); 483 psp->asd_fw = NULL; 484 } 485 if (psp->ta_fw) { 486 release_firmware(psp->ta_fw); 487 psp->ta_fw = NULL; 488 } 489 if (psp->cap_fw) { 490 release_firmware(psp->cap_fw); 491 psp->cap_fw = NULL; 492 } 493 if (psp->toc_fw) { 494 release_firmware(psp->toc_fw); 495 psp->toc_fw = NULL; 496 } 497 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 498 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 499 psp_sysfs_fini(adev); 500 501 kfree(cmd); 502 cmd = NULL; 503 504 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 505 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 506 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 507 &psp->fence_buf_mc_addr, &psp->fence_buf); 508 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 509 (void **)&psp->cmd_buf_mem); 510 511 return 0; 512 } 513 514 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 515 uint32_t reg_val, uint32_t mask, bool check_changed) 516 { 517 uint32_t val; 518 int i; 519 struct amdgpu_device *adev = psp->adev; 520 521 if (psp->adev->no_hw_access) 522 return 0; 523 524 for (i = 0; i < adev->usec_timeout; i++) { 525 val = RREG32(reg_index); 526 if (check_changed) { 527 if (val != reg_val) 528 return 0; 529 } else { 530 if ((val & mask) == reg_val) 531 return 0; 532 } 533 udelay(1); 534 } 535 536 return -ETIME; 537 } 538 539 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 540 { 541 switch (cmd_id) { 542 case GFX_CMD_ID_LOAD_TA: 543 return "LOAD_TA"; 544 case GFX_CMD_ID_UNLOAD_TA: 545 return "UNLOAD_TA"; 546 case GFX_CMD_ID_INVOKE_CMD: 547 return "INVOKE_CMD"; 548 case GFX_CMD_ID_LOAD_ASD: 549 return "LOAD_ASD"; 550 case GFX_CMD_ID_SETUP_TMR: 551 return "SETUP_TMR"; 552 case GFX_CMD_ID_LOAD_IP_FW: 553 return "LOAD_IP_FW"; 554 case GFX_CMD_ID_DESTROY_TMR: 555 return "DESTROY_TMR"; 556 case GFX_CMD_ID_SAVE_RESTORE: 557 return "SAVE_RESTORE_IP_FW"; 558 case GFX_CMD_ID_SETUP_VMR: 559 return "SETUP_VMR"; 560 case GFX_CMD_ID_DESTROY_VMR: 561 return "DESTROY_VMR"; 562 case GFX_CMD_ID_PROG_REG: 563 return "PROG_REG"; 564 case GFX_CMD_ID_GET_FW_ATTESTATION: 565 return "GET_FW_ATTESTATION"; 566 case GFX_CMD_ID_LOAD_TOC: 567 return "ID_LOAD_TOC"; 568 case GFX_CMD_ID_AUTOLOAD_RLC: 569 return "AUTOLOAD_RLC"; 570 case GFX_CMD_ID_BOOT_CFG: 571 return "BOOT_CFG"; 572 default: 573 return "UNKNOWN CMD"; 574 } 575 } 576 577 static int 578 psp_cmd_submit_buf(struct psp_context *psp, 579 struct amdgpu_firmware_info *ucode, 580 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 581 { 582 int ret; 583 int index, idx; 584 int timeout = 20000; 585 bool ras_intr = false; 586 bool skip_unsupport = false; 587 588 if (psp->adev->no_hw_access) 589 return 0; 590 591 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 592 return 0; 593 594 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 595 596 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 597 598 index = atomic_inc_return(&psp->fence_value); 599 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 600 if (ret) { 601 atomic_dec(&psp->fence_value); 602 goto exit; 603 } 604 605 amdgpu_device_invalidate_hdp(psp->adev, NULL); 606 while (*((unsigned int *)psp->fence_buf) != index) { 607 if (--timeout == 0) 608 break; 609 /* 610 * Shouldn't wait for timeout when err_event_athub occurs, 611 * because gpu reset thread triggered and lock resource should 612 * be released for psp resume sequence. 613 */ 614 ras_intr = amdgpu_ras_intr_triggered(); 615 if (ras_intr) 616 break; 617 usleep_range(10, 100); 618 amdgpu_device_invalidate_hdp(psp->adev, NULL); 619 } 620 621 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 622 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 623 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 624 625 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 626 627 /* In some cases, psp response status is not 0 even there is no 628 * problem while the command is submitted. Some version of PSP FW 629 * doesn't write 0 to that field. 630 * So here we would like to only print a warning instead of an error 631 * during psp initialization to avoid breaking hw_init and it doesn't 632 * return -EINVAL. 633 */ 634 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 635 if (ucode) 636 DRM_WARN("failed to load ucode %s(0x%X) ", 637 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 638 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 639 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 640 psp->cmd_buf_mem->resp.status); 641 /* If any firmware (including CAP) load fails under SRIOV, it should 642 * return failure to stop the VF from initializing. 643 * Also return failure in case of timeout 644 */ 645 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 646 ret = -EINVAL; 647 goto exit; 648 } 649 } 650 651 if (ucode) { 652 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 653 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 654 } 655 656 exit: 657 drm_dev_exit(idx); 658 return ret; 659 } 660 661 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 662 { 663 struct psp_gfx_cmd_resp *cmd = psp->cmd; 664 665 mutex_lock(&psp->mutex); 666 667 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 668 669 return cmd; 670 } 671 672 static void release_psp_cmd_buf(struct psp_context *psp) 673 { 674 mutex_unlock(&psp->mutex); 675 } 676 677 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 678 struct psp_gfx_cmd_resp *cmd, 679 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 680 { 681 struct amdgpu_device *adev = psp->adev; 682 uint32_t size = amdgpu_bo_size(tmr_bo); 683 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 684 685 if (amdgpu_sriov_vf(psp->adev)) 686 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 687 else 688 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 689 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 690 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 691 cmd->cmd.cmd_setup_tmr.buf_size = size; 692 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 693 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 694 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 695 } 696 697 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 698 uint64_t pri_buf_mc, uint32_t size) 699 { 700 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 701 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 702 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 703 cmd->cmd.cmd_load_toc.toc_size = size; 704 } 705 706 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 707 static int psp_load_toc(struct psp_context *psp, 708 uint32_t *tmr_size) 709 { 710 int ret; 711 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 712 713 /* Copy toc to psp firmware private buffer */ 714 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 715 716 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 717 718 ret = psp_cmd_submit_buf(psp, NULL, cmd, 719 psp->fence_buf_mc_addr); 720 if (!ret) 721 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 722 723 release_psp_cmd_buf(psp); 724 725 return ret; 726 } 727 728 /* Set up Trusted Memory Region */ 729 static int psp_tmr_init(struct psp_context *psp) 730 { 731 int ret; 732 int tmr_size; 733 void *tmr_buf; 734 void **pptr; 735 736 /* 737 * According to HW engineer, they prefer the TMR address be "naturally 738 * aligned" , e.g. the start address be an integer divide of TMR size. 739 * 740 * Note: this memory need be reserved till the driver 741 * uninitializes. 742 */ 743 tmr_size = PSP_TMR_SIZE(psp->adev); 744 745 /* For ASICs support RLC autoload, psp will parse the toc 746 * and calculate the total size of TMR needed */ 747 if (!amdgpu_sriov_vf(psp->adev) && 748 psp->toc.start_addr && 749 psp->toc.size_bytes && 750 psp->fw_pri_buf) { 751 ret = psp_load_toc(psp, &tmr_size); 752 if (ret) { 753 DRM_ERROR("Failed to load toc\n"); 754 return ret; 755 } 756 } 757 758 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 759 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 760 AMDGPU_GEM_DOMAIN_VRAM, 761 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 762 763 return ret; 764 } 765 766 static bool psp_skip_tmr(struct psp_context *psp) 767 { 768 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 769 case IP_VERSION(11, 0, 9): 770 case IP_VERSION(11, 0, 7): 771 case IP_VERSION(13, 0, 2): 772 return true; 773 default: 774 return false; 775 } 776 } 777 778 static int psp_tmr_load(struct psp_context *psp) 779 { 780 int ret; 781 struct psp_gfx_cmd_resp *cmd; 782 783 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 784 * Already set up by host driver. 785 */ 786 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 787 return 0; 788 789 cmd = acquire_psp_cmd_buf(psp); 790 791 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 792 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 793 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 794 795 ret = psp_cmd_submit_buf(psp, NULL, cmd, 796 psp->fence_buf_mc_addr); 797 798 release_psp_cmd_buf(psp); 799 800 return ret; 801 } 802 803 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 804 struct psp_gfx_cmd_resp *cmd) 805 { 806 if (amdgpu_sriov_vf(psp->adev)) 807 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 808 else 809 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 810 } 811 812 static int psp_tmr_unload(struct psp_context *psp) 813 { 814 int ret; 815 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 816 817 psp_prep_tmr_unload_cmd_buf(psp, cmd); 818 DRM_INFO("free PSP TMR buffer\n"); 819 820 ret = psp_cmd_submit_buf(psp, NULL, cmd, 821 psp->fence_buf_mc_addr); 822 823 release_psp_cmd_buf(psp); 824 825 return ret; 826 } 827 828 static int psp_tmr_terminate(struct psp_context *psp) 829 { 830 return psp_tmr_unload(psp); 831 } 832 833 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 834 uint64_t *output_ptr) 835 { 836 int ret; 837 struct psp_gfx_cmd_resp *cmd; 838 839 if (!output_ptr) 840 return -EINVAL; 841 842 if (amdgpu_sriov_vf(psp->adev)) 843 return 0; 844 845 cmd = acquire_psp_cmd_buf(psp); 846 847 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 848 849 ret = psp_cmd_submit_buf(psp, NULL, cmd, 850 psp->fence_buf_mc_addr); 851 852 if (!ret) { 853 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 854 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 855 } 856 857 release_psp_cmd_buf(psp); 858 859 return ret; 860 } 861 862 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 863 { 864 struct psp_context *psp = &adev->psp; 865 struct psp_gfx_cmd_resp *cmd; 866 int ret; 867 868 if (amdgpu_sriov_vf(adev)) 869 return 0; 870 871 cmd = acquire_psp_cmd_buf(psp); 872 873 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 874 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 875 876 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 877 if (!ret) { 878 *boot_cfg = 879 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 880 } 881 882 release_psp_cmd_buf(psp); 883 884 return ret; 885 } 886 887 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 888 { 889 int ret; 890 struct psp_context *psp = &adev->psp; 891 struct psp_gfx_cmd_resp *cmd; 892 893 if (amdgpu_sriov_vf(adev)) 894 return 0; 895 896 cmd = acquire_psp_cmd_buf(psp); 897 898 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 899 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 900 cmd->cmd.boot_cfg.boot_config = boot_cfg; 901 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 902 903 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 904 905 release_psp_cmd_buf(psp); 906 907 return ret; 908 } 909 910 static int psp_rl_load(struct amdgpu_device *adev) 911 { 912 int ret; 913 struct psp_context *psp = &adev->psp; 914 struct psp_gfx_cmd_resp *cmd; 915 916 if (!is_psp_fw_valid(psp->rl)) 917 return 0; 918 919 cmd = acquire_psp_cmd_buf(psp); 920 921 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 922 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 923 924 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 925 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 926 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 927 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 928 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 929 930 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 931 932 release_psp_cmd_buf(psp); 933 934 return ret; 935 } 936 937 static int psp_asd_initialize(struct psp_context *psp) 938 { 939 int ret; 940 941 /* If PSP version doesn't match ASD version, asd loading will be failed. 942 * add workaround to bypass it for sriov now. 943 * TODO: add version check to make it common 944 */ 945 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 946 return 0; 947 948 psp->asd_context.mem_context.shared_mc_addr = 0; 949 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 950 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 951 952 ret = psp_ta_load(psp, &psp->asd_context); 953 if (!ret) 954 psp->asd_context.initialized = true; 955 956 return ret; 957 } 958 959 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 960 uint32_t session_id) 961 { 962 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 963 cmd->cmd.cmd_unload_ta.session_id = session_id; 964 } 965 966 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 967 { 968 int ret; 969 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 970 971 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 972 973 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 974 975 release_psp_cmd_buf(psp); 976 977 return ret; 978 } 979 980 static int psp_asd_terminate(struct psp_context *psp) 981 { 982 int ret; 983 984 if (amdgpu_sriov_vf(psp->adev)) 985 return 0; 986 987 if (!psp->asd_context.initialized) 988 return 0; 989 990 ret = psp_ta_unload(psp, &psp->asd_context); 991 if (!ret) 992 psp->asd_context.initialized = false; 993 994 return ret; 995 } 996 997 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 998 uint32_t id, uint32_t value) 999 { 1000 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1001 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1002 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1003 } 1004 1005 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1006 uint32_t value) 1007 { 1008 struct psp_gfx_cmd_resp *cmd; 1009 int ret = 0; 1010 1011 if (reg >= PSP_REG_LAST) 1012 return -EINVAL; 1013 1014 cmd = acquire_psp_cmd_buf(psp); 1015 1016 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1017 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1018 if (ret) 1019 DRM_ERROR("PSP failed to program reg id %d", reg); 1020 1021 release_psp_cmd_buf(psp); 1022 1023 return ret; 1024 } 1025 1026 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1027 uint64_t ta_bin_mc, 1028 struct ta_context *context) 1029 { 1030 cmd->cmd_id = context->ta_load_type; 1031 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1032 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1033 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1034 1035 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1036 lower_32_bits(context->mem_context.shared_mc_addr); 1037 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1038 upper_32_bits(context->mem_context.shared_mc_addr); 1039 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1040 } 1041 1042 int psp_ta_init_shared_buf(struct psp_context *psp, 1043 struct ta_mem_context *mem_ctx) 1044 { 1045 /* 1046 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1047 * physical) for ta to host memory 1048 */ 1049 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1050 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1051 &mem_ctx->shared_bo, 1052 &mem_ctx->shared_mc_addr, 1053 &mem_ctx->shared_buf); 1054 } 1055 1056 static void psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1057 uint32_t ta_cmd_id, 1058 struct ta_context *context) 1059 { 1060 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1061 cmd->cmd.cmd_invoke_cmd.session_id = context->session_id; 1062 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1063 1064 cmd->cmd.cmd_invoke_cmd.buf.num_desc = 1; 1065 cmd->cmd.cmd_invoke_cmd.buf.total_size = context->mem_context.shared_mem_size; 1066 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_size = context->mem_context.shared_mem_size; 1067 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_lo = 1068 lower_32_bits(context->mem_context.shared_mc_addr); 1069 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_hi = 1070 upper_32_bits(context->mem_context.shared_mc_addr); 1071 } 1072 1073 int psp_ta_invoke_indirect(struct psp_context *psp, 1074 uint32_t ta_cmd_id, 1075 struct ta_context *context) 1076 { 1077 int ret; 1078 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1079 1080 psp_prep_ta_invoke_indirect_cmd_buf(cmd, ta_cmd_id, context); 1081 1082 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1083 psp->fence_buf_mc_addr); 1084 1085 context->resp_status = cmd->resp.status; 1086 1087 release_psp_cmd_buf(psp); 1088 1089 return ret; 1090 } 1091 1092 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1093 uint32_t ta_cmd_id, 1094 uint32_t session_id) 1095 { 1096 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1097 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1098 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1099 } 1100 1101 int psp_ta_invoke(struct psp_context *psp, 1102 uint32_t ta_cmd_id, 1103 struct ta_context *context) 1104 { 1105 int ret; 1106 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1107 1108 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1109 1110 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1111 psp->fence_buf_mc_addr); 1112 1113 context->resp_status = cmd->resp.status; 1114 1115 release_psp_cmd_buf(psp); 1116 1117 return ret; 1118 } 1119 1120 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1121 { 1122 int ret; 1123 struct psp_gfx_cmd_resp *cmd; 1124 1125 cmd = acquire_psp_cmd_buf(psp); 1126 1127 psp_copy_fw(psp, context->bin_desc.start_addr, 1128 context->bin_desc.size_bytes); 1129 1130 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1131 1132 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1133 psp->fence_buf_mc_addr); 1134 1135 context->resp_status = cmd->resp.status; 1136 1137 if (!ret) { 1138 context->session_id = cmd->resp.session_id; 1139 } 1140 1141 release_psp_cmd_buf(psp); 1142 1143 return ret; 1144 } 1145 1146 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1147 { 1148 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1149 } 1150 1151 int psp_xgmi_terminate(struct psp_context *psp) 1152 { 1153 int ret; 1154 struct amdgpu_device *adev = psp->adev; 1155 1156 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1157 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1158 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1159 adev->gmc.xgmi.connected_to_cpu)) 1160 return 0; 1161 1162 if (!psp->xgmi_context.context.initialized) 1163 return 0; 1164 1165 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1166 1167 psp->xgmi_context.context.initialized = false; 1168 1169 return ret; 1170 } 1171 1172 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1173 { 1174 struct ta_xgmi_shared_memory *xgmi_cmd; 1175 int ret; 1176 1177 if (!psp->ta_fw || 1178 !psp->xgmi_context.context.bin_desc.size_bytes || 1179 !psp->xgmi_context.context.bin_desc.start_addr) 1180 return -ENOENT; 1181 1182 if (!load_ta) 1183 goto invoke; 1184 1185 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1186 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1187 1188 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1189 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1190 if (ret) 1191 return ret; 1192 } 1193 1194 /* Load XGMI TA */ 1195 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1196 if (!ret) 1197 psp->xgmi_context.context.initialized = true; 1198 else 1199 return ret; 1200 1201 invoke: 1202 /* Initialize XGMI session */ 1203 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1204 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1205 xgmi_cmd->flag_extend_link_record = set_extended_data; 1206 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1207 1208 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1209 1210 return ret; 1211 } 1212 1213 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1214 { 1215 struct ta_xgmi_shared_memory *xgmi_cmd; 1216 int ret; 1217 1218 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1219 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1220 1221 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1222 1223 /* Invoke xgmi ta to get hive id */ 1224 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1225 if (ret) 1226 return ret; 1227 1228 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1229 1230 return 0; 1231 } 1232 1233 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1234 { 1235 struct ta_xgmi_shared_memory *xgmi_cmd; 1236 int ret; 1237 1238 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1239 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1240 1241 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1242 1243 /* Invoke xgmi ta to get the node id */ 1244 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1245 if (ret) 1246 return ret; 1247 1248 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1249 1250 return 0; 1251 } 1252 1253 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1254 { 1255 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1256 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1257 } 1258 1259 /* 1260 * Chips that support extended topology information require the driver to 1261 * reflect topology information in the opposite direction. This is 1262 * because the TA has already exceeded its link record limit and if the 1263 * TA holds bi-directional information, the driver would have to do 1264 * multiple fetches instead of just two. 1265 */ 1266 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1267 struct psp_xgmi_node_info node_info) 1268 { 1269 struct amdgpu_device *mirror_adev; 1270 struct amdgpu_hive_info *hive; 1271 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1272 uint64_t dst_node_id = node_info.node_id; 1273 uint8_t dst_num_hops = node_info.num_hops; 1274 uint8_t dst_num_links = node_info.num_links; 1275 1276 hive = amdgpu_get_xgmi_hive(psp->adev); 1277 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1278 struct psp_xgmi_topology_info *mirror_top_info; 1279 int j; 1280 1281 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1282 continue; 1283 1284 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1285 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1286 if (mirror_top_info->nodes[j].node_id != src_node_id) 1287 continue; 1288 1289 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1290 /* 1291 * prevent 0 num_links value re-reflection since reflection 1292 * criteria is based on num_hops (direct or indirect). 1293 * 1294 */ 1295 if (dst_num_links) 1296 mirror_top_info->nodes[j].num_links = dst_num_links; 1297 1298 break; 1299 } 1300 1301 break; 1302 } 1303 1304 amdgpu_put_xgmi_hive(hive); 1305 } 1306 1307 int psp_xgmi_get_topology_info(struct psp_context *psp, 1308 int number_devices, 1309 struct psp_xgmi_topology_info *topology, 1310 bool get_extended_data) 1311 { 1312 struct ta_xgmi_shared_memory *xgmi_cmd; 1313 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1314 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1315 int i; 1316 int ret; 1317 1318 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1319 return -EINVAL; 1320 1321 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1322 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1323 xgmi_cmd->flag_extend_link_record = get_extended_data; 1324 1325 /* Fill in the shared memory with topology information as input */ 1326 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1327 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1328 topology_info_input->num_nodes = number_devices; 1329 1330 for (i = 0; i < topology_info_input->num_nodes; i++) { 1331 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1332 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1333 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1334 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1335 } 1336 1337 /* Invoke xgmi ta to get the topology information */ 1338 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1339 if (ret) 1340 return ret; 1341 1342 /* Read the output topology information from the shared memory */ 1343 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1344 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1345 for (i = 0; i < topology->num_nodes; i++) { 1346 /* extended data will either be 0 or equal to non-extended data */ 1347 if (topology_info_output->nodes[i].num_hops) 1348 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1349 1350 /* non-extended data gets everything here so no need to update */ 1351 if (!get_extended_data) { 1352 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1353 topology->nodes[i].is_sharing_enabled = 1354 topology_info_output->nodes[i].is_sharing_enabled; 1355 topology->nodes[i].sdma_engine = 1356 topology_info_output->nodes[i].sdma_engine; 1357 } 1358 1359 } 1360 1361 /* Invoke xgmi ta again to get the link information */ 1362 if (psp_xgmi_peer_link_info_supported(psp)) { 1363 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1364 1365 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1366 1367 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1368 1369 if (ret) 1370 return ret; 1371 1372 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1373 for (i = 0; i < topology->num_nodes; i++) { 1374 /* accumulate num_links on extended data */ 1375 topology->nodes[i].num_links = get_extended_data ? 1376 topology->nodes[i].num_links + 1377 link_info_output->nodes[i].num_links : 1378 link_info_output->nodes[i].num_links; 1379 1380 /* reflect the topology information for bi-directionality */ 1381 if (psp->xgmi_context.supports_extended_data && 1382 get_extended_data && topology->nodes[i].num_hops) 1383 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1384 } 1385 } 1386 1387 return 0; 1388 } 1389 1390 int psp_xgmi_set_topology_info(struct psp_context *psp, 1391 int number_devices, 1392 struct psp_xgmi_topology_info *topology) 1393 { 1394 struct ta_xgmi_shared_memory *xgmi_cmd; 1395 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1396 int i; 1397 1398 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1399 return -EINVAL; 1400 1401 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1402 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1403 1404 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1405 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1406 topology_info_input->num_nodes = number_devices; 1407 1408 for (i = 0; i < topology_info_input->num_nodes; i++) { 1409 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1410 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1411 topology_info_input->nodes[i].is_sharing_enabled = 1; 1412 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1413 } 1414 1415 /* Invoke xgmi ta to set topology information */ 1416 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1417 } 1418 1419 // ras begin 1420 static void psp_ras_ta_check_status(struct psp_context *psp) 1421 { 1422 struct ta_ras_shared_memory *ras_cmd = 1423 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1424 1425 switch (ras_cmd->ras_status) { 1426 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1427 dev_warn(psp->adev->dev, 1428 "RAS WARNING: cmd failed due to unsupported ip\n"); 1429 break; 1430 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1431 dev_warn(psp->adev->dev, 1432 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1433 break; 1434 case TA_RAS_STATUS__SUCCESS: 1435 break; 1436 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1437 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1438 dev_warn(psp->adev->dev, 1439 "RAS WARNING: Inject error to critical region is not allowed\n"); 1440 break; 1441 default: 1442 dev_warn(psp->adev->dev, 1443 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1444 break; 1445 } 1446 } 1447 1448 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1449 { 1450 struct ta_ras_shared_memory *ras_cmd; 1451 int ret; 1452 1453 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1454 1455 /* 1456 * TODO: bypass the loading in sriov for now 1457 */ 1458 if (amdgpu_sriov_vf(psp->adev)) 1459 return 0; 1460 1461 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1462 1463 if (amdgpu_ras_intr_triggered()) 1464 return ret; 1465 1466 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1467 { 1468 DRM_WARN("RAS: Unsupported Interface"); 1469 return -EINVAL; 1470 } 1471 1472 if (!ret) { 1473 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1474 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1475 1476 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1477 } 1478 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1479 dev_warn(psp->adev->dev, 1480 "RAS internal register access blocked\n"); 1481 1482 psp_ras_ta_check_status(psp); 1483 } 1484 1485 return ret; 1486 } 1487 1488 int psp_ras_enable_features(struct psp_context *psp, 1489 union ta_ras_cmd_input *info, bool enable) 1490 { 1491 struct ta_ras_shared_memory *ras_cmd; 1492 int ret; 1493 1494 if (!psp->ras_context.context.initialized) 1495 return -EINVAL; 1496 1497 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1498 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1499 1500 if (enable) 1501 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1502 else 1503 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1504 1505 ras_cmd->ras_in_message = *info; 1506 1507 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1508 if (ret) 1509 return -EINVAL; 1510 1511 return 0; 1512 } 1513 1514 int psp_ras_terminate(struct psp_context *psp) 1515 { 1516 int ret; 1517 1518 /* 1519 * TODO: bypass the terminate in sriov for now 1520 */ 1521 if (amdgpu_sriov_vf(psp->adev)) 1522 return 0; 1523 1524 if (!psp->ras_context.context.initialized) 1525 return 0; 1526 1527 ret = psp_ta_unload(psp, &psp->ras_context.context); 1528 1529 psp->ras_context.context.initialized = false; 1530 1531 return ret; 1532 } 1533 1534 static int psp_ras_initialize(struct psp_context *psp) 1535 { 1536 int ret; 1537 uint32_t boot_cfg = 0xFF; 1538 struct amdgpu_device *adev = psp->adev; 1539 struct ta_ras_shared_memory *ras_cmd; 1540 1541 /* 1542 * TODO: bypass the initialize in sriov for now 1543 */ 1544 if (amdgpu_sriov_vf(adev)) 1545 return 0; 1546 1547 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1548 !adev->psp.ras_context.context.bin_desc.start_addr) { 1549 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1550 return 0; 1551 } 1552 1553 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1554 /* query GECC enablement status from boot config 1555 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1556 */ 1557 ret = psp_boot_config_get(adev, &boot_cfg); 1558 if (ret) 1559 dev_warn(adev->dev, "PSP get boot config failed\n"); 1560 1561 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1562 if (!boot_cfg) { 1563 dev_info(adev->dev, "GECC is disabled\n"); 1564 } else { 1565 /* disable GECC in next boot cycle if ras is 1566 * disabled by module parameter amdgpu_ras_enable 1567 * and/or amdgpu_ras_mask, or boot_config_get call 1568 * is failed 1569 */ 1570 ret = psp_boot_config_set(adev, 0); 1571 if (ret) 1572 dev_warn(adev->dev, "PSP set boot config failed\n"); 1573 else 1574 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1575 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1576 } 1577 } else { 1578 if (1 == boot_cfg) { 1579 dev_info(adev->dev, "GECC is enabled\n"); 1580 } else { 1581 /* enable GECC in next boot cycle if it is disabled 1582 * in boot config, or force enable GECC if failed to 1583 * get boot configuration 1584 */ 1585 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1586 if (ret) 1587 dev_warn(adev->dev, "PSP set boot config failed\n"); 1588 else 1589 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1590 } 1591 } 1592 } 1593 1594 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1595 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1596 1597 if (!psp->ras_context.context.initialized) { 1598 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1599 if (ret) 1600 return ret; 1601 } 1602 1603 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1604 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1605 1606 if (amdgpu_ras_is_poison_mode_supported(adev)) 1607 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1608 if (!adev->gmc.xgmi.connected_to_cpu) 1609 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1610 1611 ret = psp_ta_load(psp, &psp->ras_context.context); 1612 1613 if (!ret && !ras_cmd->ras_status) 1614 psp->ras_context.context.initialized = true; 1615 else { 1616 if (ras_cmd->ras_status) 1617 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1618 amdgpu_ras_fini(psp->adev); 1619 } 1620 1621 return ret; 1622 } 1623 1624 int psp_ras_trigger_error(struct psp_context *psp, 1625 struct ta_ras_trigger_error_input *info) 1626 { 1627 struct ta_ras_shared_memory *ras_cmd; 1628 int ret; 1629 1630 if (!psp->ras_context.context.initialized) 1631 return -EINVAL; 1632 1633 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1634 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1635 1636 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1637 ras_cmd->ras_in_message.trigger_error = *info; 1638 1639 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1640 if (ret) 1641 return -EINVAL; 1642 1643 /* If err_event_athub occurs error inject was successful, however 1644 return status from TA is no long reliable */ 1645 if (amdgpu_ras_intr_triggered()) 1646 return 0; 1647 1648 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1649 return -EACCES; 1650 else if (ras_cmd->ras_status) 1651 return -EINVAL; 1652 1653 return 0; 1654 } 1655 // ras end 1656 1657 // HDCP start 1658 static int psp_hdcp_initialize(struct psp_context *psp) 1659 { 1660 int ret; 1661 1662 /* 1663 * TODO: bypass the initialize in sriov for now 1664 */ 1665 if (amdgpu_sriov_vf(psp->adev)) 1666 return 0; 1667 1668 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1669 !psp->hdcp_context.context.bin_desc.start_addr) { 1670 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1671 return 0; 1672 } 1673 1674 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1675 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1676 1677 if (!psp->hdcp_context.context.initialized) { 1678 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1679 if (ret) 1680 return ret; 1681 } 1682 1683 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1684 if (!ret) { 1685 psp->hdcp_context.context.initialized = true; 1686 mutex_init(&psp->hdcp_context.mutex); 1687 } 1688 1689 return ret; 1690 } 1691 1692 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1693 { 1694 /* 1695 * TODO: bypass the loading in sriov for now 1696 */ 1697 if (amdgpu_sriov_vf(psp->adev)) 1698 return 0; 1699 1700 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1701 } 1702 1703 static int psp_hdcp_terminate(struct psp_context *psp) 1704 { 1705 int ret; 1706 1707 /* 1708 * TODO: bypass the terminate in sriov for now 1709 */ 1710 if (amdgpu_sriov_vf(psp->adev)) 1711 return 0; 1712 1713 if (!psp->hdcp_context.context.initialized) 1714 return 0; 1715 1716 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1717 1718 psp->hdcp_context.context.initialized = false; 1719 1720 return ret; 1721 } 1722 // HDCP end 1723 1724 // DTM start 1725 static int psp_dtm_initialize(struct psp_context *psp) 1726 { 1727 int ret; 1728 1729 /* 1730 * TODO: bypass the initialize in sriov for now 1731 */ 1732 if (amdgpu_sriov_vf(psp->adev)) 1733 return 0; 1734 1735 if (!psp->dtm_context.context.bin_desc.size_bytes || 1736 !psp->dtm_context.context.bin_desc.start_addr) { 1737 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1738 return 0; 1739 } 1740 1741 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1742 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1743 1744 if (!psp->dtm_context.context.initialized) { 1745 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1746 if (ret) 1747 return ret; 1748 } 1749 1750 ret = psp_ta_load(psp, &psp->dtm_context.context); 1751 if (!ret) { 1752 psp->dtm_context.context.initialized = true; 1753 mutex_init(&psp->dtm_context.mutex); 1754 } 1755 1756 return ret; 1757 } 1758 1759 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1760 { 1761 /* 1762 * TODO: bypass the loading in sriov for now 1763 */ 1764 if (amdgpu_sriov_vf(psp->adev)) 1765 return 0; 1766 1767 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1768 } 1769 1770 static int psp_dtm_terminate(struct psp_context *psp) 1771 { 1772 int ret; 1773 1774 /* 1775 * TODO: bypass the terminate in sriov for now 1776 */ 1777 if (amdgpu_sriov_vf(psp->adev)) 1778 return 0; 1779 1780 if (!psp->dtm_context.context.initialized) 1781 return 0; 1782 1783 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1784 1785 psp->dtm_context.context.initialized = false; 1786 1787 return ret; 1788 } 1789 // DTM end 1790 1791 // RAP start 1792 static int psp_rap_initialize(struct psp_context *psp) 1793 { 1794 int ret; 1795 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1796 1797 /* 1798 * TODO: bypass the initialize in sriov for now 1799 */ 1800 if (amdgpu_sriov_vf(psp->adev)) 1801 return 0; 1802 1803 if (!psp->rap_context.context.bin_desc.size_bytes || 1804 !psp->rap_context.context.bin_desc.start_addr) { 1805 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1806 return 0; 1807 } 1808 1809 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1810 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1811 1812 if (!psp->rap_context.context.initialized) { 1813 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1814 if (ret) 1815 return ret; 1816 } 1817 1818 ret = psp_ta_load(psp, &psp->rap_context.context); 1819 if (!ret) { 1820 psp->rap_context.context.initialized = true; 1821 mutex_init(&psp->rap_context.mutex); 1822 } else 1823 return ret; 1824 1825 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1826 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1827 psp_rap_terminate(psp); 1828 /* free rap shared memory */ 1829 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1830 1831 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1832 ret, status); 1833 1834 return ret; 1835 } 1836 1837 return 0; 1838 } 1839 1840 static int psp_rap_terminate(struct psp_context *psp) 1841 { 1842 int ret; 1843 1844 if (!psp->rap_context.context.initialized) 1845 return 0; 1846 1847 ret = psp_ta_unload(psp, &psp->rap_context.context); 1848 1849 psp->rap_context.context.initialized = false; 1850 1851 return ret; 1852 } 1853 1854 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1855 { 1856 struct ta_rap_shared_memory *rap_cmd; 1857 int ret = 0; 1858 1859 if (!psp->rap_context.context.initialized) 1860 return 0; 1861 1862 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1863 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1864 return -EINVAL; 1865 1866 mutex_lock(&psp->rap_context.mutex); 1867 1868 rap_cmd = (struct ta_rap_shared_memory *) 1869 psp->rap_context.context.mem_context.shared_buf; 1870 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1871 1872 rap_cmd->cmd_id = ta_cmd_id; 1873 rap_cmd->validation_method_id = METHOD_A; 1874 1875 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1876 if (ret) 1877 goto out_unlock; 1878 1879 if (status) 1880 *status = rap_cmd->rap_status; 1881 1882 out_unlock: 1883 mutex_unlock(&psp->rap_context.mutex); 1884 1885 return ret; 1886 } 1887 // RAP end 1888 1889 /* securedisplay start */ 1890 static int psp_securedisplay_initialize(struct psp_context *psp) 1891 { 1892 int ret; 1893 struct securedisplay_cmd *securedisplay_cmd; 1894 1895 /* 1896 * TODO: bypass the initialize in sriov for now 1897 */ 1898 if (amdgpu_sriov_vf(psp->adev)) 1899 return 0; 1900 1901 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1902 !psp->securedisplay_context.context.bin_desc.start_addr) { 1903 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1904 return 0; 1905 } 1906 1907 psp->securedisplay_context.context.mem_context.shared_mem_size = 1908 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1909 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1910 1911 if (!psp->securedisplay_context.context.initialized) { 1912 ret = psp_ta_init_shared_buf(psp, 1913 &psp->securedisplay_context.context.mem_context); 1914 if (ret) 1915 return ret; 1916 } 1917 1918 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 1919 if (!ret) { 1920 psp->securedisplay_context.context.initialized = true; 1921 mutex_init(&psp->securedisplay_context.mutex); 1922 } else 1923 return ret; 1924 1925 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1926 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1927 1928 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1929 if (ret) { 1930 psp_securedisplay_terminate(psp); 1931 /* free securedisplay shared memory */ 1932 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1933 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1934 return -EINVAL; 1935 } 1936 1937 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1938 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1939 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1940 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1941 } 1942 1943 return 0; 1944 } 1945 1946 static int psp_securedisplay_terminate(struct psp_context *psp) 1947 { 1948 int ret; 1949 1950 /* 1951 * TODO:bypass the terminate in sriov for now 1952 */ 1953 if (amdgpu_sriov_vf(psp->adev)) 1954 return 0; 1955 1956 if (!psp->securedisplay_context.context.initialized) 1957 return 0; 1958 1959 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 1960 1961 psp->securedisplay_context.context.initialized = false; 1962 1963 return ret; 1964 } 1965 1966 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1967 { 1968 int ret; 1969 1970 if (!psp->securedisplay_context.context.initialized) 1971 return -EINVAL; 1972 1973 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1974 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1975 return -EINVAL; 1976 1977 mutex_lock(&psp->securedisplay_context.mutex); 1978 1979 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1980 1981 mutex_unlock(&psp->securedisplay_context.mutex); 1982 1983 return ret; 1984 } 1985 /* SECUREDISPLAY end */ 1986 1987 static int psp_hw_start(struct psp_context *psp) 1988 { 1989 struct amdgpu_device *adev = psp->adev; 1990 int ret; 1991 1992 if (!amdgpu_sriov_vf(adev)) { 1993 if ((is_psp_fw_valid(psp->kdb)) && 1994 (psp->funcs->bootloader_load_kdb != NULL)) { 1995 ret = psp_bootloader_load_kdb(psp); 1996 if (ret) { 1997 DRM_ERROR("PSP load kdb failed!\n"); 1998 return ret; 1999 } 2000 } 2001 2002 if ((is_psp_fw_valid(psp->spl)) && 2003 (psp->funcs->bootloader_load_spl != NULL)) { 2004 ret = psp_bootloader_load_spl(psp); 2005 if (ret) { 2006 DRM_ERROR("PSP load spl failed!\n"); 2007 return ret; 2008 } 2009 } 2010 2011 if ((is_psp_fw_valid(psp->sys)) && 2012 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2013 ret = psp_bootloader_load_sysdrv(psp); 2014 if (ret) { 2015 DRM_ERROR("PSP load sys drv failed!\n"); 2016 return ret; 2017 } 2018 } 2019 2020 if ((is_psp_fw_valid(psp->soc_drv)) && 2021 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2022 ret = psp_bootloader_load_soc_drv(psp); 2023 if (ret) { 2024 DRM_ERROR("PSP load soc drv failed!\n"); 2025 return ret; 2026 } 2027 } 2028 2029 if ((is_psp_fw_valid(psp->intf_drv)) && 2030 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2031 ret = psp_bootloader_load_intf_drv(psp); 2032 if (ret) { 2033 DRM_ERROR("PSP load intf drv failed!\n"); 2034 return ret; 2035 } 2036 } 2037 2038 if ((is_psp_fw_valid(psp->dbg_drv)) && 2039 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2040 ret = psp_bootloader_load_dbg_drv(psp); 2041 if (ret) { 2042 DRM_ERROR("PSP load dbg drv failed!\n"); 2043 return ret; 2044 } 2045 } 2046 2047 if ((is_psp_fw_valid(psp->sos)) && 2048 (psp->funcs->bootloader_load_sos != NULL)) { 2049 ret = psp_bootloader_load_sos(psp); 2050 if (ret) { 2051 DRM_ERROR("PSP load sos failed!\n"); 2052 return ret; 2053 } 2054 } 2055 } 2056 2057 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2058 if (ret) { 2059 DRM_ERROR("PSP create ring failed!\n"); 2060 return ret; 2061 } 2062 2063 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2064 goto skip_pin_bo; 2065 2066 ret = psp_tmr_init(psp); 2067 if (ret) { 2068 DRM_ERROR("PSP tmr init failed!\n"); 2069 return ret; 2070 } 2071 2072 skip_pin_bo: 2073 /* 2074 * For ASICs with DF Cstate management centralized 2075 * to PMFW, TMR setup should be performed after PMFW 2076 * loaded and before other non-psp firmware loaded. 2077 */ 2078 if (psp->pmfw_centralized_cstate_management) { 2079 ret = psp_load_smu_fw(psp); 2080 if (ret) 2081 return ret; 2082 } 2083 2084 ret = psp_tmr_load(psp); 2085 if (ret) { 2086 DRM_ERROR("PSP load tmr failed!\n"); 2087 return ret; 2088 } 2089 2090 return 0; 2091 } 2092 2093 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2094 enum psp_gfx_fw_type *type) 2095 { 2096 switch (ucode->ucode_id) { 2097 case AMDGPU_UCODE_ID_CAP: 2098 *type = GFX_FW_TYPE_CAP; 2099 break; 2100 case AMDGPU_UCODE_ID_SDMA0: 2101 *type = GFX_FW_TYPE_SDMA0; 2102 break; 2103 case AMDGPU_UCODE_ID_SDMA1: 2104 *type = GFX_FW_TYPE_SDMA1; 2105 break; 2106 case AMDGPU_UCODE_ID_SDMA2: 2107 *type = GFX_FW_TYPE_SDMA2; 2108 break; 2109 case AMDGPU_UCODE_ID_SDMA3: 2110 *type = GFX_FW_TYPE_SDMA3; 2111 break; 2112 case AMDGPU_UCODE_ID_SDMA4: 2113 *type = GFX_FW_TYPE_SDMA4; 2114 break; 2115 case AMDGPU_UCODE_ID_SDMA5: 2116 *type = GFX_FW_TYPE_SDMA5; 2117 break; 2118 case AMDGPU_UCODE_ID_SDMA6: 2119 *type = GFX_FW_TYPE_SDMA6; 2120 break; 2121 case AMDGPU_UCODE_ID_SDMA7: 2122 *type = GFX_FW_TYPE_SDMA7; 2123 break; 2124 case AMDGPU_UCODE_ID_CP_MES: 2125 *type = GFX_FW_TYPE_CP_MES; 2126 break; 2127 case AMDGPU_UCODE_ID_CP_MES_DATA: 2128 *type = GFX_FW_TYPE_MES_STACK; 2129 break; 2130 case AMDGPU_UCODE_ID_CP_MES1: 2131 *type = GFX_FW_TYPE_CP_MES_KIQ; 2132 break; 2133 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2134 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2135 break; 2136 case AMDGPU_UCODE_ID_CP_CE: 2137 *type = GFX_FW_TYPE_CP_CE; 2138 break; 2139 case AMDGPU_UCODE_ID_CP_PFP: 2140 *type = GFX_FW_TYPE_CP_PFP; 2141 break; 2142 case AMDGPU_UCODE_ID_CP_ME: 2143 *type = GFX_FW_TYPE_CP_ME; 2144 break; 2145 case AMDGPU_UCODE_ID_CP_MEC1: 2146 *type = GFX_FW_TYPE_CP_MEC; 2147 break; 2148 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2149 *type = GFX_FW_TYPE_CP_MEC_ME1; 2150 break; 2151 case AMDGPU_UCODE_ID_CP_MEC2: 2152 *type = GFX_FW_TYPE_CP_MEC; 2153 break; 2154 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2155 *type = GFX_FW_TYPE_CP_MEC_ME2; 2156 break; 2157 case AMDGPU_UCODE_ID_RLC_P: 2158 *type = GFX_FW_TYPE_RLC_P; 2159 break; 2160 case AMDGPU_UCODE_ID_RLC_V: 2161 *type = GFX_FW_TYPE_RLC_V; 2162 break; 2163 case AMDGPU_UCODE_ID_RLC_G: 2164 *type = GFX_FW_TYPE_RLC_G; 2165 break; 2166 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2167 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2168 break; 2169 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2170 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2171 break; 2172 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2173 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2174 break; 2175 case AMDGPU_UCODE_ID_RLC_IRAM: 2176 *type = GFX_FW_TYPE_RLC_IRAM; 2177 break; 2178 case AMDGPU_UCODE_ID_RLC_DRAM: 2179 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2180 break; 2181 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2182 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2183 break; 2184 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2185 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2186 break; 2187 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2188 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2189 break; 2190 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2191 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2192 break; 2193 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2194 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2195 break; 2196 case AMDGPU_UCODE_ID_SMC: 2197 *type = GFX_FW_TYPE_SMU; 2198 break; 2199 case AMDGPU_UCODE_ID_PPTABLE: 2200 *type = GFX_FW_TYPE_PPTABLE; 2201 break; 2202 case AMDGPU_UCODE_ID_UVD: 2203 *type = GFX_FW_TYPE_UVD; 2204 break; 2205 case AMDGPU_UCODE_ID_UVD1: 2206 *type = GFX_FW_TYPE_UVD1; 2207 break; 2208 case AMDGPU_UCODE_ID_VCE: 2209 *type = GFX_FW_TYPE_VCE; 2210 break; 2211 case AMDGPU_UCODE_ID_VCN: 2212 *type = GFX_FW_TYPE_VCN; 2213 break; 2214 case AMDGPU_UCODE_ID_VCN1: 2215 *type = GFX_FW_TYPE_VCN1; 2216 break; 2217 case AMDGPU_UCODE_ID_DMCU_ERAM: 2218 *type = GFX_FW_TYPE_DMCU_ERAM; 2219 break; 2220 case AMDGPU_UCODE_ID_DMCU_INTV: 2221 *type = GFX_FW_TYPE_DMCU_ISR; 2222 break; 2223 case AMDGPU_UCODE_ID_VCN0_RAM: 2224 *type = GFX_FW_TYPE_VCN0_RAM; 2225 break; 2226 case AMDGPU_UCODE_ID_VCN1_RAM: 2227 *type = GFX_FW_TYPE_VCN1_RAM; 2228 break; 2229 case AMDGPU_UCODE_ID_DMCUB: 2230 *type = GFX_FW_TYPE_DMUB; 2231 break; 2232 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2233 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2234 break; 2235 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2236 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2237 break; 2238 case AMDGPU_UCODE_ID_IMU_I: 2239 *type = GFX_FW_TYPE_IMU_I; 2240 break; 2241 case AMDGPU_UCODE_ID_IMU_D: 2242 *type = GFX_FW_TYPE_IMU_D; 2243 break; 2244 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2245 *type = GFX_FW_TYPE_RS64_PFP; 2246 break; 2247 case AMDGPU_UCODE_ID_CP_RS64_ME: 2248 *type = GFX_FW_TYPE_RS64_ME; 2249 break; 2250 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2251 *type = GFX_FW_TYPE_RS64_MEC; 2252 break; 2253 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2254 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2255 break; 2256 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2257 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2258 break; 2259 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2260 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2261 break; 2262 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2263 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2264 break; 2265 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2266 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2267 break; 2268 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2269 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2270 break; 2271 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2272 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2273 break; 2274 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2275 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2276 break; 2277 case AMDGPU_UCODE_ID_MAXIMUM: 2278 default: 2279 return -EINVAL; 2280 } 2281 2282 return 0; 2283 } 2284 2285 static void psp_print_fw_hdr(struct psp_context *psp, 2286 struct amdgpu_firmware_info *ucode) 2287 { 2288 struct amdgpu_device *adev = psp->adev; 2289 struct common_firmware_header *hdr; 2290 2291 switch (ucode->ucode_id) { 2292 case AMDGPU_UCODE_ID_SDMA0: 2293 case AMDGPU_UCODE_ID_SDMA1: 2294 case AMDGPU_UCODE_ID_SDMA2: 2295 case AMDGPU_UCODE_ID_SDMA3: 2296 case AMDGPU_UCODE_ID_SDMA4: 2297 case AMDGPU_UCODE_ID_SDMA5: 2298 case AMDGPU_UCODE_ID_SDMA6: 2299 case AMDGPU_UCODE_ID_SDMA7: 2300 hdr = (struct common_firmware_header *) 2301 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2302 amdgpu_ucode_print_sdma_hdr(hdr); 2303 break; 2304 case AMDGPU_UCODE_ID_CP_CE: 2305 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2306 amdgpu_ucode_print_gfx_hdr(hdr); 2307 break; 2308 case AMDGPU_UCODE_ID_CP_PFP: 2309 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2310 amdgpu_ucode_print_gfx_hdr(hdr); 2311 break; 2312 case AMDGPU_UCODE_ID_CP_ME: 2313 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2314 amdgpu_ucode_print_gfx_hdr(hdr); 2315 break; 2316 case AMDGPU_UCODE_ID_CP_MEC1: 2317 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2318 amdgpu_ucode_print_gfx_hdr(hdr); 2319 break; 2320 case AMDGPU_UCODE_ID_RLC_G: 2321 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2322 amdgpu_ucode_print_rlc_hdr(hdr); 2323 break; 2324 case AMDGPU_UCODE_ID_SMC: 2325 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2326 amdgpu_ucode_print_smc_hdr(hdr); 2327 break; 2328 default: 2329 break; 2330 } 2331 } 2332 2333 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2334 struct psp_gfx_cmd_resp *cmd) 2335 { 2336 int ret; 2337 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2338 2339 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2340 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2341 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2342 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2343 2344 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2345 if (ret) 2346 DRM_ERROR("Unknown firmware type\n"); 2347 2348 return ret; 2349 } 2350 2351 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2352 struct amdgpu_firmware_info *ucode) 2353 { 2354 int ret = 0; 2355 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2356 2357 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2358 if (!ret) { 2359 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2360 psp->fence_buf_mc_addr); 2361 } 2362 2363 release_psp_cmd_buf(psp); 2364 2365 return ret; 2366 } 2367 2368 static int psp_load_smu_fw(struct psp_context *psp) 2369 { 2370 int ret; 2371 struct amdgpu_device *adev = psp->adev; 2372 struct amdgpu_firmware_info *ucode = 2373 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2374 struct amdgpu_ras *ras = psp->ras_context.ras; 2375 2376 /* 2377 * Skip SMU FW reloading in case of using BACO for runpm only, 2378 * as SMU is always alive. 2379 */ 2380 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2381 return 0; 2382 2383 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2384 return 0; 2385 2386 if ((amdgpu_in_reset(adev) && 2387 ras && adev->ras_enabled && 2388 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2389 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2390 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2391 if (ret) { 2392 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2393 } 2394 } 2395 2396 ret = psp_execute_non_psp_fw_load(psp, ucode); 2397 2398 if (ret) 2399 DRM_ERROR("PSP load smu failed!\n"); 2400 2401 return ret; 2402 } 2403 2404 static bool fw_load_skip_check(struct psp_context *psp, 2405 struct amdgpu_firmware_info *ucode) 2406 { 2407 if (!ucode->fw || !ucode->ucode_size) 2408 return true; 2409 2410 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2411 (psp_smu_reload_quirk(psp) || 2412 psp->autoload_supported || 2413 psp->pmfw_centralized_cstate_management)) 2414 return true; 2415 2416 if (amdgpu_sriov_vf(psp->adev) && 2417 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2418 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2419 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2420 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2421 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2422 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2423 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2424 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2425 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2426 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2427 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2428 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2429 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2430 /*skip ucode loading in SRIOV VF */ 2431 return true; 2432 2433 if (psp->autoload_supported && 2434 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2435 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2436 /* skip mec JT when autoload is enabled */ 2437 return true; 2438 2439 return false; 2440 } 2441 2442 int psp_load_fw_list(struct psp_context *psp, 2443 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2444 { 2445 int ret = 0, i; 2446 struct amdgpu_firmware_info *ucode; 2447 2448 for (i = 0; i < ucode_count; ++i) { 2449 ucode = ucode_list[i]; 2450 psp_print_fw_hdr(psp, ucode); 2451 ret = psp_execute_non_psp_fw_load(psp, ucode); 2452 if (ret) 2453 return ret; 2454 } 2455 return ret; 2456 } 2457 2458 static int psp_load_non_psp_fw(struct psp_context *psp) 2459 { 2460 int i, ret; 2461 struct amdgpu_firmware_info *ucode; 2462 struct amdgpu_device *adev = psp->adev; 2463 2464 if (psp->autoload_supported && 2465 !psp->pmfw_centralized_cstate_management) { 2466 ret = psp_load_smu_fw(psp); 2467 if (ret) 2468 return ret; 2469 } 2470 2471 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2472 ucode = &adev->firmware.ucode[i]; 2473 2474 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2475 !fw_load_skip_check(psp, ucode)) { 2476 ret = psp_load_smu_fw(psp); 2477 if (ret) 2478 return ret; 2479 continue; 2480 } 2481 2482 if (fw_load_skip_check(psp, ucode)) 2483 continue; 2484 2485 if (psp->autoload_supported && 2486 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2487 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2488 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2489 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2490 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2491 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2492 /* PSP only receive one SDMA fw for sienna_cichlid, 2493 * as all four sdma fw are same */ 2494 continue; 2495 2496 psp_print_fw_hdr(psp, ucode); 2497 2498 ret = psp_execute_non_psp_fw_load(psp, ucode); 2499 if (ret) 2500 return ret; 2501 2502 /* Start rlc autoload after psp recieved all the gfx firmware */ 2503 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2504 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2505 ret = psp_rlc_autoload_start(psp); 2506 if (ret) { 2507 DRM_ERROR("Failed to start rlc autoload\n"); 2508 return ret; 2509 } 2510 } 2511 } 2512 2513 return 0; 2514 } 2515 2516 static int psp_load_fw(struct amdgpu_device *adev) 2517 { 2518 int ret; 2519 struct psp_context *psp = &adev->psp; 2520 2521 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2522 /* should not destroy ring, only stop */ 2523 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2524 } else { 2525 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2526 2527 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2528 if (ret) { 2529 DRM_ERROR("PSP ring init failed!\n"); 2530 goto failed; 2531 } 2532 } 2533 2534 ret = psp_hw_start(psp); 2535 if (ret) 2536 goto failed; 2537 2538 ret = psp_load_non_psp_fw(psp); 2539 if (ret) 2540 goto failed1; 2541 2542 ret = psp_asd_initialize(psp); 2543 if (ret) { 2544 DRM_ERROR("PSP load asd failed!\n"); 2545 goto failed1; 2546 } 2547 2548 ret = psp_rl_load(adev); 2549 if (ret) { 2550 DRM_ERROR("PSP load RL failed!\n"); 2551 goto failed1; 2552 } 2553 2554 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2555 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2556 ret = psp_xgmi_initialize(psp, false, true); 2557 /* Warning the XGMI seesion initialize failure 2558 * Instead of stop driver initialization 2559 */ 2560 if (ret) 2561 dev_err(psp->adev->dev, 2562 "XGMI: Failed to initialize XGMI session\n"); 2563 } 2564 } 2565 2566 if (psp->ta_fw) { 2567 ret = psp_ras_initialize(psp); 2568 if (ret) 2569 dev_err(psp->adev->dev, 2570 "RAS: Failed to initialize RAS\n"); 2571 2572 ret = psp_hdcp_initialize(psp); 2573 if (ret) 2574 dev_err(psp->adev->dev, 2575 "HDCP: Failed to initialize HDCP\n"); 2576 2577 ret = psp_dtm_initialize(psp); 2578 if (ret) 2579 dev_err(psp->adev->dev, 2580 "DTM: Failed to initialize DTM\n"); 2581 2582 ret = psp_rap_initialize(psp); 2583 if (ret) 2584 dev_err(psp->adev->dev, 2585 "RAP: Failed to initialize RAP\n"); 2586 2587 ret = psp_securedisplay_initialize(psp); 2588 if (ret) 2589 dev_err(psp->adev->dev, 2590 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2591 } 2592 2593 return 0; 2594 2595 failed1: 2596 psp_free_shared_bufs(psp); 2597 failed: 2598 /* 2599 * all cleanup jobs (xgmi terminate, ras terminate, 2600 * ring destroy, cmd/fence/fw buffers destory, 2601 * psp->cmd destory) are delayed to psp_hw_fini 2602 */ 2603 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2604 return ret; 2605 } 2606 2607 static int psp_hw_init(void *handle) 2608 { 2609 int ret; 2610 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2611 2612 mutex_lock(&adev->firmware.mutex); 2613 /* 2614 * This sequence is just used on hw_init only once, no need on 2615 * resume. 2616 */ 2617 ret = amdgpu_ucode_init_bo(adev); 2618 if (ret) 2619 goto failed; 2620 2621 ret = psp_load_fw(adev); 2622 if (ret) { 2623 DRM_ERROR("PSP firmware loading failed\n"); 2624 goto failed; 2625 } 2626 2627 mutex_unlock(&adev->firmware.mutex); 2628 return 0; 2629 2630 failed: 2631 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2632 mutex_unlock(&adev->firmware.mutex); 2633 return -EINVAL; 2634 } 2635 2636 static int psp_hw_fini(void *handle) 2637 { 2638 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2639 struct psp_context *psp = &adev->psp; 2640 2641 if (psp->ta_fw) { 2642 psp_ras_terminate(psp); 2643 psp_securedisplay_terminate(psp); 2644 psp_rap_terminate(psp); 2645 psp_dtm_terminate(psp); 2646 psp_hdcp_terminate(psp); 2647 2648 if (adev->gmc.xgmi.num_physical_nodes > 1) 2649 psp_xgmi_terminate(psp); 2650 } 2651 2652 psp_asd_terminate(psp); 2653 psp_tmr_terminate(psp); 2654 2655 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2656 2657 psp_free_shared_bufs(psp); 2658 2659 return 0; 2660 } 2661 2662 static int psp_suspend(void *handle) 2663 { 2664 int ret = 0; 2665 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2666 struct psp_context *psp = &adev->psp; 2667 2668 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2669 psp->xgmi_context.context.initialized) { 2670 ret = psp_xgmi_terminate(psp); 2671 if (ret) { 2672 DRM_ERROR("Failed to terminate xgmi ta\n"); 2673 goto out; 2674 } 2675 } 2676 2677 if (psp->ta_fw) { 2678 ret = psp_ras_terminate(psp); 2679 if (ret) { 2680 DRM_ERROR("Failed to terminate ras ta\n"); 2681 goto out; 2682 } 2683 ret = psp_hdcp_terminate(psp); 2684 if (ret) { 2685 DRM_ERROR("Failed to terminate hdcp ta\n"); 2686 goto out; 2687 } 2688 ret = psp_dtm_terminate(psp); 2689 if (ret) { 2690 DRM_ERROR("Failed to terminate dtm ta\n"); 2691 goto out; 2692 } 2693 ret = psp_rap_terminate(psp); 2694 if (ret) { 2695 DRM_ERROR("Failed to terminate rap ta\n"); 2696 goto out; 2697 } 2698 ret = psp_securedisplay_terminate(psp); 2699 if (ret) { 2700 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2701 goto out; 2702 } 2703 } 2704 2705 ret = psp_asd_terminate(psp); 2706 if (ret) { 2707 DRM_ERROR("Failed to terminate asd\n"); 2708 goto out; 2709 } 2710 2711 ret = psp_tmr_terminate(psp); 2712 if (ret) { 2713 DRM_ERROR("Failed to terminate tmr\n"); 2714 goto out; 2715 } 2716 2717 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2718 if (ret) { 2719 DRM_ERROR("PSP ring stop failed\n"); 2720 } 2721 2722 out: 2723 psp_free_shared_bufs(psp); 2724 2725 return ret; 2726 } 2727 2728 static int psp_resume(void *handle) 2729 { 2730 int ret; 2731 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2732 struct psp_context *psp = &adev->psp; 2733 2734 DRM_INFO("PSP is resuming...\n"); 2735 2736 if (psp->mem_train_ctx.enable_mem_training) { 2737 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2738 if (ret) { 2739 DRM_ERROR("Failed to process memory training!\n"); 2740 return ret; 2741 } 2742 } 2743 2744 mutex_lock(&adev->firmware.mutex); 2745 2746 ret = psp_hw_start(psp); 2747 if (ret) 2748 goto failed; 2749 2750 ret = psp_load_non_psp_fw(psp); 2751 if (ret) 2752 goto failed; 2753 2754 ret = psp_asd_initialize(psp); 2755 if (ret) { 2756 DRM_ERROR("PSP load asd failed!\n"); 2757 goto failed; 2758 } 2759 2760 ret = psp_rl_load(adev); 2761 if (ret) { 2762 dev_err(adev->dev, "PSP load RL failed!\n"); 2763 goto failed; 2764 } 2765 2766 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2767 ret = psp_xgmi_initialize(psp, false, true); 2768 /* Warning the XGMI seesion initialize failure 2769 * Instead of stop driver initialization 2770 */ 2771 if (ret) 2772 dev_err(psp->adev->dev, 2773 "XGMI: Failed to initialize XGMI session\n"); 2774 } 2775 2776 if (psp->ta_fw) { 2777 ret = psp_ras_initialize(psp); 2778 if (ret) 2779 dev_err(psp->adev->dev, 2780 "RAS: Failed to initialize RAS\n"); 2781 2782 ret = psp_hdcp_initialize(psp); 2783 if (ret) 2784 dev_err(psp->adev->dev, 2785 "HDCP: Failed to initialize HDCP\n"); 2786 2787 ret = psp_dtm_initialize(psp); 2788 if (ret) 2789 dev_err(psp->adev->dev, 2790 "DTM: Failed to initialize DTM\n"); 2791 2792 ret = psp_rap_initialize(psp); 2793 if (ret) 2794 dev_err(psp->adev->dev, 2795 "RAP: Failed to initialize RAP\n"); 2796 2797 ret = psp_securedisplay_initialize(psp); 2798 if (ret) 2799 dev_err(psp->adev->dev, 2800 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2801 } 2802 2803 mutex_unlock(&adev->firmware.mutex); 2804 2805 return 0; 2806 2807 failed: 2808 DRM_ERROR("PSP resume failed\n"); 2809 mutex_unlock(&adev->firmware.mutex); 2810 return ret; 2811 } 2812 2813 int psp_gpu_reset(struct amdgpu_device *adev) 2814 { 2815 int ret; 2816 2817 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2818 return 0; 2819 2820 mutex_lock(&adev->psp.mutex); 2821 ret = psp_mode1_reset(&adev->psp); 2822 mutex_unlock(&adev->psp.mutex); 2823 2824 return ret; 2825 } 2826 2827 int psp_rlc_autoload_start(struct psp_context *psp) 2828 { 2829 int ret; 2830 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2831 2832 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2833 2834 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2835 psp->fence_buf_mc_addr); 2836 2837 release_psp_cmd_buf(psp); 2838 2839 return ret; 2840 } 2841 2842 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2843 uint64_t cmd_gpu_addr, int cmd_size) 2844 { 2845 struct amdgpu_firmware_info ucode = {0}; 2846 2847 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2848 AMDGPU_UCODE_ID_VCN0_RAM; 2849 ucode.mc_addr = cmd_gpu_addr; 2850 ucode.ucode_size = cmd_size; 2851 2852 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2853 } 2854 2855 int psp_ring_cmd_submit(struct psp_context *psp, 2856 uint64_t cmd_buf_mc_addr, 2857 uint64_t fence_mc_addr, 2858 int index) 2859 { 2860 unsigned int psp_write_ptr_reg = 0; 2861 struct psp_gfx_rb_frame *write_frame; 2862 struct psp_ring *ring = &psp->km_ring; 2863 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2864 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2865 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2866 struct amdgpu_device *adev = psp->adev; 2867 uint32_t ring_size_dw = ring->ring_size / 4; 2868 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2869 2870 /* KM (GPCOM) prepare write pointer */ 2871 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2872 2873 /* Update KM RB frame pointer to new frame */ 2874 /* write_frame ptr increments by size of rb_frame in bytes */ 2875 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2876 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2877 write_frame = ring_buffer_start; 2878 else 2879 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2880 /* Check invalid write_frame ptr address */ 2881 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2882 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2883 ring_buffer_start, ring_buffer_end, write_frame); 2884 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2885 return -EINVAL; 2886 } 2887 2888 /* Initialize KM RB frame */ 2889 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2890 2891 /* Update KM RB frame */ 2892 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2893 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2894 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2895 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2896 write_frame->fence_value = index; 2897 amdgpu_device_flush_hdp(adev, NULL); 2898 2899 /* Update the write Pointer in DWORDs */ 2900 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2901 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2902 return 0; 2903 } 2904 2905 int psp_init_asd_microcode(struct psp_context *psp, 2906 const char *chip_name) 2907 { 2908 struct amdgpu_device *adev = psp->adev; 2909 char fw_name[PSP_FW_NAME_LEN]; 2910 const struct psp_firmware_header_v1_0 *asd_hdr; 2911 int err = 0; 2912 2913 if (!chip_name) { 2914 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2915 return -EINVAL; 2916 } 2917 2918 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2919 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2920 if (err) 2921 goto out; 2922 2923 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2924 if (err) 2925 goto out; 2926 2927 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2928 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2929 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2930 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2931 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2932 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2933 return 0; 2934 out: 2935 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2936 release_firmware(adev->psp.asd_fw); 2937 adev->psp.asd_fw = NULL; 2938 return err; 2939 } 2940 2941 int psp_init_toc_microcode(struct psp_context *psp, 2942 const char *chip_name) 2943 { 2944 struct amdgpu_device *adev = psp->adev; 2945 char fw_name[PSP_FW_NAME_LEN]; 2946 const struct psp_firmware_header_v1_0 *toc_hdr; 2947 int err = 0; 2948 2949 if (!chip_name) { 2950 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2951 return -EINVAL; 2952 } 2953 2954 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2955 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2956 if (err) 2957 goto out; 2958 2959 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2960 if (err) 2961 goto out; 2962 2963 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2964 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2965 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2966 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2967 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2968 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2969 return 0; 2970 out: 2971 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2972 release_firmware(adev->psp.toc_fw); 2973 adev->psp.toc_fw = NULL; 2974 return err; 2975 } 2976 2977 static int parse_sos_bin_descriptor(struct psp_context *psp, 2978 const struct psp_fw_bin_desc *desc, 2979 const struct psp_firmware_header_v2_0 *sos_hdr) 2980 { 2981 uint8_t *ucode_start_addr = NULL; 2982 2983 if (!psp || !desc || !sos_hdr) 2984 return -EINVAL; 2985 2986 ucode_start_addr = (uint8_t *)sos_hdr + 2987 le32_to_cpu(desc->offset_bytes) + 2988 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2989 2990 switch (desc->fw_type) { 2991 case PSP_FW_TYPE_PSP_SOS: 2992 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2993 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2994 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2995 psp->sos.start_addr = ucode_start_addr; 2996 break; 2997 case PSP_FW_TYPE_PSP_SYS_DRV: 2998 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2999 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3000 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3001 psp->sys.start_addr = ucode_start_addr; 3002 break; 3003 case PSP_FW_TYPE_PSP_KDB: 3004 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3005 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3006 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3007 psp->kdb.start_addr = ucode_start_addr; 3008 break; 3009 case PSP_FW_TYPE_PSP_TOC: 3010 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3011 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3012 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3013 psp->toc.start_addr = ucode_start_addr; 3014 break; 3015 case PSP_FW_TYPE_PSP_SPL: 3016 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3017 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3018 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3019 psp->spl.start_addr = ucode_start_addr; 3020 break; 3021 case PSP_FW_TYPE_PSP_RL: 3022 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3023 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3024 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3025 psp->rl.start_addr = ucode_start_addr; 3026 break; 3027 case PSP_FW_TYPE_PSP_SOC_DRV: 3028 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3029 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3030 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3031 psp->soc_drv.start_addr = ucode_start_addr; 3032 break; 3033 case PSP_FW_TYPE_PSP_INTF_DRV: 3034 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3035 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3036 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3037 psp->intf_drv.start_addr = ucode_start_addr; 3038 break; 3039 case PSP_FW_TYPE_PSP_DBG_DRV: 3040 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3041 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3042 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3043 psp->dbg_drv.start_addr = ucode_start_addr; 3044 break; 3045 default: 3046 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3047 break; 3048 } 3049 3050 return 0; 3051 } 3052 3053 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3054 { 3055 const struct psp_firmware_header_v1_0 *sos_hdr; 3056 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3057 uint8_t *ucode_array_start_addr; 3058 3059 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3060 ucode_array_start_addr = (uint8_t *)sos_hdr + 3061 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3062 3063 if (adev->gmc.xgmi.connected_to_cpu || 3064 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3065 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3066 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3067 3068 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3069 adev->psp.sys.start_addr = ucode_array_start_addr; 3070 3071 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3072 adev->psp.sos.start_addr = ucode_array_start_addr + 3073 le32_to_cpu(sos_hdr->sos.offset_bytes); 3074 } else { 3075 /* Load alternate PSP SOS FW */ 3076 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3077 3078 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3079 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3080 3081 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3082 adev->psp.sys.start_addr = ucode_array_start_addr + 3083 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3084 3085 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3086 adev->psp.sos.start_addr = ucode_array_start_addr + 3087 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3088 } 3089 3090 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3091 dev_warn(adev->dev, "PSP SOS FW not available"); 3092 return -EINVAL; 3093 } 3094 3095 return 0; 3096 } 3097 3098 int psp_init_sos_microcode(struct psp_context *psp, 3099 const char *chip_name) 3100 { 3101 struct amdgpu_device *adev = psp->adev; 3102 char fw_name[PSP_FW_NAME_LEN]; 3103 const struct psp_firmware_header_v1_0 *sos_hdr; 3104 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3105 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3106 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3107 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3108 int err = 0; 3109 uint8_t *ucode_array_start_addr; 3110 int fw_index = 0; 3111 3112 if (!chip_name) { 3113 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3114 return -EINVAL; 3115 } 3116 3117 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3118 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3119 if (err) 3120 goto out; 3121 3122 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3123 if (err) 3124 goto out; 3125 3126 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3127 ucode_array_start_addr = (uint8_t *)sos_hdr + 3128 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3129 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3130 3131 switch (sos_hdr->header.header_version_major) { 3132 case 1: 3133 err = psp_init_sos_base_fw(adev); 3134 if (err) 3135 goto out; 3136 3137 if (sos_hdr->header.header_version_minor == 1) { 3138 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3139 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3140 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3141 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3142 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3143 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3144 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3145 } 3146 if (sos_hdr->header.header_version_minor == 2) { 3147 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3148 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3149 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3150 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3151 } 3152 if (sos_hdr->header.header_version_minor == 3) { 3153 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3154 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3155 adev->psp.toc.start_addr = ucode_array_start_addr + 3156 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3157 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3158 adev->psp.kdb.start_addr = ucode_array_start_addr + 3159 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3160 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3161 adev->psp.spl.start_addr = ucode_array_start_addr + 3162 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3163 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3164 adev->psp.rl.start_addr = ucode_array_start_addr + 3165 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3166 } 3167 break; 3168 case 2: 3169 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3170 3171 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3172 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3173 err = -EINVAL; 3174 goto out; 3175 } 3176 3177 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3178 err = parse_sos_bin_descriptor(psp, 3179 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3180 sos_hdr_v2_0); 3181 if (err) 3182 goto out; 3183 } 3184 break; 3185 default: 3186 dev_err(adev->dev, 3187 "unsupported psp sos firmware\n"); 3188 err = -EINVAL; 3189 goto out; 3190 } 3191 3192 return 0; 3193 out: 3194 dev_err(adev->dev, 3195 "failed to init sos firmware\n"); 3196 release_firmware(adev->psp.sos_fw); 3197 adev->psp.sos_fw = NULL; 3198 3199 return err; 3200 } 3201 3202 static int parse_ta_bin_descriptor(struct psp_context *psp, 3203 const struct psp_fw_bin_desc *desc, 3204 const struct ta_firmware_header_v2_0 *ta_hdr) 3205 { 3206 uint8_t *ucode_start_addr = NULL; 3207 3208 if (!psp || !desc || !ta_hdr) 3209 return -EINVAL; 3210 3211 ucode_start_addr = (uint8_t *)ta_hdr + 3212 le32_to_cpu(desc->offset_bytes) + 3213 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3214 3215 switch (desc->fw_type) { 3216 case TA_FW_TYPE_PSP_ASD: 3217 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3218 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3219 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3220 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3221 break; 3222 case TA_FW_TYPE_PSP_XGMI: 3223 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3224 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3225 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3226 break; 3227 case TA_FW_TYPE_PSP_RAS: 3228 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3229 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3230 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3231 break; 3232 case TA_FW_TYPE_PSP_HDCP: 3233 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3234 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3235 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3236 break; 3237 case TA_FW_TYPE_PSP_DTM: 3238 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3239 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3240 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3241 break; 3242 case TA_FW_TYPE_PSP_RAP: 3243 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3244 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3245 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3246 break; 3247 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3248 psp->securedisplay_context.context.bin_desc.fw_version = 3249 le32_to_cpu(desc->fw_version); 3250 psp->securedisplay_context.context.bin_desc.size_bytes = 3251 le32_to_cpu(desc->size_bytes); 3252 psp->securedisplay_context.context.bin_desc.start_addr = 3253 ucode_start_addr; 3254 break; 3255 default: 3256 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3257 break; 3258 } 3259 3260 return 0; 3261 } 3262 3263 int psp_init_ta_microcode(struct psp_context *psp, 3264 const char *chip_name) 3265 { 3266 struct amdgpu_device *adev = psp->adev; 3267 char fw_name[PSP_FW_NAME_LEN]; 3268 const struct ta_firmware_header_v2_0 *ta_hdr; 3269 int err = 0; 3270 int ta_index = 0; 3271 3272 if (!chip_name) { 3273 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3274 return -EINVAL; 3275 } 3276 3277 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3278 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3279 if (err) 3280 goto out; 3281 3282 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3283 if (err) 3284 goto out; 3285 3286 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3287 3288 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3289 dev_err(adev->dev, "unsupported TA header version\n"); 3290 err = -EINVAL; 3291 goto out; 3292 } 3293 3294 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3295 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3296 err = -EINVAL; 3297 goto out; 3298 } 3299 3300 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3301 err = parse_ta_bin_descriptor(psp, 3302 &ta_hdr->ta_fw_bin[ta_index], 3303 ta_hdr); 3304 if (err) 3305 goto out; 3306 } 3307 3308 return 0; 3309 out: 3310 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3311 release_firmware(adev->psp.ta_fw); 3312 adev->psp.ta_fw = NULL; 3313 return err; 3314 } 3315 3316 int psp_init_cap_microcode(struct psp_context *psp, 3317 const char *chip_name) 3318 { 3319 struct amdgpu_device *adev = psp->adev; 3320 char fw_name[PSP_FW_NAME_LEN]; 3321 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3322 struct amdgpu_firmware_info *info = NULL; 3323 int err = 0; 3324 3325 if (!chip_name) { 3326 dev_err(adev->dev, "invalid chip name for cap microcode\n"); 3327 return -EINVAL; 3328 } 3329 3330 if (!amdgpu_sriov_vf(adev)) { 3331 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3332 return -EINVAL; 3333 } 3334 3335 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3336 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev); 3337 if (err) { 3338 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3339 err = 0; 3340 goto out; 3341 } 3342 3343 err = amdgpu_ucode_validate(adev->psp.cap_fw); 3344 if (err) { 3345 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3346 goto out; 3347 } 3348 3349 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3350 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3351 info->fw = adev->psp.cap_fw; 3352 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3353 adev->psp.cap_fw->data; 3354 adev->firmware.fw_size += ALIGN( 3355 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3356 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3357 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3358 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3359 3360 return 0; 3361 3362 out: 3363 release_firmware(adev->psp.cap_fw); 3364 adev->psp.cap_fw = NULL; 3365 return err; 3366 } 3367 3368 static int psp_set_clockgating_state(void *handle, 3369 enum amd_clockgating_state state) 3370 { 3371 return 0; 3372 } 3373 3374 static int psp_set_powergating_state(void *handle, 3375 enum amd_powergating_state state) 3376 { 3377 return 0; 3378 } 3379 3380 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3381 struct device_attribute *attr, 3382 char *buf) 3383 { 3384 struct drm_device *ddev = dev_get_drvdata(dev); 3385 struct amdgpu_device *adev = drm_to_adev(ddev); 3386 uint32_t fw_ver; 3387 int ret; 3388 3389 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3390 DRM_INFO("PSP block is not ready yet."); 3391 return -EBUSY; 3392 } 3393 3394 mutex_lock(&adev->psp.mutex); 3395 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3396 mutex_unlock(&adev->psp.mutex); 3397 3398 if (ret) { 3399 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3400 return ret; 3401 } 3402 3403 return sysfs_emit(buf, "%x\n", fw_ver); 3404 } 3405 3406 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3407 struct device_attribute *attr, 3408 const char *buf, 3409 size_t count) 3410 { 3411 struct drm_device *ddev = dev_get_drvdata(dev); 3412 struct amdgpu_device *adev = drm_to_adev(ddev); 3413 int ret, idx; 3414 char fw_name[100]; 3415 const struct firmware *usbc_pd_fw; 3416 struct amdgpu_bo *fw_buf_bo = NULL; 3417 uint64_t fw_pri_mc_addr; 3418 void *fw_pri_cpu_addr; 3419 3420 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3421 DRM_INFO("PSP block is not ready yet."); 3422 return -EBUSY; 3423 } 3424 3425 if (!drm_dev_enter(ddev, &idx)) 3426 return -ENODEV; 3427 3428 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3429 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3430 if (ret) 3431 goto fail; 3432 3433 /* LFB address which is aligned to 1MB boundary per PSP request */ 3434 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3435 AMDGPU_GEM_DOMAIN_VRAM, 3436 &fw_buf_bo, 3437 &fw_pri_mc_addr, 3438 &fw_pri_cpu_addr); 3439 if (ret) 3440 goto rel_buf; 3441 3442 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3443 3444 mutex_lock(&adev->psp.mutex); 3445 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3446 mutex_unlock(&adev->psp.mutex); 3447 3448 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3449 3450 rel_buf: 3451 release_firmware(usbc_pd_fw); 3452 fail: 3453 if (ret) { 3454 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3455 count = ret; 3456 } 3457 3458 drm_dev_exit(idx); 3459 return count; 3460 } 3461 3462 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3463 { 3464 int idx; 3465 3466 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3467 return; 3468 3469 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3470 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3471 3472 drm_dev_exit(idx); 3473 } 3474 3475 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3476 psp_usbc_pd_fw_sysfs_read, 3477 psp_usbc_pd_fw_sysfs_write); 3478 3479 int is_psp_fw_valid(struct psp_bin_desc bin) 3480 { 3481 return bin.size_bytes; 3482 } 3483 3484 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3485 struct bin_attribute *bin_attr, 3486 char *buffer, loff_t pos, size_t count) 3487 { 3488 struct device *dev = kobj_to_dev(kobj); 3489 struct drm_device *ddev = dev_get_drvdata(dev); 3490 struct amdgpu_device *adev = drm_to_adev(ddev); 3491 3492 adev->psp.vbflash_done = false; 3493 3494 /* Safeguard against memory drain */ 3495 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3496 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3497 kvfree(adev->psp.vbflash_tmp_buf); 3498 adev->psp.vbflash_tmp_buf = NULL; 3499 adev->psp.vbflash_image_size = 0; 3500 return -ENOMEM; 3501 } 3502 3503 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3504 if (!adev->psp.vbflash_tmp_buf) { 3505 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3506 if (!adev->psp.vbflash_tmp_buf) 3507 return -ENOMEM; 3508 } 3509 3510 mutex_lock(&adev->psp.mutex); 3511 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3512 adev->psp.vbflash_image_size += count; 3513 mutex_unlock(&adev->psp.mutex); 3514 3515 dev_info(adev->dev, "VBIOS flash write PSP done"); 3516 3517 return count; 3518 } 3519 3520 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3521 struct bin_attribute *bin_attr, char *buffer, 3522 loff_t pos, size_t count) 3523 { 3524 struct device *dev = kobj_to_dev(kobj); 3525 struct drm_device *ddev = dev_get_drvdata(dev); 3526 struct amdgpu_device *adev = drm_to_adev(ddev); 3527 struct amdgpu_bo *fw_buf_bo = NULL; 3528 uint64_t fw_pri_mc_addr; 3529 void *fw_pri_cpu_addr; 3530 int ret; 3531 3532 dev_info(adev->dev, "VBIOS flash to PSP started"); 3533 3534 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3535 AMDGPU_GPU_PAGE_SIZE, 3536 AMDGPU_GEM_DOMAIN_VRAM, 3537 &fw_buf_bo, 3538 &fw_pri_mc_addr, 3539 &fw_pri_cpu_addr); 3540 if (ret) 3541 goto rel_buf; 3542 3543 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3544 3545 mutex_lock(&adev->psp.mutex); 3546 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3547 mutex_unlock(&adev->psp.mutex); 3548 3549 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3550 3551 rel_buf: 3552 kvfree(adev->psp.vbflash_tmp_buf); 3553 adev->psp.vbflash_tmp_buf = NULL; 3554 adev->psp.vbflash_image_size = 0; 3555 3556 if (ret) { 3557 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret); 3558 return ret; 3559 } 3560 3561 dev_info(adev->dev, "VBIOS flash to PSP done"); 3562 return 0; 3563 } 3564 3565 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3566 struct device_attribute *attr, 3567 char *buf) 3568 { 3569 struct drm_device *ddev = dev_get_drvdata(dev); 3570 struct amdgpu_device *adev = drm_to_adev(ddev); 3571 uint32_t vbflash_status; 3572 3573 vbflash_status = psp_vbflash_status(&adev->psp); 3574 if (!adev->psp.vbflash_done) 3575 vbflash_status = 0; 3576 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3577 vbflash_status = 1; 3578 3579 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3580 } 3581 3582 static const struct bin_attribute psp_vbflash_bin_attr = { 3583 .attr = {.name = "psp_vbflash", .mode = 0664}, 3584 .size = 0, 3585 .write = amdgpu_psp_vbflash_write, 3586 .read = amdgpu_psp_vbflash_read, 3587 }; 3588 3589 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL); 3590 3591 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev) 3592 { 3593 int ret = 0; 3594 struct psp_context *psp = &adev->psp; 3595 3596 if (amdgpu_sriov_vf(adev)) 3597 return -EINVAL; 3598 3599 switch (adev->ip_versions[MP0_HWIP][0]) { 3600 case IP_VERSION(13, 0, 0): 3601 case IP_VERSION(13, 0, 7): 3602 if (!psp->adev) { 3603 psp->adev = adev; 3604 psp_v13_0_set_psp_funcs(psp); 3605 } 3606 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3607 if (ret) 3608 dev_err(adev->dev, "Failed to create device file psp_vbflash"); 3609 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status); 3610 if (ret) 3611 dev_err(adev->dev, "Failed to create device file psp_vbflash_status"); 3612 return ret; 3613 default: 3614 return 0; 3615 } 3616 } 3617 3618 const struct amd_ip_funcs psp_ip_funcs = { 3619 .name = "psp", 3620 .early_init = psp_early_init, 3621 .late_init = NULL, 3622 .sw_init = psp_sw_init, 3623 .sw_fini = psp_sw_fini, 3624 .hw_init = psp_hw_init, 3625 .hw_fini = psp_hw_fini, 3626 .suspend = psp_suspend, 3627 .resume = psp_resume, 3628 .is_idle = NULL, 3629 .check_soft_reset = NULL, 3630 .wait_for_idle = NULL, 3631 .soft_reset = NULL, 3632 .set_clockgating_state = psp_set_clockgating_state, 3633 .set_powergating_state = psp_set_powergating_state, 3634 }; 3635 3636 static int psp_sysfs_init(struct amdgpu_device *adev) 3637 { 3638 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3639 3640 if (ret) 3641 DRM_ERROR("Failed to create USBC PD FW control file!"); 3642 3643 return ret; 3644 } 3645 3646 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev) 3647 { 3648 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3649 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status); 3650 } 3651 3652 static void psp_sysfs_fini(struct amdgpu_device *adev) 3653 { 3654 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3655 } 3656 3657 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3658 { 3659 .type = AMD_IP_BLOCK_TYPE_PSP, 3660 .major = 3, 3661 .minor = 1, 3662 .rev = 0, 3663 .funcs = &psp_ip_funcs, 3664 }; 3665 3666 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3667 { 3668 .type = AMD_IP_BLOCK_TYPE_PSP, 3669 .major = 10, 3670 .minor = 0, 3671 .rev = 0, 3672 .funcs = &psp_ip_funcs, 3673 }; 3674 3675 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3676 { 3677 .type = AMD_IP_BLOCK_TYPE_PSP, 3678 .major = 11, 3679 .minor = 0, 3680 .rev = 0, 3681 .funcs = &psp_ip_funcs, 3682 }; 3683 3684 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3685 .type = AMD_IP_BLOCK_TYPE_PSP, 3686 .major = 11, 3687 .minor = 0, 3688 .rev = 8, 3689 .funcs = &psp_ip_funcs, 3690 }; 3691 3692 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3693 { 3694 .type = AMD_IP_BLOCK_TYPE_PSP, 3695 .major = 12, 3696 .minor = 0, 3697 .rev = 0, 3698 .funcs = &psp_ip_funcs, 3699 }; 3700 3701 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3702 .type = AMD_IP_BLOCK_TYPE_PSP, 3703 .major = 13, 3704 .minor = 0, 3705 .rev = 0, 3706 .funcs = &psp_ip_funcs, 3707 }; 3708 3709 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3710 .type = AMD_IP_BLOCK_TYPE_PSP, 3711 .major = 13, 3712 .minor = 0, 3713 .rev = 4, 3714 .funcs = &psp_ip_funcs, 3715 }; 3716