1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 41 #include "amdgpu_ras.h" 42 #include "amdgpu_securedisplay.h" 43 #include "amdgpu_atomfirmware.h" 44 45 static int psp_sysfs_init(struct amdgpu_device *adev); 46 static void psp_sysfs_fini(struct amdgpu_device *adev); 47 48 static int psp_load_smu_fw(struct psp_context *psp); 49 static int psp_ta_unload(struct psp_context *psp, struct ta_context *context); 50 static int psp_ta_load(struct psp_context *psp, struct ta_context *context); 51 static int psp_rap_terminate(struct psp_context *psp); 52 static int psp_securedisplay_terminate(struct psp_context *psp); 53 54 /* 55 * Due to DF Cstate management centralized to PMFW, the firmware 56 * loading sequence will be updated as below: 57 * - Load KDB 58 * - Load SYS_DRV 59 * - Load tOS 60 * - Load PMFW 61 * - Setup TMR 62 * - Load other non-psp fw 63 * - Load ASD 64 * - Load XGMI/RAS/HDCP/DTM TA if any 65 * 66 * This new sequence is required for 67 * - Arcturus and onwards 68 */ 69 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 70 { 71 struct amdgpu_device *adev = psp->adev; 72 73 if (amdgpu_sriov_vf(adev)) { 74 psp->pmfw_centralized_cstate_management = false; 75 return; 76 } 77 78 switch (adev->ip_versions[MP0_HWIP][0]) { 79 case IP_VERSION(11, 0, 0): 80 case IP_VERSION(11, 0, 4): 81 case IP_VERSION(11, 0, 5): 82 case IP_VERSION(11, 0, 7): 83 case IP_VERSION(11, 0, 9): 84 case IP_VERSION(11, 0, 11): 85 case IP_VERSION(11, 0, 12): 86 case IP_VERSION(11, 0, 13): 87 case IP_VERSION(13, 0, 2): 88 psp->pmfw_centralized_cstate_management = true; 89 break; 90 default: 91 psp->pmfw_centralized_cstate_management = false; 92 break; 93 } 94 } 95 96 static int psp_early_init(void *handle) 97 { 98 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 99 struct psp_context *psp = &adev->psp; 100 101 switch (adev->ip_versions[MP0_HWIP][0]) { 102 case IP_VERSION(9, 0, 0): 103 psp_v3_1_set_psp_funcs(psp); 104 psp->autoload_supported = false; 105 break; 106 case IP_VERSION(10, 0, 0): 107 case IP_VERSION(10, 0, 1): 108 psp_v10_0_set_psp_funcs(psp); 109 psp->autoload_supported = false; 110 break; 111 case IP_VERSION(11, 0, 2): 112 case IP_VERSION(11, 0, 4): 113 psp_v11_0_set_psp_funcs(psp); 114 psp->autoload_supported = false; 115 break; 116 case IP_VERSION(11, 0, 0): 117 case IP_VERSION(11, 0, 5): 118 case IP_VERSION(11, 0, 9): 119 case IP_VERSION(11, 0, 7): 120 case IP_VERSION(11, 0, 11): 121 case IP_VERSION(11, 5, 0): 122 case IP_VERSION(11, 0, 12): 123 case IP_VERSION(11, 0, 13): 124 psp_v11_0_set_psp_funcs(psp); 125 psp->autoload_supported = true; 126 break; 127 case IP_VERSION(11, 0, 3): 128 case IP_VERSION(12, 0, 1): 129 psp_v12_0_set_psp_funcs(psp); 130 break; 131 case IP_VERSION(13, 0, 2): 132 psp_v13_0_set_psp_funcs(psp); 133 break; 134 case IP_VERSION(13, 0, 1): 135 case IP_VERSION(13, 0, 3): 136 psp_v13_0_set_psp_funcs(psp); 137 psp->autoload_supported = true; 138 break; 139 case IP_VERSION(11, 0, 8): 140 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 141 psp_v11_0_8_set_psp_funcs(psp); 142 psp->autoload_supported = false; 143 } 144 break; 145 default: 146 return -EINVAL; 147 } 148 149 psp->adev = adev; 150 151 psp_check_pmfw_centralized_cstate_management(psp); 152 153 return 0; 154 } 155 156 static void psp_memory_training_fini(struct psp_context *psp) 157 { 158 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 159 160 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 161 kfree(ctx->sys_cache); 162 ctx->sys_cache = NULL; 163 } 164 165 static int psp_memory_training_init(struct psp_context *psp) 166 { 167 int ret; 168 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 169 170 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 171 DRM_DEBUG("memory training is not supported!\n"); 172 return 0; 173 } 174 175 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 176 if (ctx->sys_cache == NULL) { 177 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 178 ret = -ENOMEM; 179 goto Err_out; 180 } 181 182 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 183 ctx->train_data_size, 184 ctx->p2c_train_data_offset, 185 ctx->c2p_train_data_offset); 186 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 187 return 0; 188 189 Err_out: 190 psp_memory_training_fini(psp); 191 return ret; 192 } 193 194 /* 195 * Helper funciton to query psp runtime database entry 196 * 197 * @adev: amdgpu_device pointer 198 * @entry_type: the type of psp runtime database entry 199 * @db_entry: runtime database entry pointer 200 * 201 * Return false if runtime database doesn't exit or entry is invalid 202 * or true if the specific database entry is found, and copy to @db_entry 203 */ 204 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 205 enum psp_runtime_entry_type entry_type, 206 void *db_entry) 207 { 208 uint64_t db_header_pos, db_dir_pos; 209 struct psp_runtime_data_header db_header = {0}; 210 struct psp_runtime_data_directory db_dir = {0}; 211 bool ret = false; 212 int i; 213 214 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 215 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 216 217 /* read runtime db header from vram */ 218 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 219 sizeof(struct psp_runtime_data_header), false); 220 221 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 222 /* runtime db doesn't exist, exit */ 223 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 224 return false; 225 } 226 227 /* read runtime database entry from vram */ 228 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 229 sizeof(struct psp_runtime_data_directory), false); 230 231 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 232 /* invalid db entry count, exit */ 233 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 234 return false; 235 } 236 237 /* look up for requested entry type */ 238 for (i = 0; i < db_dir.entry_count && !ret; i++) { 239 if (db_dir.entry_list[i].entry_type == entry_type) { 240 switch (entry_type) { 241 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 242 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 243 /* invalid db entry size */ 244 dev_warn(adev->dev, "Invalid PSP runtime database entry size\n"); 245 return false; 246 } 247 /* read runtime database entry */ 248 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 249 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 250 ret = true; 251 break; 252 default: 253 ret = false; 254 break; 255 } 256 } 257 } 258 259 return ret; 260 } 261 262 static int psp_init_sriov_microcode(struct psp_context *psp) 263 { 264 struct amdgpu_device *adev = psp->adev; 265 int ret = 0; 266 267 switch (adev->ip_versions[MP0_HWIP][0]) { 268 case IP_VERSION(9, 0, 0): 269 ret = psp_init_cap_microcode(psp, "vega10"); 270 break; 271 case IP_VERSION(11, 0, 9): 272 ret = psp_init_cap_microcode(psp, "navi12"); 273 break; 274 case IP_VERSION(11, 0, 7): 275 ret = psp_init_cap_microcode(psp, "sienna_cichlid"); 276 break; 277 case IP_VERSION(13, 0, 2): 278 ret = psp_init_ta_microcode(psp, "aldebaran"); 279 break; 280 default: 281 BUG(); 282 break; 283 } 284 285 return ret; 286 } 287 288 static int psp_sw_init(void *handle) 289 { 290 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 291 struct psp_context *psp = &adev->psp; 292 int ret; 293 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 294 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 295 296 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 297 if (!psp->cmd) { 298 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 299 ret = -ENOMEM; 300 } 301 302 if (amdgpu_sriov_vf(adev)) 303 ret = psp_init_sriov_microcode(psp); 304 else 305 ret = psp_init_microcode(psp); 306 if (ret) { 307 DRM_ERROR("Failed to load psp firmware!\n"); 308 return ret; 309 } 310 311 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 312 if (psp_get_runtime_db_entry(adev, 313 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 314 &boot_cfg_entry)) { 315 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 316 if ((psp->boot_cfg_bitmask) & 317 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 318 /* If psp runtime database exists, then 319 * only enable two stage memory training 320 * when TWO_STAGE_DRAM_TRAINING bit is set 321 * in runtime database */ 322 mem_training_ctx->enable_mem_training = true; 323 } 324 325 } else { 326 /* If psp runtime database doesn't exist or 327 * is invalid, force enable two stage memory 328 * training */ 329 mem_training_ctx->enable_mem_training = true; 330 } 331 332 if (mem_training_ctx->enable_mem_training) { 333 ret = psp_memory_training_init(psp); 334 if (ret) { 335 DRM_ERROR("Failed to initialize memory training!\n"); 336 return ret; 337 } 338 339 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 340 if (ret) { 341 DRM_ERROR("Failed to process memory training!\n"); 342 return ret; 343 } 344 } 345 346 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 347 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 348 ret= psp_sysfs_init(adev); 349 if (ret) { 350 return ret; 351 } 352 } 353 354 return 0; 355 } 356 357 static int psp_sw_fini(void *handle) 358 { 359 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 360 struct psp_context *psp = &adev->psp; 361 struct psp_gfx_cmd_resp *cmd = psp->cmd; 362 363 psp_memory_training_fini(psp); 364 if (psp->sos_fw) { 365 release_firmware(psp->sos_fw); 366 psp->sos_fw = NULL; 367 } 368 if (psp->asd_fw) { 369 release_firmware(psp->asd_fw); 370 psp->asd_fw = NULL; 371 } 372 if (psp->ta_fw) { 373 release_firmware(psp->ta_fw); 374 psp->ta_fw = NULL; 375 } 376 if (adev->psp.cap_fw) { 377 release_firmware(psp->cap_fw); 378 psp->cap_fw = NULL; 379 } 380 381 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 382 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 383 psp_sysfs_fini(adev); 384 385 kfree(cmd); 386 cmd = NULL; 387 388 return 0; 389 } 390 391 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 392 uint32_t reg_val, uint32_t mask, bool check_changed) 393 { 394 uint32_t val; 395 int i; 396 struct amdgpu_device *adev = psp->adev; 397 398 if (psp->adev->no_hw_access) 399 return 0; 400 401 for (i = 0; i < adev->usec_timeout; i++) { 402 val = RREG32(reg_index); 403 if (check_changed) { 404 if (val != reg_val) 405 return 0; 406 } else { 407 if ((val & mask) == reg_val) 408 return 0; 409 } 410 udelay(1); 411 } 412 413 return -ETIME; 414 } 415 416 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 417 { 418 switch (cmd_id) { 419 case GFX_CMD_ID_LOAD_TA: 420 return "LOAD_TA"; 421 case GFX_CMD_ID_UNLOAD_TA: 422 return "UNLOAD_TA"; 423 case GFX_CMD_ID_INVOKE_CMD: 424 return "INVOKE_CMD"; 425 case GFX_CMD_ID_LOAD_ASD: 426 return "LOAD_ASD"; 427 case GFX_CMD_ID_SETUP_TMR: 428 return "SETUP_TMR"; 429 case GFX_CMD_ID_LOAD_IP_FW: 430 return "LOAD_IP_FW"; 431 case GFX_CMD_ID_DESTROY_TMR: 432 return "DESTROY_TMR"; 433 case GFX_CMD_ID_SAVE_RESTORE: 434 return "SAVE_RESTORE_IP_FW"; 435 case GFX_CMD_ID_SETUP_VMR: 436 return "SETUP_VMR"; 437 case GFX_CMD_ID_DESTROY_VMR: 438 return "DESTROY_VMR"; 439 case GFX_CMD_ID_PROG_REG: 440 return "PROG_REG"; 441 case GFX_CMD_ID_GET_FW_ATTESTATION: 442 return "GET_FW_ATTESTATION"; 443 case GFX_CMD_ID_LOAD_TOC: 444 return "ID_LOAD_TOC"; 445 case GFX_CMD_ID_AUTOLOAD_RLC: 446 return "AUTOLOAD_RLC"; 447 case GFX_CMD_ID_BOOT_CFG: 448 return "BOOT_CFG"; 449 default: 450 return "UNKNOWN CMD"; 451 } 452 } 453 454 static int 455 psp_cmd_submit_buf(struct psp_context *psp, 456 struct amdgpu_firmware_info *ucode, 457 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 458 { 459 int ret; 460 int index, idx; 461 int timeout = 20000; 462 bool ras_intr = false; 463 bool skip_unsupport = false; 464 465 if (psp->adev->no_hw_access) 466 return 0; 467 468 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 469 return 0; 470 471 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 472 473 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 474 475 index = atomic_inc_return(&psp->fence_value); 476 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 477 if (ret) { 478 atomic_dec(&psp->fence_value); 479 goto exit; 480 } 481 482 amdgpu_device_invalidate_hdp(psp->adev, NULL); 483 while (*((unsigned int *)psp->fence_buf) != index) { 484 if (--timeout == 0) 485 break; 486 /* 487 * Shouldn't wait for timeout when err_event_athub occurs, 488 * because gpu reset thread triggered and lock resource should 489 * be released for psp resume sequence. 490 */ 491 ras_intr = amdgpu_ras_intr_triggered(); 492 if (ras_intr) 493 break; 494 usleep_range(10, 100); 495 amdgpu_device_invalidate_hdp(psp->adev, NULL); 496 } 497 498 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 499 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 500 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 501 502 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 503 504 /* In some cases, psp response status is not 0 even there is no 505 * problem while the command is submitted. Some version of PSP FW 506 * doesn't write 0 to that field. 507 * So here we would like to only print a warning instead of an error 508 * during psp initialization to avoid breaking hw_init and it doesn't 509 * return -EINVAL. 510 */ 511 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 512 if (ucode) 513 DRM_WARN("failed to load ucode %s(0x%X) ", 514 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 515 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 516 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 517 psp->cmd_buf_mem->resp.status); 518 /* If we load CAP FW, PSP must return 0 under SRIOV 519 * also return failure in case of timeout 520 */ 521 if ((ucode && (ucode->ucode_id == AMDGPU_UCODE_ID_CAP)) || !timeout) { 522 ret = -EINVAL; 523 goto exit; 524 } 525 } 526 527 if (ucode) { 528 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 529 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 530 } 531 532 exit: 533 drm_dev_exit(idx); 534 return ret; 535 } 536 537 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 538 { 539 struct psp_gfx_cmd_resp *cmd = psp->cmd; 540 541 mutex_lock(&psp->mutex); 542 543 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 544 545 return cmd; 546 } 547 548 static void release_psp_cmd_buf(struct psp_context *psp) 549 { 550 mutex_unlock(&psp->mutex); 551 } 552 553 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 554 struct psp_gfx_cmd_resp *cmd, 555 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 556 { 557 struct amdgpu_device *adev = psp->adev; 558 uint32_t size = amdgpu_bo_size(tmr_bo); 559 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 560 561 if (amdgpu_sriov_vf(psp->adev)) 562 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 563 else 564 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 565 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 566 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 567 cmd->cmd.cmd_setup_tmr.buf_size = size; 568 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 569 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 570 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 571 } 572 573 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 574 uint64_t pri_buf_mc, uint32_t size) 575 { 576 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 577 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 578 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 579 cmd->cmd.cmd_load_toc.toc_size = size; 580 } 581 582 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 583 static int psp_load_toc(struct psp_context *psp, 584 uint32_t *tmr_size) 585 { 586 int ret; 587 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 588 589 /* Copy toc to psp firmware private buffer */ 590 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 591 592 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 593 594 ret = psp_cmd_submit_buf(psp, NULL, cmd, 595 psp->fence_buf_mc_addr); 596 if (!ret) 597 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 598 599 release_psp_cmd_buf(psp); 600 601 return ret; 602 } 603 604 /* Set up Trusted Memory Region */ 605 static int psp_tmr_init(struct psp_context *psp) 606 { 607 int ret; 608 int tmr_size; 609 void *tmr_buf; 610 void **pptr; 611 612 /* 613 * According to HW engineer, they prefer the TMR address be "naturally 614 * aligned" , e.g. the start address be an integer divide of TMR size. 615 * 616 * Note: this memory need be reserved till the driver 617 * uninitializes. 618 */ 619 tmr_size = PSP_TMR_SIZE(psp->adev); 620 621 /* For ASICs support RLC autoload, psp will parse the toc 622 * and calculate the total size of TMR needed */ 623 if (!amdgpu_sriov_vf(psp->adev) && 624 psp->toc.start_addr && 625 psp->toc.size_bytes && 626 psp->fw_pri_buf) { 627 ret = psp_load_toc(psp, &tmr_size); 628 if (ret) { 629 DRM_ERROR("Failed to load toc\n"); 630 return ret; 631 } 632 } 633 634 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 635 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 636 AMDGPU_GEM_DOMAIN_VRAM, 637 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 638 639 return ret; 640 } 641 642 static bool psp_skip_tmr(struct psp_context *psp) 643 { 644 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 645 case IP_VERSION(11, 0, 9): 646 case IP_VERSION(11, 0, 7): 647 case IP_VERSION(13, 0, 2): 648 return true; 649 default: 650 return false; 651 } 652 } 653 654 static int psp_tmr_load(struct psp_context *psp) 655 { 656 int ret; 657 struct psp_gfx_cmd_resp *cmd; 658 659 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 660 * Already set up by host driver. 661 */ 662 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 663 return 0; 664 665 cmd = acquire_psp_cmd_buf(psp); 666 667 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 668 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 669 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 670 671 ret = psp_cmd_submit_buf(psp, NULL, cmd, 672 psp->fence_buf_mc_addr); 673 674 release_psp_cmd_buf(psp); 675 676 return ret; 677 } 678 679 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 680 struct psp_gfx_cmd_resp *cmd) 681 { 682 if (amdgpu_sriov_vf(psp->adev)) 683 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 684 else 685 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 686 } 687 688 static int psp_tmr_unload(struct psp_context *psp) 689 { 690 int ret; 691 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 692 693 psp_prep_tmr_unload_cmd_buf(psp, cmd); 694 DRM_INFO("free PSP TMR buffer\n"); 695 696 ret = psp_cmd_submit_buf(psp, NULL, cmd, 697 psp->fence_buf_mc_addr); 698 699 release_psp_cmd_buf(psp); 700 701 return ret; 702 } 703 704 static int psp_tmr_terminate(struct psp_context *psp) 705 { 706 int ret; 707 void *tmr_buf; 708 void **pptr; 709 710 ret = psp_tmr_unload(psp); 711 if (ret) 712 return ret; 713 714 /* free TMR memory buffer */ 715 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 716 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 717 718 return 0; 719 } 720 721 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 722 uint64_t *output_ptr) 723 { 724 int ret; 725 struct psp_gfx_cmd_resp *cmd; 726 727 if (!output_ptr) 728 return -EINVAL; 729 730 if (amdgpu_sriov_vf(psp->adev)) 731 return 0; 732 733 cmd = acquire_psp_cmd_buf(psp); 734 735 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 736 737 ret = psp_cmd_submit_buf(psp, NULL, cmd, 738 psp->fence_buf_mc_addr); 739 740 if (!ret) { 741 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 742 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 743 } 744 745 release_psp_cmd_buf(psp); 746 747 return ret; 748 } 749 750 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 751 { 752 struct psp_context *psp = &adev->psp; 753 struct psp_gfx_cmd_resp *cmd; 754 int ret; 755 756 if (amdgpu_sriov_vf(adev)) 757 return 0; 758 759 cmd = acquire_psp_cmd_buf(psp); 760 761 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 762 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 763 764 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 765 if (!ret) { 766 *boot_cfg = 767 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 768 } 769 770 release_psp_cmd_buf(psp); 771 772 return ret; 773 } 774 775 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 776 { 777 int ret; 778 struct psp_context *psp = &adev->psp; 779 struct psp_gfx_cmd_resp *cmd; 780 781 if (amdgpu_sriov_vf(adev)) 782 return 0; 783 784 cmd = acquire_psp_cmd_buf(psp); 785 786 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 787 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 788 cmd->cmd.boot_cfg.boot_config = boot_cfg; 789 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 790 791 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 792 793 release_psp_cmd_buf(psp); 794 795 return ret; 796 } 797 798 static int psp_rl_load(struct amdgpu_device *adev) 799 { 800 int ret; 801 struct psp_context *psp = &adev->psp; 802 struct psp_gfx_cmd_resp *cmd; 803 804 if (!is_psp_fw_valid(psp->rl)) 805 return 0; 806 807 cmd = acquire_psp_cmd_buf(psp); 808 809 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 810 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 811 812 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 813 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 814 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 815 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 816 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 817 818 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 819 820 release_psp_cmd_buf(psp); 821 822 return ret; 823 } 824 825 static int psp_asd_load(struct psp_context *psp) 826 { 827 return psp_ta_load(psp, &psp->asd_context); 828 } 829 830 static int psp_asd_initialize(struct psp_context *psp) 831 { 832 int ret; 833 834 /* If PSP version doesn't match ASD version, asd loading will be failed. 835 * add workaround to bypass it for sriov now. 836 * TODO: add version check to make it common 837 */ 838 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 839 return 0; 840 841 psp->asd_context.mem_context.shared_mc_addr = 0; 842 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 843 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 844 845 ret = psp_asd_load(psp); 846 if (!ret) 847 psp->asd_context.initialized = true; 848 849 return ret; 850 } 851 852 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 853 uint32_t session_id) 854 { 855 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 856 cmd->cmd.cmd_unload_ta.session_id = session_id; 857 } 858 859 static int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 860 { 861 int ret; 862 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 863 864 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 865 866 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 867 868 release_psp_cmd_buf(psp); 869 870 return ret; 871 } 872 873 static int psp_asd_unload(struct psp_context *psp) 874 { 875 return psp_ta_unload(psp, &psp->asd_context); 876 } 877 878 static int psp_asd_terminate(struct psp_context *psp) 879 { 880 int ret; 881 882 if (amdgpu_sriov_vf(psp->adev)) 883 return 0; 884 885 if (!psp->asd_context.initialized) 886 return 0; 887 888 ret = psp_asd_unload(psp); 889 890 if (!ret) 891 psp->asd_context.initialized = false; 892 893 return ret; 894 } 895 896 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 897 uint32_t id, uint32_t value) 898 { 899 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 900 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 901 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 902 } 903 904 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 905 uint32_t value) 906 { 907 struct psp_gfx_cmd_resp *cmd; 908 int ret = 0; 909 910 if (reg >= PSP_REG_LAST) 911 return -EINVAL; 912 913 cmd = acquire_psp_cmd_buf(psp); 914 915 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 916 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 917 if (ret) 918 DRM_ERROR("PSP failed to program reg id %d", reg); 919 920 release_psp_cmd_buf(psp); 921 922 return ret; 923 } 924 925 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 926 uint64_t ta_bin_mc, 927 struct ta_context *context) 928 { 929 cmd->cmd_id = context->ta_load_type; 930 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 931 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 932 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 933 934 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 935 lower_32_bits(context->mem_context.shared_mc_addr); 936 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 937 upper_32_bits(context->mem_context.shared_mc_addr); 938 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 939 } 940 941 static int psp_ta_init_shared_buf(struct psp_context *psp, 942 struct ta_mem_context *mem_ctx) 943 { 944 /* 945 * Allocate 16k memory aligned to 4k from Frame Buffer (local 946 * physical) for ta to host memory 947 */ 948 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 949 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 950 &mem_ctx->shared_bo, 951 &mem_ctx->shared_mc_addr, 952 &mem_ctx->shared_buf); 953 } 954 955 static void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 956 { 957 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 958 &mem_ctx->shared_buf); 959 } 960 961 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 962 { 963 return psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 964 } 965 966 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 967 uint32_t ta_cmd_id, 968 uint32_t session_id) 969 { 970 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 971 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 972 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 973 } 974 975 static int psp_ta_invoke(struct psp_context *psp, 976 uint32_t ta_cmd_id, 977 struct ta_context *context) 978 { 979 int ret; 980 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 981 982 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 983 984 ret = psp_cmd_submit_buf(psp, NULL, cmd, 985 psp->fence_buf_mc_addr); 986 987 release_psp_cmd_buf(psp); 988 989 return ret; 990 } 991 992 static int psp_ta_load(struct psp_context *psp, struct ta_context *context) 993 { 994 int ret; 995 struct psp_gfx_cmd_resp *cmd; 996 997 cmd = acquire_psp_cmd_buf(psp); 998 999 psp_copy_fw(psp, context->bin_desc.start_addr, 1000 context->bin_desc.size_bytes); 1001 1002 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1003 1004 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1005 psp->fence_buf_mc_addr); 1006 1007 if (!ret) { 1008 context->session_id = cmd->resp.session_id; 1009 } 1010 1011 release_psp_cmd_buf(psp); 1012 1013 return ret; 1014 } 1015 1016 static int psp_xgmi_load(struct psp_context *psp) 1017 { 1018 return psp_ta_load(psp, &psp->xgmi_context.context); 1019 } 1020 1021 static int psp_xgmi_unload(struct psp_context *psp) 1022 { 1023 return psp_ta_unload(psp, &psp->xgmi_context.context); 1024 } 1025 1026 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1027 { 1028 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1029 } 1030 1031 int psp_xgmi_terminate(struct psp_context *psp) 1032 { 1033 int ret; 1034 struct amdgpu_device *adev = psp->adev; 1035 1036 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1037 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1038 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1039 adev->gmc.xgmi.connected_to_cpu)) 1040 return 0; 1041 1042 if (!psp->xgmi_context.context.initialized) 1043 return 0; 1044 1045 ret = psp_xgmi_unload(psp); 1046 if (ret) 1047 return ret; 1048 1049 psp->xgmi_context.context.initialized = false; 1050 1051 /* free xgmi shared memory */ 1052 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 1053 1054 return 0; 1055 } 1056 1057 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1058 { 1059 struct ta_xgmi_shared_memory *xgmi_cmd; 1060 int ret; 1061 1062 if (!psp->ta_fw || 1063 !psp->xgmi_context.context.bin_desc.size_bytes || 1064 !psp->xgmi_context.context.bin_desc.start_addr) 1065 return -ENOENT; 1066 1067 if (!load_ta) 1068 goto invoke; 1069 1070 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1071 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1072 1073 if (!psp->xgmi_context.context.initialized) { 1074 ret = psp_xgmi_init_shared_buf(psp); 1075 if (ret) 1076 return ret; 1077 } 1078 1079 /* Load XGMI TA */ 1080 ret = psp_xgmi_load(psp); 1081 if (!ret) 1082 psp->xgmi_context.context.initialized = true; 1083 else 1084 return ret; 1085 1086 invoke: 1087 /* Initialize XGMI session */ 1088 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1089 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1090 xgmi_cmd->flag_extend_link_record = set_extended_data; 1091 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1092 1093 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1094 1095 return ret; 1096 } 1097 1098 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1099 { 1100 struct ta_xgmi_shared_memory *xgmi_cmd; 1101 int ret; 1102 1103 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1104 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1105 1106 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1107 1108 /* Invoke xgmi ta to get hive id */ 1109 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1110 if (ret) 1111 return ret; 1112 1113 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1114 1115 return 0; 1116 } 1117 1118 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1119 { 1120 struct ta_xgmi_shared_memory *xgmi_cmd; 1121 int ret; 1122 1123 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1124 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1125 1126 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1127 1128 /* Invoke xgmi ta to get the node id */ 1129 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1130 if (ret) 1131 return ret; 1132 1133 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1134 1135 return 0; 1136 } 1137 1138 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1139 { 1140 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1141 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1142 } 1143 1144 /* 1145 * Chips that support extended topology information require the driver to 1146 * reflect topology information in the opposite direction. This is 1147 * because the TA has already exceeded its link record limit and if the 1148 * TA holds bi-directional information, the driver would have to do 1149 * multiple fetches instead of just two. 1150 */ 1151 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1152 struct psp_xgmi_node_info node_info) 1153 { 1154 struct amdgpu_device *mirror_adev; 1155 struct amdgpu_hive_info *hive; 1156 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1157 uint64_t dst_node_id = node_info.node_id; 1158 uint8_t dst_num_hops = node_info.num_hops; 1159 uint8_t dst_num_links = node_info.num_links; 1160 1161 hive = amdgpu_get_xgmi_hive(psp->adev); 1162 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1163 struct psp_xgmi_topology_info *mirror_top_info; 1164 int j; 1165 1166 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1167 continue; 1168 1169 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1170 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1171 if (mirror_top_info->nodes[j].node_id != src_node_id) 1172 continue; 1173 1174 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1175 /* 1176 * prevent 0 num_links value re-reflection since reflection 1177 * criteria is based on num_hops (direct or indirect). 1178 * 1179 */ 1180 if (dst_num_links) 1181 mirror_top_info->nodes[j].num_links = dst_num_links; 1182 1183 break; 1184 } 1185 1186 break; 1187 } 1188 } 1189 1190 int psp_xgmi_get_topology_info(struct psp_context *psp, 1191 int number_devices, 1192 struct psp_xgmi_topology_info *topology, 1193 bool get_extended_data) 1194 { 1195 struct ta_xgmi_shared_memory *xgmi_cmd; 1196 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1197 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1198 int i; 1199 int ret; 1200 1201 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1202 return -EINVAL; 1203 1204 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1205 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1206 xgmi_cmd->flag_extend_link_record = get_extended_data; 1207 1208 /* Fill in the shared memory with topology information as input */ 1209 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1210 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1211 topology_info_input->num_nodes = number_devices; 1212 1213 for (i = 0; i < topology_info_input->num_nodes; i++) { 1214 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1215 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1216 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1217 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1218 } 1219 1220 /* Invoke xgmi ta to get the topology information */ 1221 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1222 if (ret) 1223 return ret; 1224 1225 /* Read the output topology information from the shared memory */ 1226 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1227 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1228 for (i = 0; i < topology->num_nodes; i++) { 1229 /* extended data will either be 0 or equal to non-extended data */ 1230 if (topology_info_output->nodes[i].num_hops) 1231 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1232 1233 /* non-extended data gets everything here so no need to update */ 1234 if (!get_extended_data) { 1235 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1236 topology->nodes[i].is_sharing_enabled = 1237 topology_info_output->nodes[i].is_sharing_enabled; 1238 topology->nodes[i].sdma_engine = 1239 topology_info_output->nodes[i].sdma_engine; 1240 } 1241 1242 } 1243 1244 /* Invoke xgmi ta again to get the link information */ 1245 if (psp_xgmi_peer_link_info_supported(psp)) { 1246 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1247 1248 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1249 1250 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1251 1252 if (ret) 1253 return ret; 1254 1255 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1256 for (i = 0; i < topology->num_nodes; i++) { 1257 /* accumulate num_links on extended data */ 1258 topology->nodes[i].num_links = get_extended_data ? 1259 topology->nodes[i].num_links + 1260 link_info_output->nodes[i].num_links : 1261 link_info_output->nodes[i].num_links; 1262 1263 /* reflect the topology information for bi-directionality */ 1264 if (psp->xgmi_context.supports_extended_data && 1265 get_extended_data && topology->nodes[i].num_hops) 1266 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1267 } 1268 } 1269 1270 return 0; 1271 } 1272 1273 int psp_xgmi_set_topology_info(struct psp_context *psp, 1274 int number_devices, 1275 struct psp_xgmi_topology_info *topology) 1276 { 1277 struct ta_xgmi_shared_memory *xgmi_cmd; 1278 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1279 int i; 1280 1281 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1282 return -EINVAL; 1283 1284 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1285 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1286 1287 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1288 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1289 topology_info_input->num_nodes = number_devices; 1290 1291 for (i = 0; i < topology_info_input->num_nodes; i++) { 1292 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1293 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1294 topology_info_input->nodes[i].is_sharing_enabled = 1; 1295 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1296 } 1297 1298 /* Invoke xgmi ta to set topology information */ 1299 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1300 } 1301 1302 // ras begin 1303 static int psp_ras_init_shared_buf(struct psp_context *psp) 1304 { 1305 return psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1306 } 1307 1308 static int psp_ras_load(struct psp_context *psp) 1309 { 1310 return psp_ta_load(psp, &psp->ras_context.context); 1311 } 1312 1313 static int psp_ras_unload(struct psp_context *psp) 1314 { 1315 return psp_ta_unload(psp, &psp->ras_context.context); 1316 } 1317 1318 static void psp_ras_ta_check_status(struct psp_context *psp) 1319 { 1320 struct ta_ras_shared_memory *ras_cmd = 1321 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1322 1323 switch (ras_cmd->ras_status) { 1324 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1325 dev_warn(psp->adev->dev, 1326 "RAS WARNING: cmd failed due to unsupported ip\n"); 1327 break; 1328 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1329 dev_warn(psp->adev->dev, 1330 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1331 break; 1332 case TA_RAS_STATUS__SUCCESS: 1333 break; 1334 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1335 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1336 dev_warn(psp->adev->dev, 1337 "RAS WARNING: Inject error to critical region is not allowed\n"); 1338 break; 1339 default: 1340 dev_warn(psp->adev->dev, 1341 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1342 break; 1343 } 1344 } 1345 1346 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1347 { 1348 struct ta_ras_shared_memory *ras_cmd; 1349 int ret; 1350 1351 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1352 1353 /* 1354 * TODO: bypass the loading in sriov for now 1355 */ 1356 if (amdgpu_sriov_vf(psp->adev)) 1357 return 0; 1358 1359 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1360 1361 if (amdgpu_ras_intr_triggered()) 1362 return ret; 1363 1364 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1365 { 1366 DRM_WARN("RAS: Unsupported Interface"); 1367 return -EINVAL; 1368 } 1369 1370 if (!ret) { 1371 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1372 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1373 1374 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1375 } 1376 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1377 dev_warn(psp->adev->dev, 1378 "RAS internal register access blocked\n"); 1379 1380 psp_ras_ta_check_status(psp); 1381 } 1382 1383 return ret; 1384 } 1385 1386 int psp_ras_enable_features(struct psp_context *psp, 1387 union ta_ras_cmd_input *info, bool enable) 1388 { 1389 struct ta_ras_shared_memory *ras_cmd; 1390 int ret; 1391 1392 if (!psp->ras_context.context.initialized) 1393 return -EINVAL; 1394 1395 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1396 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1397 1398 if (enable) 1399 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1400 else 1401 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1402 1403 ras_cmd->ras_in_message = *info; 1404 1405 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1406 if (ret) 1407 return -EINVAL; 1408 1409 return 0; 1410 } 1411 1412 static int psp_ras_terminate(struct psp_context *psp) 1413 { 1414 int ret; 1415 1416 /* 1417 * TODO: bypass the terminate in sriov for now 1418 */ 1419 if (amdgpu_sriov_vf(psp->adev)) 1420 return 0; 1421 1422 if (!psp->ras_context.context.initialized) 1423 return 0; 1424 1425 ret = psp_ras_unload(psp); 1426 if (ret) 1427 return ret; 1428 1429 psp->ras_context.context.initialized = false; 1430 1431 /* free ras shared memory */ 1432 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 1433 1434 return 0; 1435 } 1436 1437 static int psp_ras_initialize(struct psp_context *psp) 1438 { 1439 int ret; 1440 uint32_t boot_cfg = 0xFF; 1441 struct amdgpu_device *adev = psp->adev; 1442 struct ta_ras_shared_memory *ras_cmd; 1443 1444 /* 1445 * TODO: bypass the initialize in sriov for now 1446 */ 1447 if (amdgpu_sriov_vf(adev)) 1448 return 0; 1449 1450 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1451 !adev->psp.ras_context.context.bin_desc.start_addr) { 1452 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1453 return 0; 1454 } 1455 1456 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1457 /* query GECC enablement status from boot config 1458 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1459 */ 1460 ret = psp_boot_config_get(adev, &boot_cfg); 1461 if (ret) 1462 dev_warn(adev->dev, "PSP get boot config failed\n"); 1463 1464 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1465 if (!boot_cfg) { 1466 dev_info(adev->dev, "GECC is disabled\n"); 1467 } else { 1468 /* disable GECC in next boot cycle if ras is 1469 * disabled by module parameter amdgpu_ras_enable 1470 * and/or amdgpu_ras_mask, or boot_config_get call 1471 * is failed 1472 */ 1473 ret = psp_boot_config_set(adev, 0); 1474 if (ret) 1475 dev_warn(adev->dev, "PSP set boot config failed\n"); 1476 else 1477 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1478 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1479 } 1480 } else { 1481 if (1 == boot_cfg) { 1482 dev_info(adev->dev, "GECC is enabled\n"); 1483 } else { 1484 /* enable GECC in next boot cycle if it is disabled 1485 * in boot config, or force enable GECC if failed to 1486 * get boot configuration 1487 */ 1488 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1489 if (ret) 1490 dev_warn(adev->dev, "PSP set boot config failed\n"); 1491 else 1492 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1493 } 1494 } 1495 } 1496 1497 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1498 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1499 1500 if (!psp->ras_context.context.initialized) { 1501 ret = psp_ras_init_shared_buf(psp); 1502 if (ret) 1503 return ret; 1504 } 1505 1506 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1507 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1508 1509 if (amdgpu_ras_is_poison_mode_supported(adev)) 1510 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1511 if (!adev->gmc.xgmi.connected_to_cpu) 1512 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1513 1514 ret = psp_ras_load(psp); 1515 1516 if (!ret && !ras_cmd->ras_status) 1517 psp->ras_context.context.initialized = true; 1518 else { 1519 if (ras_cmd->ras_status) 1520 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1521 amdgpu_ras_fini(psp->adev); 1522 } 1523 1524 return ret; 1525 } 1526 1527 int psp_ras_trigger_error(struct psp_context *psp, 1528 struct ta_ras_trigger_error_input *info) 1529 { 1530 struct ta_ras_shared_memory *ras_cmd; 1531 int ret; 1532 1533 if (!psp->ras_context.context.initialized) 1534 return -EINVAL; 1535 1536 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1537 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1538 1539 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1540 ras_cmd->ras_in_message.trigger_error = *info; 1541 1542 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1543 if (ret) 1544 return -EINVAL; 1545 1546 /* If err_event_athub occurs error inject was successful, however 1547 return status from TA is no long reliable */ 1548 if (amdgpu_ras_intr_triggered()) 1549 return 0; 1550 1551 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1552 return -EACCES; 1553 else if (ras_cmd->ras_status) 1554 return -EINVAL; 1555 1556 return 0; 1557 } 1558 // ras end 1559 1560 // HDCP start 1561 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1562 { 1563 return psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1564 } 1565 1566 static int psp_hdcp_load(struct psp_context *psp) 1567 { 1568 return psp_ta_load(psp, &psp->hdcp_context.context); 1569 } 1570 1571 static int psp_hdcp_initialize(struct psp_context *psp) 1572 { 1573 int ret; 1574 1575 /* 1576 * TODO: bypass the initialize in sriov for now 1577 */ 1578 if (amdgpu_sriov_vf(psp->adev)) 1579 return 0; 1580 1581 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1582 !psp->hdcp_context.context.bin_desc.start_addr) { 1583 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1584 return 0; 1585 } 1586 1587 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1588 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1589 1590 if (!psp->hdcp_context.context.initialized) { 1591 ret = psp_hdcp_init_shared_buf(psp); 1592 if (ret) 1593 return ret; 1594 } 1595 1596 ret = psp_hdcp_load(psp); 1597 if (!ret) { 1598 psp->hdcp_context.context.initialized = true; 1599 mutex_init(&psp->hdcp_context.mutex); 1600 } 1601 1602 return ret; 1603 } 1604 1605 static int psp_hdcp_unload(struct psp_context *psp) 1606 { 1607 return psp_ta_unload(psp, &psp->hdcp_context.context); 1608 } 1609 1610 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1611 { 1612 /* 1613 * TODO: bypass the loading in sriov for now 1614 */ 1615 if (amdgpu_sriov_vf(psp->adev)) 1616 return 0; 1617 1618 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1619 } 1620 1621 static int psp_hdcp_terminate(struct psp_context *psp) 1622 { 1623 int ret; 1624 1625 /* 1626 * TODO: bypass the terminate in sriov for now 1627 */ 1628 if (amdgpu_sriov_vf(psp->adev)) 1629 return 0; 1630 1631 if (!psp->hdcp_context.context.initialized) { 1632 if (psp->hdcp_context.context.mem_context.shared_buf) 1633 goto out; 1634 else 1635 return 0; 1636 } 1637 1638 ret = psp_hdcp_unload(psp); 1639 if (ret) 1640 return ret; 1641 1642 psp->hdcp_context.context.initialized = false; 1643 1644 out: 1645 /* free hdcp shared memory */ 1646 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 1647 1648 return 0; 1649 } 1650 // HDCP end 1651 1652 // DTM start 1653 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1654 { 1655 return psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1656 } 1657 1658 static int psp_dtm_load(struct psp_context *psp) 1659 { 1660 return psp_ta_load(psp, &psp->dtm_context.context); 1661 } 1662 1663 static int psp_dtm_initialize(struct psp_context *psp) 1664 { 1665 int ret; 1666 1667 /* 1668 * TODO: bypass the initialize in sriov for now 1669 */ 1670 if (amdgpu_sriov_vf(psp->adev)) 1671 return 0; 1672 1673 if (!psp->dtm_context.context.bin_desc.size_bytes || 1674 !psp->dtm_context.context.bin_desc.start_addr) { 1675 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1676 return 0; 1677 } 1678 1679 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1680 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1681 1682 if (!psp->dtm_context.context.initialized) { 1683 ret = psp_dtm_init_shared_buf(psp); 1684 if (ret) 1685 return ret; 1686 } 1687 1688 ret = psp_dtm_load(psp); 1689 if (!ret) { 1690 psp->dtm_context.context.initialized = true; 1691 mutex_init(&psp->dtm_context.mutex); 1692 } 1693 1694 return ret; 1695 } 1696 1697 static int psp_dtm_unload(struct psp_context *psp) 1698 { 1699 return psp_ta_unload(psp, &psp->dtm_context.context); 1700 } 1701 1702 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1703 { 1704 /* 1705 * TODO: bypass the loading in sriov for now 1706 */ 1707 if (amdgpu_sriov_vf(psp->adev)) 1708 return 0; 1709 1710 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1711 } 1712 1713 static int psp_dtm_terminate(struct psp_context *psp) 1714 { 1715 int ret; 1716 1717 /* 1718 * TODO: bypass the terminate in sriov for now 1719 */ 1720 if (amdgpu_sriov_vf(psp->adev)) 1721 return 0; 1722 1723 if (!psp->dtm_context.context.initialized) { 1724 if (psp->dtm_context.context.mem_context.shared_buf) 1725 goto out; 1726 else 1727 return 0; 1728 } 1729 1730 ret = psp_dtm_unload(psp); 1731 if (ret) 1732 return ret; 1733 1734 psp->dtm_context.context.initialized = false; 1735 1736 out: 1737 /* free dtm shared memory */ 1738 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 1739 1740 return 0; 1741 } 1742 // DTM end 1743 1744 // RAP start 1745 static int psp_rap_init_shared_buf(struct psp_context *psp) 1746 { 1747 return psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1748 } 1749 1750 static int psp_rap_load(struct psp_context *psp) 1751 { 1752 return psp_ta_load(psp, &psp->rap_context.context); 1753 } 1754 1755 static int psp_rap_unload(struct psp_context *psp) 1756 { 1757 return psp_ta_unload(psp, &psp->rap_context.context); 1758 } 1759 1760 static int psp_rap_initialize(struct psp_context *psp) 1761 { 1762 int ret; 1763 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1764 1765 /* 1766 * TODO: bypass the initialize in sriov for now 1767 */ 1768 if (amdgpu_sriov_vf(psp->adev)) 1769 return 0; 1770 1771 if (!psp->rap_context.context.bin_desc.size_bytes || 1772 !psp->rap_context.context.bin_desc.start_addr) { 1773 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1774 return 0; 1775 } 1776 1777 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1778 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1779 1780 if (!psp->rap_context.context.initialized) { 1781 ret = psp_rap_init_shared_buf(psp); 1782 if (ret) 1783 return ret; 1784 } 1785 1786 ret = psp_rap_load(psp); 1787 if (!ret) { 1788 psp->rap_context.context.initialized = true; 1789 mutex_init(&psp->rap_context.mutex); 1790 } else 1791 return ret; 1792 1793 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1794 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1795 psp_rap_terminate(psp); 1796 1797 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1798 ret, status); 1799 1800 return ret; 1801 } 1802 1803 return 0; 1804 } 1805 1806 static int psp_rap_terminate(struct psp_context *psp) 1807 { 1808 int ret; 1809 1810 if (!psp->rap_context.context.initialized) 1811 return 0; 1812 1813 ret = psp_rap_unload(psp); 1814 1815 psp->rap_context.context.initialized = false; 1816 1817 /* free rap shared memory */ 1818 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1819 1820 return ret; 1821 } 1822 1823 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1824 { 1825 struct ta_rap_shared_memory *rap_cmd; 1826 int ret = 0; 1827 1828 if (!psp->rap_context.context.initialized) 1829 return 0; 1830 1831 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1832 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1833 return -EINVAL; 1834 1835 mutex_lock(&psp->rap_context.mutex); 1836 1837 rap_cmd = (struct ta_rap_shared_memory *) 1838 psp->rap_context.context.mem_context.shared_buf; 1839 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1840 1841 rap_cmd->cmd_id = ta_cmd_id; 1842 rap_cmd->validation_method_id = METHOD_A; 1843 1844 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1845 if (ret) 1846 goto out_unlock; 1847 1848 if (status) 1849 *status = rap_cmd->rap_status; 1850 1851 out_unlock: 1852 mutex_unlock(&psp->rap_context.mutex); 1853 1854 return ret; 1855 } 1856 // RAP end 1857 1858 /* securedisplay start */ 1859 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1860 { 1861 return psp_ta_init_shared_buf( 1862 psp, &psp->securedisplay_context.context.mem_context); 1863 } 1864 1865 static int psp_securedisplay_load(struct psp_context *psp) 1866 { 1867 return psp_ta_load(psp, &psp->securedisplay_context.context); 1868 } 1869 1870 static int psp_securedisplay_unload(struct psp_context *psp) 1871 { 1872 return psp_ta_unload(psp, &psp->securedisplay_context.context); 1873 } 1874 1875 static int psp_securedisplay_initialize(struct psp_context *psp) 1876 { 1877 int ret; 1878 struct securedisplay_cmd *securedisplay_cmd; 1879 1880 /* 1881 * TODO: bypass the initialize in sriov for now 1882 */ 1883 if (amdgpu_sriov_vf(psp->adev)) 1884 return 0; 1885 1886 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1887 !psp->securedisplay_context.context.bin_desc.start_addr) { 1888 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1889 return 0; 1890 } 1891 1892 psp->securedisplay_context.context.mem_context.shared_mem_size = 1893 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1894 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1895 1896 if (!psp->securedisplay_context.context.initialized) { 1897 ret = psp_securedisplay_init_shared_buf(psp); 1898 if (ret) 1899 return ret; 1900 } 1901 1902 ret = psp_securedisplay_load(psp); 1903 if (!ret) { 1904 psp->securedisplay_context.context.initialized = true; 1905 mutex_init(&psp->securedisplay_context.mutex); 1906 } else 1907 return ret; 1908 1909 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1910 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1911 1912 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1913 if (ret) { 1914 psp_securedisplay_terminate(psp); 1915 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1916 return -EINVAL; 1917 } 1918 1919 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1920 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1921 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1922 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1923 } 1924 1925 return 0; 1926 } 1927 1928 static int psp_securedisplay_terminate(struct psp_context *psp) 1929 { 1930 int ret; 1931 1932 /* 1933 * TODO:bypass the terminate in sriov for now 1934 */ 1935 if (amdgpu_sriov_vf(psp->adev)) 1936 return 0; 1937 1938 if (!psp->securedisplay_context.context.initialized) 1939 return 0; 1940 1941 ret = psp_securedisplay_unload(psp); 1942 if (ret) 1943 return ret; 1944 1945 psp->securedisplay_context.context.initialized = false; 1946 1947 /* free securedisplay shared memory */ 1948 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1949 1950 return ret; 1951 } 1952 1953 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1954 { 1955 int ret; 1956 1957 if (!psp->securedisplay_context.context.initialized) 1958 return -EINVAL; 1959 1960 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1961 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1962 return -EINVAL; 1963 1964 mutex_lock(&psp->securedisplay_context.mutex); 1965 1966 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1967 1968 mutex_unlock(&psp->securedisplay_context.mutex); 1969 1970 return ret; 1971 } 1972 /* SECUREDISPLAY end */ 1973 1974 static int psp_hw_start(struct psp_context *psp) 1975 { 1976 struct amdgpu_device *adev = psp->adev; 1977 int ret; 1978 1979 if (!amdgpu_sriov_vf(adev)) { 1980 if ((is_psp_fw_valid(psp->kdb)) && 1981 (psp->funcs->bootloader_load_kdb != NULL)) { 1982 ret = psp_bootloader_load_kdb(psp); 1983 if (ret) { 1984 DRM_ERROR("PSP load kdb failed!\n"); 1985 return ret; 1986 } 1987 } 1988 1989 if ((is_psp_fw_valid(psp->spl)) && 1990 (psp->funcs->bootloader_load_spl != NULL)) { 1991 ret = psp_bootloader_load_spl(psp); 1992 if (ret) { 1993 DRM_ERROR("PSP load spl failed!\n"); 1994 return ret; 1995 } 1996 } 1997 1998 if ((is_psp_fw_valid(psp->sys)) && 1999 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2000 ret = psp_bootloader_load_sysdrv(psp); 2001 if (ret) { 2002 DRM_ERROR("PSP load sys drv failed!\n"); 2003 return ret; 2004 } 2005 } 2006 2007 if ((is_psp_fw_valid(psp->soc_drv)) && 2008 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2009 ret = psp_bootloader_load_soc_drv(psp); 2010 if (ret) { 2011 DRM_ERROR("PSP load soc drv failed!\n"); 2012 return ret; 2013 } 2014 } 2015 2016 if ((is_psp_fw_valid(psp->intf_drv)) && 2017 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2018 ret = psp_bootloader_load_intf_drv(psp); 2019 if (ret) { 2020 DRM_ERROR("PSP load intf drv failed!\n"); 2021 return ret; 2022 } 2023 } 2024 2025 if ((is_psp_fw_valid(psp->dbg_drv)) && 2026 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2027 ret = psp_bootloader_load_dbg_drv(psp); 2028 if (ret) { 2029 DRM_ERROR("PSP load dbg drv failed!\n"); 2030 return ret; 2031 } 2032 } 2033 2034 if ((is_psp_fw_valid(psp->sos)) && 2035 (psp->funcs->bootloader_load_sos != NULL)) { 2036 ret = psp_bootloader_load_sos(psp); 2037 if (ret) { 2038 DRM_ERROR("PSP load sos failed!\n"); 2039 return ret; 2040 } 2041 } 2042 } 2043 2044 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2045 if (ret) { 2046 DRM_ERROR("PSP create ring failed!\n"); 2047 return ret; 2048 } 2049 2050 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2051 goto skip_pin_bo; 2052 2053 ret = psp_tmr_init(psp); 2054 if (ret) { 2055 DRM_ERROR("PSP tmr init failed!\n"); 2056 return ret; 2057 } 2058 2059 skip_pin_bo: 2060 /* 2061 * For ASICs with DF Cstate management centralized 2062 * to PMFW, TMR setup should be performed after PMFW 2063 * loaded and before other non-psp firmware loaded. 2064 */ 2065 if (psp->pmfw_centralized_cstate_management) { 2066 ret = psp_load_smu_fw(psp); 2067 if (ret) 2068 return ret; 2069 } 2070 2071 ret = psp_tmr_load(psp); 2072 if (ret) { 2073 DRM_ERROR("PSP load tmr failed!\n"); 2074 return ret; 2075 } 2076 2077 return 0; 2078 } 2079 2080 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2081 enum psp_gfx_fw_type *type) 2082 { 2083 switch (ucode->ucode_id) { 2084 case AMDGPU_UCODE_ID_CAP: 2085 *type = GFX_FW_TYPE_CAP; 2086 break; 2087 case AMDGPU_UCODE_ID_SDMA0: 2088 *type = GFX_FW_TYPE_SDMA0; 2089 break; 2090 case AMDGPU_UCODE_ID_SDMA1: 2091 *type = GFX_FW_TYPE_SDMA1; 2092 break; 2093 case AMDGPU_UCODE_ID_SDMA2: 2094 *type = GFX_FW_TYPE_SDMA2; 2095 break; 2096 case AMDGPU_UCODE_ID_SDMA3: 2097 *type = GFX_FW_TYPE_SDMA3; 2098 break; 2099 case AMDGPU_UCODE_ID_SDMA4: 2100 *type = GFX_FW_TYPE_SDMA4; 2101 break; 2102 case AMDGPU_UCODE_ID_SDMA5: 2103 *type = GFX_FW_TYPE_SDMA5; 2104 break; 2105 case AMDGPU_UCODE_ID_SDMA6: 2106 *type = GFX_FW_TYPE_SDMA6; 2107 break; 2108 case AMDGPU_UCODE_ID_SDMA7: 2109 *type = GFX_FW_TYPE_SDMA7; 2110 break; 2111 case AMDGPU_UCODE_ID_CP_MES: 2112 *type = GFX_FW_TYPE_CP_MES; 2113 break; 2114 case AMDGPU_UCODE_ID_CP_MES_DATA: 2115 *type = GFX_FW_TYPE_MES_STACK; 2116 break; 2117 case AMDGPU_UCODE_ID_CP_CE: 2118 *type = GFX_FW_TYPE_CP_CE; 2119 break; 2120 case AMDGPU_UCODE_ID_CP_PFP: 2121 *type = GFX_FW_TYPE_CP_PFP; 2122 break; 2123 case AMDGPU_UCODE_ID_CP_ME: 2124 *type = GFX_FW_TYPE_CP_ME; 2125 break; 2126 case AMDGPU_UCODE_ID_CP_MEC1: 2127 *type = GFX_FW_TYPE_CP_MEC; 2128 break; 2129 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2130 *type = GFX_FW_TYPE_CP_MEC_ME1; 2131 break; 2132 case AMDGPU_UCODE_ID_CP_MEC2: 2133 *type = GFX_FW_TYPE_CP_MEC; 2134 break; 2135 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2136 *type = GFX_FW_TYPE_CP_MEC_ME2; 2137 break; 2138 case AMDGPU_UCODE_ID_RLC_G: 2139 *type = GFX_FW_TYPE_RLC_G; 2140 break; 2141 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2142 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2143 break; 2144 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2145 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2146 break; 2147 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2148 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2149 break; 2150 case AMDGPU_UCODE_ID_RLC_IRAM: 2151 *type = GFX_FW_TYPE_RLC_IRAM; 2152 break; 2153 case AMDGPU_UCODE_ID_RLC_DRAM: 2154 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2155 break; 2156 case AMDGPU_UCODE_ID_SMC: 2157 *type = GFX_FW_TYPE_SMU; 2158 break; 2159 case AMDGPU_UCODE_ID_UVD: 2160 *type = GFX_FW_TYPE_UVD; 2161 break; 2162 case AMDGPU_UCODE_ID_UVD1: 2163 *type = GFX_FW_TYPE_UVD1; 2164 break; 2165 case AMDGPU_UCODE_ID_VCE: 2166 *type = GFX_FW_TYPE_VCE; 2167 break; 2168 case AMDGPU_UCODE_ID_VCN: 2169 *type = GFX_FW_TYPE_VCN; 2170 break; 2171 case AMDGPU_UCODE_ID_VCN1: 2172 *type = GFX_FW_TYPE_VCN1; 2173 break; 2174 case AMDGPU_UCODE_ID_DMCU_ERAM: 2175 *type = GFX_FW_TYPE_DMCU_ERAM; 2176 break; 2177 case AMDGPU_UCODE_ID_DMCU_INTV: 2178 *type = GFX_FW_TYPE_DMCU_ISR; 2179 break; 2180 case AMDGPU_UCODE_ID_VCN0_RAM: 2181 *type = GFX_FW_TYPE_VCN0_RAM; 2182 break; 2183 case AMDGPU_UCODE_ID_VCN1_RAM: 2184 *type = GFX_FW_TYPE_VCN1_RAM; 2185 break; 2186 case AMDGPU_UCODE_ID_DMCUB: 2187 *type = GFX_FW_TYPE_DMUB; 2188 break; 2189 case AMDGPU_UCODE_ID_MAXIMUM: 2190 default: 2191 return -EINVAL; 2192 } 2193 2194 return 0; 2195 } 2196 2197 static void psp_print_fw_hdr(struct psp_context *psp, 2198 struct amdgpu_firmware_info *ucode) 2199 { 2200 struct amdgpu_device *adev = psp->adev; 2201 struct common_firmware_header *hdr; 2202 2203 switch (ucode->ucode_id) { 2204 case AMDGPU_UCODE_ID_SDMA0: 2205 case AMDGPU_UCODE_ID_SDMA1: 2206 case AMDGPU_UCODE_ID_SDMA2: 2207 case AMDGPU_UCODE_ID_SDMA3: 2208 case AMDGPU_UCODE_ID_SDMA4: 2209 case AMDGPU_UCODE_ID_SDMA5: 2210 case AMDGPU_UCODE_ID_SDMA6: 2211 case AMDGPU_UCODE_ID_SDMA7: 2212 hdr = (struct common_firmware_header *) 2213 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2214 amdgpu_ucode_print_sdma_hdr(hdr); 2215 break; 2216 case AMDGPU_UCODE_ID_CP_CE: 2217 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2218 amdgpu_ucode_print_gfx_hdr(hdr); 2219 break; 2220 case AMDGPU_UCODE_ID_CP_PFP: 2221 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2222 amdgpu_ucode_print_gfx_hdr(hdr); 2223 break; 2224 case AMDGPU_UCODE_ID_CP_ME: 2225 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2226 amdgpu_ucode_print_gfx_hdr(hdr); 2227 break; 2228 case AMDGPU_UCODE_ID_CP_MEC1: 2229 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2230 amdgpu_ucode_print_gfx_hdr(hdr); 2231 break; 2232 case AMDGPU_UCODE_ID_RLC_G: 2233 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2234 amdgpu_ucode_print_rlc_hdr(hdr); 2235 break; 2236 case AMDGPU_UCODE_ID_SMC: 2237 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2238 amdgpu_ucode_print_smc_hdr(hdr); 2239 break; 2240 default: 2241 break; 2242 } 2243 } 2244 2245 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2246 struct psp_gfx_cmd_resp *cmd) 2247 { 2248 int ret; 2249 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2250 2251 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2252 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2253 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2254 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2255 2256 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2257 if (ret) 2258 DRM_ERROR("Unknown firmware type\n"); 2259 2260 return ret; 2261 } 2262 2263 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2264 struct amdgpu_firmware_info *ucode) 2265 { 2266 int ret = 0; 2267 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2268 2269 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2270 if (!ret) { 2271 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2272 psp->fence_buf_mc_addr); 2273 } 2274 2275 release_psp_cmd_buf(psp); 2276 2277 return ret; 2278 } 2279 2280 static int psp_load_smu_fw(struct psp_context *psp) 2281 { 2282 int ret; 2283 struct amdgpu_device *adev = psp->adev; 2284 struct amdgpu_firmware_info *ucode = 2285 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2286 struct amdgpu_ras *ras = psp->ras_context.ras; 2287 2288 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2289 return 0; 2290 2291 if ((amdgpu_in_reset(adev) && 2292 ras && adev->ras_enabled && 2293 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2294 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2295 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2296 if (ret) { 2297 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2298 } 2299 } 2300 2301 ret = psp_execute_non_psp_fw_load(psp, ucode); 2302 2303 if (ret) 2304 DRM_ERROR("PSP load smu failed!\n"); 2305 2306 return ret; 2307 } 2308 2309 static bool fw_load_skip_check(struct psp_context *psp, 2310 struct amdgpu_firmware_info *ucode) 2311 { 2312 if (!ucode->fw) 2313 return true; 2314 2315 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2316 (psp_smu_reload_quirk(psp) || 2317 psp->autoload_supported || 2318 psp->pmfw_centralized_cstate_management)) 2319 return true; 2320 2321 if (amdgpu_sriov_vf(psp->adev) && 2322 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2323 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2324 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2325 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2326 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2327 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2328 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2329 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2330 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2331 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2332 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2333 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2334 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2335 /*skip ucode loading in SRIOV VF */ 2336 return true; 2337 2338 if (psp->autoload_supported && 2339 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2340 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2341 /* skip mec JT when autoload is enabled */ 2342 return true; 2343 2344 return false; 2345 } 2346 2347 int psp_load_fw_list(struct psp_context *psp, 2348 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2349 { 2350 int ret = 0, i; 2351 struct amdgpu_firmware_info *ucode; 2352 2353 for (i = 0; i < ucode_count; ++i) { 2354 ucode = ucode_list[i]; 2355 psp_print_fw_hdr(psp, ucode); 2356 ret = psp_execute_non_psp_fw_load(psp, ucode); 2357 if (ret) 2358 return ret; 2359 } 2360 return ret; 2361 } 2362 2363 static int psp_load_non_psp_fw(struct psp_context *psp) 2364 { 2365 int i, ret; 2366 struct amdgpu_firmware_info *ucode; 2367 struct amdgpu_device *adev = psp->adev; 2368 2369 if (psp->autoload_supported && 2370 !psp->pmfw_centralized_cstate_management) { 2371 ret = psp_load_smu_fw(psp); 2372 if (ret) 2373 return ret; 2374 } 2375 2376 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2377 ucode = &adev->firmware.ucode[i]; 2378 2379 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2380 !fw_load_skip_check(psp, ucode)) { 2381 ret = psp_load_smu_fw(psp); 2382 if (ret) 2383 return ret; 2384 continue; 2385 } 2386 2387 if (fw_load_skip_check(psp, ucode)) 2388 continue; 2389 2390 if (psp->autoload_supported && 2391 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2392 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2393 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2394 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2395 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2396 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2397 /* PSP only receive one SDMA fw for sienna_cichlid, 2398 * as all four sdma fw are same */ 2399 continue; 2400 2401 psp_print_fw_hdr(psp, ucode); 2402 2403 ret = psp_execute_non_psp_fw_load(psp, ucode); 2404 if (ret) 2405 return ret; 2406 2407 /* Start rlc autoload after psp recieved all the gfx firmware */ 2408 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2409 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2410 ret = psp_rlc_autoload_start(psp); 2411 if (ret) { 2412 DRM_ERROR("Failed to start rlc autoload\n"); 2413 return ret; 2414 } 2415 } 2416 } 2417 2418 return 0; 2419 } 2420 2421 static int psp_load_fw(struct amdgpu_device *adev) 2422 { 2423 int ret; 2424 struct psp_context *psp = &adev->psp; 2425 2426 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2427 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2428 goto skip_memalloc; 2429 } 2430 2431 if (amdgpu_sriov_vf(adev)) { 2432 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2433 AMDGPU_GEM_DOMAIN_VRAM, 2434 &psp->fw_pri_bo, 2435 &psp->fw_pri_mc_addr, 2436 &psp->fw_pri_buf); 2437 } else { 2438 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2439 AMDGPU_GEM_DOMAIN_GTT, 2440 &psp->fw_pri_bo, 2441 &psp->fw_pri_mc_addr, 2442 &psp->fw_pri_buf); 2443 } 2444 2445 if (ret) 2446 goto failed; 2447 2448 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2449 AMDGPU_GEM_DOMAIN_VRAM, 2450 &psp->fence_buf_bo, 2451 &psp->fence_buf_mc_addr, 2452 &psp->fence_buf); 2453 if (ret) 2454 goto failed; 2455 2456 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2457 AMDGPU_GEM_DOMAIN_VRAM, 2458 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2459 (void **)&psp->cmd_buf_mem); 2460 if (ret) 2461 goto failed; 2462 2463 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2464 2465 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2466 if (ret) { 2467 DRM_ERROR("PSP ring init failed!\n"); 2468 goto failed; 2469 } 2470 2471 skip_memalloc: 2472 ret = psp_hw_start(psp); 2473 if (ret) 2474 goto failed; 2475 2476 ret = psp_load_non_psp_fw(psp); 2477 if (ret) 2478 goto failed; 2479 2480 ret = psp_asd_initialize(psp); 2481 if (ret) { 2482 DRM_ERROR("PSP load asd failed!\n"); 2483 return ret; 2484 } 2485 2486 ret = psp_rl_load(adev); 2487 if (ret) { 2488 DRM_ERROR("PSP load RL failed!\n"); 2489 return ret; 2490 } 2491 2492 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2493 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2494 ret = psp_xgmi_initialize(psp, false, true); 2495 /* Warning the XGMI seesion initialize failure 2496 * Instead of stop driver initialization 2497 */ 2498 if (ret) 2499 dev_err(psp->adev->dev, 2500 "XGMI: Failed to initialize XGMI session\n"); 2501 } 2502 } 2503 2504 if (psp->ta_fw) { 2505 ret = psp_ras_initialize(psp); 2506 if (ret) 2507 dev_err(psp->adev->dev, 2508 "RAS: Failed to initialize RAS\n"); 2509 2510 ret = psp_hdcp_initialize(psp); 2511 if (ret) 2512 dev_err(psp->adev->dev, 2513 "HDCP: Failed to initialize HDCP\n"); 2514 2515 ret = psp_dtm_initialize(psp); 2516 if (ret) 2517 dev_err(psp->adev->dev, 2518 "DTM: Failed to initialize DTM\n"); 2519 2520 ret = psp_rap_initialize(psp); 2521 if (ret) 2522 dev_err(psp->adev->dev, 2523 "RAP: Failed to initialize RAP\n"); 2524 2525 ret = psp_securedisplay_initialize(psp); 2526 if (ret) 2527 dev_err(psp->adev->dev, 2528 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2529 } 2530 2531 return 0; 2532 2533 failed: 2534 /* 2535 * all cleanup jobs (xgmi terminate, ras terminate, 2536 * ring destroy, cmd/fence/fw buffers destory, 2537 * psp->cmd destory) are delayed to psp_hw_fini 2538 */ 2539 return ret; 2540 } 2541 2542 static int psp_hw_init(void *handle) 2543 { 2544 int ret; 2545 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2546 2547 mutex_lock(&adev->firmware.mutex); 2548 /* 2549 * This sequence is just used on hw_init only once, no need on 2550 * resume. 2551 */ 2552 ret = amdgpu_ucode_init_bo(adev); 2553 if (ret) 2554 goto failed; 2555 2556 ret = psp_load_fw(adev); 2557 if (ret) { 2558 DRM_ERROR("PSP firmware loading failed\n"); 2559 goto failed; 2560 } 2561 2562 mutex_unlock(&adev->firmware.mutex); 2563 return 0; 2564 2565 failed: 2566 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2567 mutex_unlock(&adev->firmware.mutex); 2568 return -EINVAL; 2569 } 2570 2571 static int psp_hw_fini(void *handle) 2572 { 2573 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2574 struct psp_context *psp = &adev->psp; 2575 2576 if (psp->ta_fw) { 2577 psp_ras_terminate(psp); 2578 psp_securedisplay_terminate(psp); 2579 psp_rap_terminate(psp); 2580 psp_dtm_terminate(psp); 2581 psp_hdcp_terminate(psp); 2582 } 2583 2584 psp_asd_terminate(psp); 2585 2586 psp_tmr_terminate(psp); 2587 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2588 2589 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2590 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2591 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2592 &psp->fence_buf_mc_addr, &psp->fence_buf); 2593 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2594 (void **)&psp->cmd_buf_mem); 2595 2596 return 0; 2597 } 2598 2599 static int psp_suspend(void *handle) 2600 { 2601 int ret; 2602 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2603 struct psp_context *psp = &adev->psp; 2604 2605 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2606 psp->xgmi_context.context.initialized) { 2607 ret = psp_xgmi_terminate(psp); 2608 if (ret) { 2609 DRM_ERROR("Failed to terminate xgmi ta\n"); 2610 return ret; 2611 } 2612 } 2613 2614 if (psp->ta_fw) { 2615 ret = psp_ras_terminate(psp); 2616 if (ret) { 2617 DRM_ERROR("Failed to terminate ras ta\n"); 2618 return ret; 2619 } 2620 ret = psp_hdcp_terminate(psp); 2621 if (ret) { 2622 DRM_ERROR("Failed to terminate hdcp ta\n"); 2623 return ret; 2624 } 2625 ret = psp_dtm_terminate(psp); 2626 if (ret) { 2627 DRM_ERROR("Failed to terminate dtm ta\n"); 2628 return ret; 2629 } 2630 ret = psp_rap_terminate(psp); 2631 if (ret) { 2632 DRM_ERROR("Failed to terminate rap ta\n"); 2633 return ret; 2634 } 2635 ret = psp_securedisplay_terminate(psp); 2636 if (ret) { 2637 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2638 return ret; 2639 } 2640 } 2641 2642 ret = psp_asd_terminate(psp); 2643 if (ret) { 2644 DRM_ERROR("Failed to terminate asd\n"); 2645 return ret; 2646 } 2647 2648 ret = psp_tmr_terminate(psp); 2649 if (ret) { 2650 DRM_ERROR("Failed to terminate tmr\n"); 2651 return ret; 2652 } 2653 2654 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2655 if (ret) { 2656 DRM_ERROR("PSP ring stop failed\n"); 2657 return ret; 2658 } 2659 2660 return 0; 2661 } 2662 2663 static int psp_resume(void *handle) 2664 { 2665 int ret; 2666 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2667 struct psp_context *psp = &adev->psp; 2668 2669 DRM_INFO("PSP is resuming...\n"); 2670 2671 if (psp->mem_train_ctx.enable_mem_training) { 2672 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2673 if (ret) { 2674 DRM_ERROR("Failed to process memory training!\n"); 2675 return ret; 2676 } 2677 } 2678 2679 mutex_lock(&adev->firmware.mutex); 2680 2681 ret = psp_hw_start(psp); 2682 if (ret) 2683 goto failed; 2684 2685 ret = psp_load_non_psp_fw(psp); 2686 if (ret) 2687 goto failed; 2688 2689 ret = psp_asd_initialize(psp); 2690 if (ret) { 2691 DRM_ERROR("PSP load asd failed!\n"); 2692 goto failed; 2693 } 2694 2695 ret = psp_rl_load(adev); 2696 if (ret) { 2697 dev_err(adev->dev, "PSP load RL failed!\n"); 2698 goto failed; 2699 } 2700 2701 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2702 ret = psp_xgmi_initialize(psp, false, true); 2703 /* Warning the XGMI seesion initialize failure 2704 * Instead of stop driver initialization 2705 */ 2706 if (ret) 2707 dev_err(psp->adev->dev, 2708 "XGMI: Failed to initialize XGMI session\n"); 2709 } 2710 2711 if (psp->ta_fw) { 2712 ret = psp_ras_initialize(psp); 2713 if (ret) 2714 dev_err(psp->adev->dev, 2715 "RAS: Failed to initialize RAS\n"); 2716 2717 ret = psp_hdcp_initialize(psp); 2718 if (ret) 2719 dev_err(psp->adev->dev, 2720 "HDCP: Failed to initialize HDCP\n"); 2721 2722 ret = psp_dtm_initialize(psp); 2723 if (ret) 2724 dev_err(psp->adev->dev, 2725 "DTM: Failed to initialize DTM\n"); 2726 2727 ret = psp_rap_initialize(psp); 2728 if (ret) 2729 dev_err(psp->adev->dev, 2730 "RAP: Failed to initialize RAP\n"); 2731 2732 ret = psp_securedisplay_initialize(psp); 2733 if (ret) 2734 dev_err(psp->adev->dev, 2735 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2736 } 2737 2738 mutex_unlock(&adev->firmware.mutex); 2739 2740 return 0; 2741 2742 failed: 2743 DRM_ERROR("PSP resume failed\n"); 2744 mutex_unlock(&adev->firmware.mutex); 2745 return ret; 2746 } 2747 2748 int psp_gpu_reset(struct amdgpu_device *adev) 2749 { 2750 int ret; 2751 2752 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2753 return 0; 2754 2755 mutex_lock(&adev->psp.mutex); 2756 ret = psp_mode1_reset(&adev->psp); 2757 mutex_unlock(&adev->psp.mutex); 2758 2759 return ret; 2760 } 2761 2762 int psp_rlc_autoload_start(struct psp_context *psp) 2763 { 2764 int ret; 2765 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2766 2767 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2768 2769 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2770 psp->fence_buf_mc_addr); 2771 2772 release_psp_cmd_buf(psp); 2773 2774 return ret; 2775 } 2776 2777 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2778 uint64_t cmd_gpu_addr, int cmd_size) 2779 { 2780 struct amdgpu_firmware_info ucode = {0}; 2781 2782 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2783 AMDGPU_UCODE_ID_VCN0_RAM; 2784 ucode.mc_addr = cmd_gpu_addr; 2785 ucode.ucode_size = cmd_size; 2786 2787 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2788 } 2789 2790 int psp_ring_cmd_submit(struct psp_context *psp, 2791 uint64_t cmd_buf_mc_addr, 2792 uint64_t fence_mc_addr, 2793 int index) 2794 { 2795 unsigned int psp_write_ptr_reg = 0; 2796 struct psp_gfx_rb_frame *write_frame; 2797 struct psp_ring *ring = &psp->km_ring; 2798 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2799 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2800 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2801 struct amdgpu_device *adev = psp->adev; 2802 uint32_t ring_size_dw = ring->ring_size / 4; 2803 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2804 2805 /* KM (GPCOM) prepare write pointer */ 2806 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2807 2808 /* Update KM RB frame pointer to new frame */ 2809 /* write_frame ptr increments by size of rb_frame in bytes */ 2810 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2811 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2812 write_frame = ring_buffer_start; 2813 else 2814 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2815 /* Check invalid write_frame ptr address */ 2816 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2817 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2818 ring_buffer_start, ring_buffer_end, write_frame); 2819 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2820 return -EINVAL; 2821 } 2822 2823 /* Initialize KM RB frame */ 2824 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2825 2826 /* Update KM RB frame */ 2827 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2828 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2829 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2830 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2831 write_frame->fence_value = index; 2832 amdgpu_device_flush_hdp(adev, NULL); 2833 2834 /* Update the write Pointer in DWORDs */ 2835 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2836 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2837 return 0; 2838 } 2839 2840 int psp_init_asd_microcode(struct psp_context *psp, 2841 const char *chip_name) 2842 { 2843 struct amdgpu_device *adev = psp->adev; 2844 char fw_name[PSP_FW_NAME_LEN]; 2845 const struct psp_firmware_header_v1_0 *asd_hdr; 2846 int err = 0; 2847 2848 if (!chip_name) { 2849 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2850 return -EINVAL; 2851 } 2852 2853 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2854 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2855 if (err) 2856 goto out; 2857 2858 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2859 if (err) 2860 goto out; 2861 2862 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2863 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2864 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2865 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2866 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2867 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2868 return 0; 2869 out: 2870 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2871 release_firmware(adev->psp.asd_fw); 2872 adev->psp.asd_fw = NULL; 2873 return err; 2874 } 2875 2876 int psp_init_toc_microcode(struct psp_context *psp, 2877 const char *chip_name) 2878 { 2879 struct amdgpu_device *adev = psp->adev; 2880 char fw_name[PSP_FW_NAME_LEN]; 2881 const struct psp_firmware_header_v1_0 *toc_hdr; 2882 int err = 0; 2883 2884 if (!chip_name) { 2885 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2886 return -EINVAL; 2887 } 2888 2889 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2890 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2891 if (err) 2892 goto out; 2893 2894 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2895 if (err) 2896 goto out; 2897 2898 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2899 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2900 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2901 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2902 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2903 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2904 return 0; 2905 out: 2906 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2907 release_firmware(adev->psp.toc_fw); 2908 adev->psp.toc_fw = NULL; 2909 return err; 2910 } 2911 2912 static int parse_sos_bin_descriptor(struct psp_context *psp, 2913 const struct psp_fw_bin_desc *desc, 2914 const struct psp_firmware_header_v2_0 *sos_hdr) 2915 { 2916 uint8_t *ucode_start_addr = NULL; 2917 2918 if (!psp || !desc || !sos_hdr) 2919 return -EINVAL; 2920 2921 ucode_start_addr = (uint8_t *)sos_hdr + 2922 le32_to_cpu(desc->offset_bytes) + 2923 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2924 2925 switch (desc->fw_type) { 2926 case PSP_FW_TYPE_PSP_SOS: 2927 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2928 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2929 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2930 psp->sos.start_addr = ucode_start_addr; 2931 break; 2932 case PSP_FW_TYPE_PSP_SYS_DRV: 2933 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2934 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2935 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2936 psp->sys.start_addr = ucode_start_addr; 2937 break; 2938 case PSP_FW_TYPE_PSP_KDB: 2939 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2940 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2941 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2942 psp->kdb.start_addr = ucode_start_addr; 2943 break; 2944 case PSP_FW_TYPE_PSP_TOC: 2945 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2946 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2947 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 2948 psp->toc.start_addr = ucode_start_addr; 2949 break; 2950 case PSP_FW_TYPE_PSP_SPL: 2951 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 2952 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 2953 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 2954 psp->spl.start_addr = ucode_start_addr; 2955 break; 2956 case PSP_FW_TYPE_PSP_RL: 2957 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 2958 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 2959 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 2960 psp->rl.start_addr = ucode_start_addr; 2961 break; 2962 case PSP_FW_TYPE_PSP_SOC_DRV: 2963 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 2964 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 2965 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2966 psp->soc_drv.start_addr = ucode_start_addr; 2967 break; 2968 case PSP_FW_TYPE_PSP_INTF_DRV: 2969 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 2970 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 2971 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2972 psp->intf_drv.start_addr = ucode_start_addr; 2973 break; 2974 case PSP_FW_TYPE_PSP_DBG_DRV: 2975 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 2976 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 2977 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2978 psp->dbg_drv.start_addr = ucode_start_addr; 2979 break; 2980 default: 2981 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 2982 break; 2983 } 2984 2985 return 0; 2986 } 2987 2988 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 2989 { 2990 const struct psp_firmware_header_v1_0 *sos_hdr; 2991 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2992 uint8_t *ucode_array_start_addr; 2993 2994 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2995 ucode_array_start_addr = (uint8_t *)sos_hdr + 2996 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2997 2998 if (adev->gmc.xgmi.connected_to_cpu || 2999 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3000 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3001 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3002 3003 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3004 adev->psp.sys.start_addr = ucode_array_start_addr; 3005 3006 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3007 adev->psp.sos.start_addr = ucode_array_start_addr + 3008 le32_to_cpu(sos_hdr->sos.offset_bytes); 3009 adev->psp.xgmi_context.supports_extended_data = false; 3010 } else { 3011 /* Load alternate PSP SOS FW */ 3012 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3013 3014 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3015 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3016 3017 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3018 adev->psp.sys.start_addr = ucode_array_start_addr + 3019 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3020 3021 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3022 adev->psp.sos.start_addr = ucode_array_start_addr + 3023 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3024 adev->psp.xgmi_context.supports_extended_data = true; 3025 } 3026 3027 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3028 dev_warn(adev->dev, "PSP SOS FW not available"); 3029 return -EINVAL; 3030 } 3031 3032 return 0; 3033 } 3034 3035 int psp_init_sos_microcode(struct psp_context *psp, 3036 const char *chip_name) 3037 { 3038 struct amdgpu_device *adev = psp->adev; 3039 char fw_name[PSP_FW_NAME_LEN]; 3040 const struct psp_firmware_header_v1_0 *sos_hdr; 3041 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3042 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3043 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3044 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3045 int err = 0; 3046 uint8_t *ucode_array_start_addr; 3047 int fw_index = 0; 3048 3049 if (!chip_name) { 3050 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3051 return -EINVAL; 3052 } 3053 3054 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3055 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3056 if (err) 3057 goto out; 3058 3059 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3060 if (err) 3061 goto out; 3062 3063 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3064 ucode_array_start_addr = (uint8_t *)sos_hdr + 3065 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3066 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3067 3068 switch (sos_hdr->header.header_version_major) { 3069 case 1: 3070 err = psp_init_sos_base_fw(adev); 3071 if (err) 3072 goto out; 3073 3074 if (sos_hdr->header.header_version_minor == 1) { 3075 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3076 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3077 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3078 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3079 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3080 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3081 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3082 } 3083 if (sos_hdr->header.header_version_minor == 2) { 3084 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3085 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3086 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3087 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3088 } 3089 if (sos_hdr->header.header_version_minor == 3) { 3090 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3091 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3092 adev->psp.toc.start_addr = ucode_array_start_addr + 3093 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3094 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3095 adev->psp.kdb.start_addr = ucode_array_start_addr + 3096 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3097 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3098 adev->psp.spl.start_addr = ucode_array_start_addr + 3099 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3100 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3101 adev->psp.rl.start_addr = ucode_array_start_addr + 3102 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3103 } 3104 break; 3105 case 2: 3106 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3107 3108 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3109 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3110 err = -EINVAL; 3111 goto out; 3112 } 3113 3114 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3115 err = parse_sos_bin_descriptor(psp, 3116 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3117 sos_hdr_v2_0); 3118 if (err) 3119 goto out; 3120 } 3121 break; 3122 default: 3123 dev_err(adev->dev, 3124 "unsupported psp sos firmware\n"); 3125 err = -EINVAL; 3126 goto out; 3127 } 3128 3129 return 0; 3130 out: 3131 dev_err(adev->dev, 3132 "failed to init sos firmware\n"); 3133 release_firmware(adev->psp.sos_fw); 3134 adev->psp.sos_fw = NULL; 3135 3136 return err; 3137 } 3138 3139 static int parse_ta_bin_descriptor(struct psp_context *psp, 3140 const struct psp_fw_bin_desc *desc, 3141 const struct ta_firmware_header_v2_0 *ta_hdr) 3142 { 3143 uint8_t *ucode_start_addr = NULL; 3144 3145 if (!psp || !desc || !ta_hdr) 3146 return -EINVAL; 3147 3148 ucode_start_addr = (uint8_t *)ta_hdr + 3149 le32_to_cpu(desc->offset_bytes) + 3150 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3151 3152 switch (desc->fw_type) { 3153 case TA_FW_TYPE_PSP_ASD: 3154 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3155 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3156 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3157 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3158 break; 3159 case TA_FW_TYPE_PSP_XGMI: 3160 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3161 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3162 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3163 break; 3164 case TA_FW_TYPE_PSP_RAS: 3165 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3166 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3167 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3168 break; 3169 case TA_FW_TYPE_PSP_HDCP: 3170 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3171 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3172 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3173 break; 3174 case TA_FW_TYPE_PSP_DTM: 3175 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3176 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3177 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3178 break; 3179 case TA_FW_TYPE_PSP_RAP: 3180 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3181 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3182 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3183 break; 3184 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3185 psp->securedisplay_context.context.bin_desc.fw_version = 3186 le32_to_cpu(desc->fw_version); 3187 psp->securedisplay_context.context.bin_desc.size_bytes = 3188 le32_to_cpu(desc->size_bytes); 3189 psp->securedisplay_context.context.bin_desc.start_addr = 3190 ucode_start_addr; 3191 break; 3192 default: 3193 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3194 break; 3195 } 3196 3197 return 0; 3198 } 3199 3200 int psp_init_ta_microcode(struct psp_context *psp, 3201 const char *chip_name) 3202 { 3203 struct amdgpu_device *adev = psp->adev; 3204 char fw_name[PSP_FW_NAME_LEN]; 3205 const struct ta_firmware_header_v2_0 *ta_hdr; 3206 int err = 0; 3207 int ta_index = 0; 3208 3209 if (!chip_name) { 3210 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3211 return -EINVAL; 3212 } 3213 3214 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3215 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3216 if (err) 3217 goto out; 3218 3219 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3220 if (err) 3221 goto out; 3222 3223 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3224 3225 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3226 dev_err(adev->dev, "unsupported TA header version\n"); 3227 err = -EINVAL; 3228 goto out; 3229 } 3230 3231 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3232 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3233 err = -EINVAL; 3234 goto out; 3235 } 3236 3237 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3238 err = parse_ta_bin_descriptor(psp, 3239 &ta_hdr->ta_fw_bin[ta_index], 3240 ta_hdr); 3241 if (err) 3242 goto out; 3243 } 3244 3245 return 0; 3246 out: 3247 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3248 release_firmware(adev->psp.ta_fw); 3249 adev->psp.ta_fw = NULL; 3250 return err; 3251 } 3252 3253 int psp_init_cap_microcode(struct psp_context *psp, 3254 const char *chip_name) 3255 { 3256 struct amdgpu_device *adev = psp->adev; 3257 char fw_name[PSP_FW_NAME_LEN]; 3258 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3259 struct amdgpu_firmware_info *info = NULL; 3260 int err = 0; 3261 3262 if (!chip_name) { 3263 dev_err(adev->dev, "invalid chip name for cap microcode\n"); 3264 return -EINVAL; 3265 } 3266 3267 if (!amdgpu_sriov_vf(adev)) { 3268 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3269 return -EINVAL; 3270 } 3271 3272 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3273 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev); 3274 if (err) { 3275 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3276 err = 0; 3277 goto out; 3278 } 3279 3280 err = amdgpu_ucode_validate(adev->psp.cap_fw); 3281 if (err) { 3282 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3283 goto out; 3284 } 3285 3286 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3287 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3288 info->fw = adev->psp.cap_fw; 3289 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3290 adev->psp.cap_fw->data; 3291 adev->firmware.fw_size += ALIGN( 3292 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3293 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3294 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3295 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3296 3297 return 0; 3298 3299 out: 3300 release_firmware(adev->psp.cap_fw); 3301 adev->psp.cap_fw = NULL; 3302 return err; 3303 } 3304 3305 static int psp_set_clockgating_state(void *handle, 3306 enum amd_clockgating_state state) 3307 { 3308 return 0; 3309 } 3310 3311 static int psp_set_powergating_state(void *handle, 3312 enum amd_powergating_state state) 3313 { 3314 return 0; 3315 } 3316 3317 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3318 struct device_attribute *attr, 3319 char *buf) 3320 { 3321 struct drm_device *ddev = dev_get_drvdata(dev); 3322 struct amdgpu_device *adev = drm_to_adev(ddev); 3323 uint32_t fw_ver; 3324 int ret; 3325 3326 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3327 DRM_INFO("PSP block is not ready yet."); 3328 return -EBUSY; 3329 } 3330 3331 mutex_lock(&adev->psp.mutex); 3332 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3333 mutex_unlock(&adev->psp.mutex); 3334 3335 if (ret) { 3336 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3337 return ret; 3338 } 3339 3340 return sysfs_emit(buf, "%x\n", fw_ver); 3341 } 3342 3343 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3344 struct device_attribute *attr, 3345 const char *buf, 3346 size_t count) 3347 { 3348 struct drm_device *ddev = dev_get_drvdata(dev); 3349 struct amdgpu_device *adev = drm_to_adev(ddev); 3350 int ret, idx; 3351 char fw_name[100]; 3352 const struct firmware *usbc_pd_fw; 3353 struct amdgpu_bo *fw_buf_bo = NULL; 3354 uint64_t fw_pri_mc_addr; 3355 void *fw_pri_cpu_addr; 3356 3357 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3358 DRM_INFO("PSP block is not ready yet."); 3359 return -EBUSY; 3360 } 3361 3362 if (!drm_dev_enter(ddev, &idx)) 3363 return -ENODEV; 3364 3365 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3366 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3367 if (ret) 3368 goto fail; 3369 3370 /* LFB address which is aligned to 1MB boundary per PSP request */ 3371 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3372 AMDGPU_GEM_DOMAIN_VRAM, 3373 &fw_buf_bo, 3374 &fw_pri_mc_addr, 3375 &fw_pri_cpu_addr); 3376 if (ret) 3377 goto rel_buf; 3378 3379 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3380 3381 mutex_lock(&adev->psp.mutex); 3382 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3383 mutex_unlock(&adev->psp.mutex); 3384 3385 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3386 3387 rel_buf: 3388 release_firmware(usbc_pd_fw); 3389 fail: 3390 if (ret) { 3391 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3392 count = ret; 3393 } 3394 3395 drm_dev_exit(idx); 3396 return count; 3397 } 3398 3399 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3400 { 3401 int idx; 3402 3403 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3404 return; 3405 3406 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3407 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3408 3409 drm_dev_exit(idx); 3410 } 3411 3412 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3413 psp_usbc_pd_fw_sysfs_read, 3414 psp_usbc_pd_fw_sysfs_write); 3415 3416 int is_psp_fw_valid(struct psp_bin_desc bin) 3417 { 3418 return bin.size_bytes; 3419 } 3420 3421 const struct amd_ip_funcs psp_ip_funcs = { 3422 .name = "psp", 3423 .early_init = psp_early_init, 3424 .late_init = NULL, 3425 .sw_init = psp_sw_init, 3426 .sw_fini = psp_sw_fini, 3427 .hw_init = psp_hw_init, 3428 .hw_fini = psp_hw_fini, 3429 .suspend = psp_suspend, 3430 .resume = psp_resume, 3431 .is_idle = NULL, 3432 .check_soft_reset = NULL, 3433 .wait_for_idle = NULL, 3434 .soft_reset = NULL, 3435 .set_clockgating_state = psp_set_clockgating_state, 3436 .set_powergating_state = psp_set_powergating_state, 3437 }; 3438 3439 static int psp_sysfs_init(struct amdgpu_device *adev) 3440 { 3441 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3442 3443 if (ret) 3444 DRM_ERROR("Failed to create USBC PD FW control file!"); 3445 3446 return ret; 3447 } 3448 3449 static void psp_sysfs_fini(struct amdgpu_device *adev) 3450 { 3451 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3452 } 3453 3454 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3455 { 3456 .type = AMD_IP_BLOCK_TYPE_PSP, 3457 .major = 3, 3458 .minor = 1, 3459 .rev = 0, 3460 .funcs = &psp_ip_funcs, 3461 }; 3462 3463 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3464 { 3465 .type = AMD_IP_BLOCK_TYPE_PSP, 3466 .major = 10, 3467 .minor = 0, 3468 .rev = 0, 3469 .funcs = &psp_ip_funcs, 3470 }; 3471 3472 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3473 { 3474 .type = AMD_IP_BLOCK_TYPE_PSP, 3475 .major = 11, 3476 .minor = 0, 3477 .rev = 0, 3478 .funcs = &psp_ip_funcs, 3479 }; 3480 3481 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3482 .type = AMD_IP_BLOCK_TYPE_PSP, 3483 .major = 11, 3484 .minor = 0, 3485 .rev = 8, 3486 .funcs = &psp_ip_funcs, 3487 }; 3488 3489 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3490 { 3491 .type = AMD_IP_BLOCK_TYPE_PSP, 3492 .major = 12, 3493 .minor = 0, 3494 .rev = 0, 3495 .funcs = &psp_ip_funcs, 3496 }; 3497 3498 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3499 .type = AMD_IP_BLOCK_TYPE_PSP, 3500 .major = 13, 3501 .minor = 0, 3502 .rev = 0, 3503 .funcs = &psp_ip_funcs, 3504 }; 3505