1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 42 #include "amdgpu_ras.h" 43 #include "amdgpu_securedisplay.h" 44 #include "amdgpu_atomfirmware.h" 45 46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 47 48 static int psp_sysfs_init(struct amdgpu_device *adev); 49 static void psp_sysfs_fini(struct amdgpu_device *adev); 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 static int psp_ring_init(struct psp_context *psp, 56 enum psp_ring_type ring_type) 57 { 58 int ret = 0; 59 struct psp_ring *ring; 60 struct amdgpu_device *adev = psp->adev; 61 62 ring = &psp->km_ring; 63 64 ring->ring_type = ring_type; 65 66 /* allocate 4k Page of Local Frame Buffer memory for ring */ 67 ring->ring_size = 0x1000; 68 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 69 AMDGPU_GEM_DOMAIN_VRAM | 70 AMDGPU_GEM_DOMAIN_GTT, 71 &adev->firmware.rbuf, 72 &ring->ring_mem_mc_addr, 73 (void **)&ring->ring_mem); 74 if (ret) { 75 ring->ring_size = 0; 76 return ret; 77 } 78 79 return 0; 80 } 81 82 /* 83 * Due to DF Cstate management centralized to PMFW, the firmware 84 * loading sequence will be updated as below: 85 * - Load KDB 86 * - Load SYS_DRV 87 * - Load tOS 88 * - Load PMFW 89 * - Setup TMR 90 * - Load other non-psp fw 91 * - Load ASD 92 * - Load XGMI/RAS/HDCP/DTM TA if any 93 * 94 * This new sequence is required for 95 * - Arcturus and onwards 96 */ 97 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 98 { 99 struct amdgpu_device *adev = psp->adev; 100 101 if (amdgpu_sriov_vf(adev)) { 102 psp->pmfw_centralized_cstate_management = false; 103 return; 104 } 105 106 switch (adev->ip_versions[MP0_HWIP][0]) { 107 case IP_VERSION(11, 0, 0): 108 case IP_VERSION(11, 0, 4): 109 case IP_VERSION(11, 0, 5): 110 case IP_VERSION(11, 0, 7): 111 case IP_VERSION(11, 0, 9): 112 case IP_VERSION(11, 0, 11): 113 case IP_VERSION(11, 0, 12): 114 case IP_VERSION(11, 0, 13): 115 case IP_VERSION(13, 0, 0): 116 case IP_VERSION(13, 0, 2): 117 case IP_VERSION(13, 0, 7): 118 psp->pmfw_centralized_cstate_management = true; 119 break; 120 default: 121 psp->pmfw_centralized_cstate_management = false; 122 break; 123 } 124 } 125 126 static int psp_init_sriov_microcode(struct psp_context *psp) 127 { 128 struct amdgpu_device *adev = psp->adev; 129 char ucode_prefix[30]; 130 int ret = 0; 131 132 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 133 134 switch (adev->ip_versions[MP0_HWIP][0]) { 135 case IP_VERSION(9, 0, 0): 136 case IP_VERSION(11, 0, 7): 137 case IP_VERSION(11, 0, 9): 138 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 139 ret = psp_init_cap_microcode(psp, ucode_prefix); 140 break; 141 case IP_VERSION(13, 0, 2): 142 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 143 ret = psp_init_cap_microcode(psp, ucode_prefix); 144 ret &= psp_init_ta_microcode(psp, ucode_prefix); 145 break; 146 case IP_VERSION(13, 0, 0): 147 adev->virt.autoload_ucode_id = 0; 148 break; 149 case IP_VERSION(13, 0, 10): 150 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 151 break; 152 default: 153 return -EINVAL; 154 } 155 return ret; 156 } 157 158 static int psp_early_init(void *handle) 159 { 160 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 161 struct psp_context *psp = &adev->psp; 162 163 switch (adev->ip_versions[MP0_HWIP][0]) { 164 case IP_VERSION(9, 0, 0): 165 psp_v3_1_set_psp_funcs(psp); 166 psp->autoload_supported = false; 167 break; 168 case IP_VERSION(10, 0, 0): 169 case IP_VERSION(10, 0, 1): 170 psp_v10_0_set_psp_funcs(psp); 171 psp->autoload_supported = false; 172 break; 173 case IP_VERSION(11, 0, 2): 174 case IP_VERSION(11, 0, 4): 175 psp_v11_0_set_psp_funcs(psp); 176 psp->autoload_supported = false; 177 break; 178 case IP_VERSION(11, 0, 0): 179 case IP_VERSION(11, 0, 5): 180 case IP_VERSION(11, 0, 9): 181 case IP_VERSION(11, 0, 7): 182 case IP_VERSION(11, 0, 11): 183 case IP_VERSION(11, 5, 0): 184 case IP_VERSION(11, 0, 12): 185 case IP_VERSION(11, 0, 13): 186 psp_v11_0_set_psp_funcs(psp); 187 psp->autoload_supported = true; 188 break; 189 case IP_VERSION(11, 0, 3): 190 case IP_VERSION(12, 0, 1): 191 psp_v12_0_set_psp_funcs(psp); 192 break; 193 case IP_VERSION(13, 0, 2): 194 psp_v13_0_set_psp_funcs(psp); 195 break; 196 case IP_VERSION(13, 0, 1): 197 case IP_VERSION(13, 0, 3): 198 case IP_VERSION(13, 0, 5): 199 case IP_VERSION(13, 0, 8): 200 case IP_VERSION(13, 0, 10): 201 case IP_VERSION(13, 0, 11): 202 psp_v13_0_set_psp_funcs(psp); 203 psp->autoload_supported = true; 204 break; 205 case IP_VERSION(11, 0, 8): 206 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 207 psp_v11_0_8_set_psp_funcs(psp); 208 psp->autoload_supported = false; 209 } 210 break; 211 case IP_VERSION(13, 0, 0): 212 case IP_VERSION(13, 0, 7): 213 psp_v13_0_set_psp_funcs(psp); 214 psp->autoload_supported = true; 215 break; 216 case IP_VERSION(13, 0, 4): 217 psp_v13_0_4_set_psp_funcs(psp); 218 psp->autoload_supported = true; 219 break; 220 default: 221 return -EINVAL; 222 } 223 224 psp->adev = adev; 225 226 psp_check_pmfw_centralized_cstate_management(psp); 227 228 if (amdgpu_sriov_vf(adev)) 229 return psp_init_sriov_microcode(psp); 230 else 231 return psp_init_microcode(psp); 232 } 233 234 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 235 { 236 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 237 &mem_ctx->shared_buf); 238 mem_ctx->shared_bo = NULL; 239 } 240 241 static void psp_free_shared_bufs(struct psp_context *psp) 242 { 243 void *tmr_buf; 244 void **pptr; 245 246 /* free TMR memory buffer */ 247 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 248 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 249 psp->tmr_bo = NULL; 250 251 /* free xgmi shared memory */ 252 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 253 254 /* free ras shared memory */ 255 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 256 257 /* free hdcp shared memory */ 258 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 259 260 /* free dtm shared memory */ 261 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 262 263 /* free rap shared memory */ 264 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 265 266 /* free securedisplay shared memory */ 267 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 268 269 270 } 271 272 static void psp_memory_training_fini(struct psp_context *psp) 273 { 274 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 275 276 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 277 kfree(ctx->sys_cache); 278 ctx->sys_cache = NULL; 279 } 280 281 static int psp_memory_training_init(struct psp_context *psp) 282 { 283 int ret; 284 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 285 286 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 287 DRM_DEBUG("memory training is not supported!\n"); 288 return 0; 289 } 290 291 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 292 if (ctx->sys_cache == NULL) { 293 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 294 ret = -ENOMEM; 295 goto Err_out; 296 } 297 298 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 299 ctx->train_data_size, 300 ctx->p2c_train_data_offset, 301 ctx->c2p_train_data_offset); 302 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 303 return 0; 304 305 Err_out: 306 psp_memory_training_fini(psp); 307 return ret; 308 } 309 310 /* 311 * Helper funciton to query psp runtime database entry 312 * 313 * @adev: amdgpu_device pointer 314 * @entry_type: the type of psp runtime database entry 315 * @db_entry: runtime database entry pointer 316 * 317 * Return false if runtime database doesn't exit or entry is invalid 318 * or true if the specific database entry is found, and copy to @db_entry 319 */ 320 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 321 enum psp_runtime_entry_type entry_type, 322 void *db_entry) 323 { 324 uint64_t db_header_pos, db_dir_pos; 325 struct psp_runtime_data_header db_header = {0}; 326 struct psp_runtime_data_directory db_dir = {0}; 327 bool ret = false; 328 int i; 329 330 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 331 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 332 333 /* read runtime db header from vram */ 334 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 335 sizeof(struct psp_runtime_data_header), false); 336 337 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 338 /* runtime db doesn't exist, exit */ 339 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 340 return false; 341 } 342 343 /* read runtime database entry from vram */ 344 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 345 sizeof(struct psp_runtime_data_directory), false); 346 347 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 348 /* invalid db entry count, exit */ 349 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 350 return false; 351 } 352 353 /* look up for requested entry type */ 354 for (i = 0; i < db_dir.entry_count && !ret; i++) { 355 if (db_dir.entry_list[i].entry_type == entry_type) { 356 switch (entry_type) { 357 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 358 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 359 /* invalid db entry size */ 360 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 361 return false; 362 } 363 /* read runtime database entry */ 364 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 365 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 366 ret = true; 367 break; 368 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 369 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 370 /* invalid db entry size */ 371 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 372 return false; 373 } 374 /* read runtime database entry */ 375 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 376 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 377 ret = true; 378 break; 379 default: 380 ret = false; 381 break; 382 } 383 } 384 } 385 386 return ret; 387 } 388 389 static int psp_sw_init(void *handle) 390 { 391 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 392 struct psp_context *psp = &adev->psp; 393 int ret; 394 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 395 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 396 struct psp_runtime_scpm_entry scpm_entry; 397 398 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 399 if (!psp->cmd) { 400 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 401 ret = -ENOMEM; 402 } 403 404 adev->psp.xgmi_context.supports_extended_data = 405 !adev->gmc.xgmi.connected_to_cpu && 406 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 407 408 memset(&scpm_entry, 0, sizeof(scpm_entry)); 409 if ((psp_get_runtime_db_entry(adev, 410 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 411 &scpm_entry)) && 412 (SCPM_DISABLE != scpm_entry.scpm_status)) { 413 adev->scpm_enabled = true; 414 adev->scpm_status = scpm_entry.scpm_status; 415 } else { 416 adev->scpm_enabled = false; 417 adev->scpm_status = SCPM_DISABLE; 418 } 419 420 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 421 422 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 423 if (psp_get_runtime_db_entry(adev, 424 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 425 &boot_cfg_entry)) { 426 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 427 if ((psp->boot_cfg_bitmask) & 428 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 429 /* If psp runtime database exists, then 430 * only enable two stage memory training 431 * when TWO_STAGE_DRAM_TRAINING bit is set 432 * in runtime database */ 433 mem_training_ctx->enable_mem_training = true; 434 } 435 436 } else { 437 /* If psp runtime database doesn't exist or 438 * is invalid, force enable two stage memory 439 * training */ 440 mem_training_ctx->enable_mem_training = true; 441 } 442 443 if (mem_training_ctx->enable_mem_training) { 444 ret = psp_memory_training_init(psp); 445 if (ret) { 446 DRM_ERROR("Failed to initialize memory training!\n"); 447 return ret; 448 } 449 450 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 451 if (ret) { 452 DRM_ERROR("Failed to process memory training!\n"); 453 return ret; 454 } 455 } 456 457 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 458 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 459 ret= psp_sysfs_init(adev); 460 if (ret) { 461 return ret; 462 } 463 } 464 465 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 466 amdgpu_sriov_vf(adev) ? 467 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 468 &psp->fw_pri_bo, 469 &psp->fw_pri_mc_addr, 470 &psp->fw_pri_buf); 471 if (ret) 472 return ret; 473 474 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 475 AMDGPU_GEM_DOMAIN_VRAM, 476 &psp->fence_buf_bo, 477 &psp->fence_buf_mc_addr, 478 &psp->fence_buf); 479 if (ret) 480 goto failed1; 481 482 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 483 AMDGPU_GEM_DOMAIN_VRAM, 484 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 485 (void **)&psp->cmd_buf_mem); 486 if (ret) 487 goto failed2; 488 489 return 0; 490 491 failed2: 492 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 493 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 494 failed1: 495 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 496 &psp->fence_buf_mc_addr, &psp->fence_buf); 497 return ret; 498 } 499 500 static int psp_sw_fini(void *handle) 501 { 502 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 503 struct psp_context *psp = &adev->psp; 504 struct psp_gfx_cmd_resp *cmd = psp->cmd; 505 506 psp_memory_training_fini(psp); 507 508 amdgpu_ucode_release(&psp->sos_fw); 509 amdgpu_ucode_release(&psp->asd_fw); 510 amdgpu_ucode_release(&psp->ta_fw); 511 amdgpu_ucode_release(&psp->cap_fw); 512 amdgpu_ucode_release(&psp->toc_fw); 513 514 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 515 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 516 psp_sysfs_fini(adev); 517 518 kfree(cmd); 519 cmd = NULL; 520 521 if (psp->km_ring.ring_mem) 522 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 523 &psp->km_ring.ring_mem_mc_addr, 524 (void **)&psp->km_ring.ring_mem); 525 526 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 527 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 528 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 529 &psp->fence_buf_mc_addr, &psp->fence_buf); 530 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 531 (void **)&psp->cmd_buf_mem); 532 533 return 0; 534 } 535 536 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 537 uint32_t reg_val, uint32_t mask, bool check_changed) 538 { 539 uint32_t val; 540 int i; 541 struct amdgpu_device *adev = psp->adev; 542 543 if (psp->adev->no_hw_access) 544 return 0; 545 546 for (i = 0; i < adev->usec_timeout; i++) { 547 val = RREG32(reg_index); 548 if (check_changed) { 549 if (val != reg_val) 550 return 0; 551 } else { 552 if ((val & mask) == reg_val) 553 return 0; 554 } 555 udelay(1); 556 } 557 558 return -ETIME; 559 } 560 561 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 562 { 563 switch (cmd_id) { 564 case GFX_CMD_ID_LOAD_TA: 565 return "LOAD_TA"; 566 case GFX_CMD_ID_UNLOAD_TA: 567 return "UNLOAD_TA"; 568 case GFX_CMD_ID_INVOKE_CMD: 569 return "INVOKE_CMD"; 570 case GFX_CMD_ID_LOAD_ASD: 571 return "LOAD_ASD"; 572 case GFX_CMD_ID_SETUP_TMR: 573 return "SETUP_TMR"; 574 case GFX_CMD_ID_LOAD_IP_FW: 575 return "LOAD_IP_FW"; 576 case GFX_CMD_ID_DESTROY_TMR: 577 return "DESTROY_TMR"; 578 case GFX_CMD_ID_SAVE_RESTORE: 579 return "SAVE_RESTORE_IP_FW"; 580 case GFX_CMD_ID_SETUP_VMR: 581 return "SETUP_VMR"; 582 case GFX_CMD_ID_DESTROY_VMR: 583 return "DESTROY_VMR"; 584 case GFX_CMD_ID_PROG_REG: 585 return "PROG_REG"; 586 case GFX_CMD_ID_GET_FW_ATTESTATION: 587 return "GET_FW_ATTESTATION"; 588 case GFX_CMD_ID_LOAD_TOC: 589 return "ID_LOAD_TOC"; 590 case GFX_CMD_ID_AUTOLOAD_RLC: 591 return "AUTOLOAD_RLC"; 592 case GFX_CMD_ID_BOOT_CFG: 593 return "BOOT_CFG"; 594 default: 595 return "UNKNOWN CMD"; 596 } 597 } 598 599 static int 600 psp_cmd_submit_buf(struct psp_context *psp, 601 struct amdgpu_firmware_info *ucode, 602 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 603 { 604 int ret; 605 int index, idx; 606 int timeout = 20000; 607 bool ras_intr = false; 608 bool skip_unsupport = false; 609 bool dev_entered; 610 611 if (psp->adev->no_hw_access) 612 return 0; 613 614 dev_entered = drm_dev_enter(adev_to_drm(psp->adev), &idx); 615 /* 616 * We allow sending PSP messages LOAD_ASD and UNLOAD_TA without acquiring 617 * a lock in drm_dev_enter during driver unload because we must call 618 * drm_dev_unplug as the beginning of unload driver sequence . It is very 619 * crucial that userspace can't access device instances anymore. 620 */ 621 if (!dev_entered) 622 WARN_ON(psp->cmd_buf_mem->cmd_id != GFX_CMD_ID_LOAD_ASD && 623 psp->cmd_buf_mem->cmd_id != GFX_CMD_ID_UNLOAD_TA && 624 psp->cmd_buf_mem->cmd_id != GFX_CMD_ID_INVOKE_CMD); 625 626 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 627 628 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 629 630 index = atomic_inc_return(&psp->fence_value); 631 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 632 if (ret) { 633 atomic_dec(&psp->fence_value); 634 goto exit; 635 } 636 637 amdgpu_device_invalidate_hdp(psp->adev, NULL); 638 while (*((unsigned int *)psp->fence_buf) != index) { 639 if (--timeout == 0) 640 break; 641 /* 642 * Shouldn't wait for timeout when err_event_athub occurs, 643 * because gpu reset thread triggered and lock resource should 644 * be released for psp resume sequence. 645 */ 646 ras_intr = amdgpu_ras_intr_triggered(); 647 if (ras_intr) 648 break; 649 usleep_range(10, 100); 650 amdgpu_device_invalidate_hdp(psp->adev, NULL); 651 } 652 653 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 654 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 655 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 656 657 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 658 659 /* In some cases, psp response status is not 0 even there is no 660 * problem while the command is submitted. Some version of PSP FW 661 * doesn't write 0 to that field. 662 * So here we would like to only print a warning instead of an error 663 * during psp initialization to avoid breaking hw_init and it doesn't 664 * return -EINVAL. 665 */ 666 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 667 if (ucode) 668 DRM_WARN("failed to load ucode %s(0x%X) ", 669 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 670 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 671 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 672 psp->cmd_buf_mem->resp.status); 673 /* If any firmware (including CAP) load fails under SRIOV, it should 674 * return failure to stop the VF from initializing. 675 * Also return failure in case of timeout 676 */ 677 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 678 ret = -EINVAL; 679 goto exit; 680 } 681 } 682 683 if (ucode) { 684 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 685 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 686 } 687 688 exit: 689 if (dev_entered) 690 drm_dev_exit(idx); 691 return ret; 692 } 693 694 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 695 { 696 struct psp_gfx_cmd_resp *cmd = psp->cmd; 697 698 mutex_lock(&psp->mutex); 699 700 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 701 702 return cmd; 703 } 704 705 static void release_psp_cmd_buf(struct psp_context *psp) 706 { 707 mutex_unlock(&psp->mutex); 708 } 709 710 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 711 struct psp_gfx_cmd_resp *cmd, 712 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 713 { 714 struct amdgpu_device *adev = psp->adev; 715 uint32_t size = amdgpu_bo_size(tmr_bo); 716 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 717 718 if (amdgpu_sriov_vf(psp->adev)) 719 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 720 else 721 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 722 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 723 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 724 cmd->cmd.cmd_setup_tmr.buf_size = size; 725 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 726 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 727 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 728 } 729 730 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 731 uint64_t pri_buf_mc, uint32_t size) 732 { 733 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 734 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 735 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 736 cmd->cmd.cmd_load_toc.toc_size = size; 737 } 738 739 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 740 static int psp_load_toc(struct psp_context *psp, 741 uint32_t *tmr_size) 742 { 743 int ret; 744 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 745 746 /* Copy toc to psp firmware private buffer */ 747 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 748 749 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 750 751 ret = psp_cmd_submit_buf(psp, NULL, cmd, 752 psp->fence_buf_mc_addr); 753 if (!ret) 754 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 755 756 release_psp_cmd_buf(psp); 757 758 return ret; 759 } 760 761 /* Set up Trusted Memory Region */ 762 static int psp_tmr_init(struct psp_context *psp) 763 { 764 int ret = 0; 765 int tmr_size; 766 void *tmr_buf; 767 void **pptr; 768 769 /* 770 * According to HW engineer, they prefer the TMR address be "naturally 771 * aligned" , e.g. the start address be an integer divide of TMR size. 772 * 773 * Note: this memory need be reserved till the driver 774 * uninitializes. 775 */ 776 tmr_size = PSP_TMR_SIZE(psp->adev); 777 778 /* For ASICs support RLC autoload, psp will parse the toc 779 * and calculate the total size of TMR needed */ 780 if (!amdgpu_sriov_vf(psp->adev) && 781 psp->toc.start_addr && 782 psp->toc.size_bytes && 783 psp->fw_pri_buf) { 784 ret = psp_load_toc(psp, &tmr_size); 785 if (ret) { 786 DRM_ERROR("Failed to load toc\n"); 787 return ret; 788 } 789 } 790 791 if (!psp->tmr_bo) { 792 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 793 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 794 PSP_TMR_ALIGNMENT, 795 AMDGPU_HAS_VRAM(psp->adev) ? 796 AMDGPU_GEM_DOMAIN_VRAM : 797 AMDGPU_GEM_DOMAIN_GTT, 798 &psp->tmr_bo, &psp->tmr_mc_addr, 799 pptr); 800 } 801 802 return ret; 803 } 804 805 static bool psp_skip_tmr(struct psp_context *psp) 806 { 807 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 808 case IP_VERSION(11, 0, 9): 809 case IP_VERSION(11, 0, 7): 810 case IP_VERSION(13, 0, 2): 811 case IP_VERSION(13, 0, 10): 812 return true; 813 default: 814 return false; 815 } 816 } 817 818 static int psp_tmr_load(struct psp_context *psp) 819 { 820 int ret; 821 struct psp_gfx_cmd_resp *cmd; 822 823 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 824 * Already set up by host driver. 825 */ 826 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 827 return 0; 828 829 cmd = acquire_psp_cmd_buf(psp); 830 831 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 832 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 833 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 834 835 ret = psp_cmd_submit_buf(psp, NULL, cmd, 836 psp->fence_buf_mc_addr); 837 838 release_psp_cmd_buf(psp); 839 840 return ret; 841 } 842 843 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 844 struct psp_gfx_cmd_resp *cmd) 845 { 846 if (amdgpu_sriov_vf(psp->adev)) 847 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 848 else 849 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 850 } 851 852 static int psp_tmr_unload(struct psp_context *psp) 853 { 854 int ret; 855 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 856 857 psp_prep_tmr_unload_cmd_buf(psp, cmd); 858 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 859 860 ret = psp_cmd_submit_buf(psp, NULL, cmd, 861 psp->fence_buf_mc_addr); 862 863 release_psp_cmd_buf(psp); 864 865 return ret; 866 } 867 868 static int psp_tmr_terminate(struct psp_context *psp) 869 { 870 return psp_tmr_unload(psp); 871 } 872 873 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 874 uint64_t *output_ptr) 875 { 876 int ret; 877 struct psp_gfx_cmd_resp *cmd; 878 879 if (!output_ptr) 880 return -EINVAL; 881 882 if (amdgpu_sriov_vf(psp->adev)) 883 return 0; 884 885 cmd = acquire_psp_cmd_buf(psp); 886 887 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 888 889 ret = psp_cmd_submit_buf(psp, NULL, cmd, 890 psp->fence_buf_mc_addr); 891 892 if (!ret) { 893 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 894 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 895 } 896 897 release_psp_cmd_buf(psp); 898 899 return ret; 900 } 901 902 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 903 { 904 struct psp_context *psp = &adev->psp; 905 struct psp_gfx_cmd_resp *cmd; 906 int ret; 907 908 if (amdgpu_sriov_vf(adev)) 909 return 0; 910 911 cmd = acquire_psp_cmd_buf(psp); 912 913 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 914 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 915 916 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 917 if (!ret) { 918 *boot_cfg = 919 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 920 } 921 922 release_psp_cmd_buf(psp); 923 924 return ret; 925 } 926 927 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 928 { 929 int ret; 930 struct psp_context *psp = &adev->psp; 931 struct psp_gfx_cmd_resp *cmd; 932 933 if (amdgpu_sriov_vf(adev)) 934 return 0; 935 936 cmd = acquire_psp_cmd_buf(psp); 937 938 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 939 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 940 cmd->cmd.boot_cfg.boot_config = boot_cfg; 941 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 942 943 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 944 945 release_psp_cmd_buf(psp); 946 947 return ret; 948 } 949 950 static int psp_rl_load(struct amdgpu_device *adev) 951 { 952 int ret; 953 struct psp_context *psp = &adev->psp; 954 struct psp_gfx_cmd_resp *cmd; 955 956 if (!is_psp_fw_valid(psp->rl)) 957 return 0; 958 959 cmd = acquire_psp_cmd_buf(psp); 960 961 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 962 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 963 964 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 965 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 966 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 967 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 968 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 969 970 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 971 972 release_psp_cmd_buf(psp); 973 974 return ret; 975 } 976 977 static int psp_asd_initialize(struct psp_context *psp) 978 { 979 int ret; 980 981 /* If PSP version doesn't match ASD version, asd loading will be failed. 982 * add workaround to bypass it for sriov now. 983 * TODO: add version check to make it common 984 */ 985 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 986 return 0; 987 988 psp->asd_context.mem_context.shared_mc_addr = 0; 989 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 990 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 991 992 ret = psp_ta_load(psp, &psp->asd_context); 993 if (!ret) 994 psp->asd_context.initialized = true; 995 996 return ret; 997 } 998 999 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1000 uint32_t session_id) 1001 { 1002 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1003 cmd->cmd.cmd_unload_ta.session_id = session_id; 1004 } 1005 1006 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1007 { 1008 int ret; 1009 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1010 1011 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1012 1013 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1014 1015 context->resp_status = cmd->resp.status; 1016 1017 release_psp_cmd_buf(psp); 1018 1019 return ret; 1020 } 1021 1022 static int psp_asd_terminate(struct psp_context *psp) 1023 { 1024 int ret; 1025 1026 if (amdgpu_sriov_vf(psp->adev)) 1027 return 0; 1028 1029 if (!psp->asd_context.initialized) 1030 return 0; 1031 1032 ret = psp_ta_unload(psp, &psp->asd_context); 1033 if (!ret) 1034 psp->asd_context.initialized = false; 1035 1036 return ret; 1037 } 1038 1039 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1040 uint32_t id, uint32_t value) 1041 { 1042 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1043 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1044 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1045 } 1046 1047 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1048 uint32_t value) 1049 { 1050 struct psp_gfx_cmd_resp *cmd; 1051 int ret = 0; 1052 1053 if (reg >= PSP_REG_LAST) 1054 return -EINVAL; 1055 1056 cmd = acquire_psp_cmd_buf(psp); 1057 1058 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1059 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1060 if (ret) 1061 DRM_ERROR("PSP failed to program reg id %d", reg); 1062 1063 release_psp_cmd_buf(psp); 1064 1065 return ret; 1066 } 1067 1068 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1069 uint64_t ta_bin_mc, 1070 struct ta_context *context) 1071 { 1072 cmd->cmd_id = context->ta_load_type; 1073 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1074 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1075 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1076 1077 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1078 lower_32_bits(context->mem_context.shared_mc_addr); 1079 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1080 upper_32_bits(context->mem_context.shared_mc_addr); 1081 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1082 } 1083 1084 int psp_ta_init_shared_buf(struct psp_context *psp, 1085 struct ta_mem_context *mem_ctx) 1086 { 1087 /* 1088 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1089 * physical) for ta to host memory 1090 */ 1091 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1092 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1093 AMDGPU_GEM_DOMAIN_GTT, 1094 &mem_ctx->shared_bo, 1095 &mem_ctx->shared_mc_addr, 1096 &mem_ctx->shared_buf); 1097 } 1098 1099 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1100 uint32_t ta_cmd_id, 1101 uint32_t session_id) 1102 { 1103 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1104 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1105 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1106 } 1107 1108 int psp_ta_invoke(struct psp_context *psp, 1109 uint32_t ta_cmd_id, 1110 struct ta_context *context) 1111 { 1112 int ret; 1113 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1114 1115 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1116 1117 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1118 psp->fence_buf_mc_addr); 1119 1120 context->resp_status = cmd->resp.status; 1121 1122 release_psp_cmd_buf(psp); 1123 1124 return ret; 1125 } 1126 1127 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1128 { 1129 int ret; 1130 struct psp_gfx_cmd_resp *cmd; 1131 1132 cmd = acquire_psp_cmd_buf(psp); 1133 1134 psp_copy_fw(psp, context->bin_desc.start_addr, 1135 context->bin_desc.size_bytes); 1136 1137 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1138 1139 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1140 psp->fence_buf_mc_addr); 1141 1142 context->resp_status = cmd->resp.status; 1143 1144 if (!ret) { 1145 context->session_id = cmd->resp.session_id; 1146 } 1147 1148 release_psp_cmd_buf(psp); 1149 1150 return ret; 1151 } 1152 1153 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1154 { 1155 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1156 } 1157 1158 int psp_xgmi_terminate(struct psp_context *psp) 1159 { 1160 int ret; 1161 struct amdgpu_device *adev = psp->adev; 1162 1163 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1164 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1165 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1166 adev->gmc.xgmi.connected_to_cpu)) 1167 return 0; 1168 1169 if (!psp->xgmi_context.context.initialized) 1170 return 0; 1171 1172 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1173 1174 psp->xgmi_context.context.initialized = false; 1175 1176 return ret; 1177 } 1178 1179 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1180 { 1181 struct ta_xgmi_shared_memory *xgmi_cmd; 1182 int ret; 1183 1184 if (!psp->ta_fw || 1185 !psp->xgmi_context.context.bin_desc.size_bytes || 1186 !psp->xgmi_context.context.bin_desc.start_addr) 1187 return -ENOENT; 1188 1189 if (!load_ta) 1190 goto invoke; 1191 1192 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1193 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1194 1195 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1196 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1197 if (ret) 1198 return ret; 1199 } 1200 1201 /* Load XGMI TA */ 1202 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1203 if (!ret) 1204 psp->xgmi_context.context.initialized = true; 1205 else 1206 return ret; 1207 1208 invoke: 1209 /* Initialize XGMI session */ 1210 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1211 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1212 xgmi_cmd->flag_extend_link_record = set_extended_data; 1213 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1214 1215 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1216 1217 return ret; 1218 } 1219 1220 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1221 { 1222 struct ta_xgmi_shared_memory *xgmi_cmd; 1223 int ret; 1224 1225 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1226 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1227 1228 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1229 1230 /* Invoke xgmi ta to get hive id */ 1231 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1232 if (ret) 1233 return ret; 1234 1235 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1236 1237 return 0; 1238 } 1239 1240 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1241 { 1242 struct ta_xgmi_shared_memory *xgmi_cmd; 1243 int ret; 1244 1245 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1246 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1247 1248 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1249 1250 /* Invoke xgmi ta to get the node id */ 1251 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1252 if (ret) 1253 return ret; 1254 1255 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1256 1257 return 0; 1258 } 1259 1260 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1261 { 1262 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1263 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1264 } 1265 1266 /* 1267 * Chips that support extended topology information require the driver to 1268 * reflect topology information in the opposite direction. This is 1269 * because the TA has already exceeded its link record limit and if the 1270 * TA holds bi-directional information, the driver would have to do 1271 * multiple fetches instead of just two. 1272 */ 1273 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1274 struct psp_xgmi_node_info node_info) 1275 { 1276 struct amdgpu_device *mirror_adev; 1277 struct amdgpu_hive_info *hive; 1278 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1279 uint64_t dst_node_id = node_info.node_id; 1280 uint8_t dst_num_hops = node_info.num_hops; 1281 uint8_t dst_num_links = node_info.num_links; 1282 1283 hive = amdgpu_get_xgmi_hive(psp->adev); 1284 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1285 struct psp_xgmi_topology_info *mirror_top_info; 1286 int j; 1287 1288 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1289 continue; 1290 1291 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1292 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1293 if (mirror_top_info->nodes[j].node_id != src_node_id) 1294 continue; 1295 1296 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1297 /* 1298 * prevent 0 num_links value re-reflection since reflection 1299 * criteria is based on num_hops (direct or indirect). 1300 * 1301 */ 1302 if (dst_num_links) 1303 mirror_top_info->nodes[j].num_links = dst_num_links; 1304 1305 break; 1306 } 1307 1308 break; 1309 } 1310 1311 amdgpu_put_xgmi_hive(hive); 1312 } 1313 1314 int psp_xgmi_get_topology_info(struct psp_context *psp, 1315 int number_devices, 1316 struct psp_xgmi_topology_info *topology, 1317 bool get_extended_data) 1318 { 1319 struct ta_xgmi_shared_memory *xgmi_cmd; 1320 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1321 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1322 int i; 1323 int ret; 1324 1325 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1326 return -EINVAL; 1327 1328 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1329 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1330 xgmi_cmd->flag_extend_link_record = get_extended_data; 1331 1332 /* Fill in the shared memory with topology information as input */ 1333 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1334 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1335 topology_info_input->num_nodes = number_devices; 1336 1337 for (i = 0; i < topology_info_input->num_nodes; i++) { 1338 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1339 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1340 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1341 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1342 } 1343 1344 /* Invoke xgmi ta to get the topology information */ 1345 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1346 if (ret) 1347 return ret; 1348 1349 /* Read the output topology information from the shared memory */ 1350 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1351 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1352 for (i = 0; i < topology->num_nodes; i++) { 1353 /* extended data will either be 0 or equal to non-extended data */ 1354 if (topology_info_output->nodes[i].num_hops) 1355 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1356 1357 /* non-extended data gets everything here so no need to update */ 1358 if (!get_extended_data) { 1359 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1360 topology->nodes[i].is_sharing_enabled = 1361 topology_info_output->nodes[i].is_sharing_enabled; 1362 topology->nodes[i].sdma_engine = 1363 topology_info_output->nodes[i].sdma_engine; 1364 } 1365 1366 } 1367 1368 /* Invoke xgmi ta again to get the link information */ 1369 if (psp_xgmi_peer_link_info_supported(psp)) { 1370 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1371 1372 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1373 1374 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1375 1376 if (ret) 1377 return ret; 1378 1379 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1380 for (i = 0; i < topology->num_nodes; i++) { 1381 /* accumulate num_links on extended data */ 1382 topology->nodes[i].num_links = get_extended_data ? 1383 topology->nodes[i].num_links + 1384 link_info_output->nodes[i].num_links : 1385 link_info_output->nodes[i].num_links; 1386 1387 /* reflect the topology information for bi-directionality */ 1388 if (psp->xgmi_context.supports_extended_data && 1389 get_extended_data && topology->nodes[i].num_hops) 1390 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1391 } 1392 } 1393 1394 return 0; 1395 } 1396 1397 int psp_xgmi_set_topology_info(struct psp_context *psp, 1398 int number_devices, 1399 struct psp_xgmi_topology_info *topology) 1400 { 1401 struct ta_xgmi_shared_memory *xgmi_cmd; 1402 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1403 int i; 1404 1405 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1406 return -EINVAL; 1407 1408 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1409 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1410 1411 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1412 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1413 topology_info_input->num_nodes = number_devices; 1414 1415 for (i = 0; i < topology_info_input->num_nodes; i++) { 1416 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1417 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1418 topology_info_input->nodes[i].is_sharing_enabled = 1; 1419 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1420 } 1421 1422 /* Invoke xgmi ta to set topology information */ 1423 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1424 } 1425 1426 // ras begin 1427 static void psp_ras_ta_check_status(struct psp_context *psp) 1428 { 1429 struct ta_ras_shared_memory *ras_cmd = 1430 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1431 1432 switch (ras_cmd->ras_status) { 1433 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1434 dev_warn(psp->adev->dev, 1435 "RAS WARNING: cmd failed due to unsupported ip\n"); 1436 break; 1437 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1438 dev_warn(psp->adev->dev, 1439 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1440 break; 1441 case TA_RAS_STATUS__SUCCESS: 1442 break; 1443 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1444 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1445 dev_warn(psp->adev->dev, 1446 "RAS WARNING: Inject error to critical region is not allowed\n"); 1447 break; 1448 default: 1449 dev_warn(psp->adev->dev, 1450 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1451 break; 1452 } 1453 } 1454 1455 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1456 { 1457 struct ta_ras_shared_memory *ras_cmd; 1458 int ret; 1459 1460 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1461 1462 /* 1463 * TODO: bypass the loading in sriov for now 1464 */ 1465 if (amdgpu_sriov_vf(psp->adev)) 1466 return 0; 1467 1468 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1469 1470 if (amdgpu_ras_intr_triggered()) 1471 return ret; 1472 1473 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1474 { 1475 DRM_WARN("RAS: Unsupported Interface"); 1476 return -EINVAL; 1477 } 1478 1479 if (!ret) { 1480 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1481 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1482 1483 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1484 } 1485 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1486 dev_warn(psp->adev->dev, 1487 "RAS internal register access blocked\n"); 1488 1489 psp_ras_ta_check_status(psp); 1490 } 1491 1492 return ret; 1493 } 1494 1495 int psp_ras_enable_features(struct psp_context *psp, 1496 union ta_ras_cmd_input *info, bool enable) 1497 { 1498 struct ta_ras_shared_memory *ras_cmd; 1499 int ret; 1500 1501 if (!psp->ras_context.context.initialized) 1502 return -EINVAL; 1503 1504 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1505 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1506 1507 if (enable) 1508 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1509 else 1510 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1511 1512 ras_cmd->ras_in_message = *info; 1513 1514 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1515 if (ret) 1516 return -EINVAL; 1517 1518 return 0; 1519 } 1520 1521 int psp_ras_terminate(struct psp_context *psp) 1522 { 1523 int ret; 1524 1525 /* 1526 * TODO: bypass the terminate in sriov for now 1527 */ 1528 if (amdgpu_sriov_vf(psp->adev)) 1529 return 0; 1530 1531 if (!psp->ras_context.context.initialized) 1532 return 0; 1533 1534 ret = psp_ta_unload(psp, &psp->ras_context.context); 1535 1536 psp->ras_context.context.initialized = false; 1537 1538 return ret; 1539 } 1540 1541 int psp_ras_initialize(struct psp_context *psp) 1542 { 1543 int ret; 1544 uint32_t boot_cfg = 0xFF; 1545 struct amdgpu_device *adev = psp->adev; 1546 struct ta_ras_shared_memory *ras_cmd; 1547 1548 /* 1549 * TODO: bypass the initialize in sriov for now 1550 */ 1551 if (amdgpu_sriov_vf(adev)) 1552 return 0; 1553 1554 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1555 !adev->psp.ras_context.context.bin_desc.start_addr) { 1556 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1557 return 0; 1558 } 1559 1560 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1561 /* query GECC enablement status from boot config 1562 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1563 */ 1564 ret = psp_boot_config_get(adev, &boot_cfg); 1565 if (ret) 1566 dev_warn(adev->dev, "PSP get boot config failed\n"); 1567 1568 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1569 if (!boot_cfg) { 1570 dev_info(adev->dev, "GECC is disabled\n"); 1571 } else { 1572 /* disable GECC in next boot cycle if ras is 1573 * disabled by module parameter amdgpu_ras_enable 1574 * and/or amdgpu_ras_mask, or boot_config_get call 1575 * is failed 1576 */ 1577 ret = psp_boot_config_set(adev, 0); 1578 if (ret) 1579 dev_warn(adev->dev, "PSP set boot config failed\n"); 1580 else 1581 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1582 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1583 } 1584 } else { 1585 if (1 == boot_cfg) { 1586 dev_info(adev->dev, "GECC is enabled\n"); 1587 } else { 1588 /* enable GECC in next boot cycle if it is disabled 1589 * in boot config, or force enable GECC if failed to 1590 * get boot configuration 1591 */ 1592 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1593 if (ret) 1594 dev_warn(adev->dev, "PSP set boot config failed\n"); 1595 else 1596 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1597 } 1598 } 1599 } 1600 1601 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1602 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1603 1604 if (!psp->ras_context.context.mem_context.shared_buf) { 1605 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1606 if (ret) 1607 return ret; 1608 } 1609 1610 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1611 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1612 1613 if (amdgpu_ras_is_poison_mode_supported(adev)) 1614 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1615 if (!adev->gmc.xgmi.connected_to_cpu) 1616 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1617 1618 ret = psp_ta_load(psp, &psp->ras_context.context); 1619 1620 if (!ret && !ras_cmd->ras_status) 1621 psp->ras_context.context.initialized = true; 1622 else { 1623 if (ras_cmd->ras_status) 1624 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1625 1626 /* fail to load RAS TA */ 1627 psp->ras_context.context.initialized = false; 1628 } 1629 1630 return ret; 1631 } 1632 1633 int psp_ras_trigger_error(struct psp_context *psp, 1634 struct ta_ras_trigger_error_input *info) 1635 { 1636 struct ta_ras_shared_memory *ras_cmd; 1637 int ret; 1638 1639 if (!psp->ras_context.context.initialized) 1640 return -EINVAL; 1641 1642 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1643 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1644 1645 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1646 ras_cmd->ras_in_message.trigger_error = *info; 1647 1648 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1649 if (ret) 1650 return -EINVAL; 1651 1652 /* If err_event_athub occurs error inject was successful, however 1653 return status from TA is no long reliable */ 1654 if (amdgpu_ras_intr_triggered()) 1655 return 0; 1656 1657 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1658 return -EACCES; 1659 else if (ras_cmd->ras_status) 1660 return -EINVAL; 1661 1662 return 0; 1663 } 1664 // ras end 1665 1666 // HDCP start 1667 static int psp_hdcp_initialize(struct psp_context *psp) 1668 { 1669 int ret; 1670 1671 /* 1672 * TODO: bypass the initialize in sriov for now 1673 */ 1674 if (amdgpu_sriov_vf(psp->adev)) 1675 return 0; 1676 1677 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1678 !psp->hdcp_context.context.bin_desc.start_addr) { 1679 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1680 return 0; 1681 } 1682 1683 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1684 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1685 1686 if (!psp->hdcp_context.context.mem_context.shared_buf) { 1687 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1688 if (ret) 1689 return ret; 1690 } 1691 1692 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1693 if (!ret) { 1694 psp->hdcp_context.context.initialized = true; 1695 mutex_init(&psp->hdcp_context.mutex); 1696 } 1697 1698 return ret; 1699 } 1700 1701 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1702 { 1703 /* 1704 * TODO: bypass the loading in sriov for now 1705 */ 1706 if (amdgpu_sriov_vf(psp->adev)) 1707 return 0; 1708 1709 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1710 } 1711 1712 static int psp_hdcp_terminate(struct psp_context *psp) 1713 { 1714 int ret; 1715 1716 /* 1717 * TODO: bypass the terminate in sriov for now 1718 */ 1719 if (amdgpu_sriov_vf(psp->adev)) 1720 return 0; 1721 1722 if (!psp->hdcp_context.context.initialized) 1723 return 0; 1724 1725 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1726 1727 psp->hdcp_context.context.initialized = false; 1728 1729 return ret; 1730 } 1731 // HDCP end 1732 1733 // DTM start 1734 static int psp_dtm_initialize(struct psp_context *psp) 1735 { 1736 int ret; 1737 1738 /* 1739 * TODO: bypass the initialize in sriov for now 1740 */ 1741 if (amdgpu_sriov_vf(psp->adev)) 1742 return 0; 1743 1744 if (!psp->dtm_context.context.bin_desc.size_bytes || 1745 !psp->dtm_context.context.bin_desc.start_addr) { 1746 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1747 return 0; 1748 } 1749 1750 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1751 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1752 1753 if (!psp->dtm_context.context.mem_context.shared_buf) { 1754 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1755 if (ret) 1756 return ret; 1757 } 1758 1759 ret = psp_ta_load(psp, &psp->dtm_context.context); 1760 if (!ret) { 1761 psp->dtm_context.context.initialized = true; 1762 mutex_init(&psp->dtm_context.mutex); 1763 } 1764 1765 return ret; 1766 } 1767 1768 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1769 { 1770 /* 1771 * TODO: bypass the loading in sriov for now 1772 */ 1773 if (amdgpu_sriov_vf(psp->adev)) 1774 return 0; 1775 1776 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1777 } 1778 1779 static int psp_dtm_terminate(struct psp_context *psp) 1780 { 1781 int ret; 1782 1783 /* 1784 * TODO: bypass the terminate in sriov for now 1785 */ 1786 if (amdgpu_sriov_vf(psp->adev)) 1787 return 0; 1788 1789 if (!psp->dtm_context.context.initialized) 1790 return 0; 1791 1792 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1793 1794 psp->dtm_context.context.initialized = false; 1795 1796 return ret; 1797 } 1798 // DTM end 1799 1800 // RAP start 1801 static int psp_rap_initialize(struct psp_context *psp) 1802 { 1803 int ret; 1804 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1805 1806 /* 1807 * TODO: bypass the initialize in sriov for now 1808 */ 1809 if (amdgpu_sriov_vf(psp->adev)) 1810 return 0; 1811 1812 if (!psp->rap_context.context.bin_desc.size_bytes || 1813 !psp->rap_context.context.bin_desc.start_addr) { 1814 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1815 return 0; 1816 } 1817 1818 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1819 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1820 1821 if (!psp->rap_context.context.mem_context.shared_buf) { 1822 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1823 if (ret) 1824 return ret; 1825 } 1826 1827 ret = psp_ta_load(psp, &psp->rap_context.context); 1828 if (!ret) { 1829 psp->rap_context.context.initialized = true; 1830 mutex_init(&psp->rap_context.mutex); 1831 } else 1832 return ret; 1833 1834 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1835 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1836 psp_rap_terminate(psp); 1837 /* free rap shared memory */ 1838 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1839 1840 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1841 ret, status); 1842 1843 return ret; 1844 } 1845 1846 return 0; 1847 } 1848 1849 static int psp_rap_terminate(struct psp_context *psp) 1850 { 1851 int ret; 1852 1853 if (!psp->rap_context.context.initialized) 1854 return 0; 1855 1856 ret = psp_ta_unload(psp, &psp->rap_context.context); 1857 1858 psp->rap_context.context.initialized = false; 1859 1860 return ret; 1861 } 1862 1863 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1864 { 1865 struct ta_rap_shared_memory *rap_cmd; 1866 int ret = 0; 1867 1868 if (!psp->rap_context.context.initialized) 1869 return 0; 1870 1871 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1872 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1873 return -EINVAL; 1874 1875 mutex_lock(&psp->rap_context.mutex); 1876 1877 rap_cmd = (struct ta_rap_shared_memory *) 1878 psp->rap_context.context.mem_context.shared_buf; 1879 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1880 1881 rap_cmd->cmd_id = ta_cmd_id; 1882 rap_cmd->validation_method_id = METHOD_A; 1883 1884 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1885 if (ret) 1886 goto out_unlock; 1887 1888 if (status) 1889 *status = rap_cmd->rap_status; 1890 1891 out_unlock: 1892 mutex_unlock(&psp->rap_context.mutex); 1893 1894 return ret; 1895 } 1896 // RAP end 1897 1898 /* securedisplay start */ 1899 static int psp_securedisplay_initialize(struct psp_context *psp) 1900 { 1901 int ret; 1902 struct ta_securedisplay_cmd *securedisplay_cmd; 1903 1904 /* 1905 * TODO: bypass the initialize in sriov for now 1906 */ 1907 if (amdgpu_sriov_vf(psp->adev)) 1908 return 0; 1909 1910 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1911 !psp->securedisplay_context.context.bin_desc.start_addr) { 1912 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1913 return 0; 1914 } 1915 1916 psp->securedisplay_context.context.mem_context.shared_mem_size = 1917 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1918 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1919 1920 if (!psp->securedisplay_context.context.initialized) { 1921 ret = psp_ta_init_shared_buf(psp, 1922 &psp->securedisplay_context.context.mem_context); 1923 if (ret) 1924 return ret; 1925 } 1926 1927 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 1928 if (!ret) { 1929 psp->securedisplay_context.context.initialized = true; 1930 mutex_init(&psp->securedisplay_context.mutex); 1931 } else 1932 return ret; 1933 1934 mutex_lock(&psp->securedisplay_context.mutex); 1935 1936 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1937 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1938 1939 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1940 1941 mutex_unlock(&psp->securedisplay_context.mutex); 1942 1943 if (ret) { 1944 psp_securedisplay_terminate(psp); 1945 /* free securedisplay shared memory */ 1946 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1947 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1948 return -EINVAL; 1949 } 1950 1951 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1952 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1953 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1954 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1955 } 1956 1957 return 0; 1958 } 1959 1960 static int psp_securedisplay_terminate(struct psp_context *psp) 1961 { 1962 int ret; 1963 1964 /* 1965 * TODO:bypass the terminate in sriov for now 1966 */ 1967 if (amdgpu_sriov_vf(psp->adev)) 1968 return 0; 1969 1970 if (!psp->securedisplay_context.context.initialized) 1971 return 0; 1972 1973 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 1974 1975 psp->securedisplay_context.context.initialized = false; 1976 1977 return ret; 1978 } 1979 1980 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1981 { 1982 int ret; 1983 1984 if (!psp->securedisplay_context.context.initialized) 1985 return -EINVAL; 1986 1987 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1988 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1989 return -EINVAL; 1990 1991 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1992 1993 return ret; 1994 } 1995 /* SECUREDISPLAY end */ 1996 1997 static int psp_hw_start(struct psp_context *psp) 1998 { 1999 struct amdgpu_device *adev = psp->adev; 2000 int ret; 2001 2002 if (!amdgpu_sriov_vf(adev)) { 2003 if ((is_psp_fw_valid(psp->kdb)) && 2004 (psp->funcs->bootloader_load_kdb != NULL)) { 2005 ret = psp_bootloader_load_kdb(psp); 2006 if (ret) { 2007 DRM_ERROR("PSP load kdb failed!\n"); 2008 return ret; 2009 } 2010 } 2011 2012 if ((is_psp_fw_valid(psp->spl)) && 2013 (psp->funcs->bootloader_load_spl != NULL)) { 2014 ret = psp_bootloader_load_spl(psp); 2015 if (ret) { 2016 DRM_ERROR("PSP load spl failed!\n"); 2017 return ret; 2018 } 2019 } 2020 2021 if ((is_psp_fw_valid(psp->sys)) && 2022 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2023 ret = psp_bootloader_load_sysdrv(psp); 2024 if (ret) { 2025 DRM_ERROR("PSP load sys drv failed!\n"); 2026 return ret; 2027 } 2028 } 2029 2030 if ((is_psp_fw_valid(psp->soc_drv)) && 2031 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2032 ret = psp_bootloader_load_soc_drv(psp); 2033 if (ret) { 2034 DRM_ERROR("PSP load soc drv failed!\n"); 2035 return ret; 2036 } 2037 } 2038 2039 if ((is_psp_fw_valid(psp->intf_drv)) && 2040 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2041 ret = psp_bootloader_load_intf_drv(psp); 2042 if (ret) { 2043 DRM_ERROR("PSP load intf drv failed!\n"); 2044 return ret; 2045 } 2046 } 2047 2048 if ((is_psp_fw_valid(psp->dbg_drv)) && 2049 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2050 ret = psp_bootloader_load_dbg_drv(psp); 2051 if (ret) { 2052 DRM_ERROR("PSP load dbg drv failed!\n"); 2053 return ret; 2054 } 2055 } 2056 2057 if ((is_psp_fw_valid(psp->ras_drv)) && 2058 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2059 ret = psp_bootloader_load_ras_drv(psp); 2060 if (ret) { 2061 DRM_ERROR("PSP load ras_drv failed!\n"); 2062 return ret; 2063 } 2064 } 2065 2066 if ((is_psp_fw_valid(psp->sos)) && 2067 (psp->funcs->bootloader_load_sos != NULL)) { 2068 ret = psp_bootloader_load_sos(psp); 2069 if (ret) { 2070 DRM_ERROR("PSP load sos failed!\n"); 2071 return ret; 2072 } 2073 } 2074 } 2075 2076 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2077 if (ret) { 2078 DRM_ERROR("PSP create ring failed!\n"); 2079 return ret; 2080 } 2081 2082 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2083 goto skip_pin_bo; 2084 2085 ret = psp_tmr_init(psp); 2086 if (ret) { 2087 DRM_ERROR("PSP tmr init failed!\n"); 2088 return ret; 2089 } 2090 2091 skip_pin_bo: 2092 /* 2093 * For ASICs with DF Cstate management centralized 2094 * to PMFW, TMR setup should be performed after PMFW 2095 * loaded and before other non-psp firmware loaded. 2096 */ 2097 if (psp->pmfw_centralized_cstate_management) { 2098 ret = psp_load_smu_fw(psp); 2099 if (ret) 2100 return ret; 2101 } 2102 2103 ret = psp_tmr_load(psp); 2104 if (ret) { 2105 DRM_ERROR("PSP load tmr failed!\n"); 2106 return ret; 2107 } 2108 2109 return 0; 2110 } 2111 2112 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2113 enum psp_gfx_fw_type *type) 2114 { 2115 switch (ucode->ucode_id) { 2116 case AMDGPU_UCODE_ID_CAP: 2117 *type = GFX_FW_TYPE_CAP; 2118 break; 2119 case AMDGPU_UCODE_ID_SDMA0: 2120 *type = GFX_FW_TYPE_SDMA0; 2121 break; 2122 case AMDGPU_UCODE_ID_SDMA1: 2123 *type = GFX_FW_TYPE_SDMA1; 2124 break; 2125 case AMDGPU_UCODE_ID_SDMA2: 2126 *type = GFX_FW_TYPE_SDMA2; 2127 break; 2128 case AMDGPU_UCODE_ID_SDMA3: 2129 *type = GFX_FW_TYPE_SDMA3; 2130 break; 2131 case AMDGPU_UCODE_ID_SDMA4: 2132 *type = GFX_FW_TYPE_SDMA4; 2133 break; 2134 case AMDGPU_UCODE_ID_SDMA5: 2135 *type = GFX_FW_TYPE_SDMA5; 2136 break; 2137 case AMDGPU_UCODE_ID_SDMA6: 2138 *type = GFX_FW_TYPE_SDMA6; 2139 break; 2140 case AMDGPU_UCODE_ID_SDMA7: 2141 *type = GFX_FW_TYPE_SDMA7; 2142 break; 2143 case AMDGPU_UCODE_ID_CP_MES: 2144 *type = GFX_FW_TYPE_CP_MES; 2145 break; 2146 case AMDGPU_UCODE_ID_CP_MES_DATA: 2147 *type = GFX_FW_TYPE_MES_STACK; 2148 break; 2149 case AMDGPU_UCODE_ID_CP_MES1: 2150 *type = GFX_FW_TYPE_CP_MES_KIQ; 2151 break; 2152 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2153 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2154 break; 2155 case AMDGPU_UCODE_ID_CP_CE: 2156 *type = GFX_FW_TYPE_CP_CE; 2157 break; 2158 case AMDGPU_UCODE_ID_CP_PFP: 2159 *type = GFX_FW_TYPE_CP_PFP; 2160 break; 2161 case AMDGPU_UCODE_ID_CP_ME: 2162 *type = GFX_FW_TYPE_CP_ME; 2163 break; 2164 case AMDGPU_UCODE_ID_CP_MEC1: 2165 *type = GFX_FW_TYPE_CP_MEC; 2166 break; 2167 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2168 *type = GFX_FW_TYPE_CP_MEC_ME1; 2169 break; 2170 case AMDGPU_UCODE_ID_CP_MEC2: 2171 *type = GFX_FW_TYPE_CP_MEC; 2172 break; 2173 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2174 *type = GFX_FW_TYPE_CP_MEC_ME2; 2175 break; 2176 case AMDGPU_UCODE_ID_RLC_P: 2177 *type = GFX_FW_TYPE_RLC_P; 2178 break; 2179 case AMDGPU_UCODE_ID_RLC_V: 2180 *type = GFX_FW_TYPE_RLC_V; 2181 break; 2182 case AMDGPU_UCODE_ID_RLC_G: 2183 *type = GFX_FW_TYPE_RLC_G; 2184 break; 2185 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2186 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2187 break; 2188 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2189 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2190 break; 2191 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2192 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2193 break; 2194 case AMDGPU_UCODE_ID_RLC_IRAM: 2195 *type = GFX_FW_TYPE_RLC_IRAM; 2196 break; 2197 case AMDGPU_UCODE_ID_RLC_DRAM: 2198 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2199 break; 2200 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2201 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2202 break; 2203 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2204 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2205 break; 2206 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2207 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2208 break; 2209 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2210 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2211 break; 2212 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2213 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2214 break; 2215 case AMDGPU_UCODE_ID_SMC: 2216 *type = GFX_FW_TYPE_SMU; 2217 break; 2218 case AMDGPU_UCODE_ID_PPTABLE: 2219 *type = GFX_FW_TYPE_PPTABLE; 2220 break; 2221 case AMDGPU_UCODE_ID_UVD: 2222 *type = GFX_FW_TYPE_UVD; 2223 break; 2224 case AMDGPU_UCODE_ID_UVD1: 2225 *type = GFX_FW_TYPE_UVD1; 2226 break; 2227 case AMDGPU_UCODE_ID_VCE: 2228 *type = GFX_FW_TYPE_VCE; 2229 break; 2230 case AMDGPU_UCODE_ID_VCN: 2231 *type = GFX_FW_TYPE_VCN; 2232 break; 2233 case AMDGPU_UCODE_ID_VCN1: 2234 *type = GFX_FW_TYPE_VCN1; 2235 break; 2236 case AMDGPU_UCODE_ID_DMCU_ERAM: 2237 *type = GFX_FW_TYPE_DMCU_ERAM; 2238 break; 2239 case AMDGPU_UCODE_ID_DMCU_INTV: 2240 *type = GFX_FW_TYPE_DMCU_ISR; 2241 break; 2242 case AMDGPU_UCODE_ID_VCN0_RAM: 2243 *type = GFX_FW_TYPE_VCN0_RAM; 2244 break; 2245 case AMDGPU_UCODE_ID_VCN1_RAM: 2246 *type = GFX_FW_TYPE_VCN1_RAM; 2247 break; 2248 case AMDGPU_UCODE_ID_DMCUB: 2249 *type = GFX_FW_TYPE_DMUB; 2250 break; 2251 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2252 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2253 break; 2254 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2255 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2256 break; 2257 case AMDGPU_UCODE_ID_IMU_I: 2258 *type = GFX_FW_TYPE_IMU_I; 2259 break; 2260 case AMDGPU_UCODE_ID_IMU_D: 2261 *type = GFX_FW_TYPE_IMU_D; 2262 break; 2263 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2264 *type = GFX_FW_TYPE_RS64_PFP; 2265 break; 2266 case AMDGPU_UCODE_ID_CP_RS64_ME: 2267 *type = GFX_FW_TYPE_RS64_ME; 2268 break; 2269 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2270 *type = GFX_FW_TYPE_RS64_MEC; 2271 break; 2272 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2273 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2274 break; 2275 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2276 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2277 break; 2278 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2279 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2280 break; 2281 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2282 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2283 break; 2284 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2285 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2286 break; 2287 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2288 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2289 break; 2290 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2291 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2292 break; 2293 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2294 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2295 break; 2296 case AMDGPU_UCODE_ID_MAXIMUM: 2297 default: 2298 return -EINVAL; 2299 } 2300 2301 return 0; 2302 } 2303 2304 static void psp_print_fw_hdr(struct psp_context *psp, 2305 struct amdgpu_firmware_info *ucode) 2306 { 2307 struct amdgpu_device *adev = psp->adev; 2308 struct common_firmware_header *hdr; 2309 2310 switch (ucode->ucode_id) { 2311 case AMDGPU_UCODE_ID_SDMA0: 2312 case AMDGPU_UCODE_ID_SDMA1: 2313 case AMDGPU_UCODE_ID_SDMA2: 2314 case AMDGPU_UCODE_ID_SDMA3: 2315 case AMDGPU_UCODE_ID_SDMA4: 2316 case AMDGPU_UCODE_ID_SDMA5: 2317 case AMDGPU_UCODE_ID_SDMA6: 2318 case AMDGPU_UCODE_ID_SDMA7: 2319 hdr = (struct common_firmware_header *) 2320 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2321 amdgpu_ucode_print_sdma_hdr(hdr); 2322 break; 2323 case AMDGPU_UCODE_ID_CP_CE: 2324 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2325 amdgpu_ucode_print_gfx_hdr(hdr); 2326 break; 2327 case AMDGPU_UCODE_ID_CP_PFP: 2328 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2329 amdgpu_ucode_print_gfx_hdr(hdr); 2330 break; 2331 case AMDGPU_UCODE_ID_CP_ME: 2332 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2333 amdgpu_ucode_print_gfx_hdr(hdr); 2334 break; 2335 case AMDGPU_UCODE_ID_CP_MEC1: 2336 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2337 amdgpu_ucode_print_gfx_hdr(hdr); 2338 break; 2339 case AMDGPU_UCODE_ID_RLC_G: 2340 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2341 amdgpu_ucode_print_rlc_hdr(hdr); 2342 break; 2343 case AMDGPU_UCODE_ID_SMC: 2344 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2345 amdgpu_ucode_print_smc_hdr(hdr); 2346 break; 2347 default: 2348 break; 2349 } 2350 } 2351 2352 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2353 struct psp_gfx_cmd_resp *cmd) 2354 { 2355 int ret; 2356 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2357 2358 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2359 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2360 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2361 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2362 2363 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2364 if (ret) 2365 DRM_ERROR("Unknown firmware type\n"); 2366 2367 return ret; 2368 } 2369 2370 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2371 struct amdgpu_firmware_info *ucode) 2372 { 2373 int ret = 0; 2374 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2375 2376 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2377 if (!ret) { 2378 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2379 psp->fence_buf_mc_addr); 2380 } 2381 2382 release_psp_cmd_buf(psp); 2383 2384 return ret; 2385 } 2386 2387 static int psp_load_smu_fw(struct psp_context *psp) 2388 { 2389 int ret; 2390 struct amdgpu_device *adev = psp->adev; 2391 struct amdgpu_firmware_info *ucode = 2392 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2393 struct amdgpu_ras *ras = psp->ras_context.ras; 2394 2395 /* 2396 * Skip SMU FW reloading in case of using BACO for runpm only, 2397 * as SMU is always alive. 2398 */ 2399 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2400 return 0; 2401 2402 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2403 return 0; 2404 2405 if ((amdgpu_in_reset(adev) && 2406 ras && adev->ras_enabled && 2407 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2408 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2409 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2410 if (ret) { 2411 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2412 } 2413 } 2414 2415 ret = psp_execute_non_psp_fw_load(psp, ucode); 2416 2417 if (ret) 2418 DRM_ERROR("PSP load smu failed!\n"); 2419 2420 return ret; 2421 } 2422 2423 static bool fw_load_skip_check(struct psp_context *psp, 2424 struct amdgpu_firmware_info *ucode) 2425 { 2426 if (!ucode->fw || !ucode->ucode_size) 2427 return true; 2428 2429 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2430 (psp_smu_reload_quirk(psp) || 2431 psp->autoload_supported || 2432 psp->pmfw_centralized_cstate_management)) 2433 return true; 2434 2435 if (amdgpu_sriov_vf(psp->adev) && 2436 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2437 return true; 2438 2439 if (psp->autoload_supported && 2440 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2441 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2442 /* skip mec JT when autoload is enabled */ 2443 return true; 2444 2445 return false; 2446 } 2447 2448 int psp_load_fw_list(struct psp_context *psp, 2449 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2450 { 2451 int ret = 0, i; 2452 struct amdgpu_firmware_info *ucode; 2453 2454 for (i = 0; i < ucode_count; ++i) { 2455 ucode = ucode_list[i]; 2456 psp_print_fw_hdr(psp, ucode); 2457 ret = psp_execute_non_psp_fw_load(psp, ucode); 2458 if (ret) 2459 return ret; 2460 } 2461 return ret; 2462 } 2463 2464 static int psp_load_non_psp_fw(struct psp_context *psp) 2465 { 2466 int i, ret; 2467 struct amdgpu_firmware_info *ucode; 2468 struct amdgpu_device *adev = psp->adev; 2469 2470 if (psp->autoload_supported && 2471 !psp->pmfw_centralized_cstate_management) { 2472 ret = psp_load_smu_fw(psp); 2473 if (ret) 2474 return ret; 2475 } 2476 2477 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2478 ucode = &adev->firmware.ucode[i]; 2479 2480 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2481 !fw_load_skip_check(psp, ucode)) { 2482 ret = psp_load_smu_fw(psp); 2483 if (ret) 2484 return ret; 2485 continue; 2486 } 2487 2488 if (fw_load_skip_check(psp, ucode)) 2489 continue; 2490 2491 if (psp->autoload_supported && 2492 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2493 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2494 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2495 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2496 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2497 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2498 /* PSP only receive one SDMA fw for sienna_cichlid, 2499 * as all four sdma fw are same */ 2500 continue; 2501 2502 psp_print_fw_hdr(psp, ucode); 2503 2504 ret = psp_execute_non_psp_fw_load(psp, ucode); 2505 if (ret) 2506 return ret; 2507 2508 /* Start rlc autoload after psp recieved all the gfx firmware */ 2509 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2510 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2511 ret = psp_rlc_autoload_start(psp); 2512 if (ret) { 2513 DRM_ERROR("Failed to start rlc autoload\n"); 2514 return ret; 2515 } 2516 } 2517 } 2518 2519 return 0; 2520 } 2521 2522 static int psp_load_fw(struct amdgpu_device *adev) 2523 { 2524 int ret; 2525 struct psp_context *psp = &adev->psp; 2526 2527 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2528 /* should not destroy ring, only stop */ 2529 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2530 } else { 2531 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2532 2533 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2534 if (ret) { 2535 DRM_ERROR("PSP ring init failed!\n"); 2536 goto failed; 2537 } 2538 } 2539 2540 ret = psp_hw_start(psp); 2541 if (ret) 2542 goto failed; 2543 2544 ret = psp_load_non_psp_fw(psp); 2545 if (ret) 2546 goto failed1; 2547 2548 ret = psp_asd_initialize(psp); 2549 if (ret) { 2550 DRM_ERROR("PSP load asd failed!\n"); 2551 goto failed1; 2552 } 2553 2554 ret = psp_rl_load(adev); 2555 if (ret) { 2556 DRM_ERROR("PSP load RL failed!\n"); 2557 goto failed1; 2558 } 2559 2560 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2561 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2562 ret = psp_xgmi_initialize(psp, false, true); 2563 /* Warning the XGMI seesion initialize failure 2564 * Instead of stop driver initialization 2565 */ 2566 if (ret) 2567 dev_err(psp->adev->dev, 2568 "XGMI: Failed to initialize XGMI session\n"); 2569 } 2570 } 2571 2572 if (psp->ta_fw) { 2573 ret = psp_ras_initialize(psp); 2574 if (ret) 2575 dev_err(psp->adev->dev, 2576 "RAS: Failed to initialize RAS\n"); 2577 2578 ret = psp_hdcp_initialize(psp); 2579 if (ret) 2580 dev_err(psp->adev->dev, 2581 "HDCP: Failed to initialize HDCP\n"); 2582 2583 ret = psp_dtm_initialize(psp); 2584 if (ret) 2585 dev_err(psp->adev->dev, 2586 "DTM: Failed to initialize DTM\n"); 2587 2588 ret = psp_rap_initialize(psp); 2589 if (ret) 2590 dev_err(psp->adev->dev, 2591 "RAP: Failed to initialize RAP\n"); 2592 2593 ret = psp_securedisplay_initialize(psp); 2594 if (ret) 2595 dev_err(psp->adev->dev, 2596 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2597 } 2598 2599 return 0; 2600 2601 failed1: 2602 psp_free_shared_bufs(psp); 2603 failed: 2604 /* 2605 * all cleanup jobs (xgmi terminate, ras terminate, 2606 * ring destroy, cmd/fence/fw buffers destory, 2607 * psp->cmd destory) are delayed to psp_hw_fini 2608 */ 2609 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2610 return ret; 2611 } 2612 2613 static int psp_hw_init(void *handle) 2614 { 2615 int ret; 2616 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2617 2618 mutex_lock(&adev->firmware.mutex); 2619 /* 2620 * This sequence is just used on hw_init only once, no need on 2621 * resume. 2622 */ 2623 ret = amdgpu_ucode_init_bo(adev); 2624 if (ret) 2625 goto failed; 2626 2627 ret = psp_load_fw(adev); 2628 if (ret) { 2629 DRM_ERROR("PSP firmware loading failed\n"); 2630 goto failed; 2631 } 2632 2633 mutex_unlock(&adev->firmware.mutex); 2634 return 0; 2635 2636 failed: 2637 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2638 mutex_unlock(&adev->firmware.mutex); 2639 return -EINVAL; 2640 } 2641 2642 static int psp_hw_fini(void *handle) 2643 { 2644 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2645 struct psp_context *psp = &adev->psp; 2646 2647 if (psp->ta_fw) { 2648 psp_ras_terminate(psp); 2649 psp_securedisplay_terminate(psp); 2650 psp_rap_terminate(psp); 2651 psp_dtm_terminate(psp); 2652 psp_hdcp_terminate(psp); 2653 2654 if (adev->gmc.xgmi.num_physical_nodes > 1) 2655 psp_xgmi_terminate(psp); 2656 } 2657 2658 psp_asd_terminate(psp); 2659 psp_tmr_terminate(psp); 2660 2661 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2662 2663 psp_free_shared_bufs(psp); 2664 2665 return 0; 2666 } 2667 2668 static int psp_suspend(void *handle) 2669 { 2670 int ret = 0; 2671 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2672 struct psp_context *psp = &adev->psp; 2673 2674 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2675 psp->xgmi_context.context.initialized) { 2676 ret = psp_xgmi_terminate(psp); 2677 if (ret) { 2678 DRM_ERROR("Failed to terminate xgmi ta\n"); 2679 goto out; 2680 } 2681 } 2682 2683 if (psp->ta_fw) { 2684 ret = psp_ras_terminate(psp); 2685 if (ret) { 2686 DRM_ERROR("Failed to terminate ras ta\n"); 2687 goto out; 2688 } 2689 ret = psp_hdcp_terminate(psp); 2690 if (ret) { 2691 DRM_ERROR("Failed to terminate hdcp ta\n"); 2692 goto out; 2693 } 2694 ret = psp_dtm_terminate(psp); 2695 if (ret) { 2696 DRM_ERROR("Failed to terminate dtm ta\n"); 2697 goto out; 2698 } 2699 ret = psp_rap_terminate(psp); 2700 if (ret) { 2701 DRM_ERROR("Failed to terminate rap ta\n"); 2702 goto out; 2703 } 2704 ret = psp_securedisplay_terminate(psp); 2705 if (ret) { 2706 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2707 goto out; 2708 } 2709 } 2710 2711 ret = psp_asd_terminate(psp); 2712 if (ret) { 2713 DRM_ERROR("Failed to terminate asd\n"); 2714 goto out; 2715 } 2716 2717 ret = psp_tmr_terminate(psp); 2718 if (ret) { 2719 DRM_ERROR("Failed to terminate tmr\n"); 2720 goto out; 2721 } 2722 2723 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2724 if (ret) { 2725 DRM_ERROR("PSP ring stop failed\n"); 2726 } 2727 2728 out: 2729 return ret; 2730 } 2731 2732 static int psp_resume(void *handle) 2733 { 2734 int ret; 2735 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2736 struct psp_context *psp = &adev->psp; 2737 2738 DRM_INFO("PSP is resuming...\n"); 2739 2740 if (psp->mem_train_ctx.enable_mem_training) { 2741 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2742 if (ret) { 2743 DRM_ERROR("Failed to process memory training!\n"); 2744 return ret; 2745 } 2746 } 2747 2748 mutex_lock(&adev->firmware.mutex); 2749 2750 ret = psp_hw_start(psp); 2751 if (ret) 2752 goto failed; 2753 2754 ret = psp_load_non_psp_fw(psp); 2755 if (ret) 2756 goto failed; 2757 2758 ret = psp_asd_initialize(psp); 2759 if (ret) { 2760 DRM_ERROR("PSP load asd failed!\n"); 2761 goto failed; 2762 } 2763 2764 ret = psp_rl_load(adev); 2765 if (ret) { 2766 dev_err(adev->dev, "PSP load RL failed!\n"); 2767 goto failed; 2768 } 2769 2770 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2771 ret = psp_xgmi_initialize(psp, false, true); 2772 /* Warning the XGMI seesion initialize failure 2773 * Instead of stop driver initialization 2774 */ 2775 if (ret) 2776 dev_err(psp->adev->dev, 2777 "XGMI: Failed to initialize XGMI session\n"); 2778 } 2779 2780 if (psp->ta_fw) { 2781 ret = psp_ras_initialize(psp); 2782 if (ret) 2783 dev_err(psp->adev->dev, 2784 "RAS: Failed to initialize RAS\n"); 2785 2786 ret = psp_hdcp_initialize(psp); 2787 if (ret) 2788 dev_err(psp->adev->dev, 2789 "HDCP: Failed to initialize HDCP\n"); 2790 2791 ret = psp_dtm_initialize(psp); 2792 if (ret) 2793 dev_err(psp->adev->dev, 2794 "DTM: Failed to initialize DTM\n"); 2795 2796 ret = psp_rap_initialize(psp); 2797 if (ret) 2798 dev_err(psp->adev->dev, 2799 "RAP: Failed to initialize RAP\n"); 2800 2801 ret = psp_securedisplay_initialize(psp); 2802 if (ret) 2803 dev_err(psp->adev->dev, 2804 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2805 } 2806 2807 mutex_unlock(&adev->firmware.mutex); 2808 2809 return 0; 2810 2811 failed: 2812 DRM_ERROR("PSP resume failed\n"); 2813 mutex_unlock(&adev->firmware.mutex); 2814 return ret; 2815 } 2816 2817 int psp_gpu_reset(struct amdgpu_device *adev) 2818 { 2819 int ret; 2820 2821 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2822 return 0; 2823 2824 mutex_lock(&adev->psp.mutex); 2825 ret = psp_mode1_reset(&adev->psp); 2826 mutex_unlock(&adev->psp.mutex); 2827 2828 return ret; 2829 } 2830 2831 int psp_rlc_autoload_start(struct psp_context *psp) 2832 { 2833 int ret; 2834 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2835 2836 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2837 2838 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2839 psp->fence_buf_mc_addr); 2840 2841 release_psp_cmd_buf(psp); 2842 2843 return ret; 2844 } 2845 2846 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2847 uint64_t cmd_gpu_addr, int cmd_size) 2848 { 2849 struct amdgpu_firmware_info ucode = {0}; 2850 2851 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2852 AMDGPU_UCODE_ID_VCN0_RAM; 2853 ucode.mc_addr = cmd_gpu_addr; 2854 ucode.ucode_size = cmd_size; 2855 2856 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2857 } 2858 2859 int psp_ring_cmd_submit(struct psp_context *psp, 2860 uint64_t cmd_buf_mc_addr, 2861 uint64_t fence_mc_addr, 2862 int index) 2863 { 2864 unsigned int psp_write_ptr_reg = 0; 2865 struct psp_gfx_rb_frame *write_frame; 2866 struct psp_ring *ring = &psp->km_ring; 2867 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2868 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2869 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2870 struct amdgpu_device *adev = psp->adev; 2871 uint32_t ring_size_dw = ring->ring_size / 4; 2872 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2873 2874 /* KM (GPCOM) prepare write pointer */ 2875 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2876 2877 /* Update KM RB frame pointer to new frame */ 2878 /* write_frame ptr increments by size of rb_frame in bytes */ 2879 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2880 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2881 write_frame = ring_buffer_start; 2882 else 2883 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2884 /* Check invalid write_frame ptr address */ 2885 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2886 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2887 ring_buffer_start, ring_buffer_end, write_frame); 2888 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2889 return -EINVAL; 2890 } 2891 2892 /* Initialize KM RB frame */ 2893 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2894 2895 /* Update KM RB frame */ 2896 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2897 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2898 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2899 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2900 write_frame->fence_value = index; 2901 amdgpu_device_flush_hdp(adev, NULL); 2902 2903 /* Update the write Pointer in DWORDs */ 2904 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2905 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2906 return 0; 2907 } 2908 2909 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 2910 { 2911 struct amdgpu_device *adev = psp->adev; 2912 char fw_name[PSP_FW_NAME_LEN]; 2913 const struct psp_firmware_header_v1_0 *asd_hdr; 2914 int err = 0; 2915 2916 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2917 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name); 2918 if (err) 2919 goto out; 2920 2921 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2922 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2923 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2924 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2925 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2926 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2927 return 0; 2928 out: 2929 amdgpu_ucode_release(&adev->psp.asd_fw); 2930 return err; 2931 } 2932 2933 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 2934 { 2935 struct amdgpu_device *adev = psp->adev; 2936 char fw_name[PSP_FW_NAME_LEN]; 2937 const struct psp_firmware_header_v1_0 *toc_hdr; 2938 int err = 0; 2939 2940 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2941 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 2942 if (err) 2943 goto out; 2944 2945 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2946 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2947 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2948 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2949 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2950 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2951 return 0; 2952 out: 2953 amdgpu_ucode_release(&adev->psp.toc_fw); 2954 return err; 2955 } 2956 2957 static int parse_sos_bin_descriptor(struct psp_context *psp, 2958 const struct psp_fw_bin_desc *desc, 2959 const struct psp_firmware_header_v2_0 *sos_hdr) 2960 { 2961 uint8_t *ucode_start_addr = NULL; 2962 2963 if (!psp || !desc || !sos_hdr) 2964 return -EINVAL; 2965 2966 ucode_start_addr = (uint8_t *)sos_hdr + 2967 le32_to_cpu(desc->offset_bytes) + 2968 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2969 2970 switch (desc->fw_type) { 2971 case PSP_FW_TYPE_PSP_SOS: 2972 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2973 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2974 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2975 psp->sos.start_addr = ucode_start_addr; 2976 break; 2977 case PSP_FW_TYPE_PSP_SYS_DRV: 2978 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2979 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2980 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2981 psp->sys.start_addr = ucode_start_addr; 2982 break; 2983 case PSP_FW_TYPE_PSP_KDB: 2984 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2985 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2986 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2987 psp->kdb.start_addr = ucode_start_addr; 2988 break; 2989 case PSP_FW_TYPE_PSP_TOC: 2990 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2991 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2992 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 2993 psp->toc.start_addr = ucode_start_addr; 2994 break; 2995 case PSP_FW_TYPE_PSP_SPL: 2996 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 2997 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 2998 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 2999 psp->spl.start_addr = ucode_start_addr; 3000 break; 3001 case PSP_FW_TYPE_PSP_RL: 3002 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3003 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3004 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3005 psp->rl.start_addr = ucode_start_addr; 3006 break; 3007 case PSP_FW_TYPE_PSP_SOC_DRV: 3008 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3009 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3010 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3011 psp->soc_drv.start_addr = ucode_start_addr; 3012 break; 3013 case PSP_FW_TYPE_PSP_INTF_DRV: 3014 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3015 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3016 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3017 psp->intf_drv.start_addr = ucode_start_addr; 3018 break; 3019 case PSP_FW_TYPE_PSP_DBG_DRV: 3020 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3021 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3022 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3023 psp->dbg_drv.start_addr = ucode_start_addr; 3024 break; 3025 case PSP_FW_TYPE_PSP_RAS_DRV: 3026 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3027 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3028 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3029 psp->ras_drv.start_addr = ucode_start_addr; 3030 break; 3031 default: 3032 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3033 break; 3034 } 3035 3036 return 0; 3037 } 3038 3039 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3040 { 3041 const struct psp_firmware_header_v1_0 *sos_hdr; 3042 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3043 uint8_t *ucode_array_start_addr; 3044 3045 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3046 ucode_array_start_addr = (uint8_t *)sos_hdr + 3047 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3048 3049 if (adev->gmc.xgmi.connected_to_cpu || 3050 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3051 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3052 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3053 3054 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3055 adev->psp.sys.start_addr = ucode_array_start_addr; 3056 3057 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3058 adev->psp.sos.start_addr = ucode_array_start_addr + 3059 le32_to_cpu(sos_hdr->sos.offset_bytes); 3060 } else { 3061 /* Load alternate PSP SOS FW */ 3062 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3063 3064 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3065 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3066 3067 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3068 adev->psp.sys.start_addr = ucode_array_start_addr + 3069 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3070 3071 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3072 adev->psp.sos.start_addr = ucode_array_start_addr + 3073 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3074 } 3075 3076 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3077 dev_warn(adev->dev, "PSP SOS FW not available"); 3078 return -EINVAL; 3079 } 3080 3081 return 0; 3082 } 3083 3084 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3085 { 3086 struct amdgpu_device *adev = psp->adev; 3087 char fw_name[PSP_FW_NAME_LEN]; 3088 const struct psp_firmware_header_v1_0 *sos_hdr; 3089 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3090 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3091 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3092 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3093 int err = 0; 3094 uint8_t *ucode_array_start_addr; 3095 int fw_index = 0; 3096 3097 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3098 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name); 3099 if (err) 3100 goto out; 3101 3102 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3103 ucode_array_start_addr = (uint8_t *)sos_hdr + 3104 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3105 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3106 3107 switch (sos_hdr->header.header_version_major) { 3108 case 1: 3109 err = psp_init_sos_base_fw(adev); 3110 if (err) 3111 goto out; 3112 3113 if (sos_hdr->header.header_version_minor == 1) { 3114 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3115 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3116 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3117 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3118 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3119 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3120 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3121 } 3122 if (sos_hdr->header.header_version_minor == 2) { 3123 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3124 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3125 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3126 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3127 } 3128 if (sos_hdr->header.header_version_minor == 3) { 3129 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3130 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3131 adev->psp.toc.start_addr = ucode_array_start_addr + 3132 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3133 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3134 adev->psp.kdb.start_addr = ucode_array_start_addr + 3135 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3136 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3137 adev->psp.spl.start_addr = ucode_array_start_addr + 3138 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3139 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3140 adev->psp.rl.start_addr = ucode_array_start_addr + 3141 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3142 } 3143 break; 3144 case 2: 3145 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3146 3147 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3148 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3149 err = -EINVAL; 3150 goto out; 3151 } 3152 3153 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3154 err = parse_sos_bin_descriptor(psp, 3155 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3156 sos_hdr_v2_0); 3157 if (err) 3158 goto out; 3159 } 3160 break; 3161 default: 3162 dev_err(adev->dev, 3163 "unsupported psp sos firmware\n"); 3164 err = -EINVAL; 3165 goto out; 3166 } 3167 3168 return 0; 3169 out: 3170 amdgpu_ucode_release(&adev->psp.sos_fw); 3171 3172 return err; 3173 } 3174 3175 static int parse_ta_bin_descriptor(struct psp_context *psp, 3176 const struct psp_fw_bin_desc *desc, 3177 const struct ta_firmware_header_v2_0 *ta_hdr) 3178 { 3179 uint8_t *ucode_start_addr = NULL; 3180 3181 if (!psp || !desc || !ta_hdr) 3182 return -EINVAL; 3183 3184 ucode_start_addr = (uint8_t *)ta_hdr + 3185 le32_to_cpu(desc->offset_bytes) + 3186 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3187 3188 switch (desc->fw_type) { 3189 case TA_FW_TYPE_PSP_ASD: 3190 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3191 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3192 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3193 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3194 break; 3195 case TA_FW_TYPE_PSP_XGMI: 3196 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3197 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3198 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3199 break; 3200 case TA_FW_TYPE_PSP_RAS: 3201 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3202 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3203 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3204 break; 3205 case TA_FW_TYPE_PSP_HDCP: 3206 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3207 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3208 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3209 break; 3210 case TA_FW_TYPE_PSP_DTM: 3211 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3212 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3213 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3214 break; 3215 case TA_FW_TYPE_PSP_RAP: 3216 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3217 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3218 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3219 break; 3220 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3221 psp->securedisplay_context.context.bin_desc.fw_version = 3222 le32_to_cpu(desc->fw_version); 3223 psp->securedisplay_context.context.bin_desc.size_bytes = 3224 le32_to_cpu(desc->size_bytes); 3225 psp->securedisplay_context.context.bin_desc.start_addr = 3226 ucode_start_addr; 3227 break; 3228 default: 3229 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3230 break; 3231 } 3232 3233 return 0; 3234 } 3235 3236 static int parse_ta_v1_microcode(struct psp_context *psp) 3237 { 3238 const struct ta_firmware_header_v1_0 *ta_hdr; 3239 struct amdgpu_device *adev = psp->adev; 3240 3241 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3242 3243 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3244 return -EINVAL; 3245 3246 adev->psp.xgmi_context.context.bin_desc.fw_version = 3247 le32_to_cpu(ta_hdr->xgmi.fw_version); 3248 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3249 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3250 adev->psp.xgmi_context.context.bin_desc.start_addr = 3251 (uint8_t *)ta_hdr + 3252 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3253 3254 adev->psp.ras_context.context.bin_desc.fw_version = 3255 le32_to_cpu(ta_hdr->ras.fw_version); 3256 adev->psp.ras_context.context.bin_desc.size_bytes = 3257 le32_to_cpu(ta_hdr->ras.size_bytes); 3258 adev->psp.ras_context.context.bin_desc.start_addr = 3259 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3260 le32_to_cpu(ta_hdr->ras.offset_bytes); 3261 3262 adev->psp.hdcp_context.context.bin_desc.fw_version = 3263 le32_to_cpu(ta_hdr->hdcp.fw_version); 3264 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3265 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3266 adev->psp.hdcp_context.context.bin_desc.start_addr = 3267 (uint8_t *)ta_hdr + 3268 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3269 3270 adev->psp.dtm_context.context.bin_desc.fw_version = 3271 le32_to_cpu(ta_hdr->dtm.fw_version); 3272 adev->psp.dtm_context.context.bin_desc.size_bytes = 3273 le32_to_cpu(ta_hdr->dtm.size_bytes); 3274 adev->psp.dtm_context.context.bin_desc.start_addr = 3275 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3276 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3277 3278 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3279 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3280 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3281 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3282 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3283 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3284 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3285 3286 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3287 3288 return 0; 3289 } 3290 3291 static int parse_ta_v2_microcode(struct psp_context *psp) 3292 { 3293 const struct ta_firmware_header_v2_0 *ta_hdr; 3294 struct amdgpu_device *adev = psp->adev; 3295 int err = 0; 3296 int ta_index = 0; 3297 3298 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3299 3300 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3301 return -EINVAL; 3302 3303 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3304 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3305 return -EINVAL; 3306 } 3307 3308 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3309 err = parse_ta_bin_descriptor(psp, 3310 &ta_hdr->ta_fw_bin[ta_index], 3311 ta_hdr); 3312 if (err) 3313 return err; 3314 } 3315 3316 return 0; 3317 } 3318 3319 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3320 { 3321 const struct common_firmware_header *hdr; 3322 struct amdgpu_device *adev = psp->adev; 3323 char fw_name[PSP_FW_NAME_LEN]; 3324 int err; 3325 3326 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3327 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name); 3328 if (err) 3329 return err; 3330 3331 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3332 switch (le16_to_cpu(hdr->header_version_major)) { 3333 case 1: 3334 err = parse_ta_v1_microcode(psp); 3335 break; 3336 case 2: 3337 err = parse_ta_v2_microcode(psp); 3338 break; 3339 default: 3340 dev_err(adev->dev, "unsupported TA header version\n"); 3341 err = -EINVAL; 3342 } 3343 3344 if (err) 3345 amdgpu_ucode_release(&adev->psp.ta_fw); 3346 3347 return err; 3348 } 3349 3350 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 3351 { 3352 struct amdgpu_device *adev = psp->adev; 3353 char fw_name[PSP_FW_NAME_LEN]; 3354 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3355 struct amdgpu_firmware_info *info = NULL; 3356 int err = 0; 3357 3358 if (!amdgpu_sriov_vf(adev)) { 3359 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3360 return -EINVAL; 3361 } 3362 3363 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3364 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name); 3365 if (err) { 3366 if (err == -ENODEV) { 3367 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3368 err = 0; 3369 goto out; 3370 } 3371 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3372 } 3373 3374 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3375 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3376 info->fw = adev->psp.cap_fw; 3377 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3378 adev->psp.cap_fw->data; 3379 adev->firmware.fw_size += ALIGN( 3380 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3381 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3382 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3383 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3384 3385 return 0; 3386 3387 out: 3388 amdgpu_ucode_release(&adev->psp.cap_fw); 3389 return err; 3390 } 3391 3392 static int psp_set_clockgating_state(void *handle, 3393 enum amd_clockgating_state state) 3394 { 3395 return 0; 3396 } 3397 3398 static int psp_set_powergating_state(void *handle, 3399 enum amd_powergating_state state) 3400 { 3401 return 0; 3402 } 3403 3404 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3405 struct device_attribute *attr, 3406 char *buf) 3407 { 3408 struct drm_device *ddev = dev_get_drvdata(dev); 3409 struct amdgpu_device *adev = drm_to_adev(ddev); 3410 uint32_t fw_ver; 3411 int ret; 3412 3413 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3414 DRM_INFO("PSP block is not ready yet."); 3415 return -EBUSY; 3416 } 3417 3418 mutex_lock(&adev->psp.mutex); 3419 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3420 mutex_unlock(&adev->psp.mutex); 3421 3422 if (ret) { 3423 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3424 return ret; 3425 } 3426 3427 return sysfs_emit(buf, "%x\n", fw_ver); 3428 } 3429 3430 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3431 struct device_attribute *attr, 3432 const char *buf, 3433 size_t count) 3434 { 3435 struct drm_device *ddev = dev_get_drvdata(dev); 3436 struct amdgpu_device *adev = drm_to_adev(ddev); 3437 int ret, idx; 3438 char fw_name[100]; 3439 const struct firmware *usbc_pd_fw; 3440 struct amdgpu_bo *fw_buf_bo = NULL; 3441 uint64_t fw_pri_mc_addr; 3442 void *fw_pri_cpu_addr; 3443 3444 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3445 DRM_INFO("PSP block is not ready yet."); 3446 return -EBUSY; 3447 } 3448 3449 if (!drm_dev_enter(ddev, &idx)) 3450 return -ENODEV; 3451 3452 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3453 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3454 if (ret) 3455 goto fail; 3456 3457 /* LFB address which is aligned to 1MB boundary per PSP request */ 3458 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3459 AMDGPU_GEM_DOMAIN_VRAM | 3460 AMDGPU_GEM_DOMAIN_GTT, 3461 &fw_buf_bo, &fw_pri_mc_addr, 3462 &fw_pri_cpu_addr); 3463 if (ret) 3464 goto rel_buf; 3465 3466 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3467 3468 mutex_lock(&adev->psp.mutex); 3469 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3470 mutex_unlock(&adev->psp.mutex); 3471 3472 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3473 3474 rel_buf: 3475 release_firmware(usbc_pd_fw); 3476 fail: 3477 if (ret) { 3478 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3479 count = ret; 3480 } 3481 3482 drm_dev_exit(idx); 3483 return count; 3484 } 3485 3486 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3487 { 3488 int idx; 3489 3490 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3491 return; 3492 3493 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3494 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3495 3496 drm_dev_exit(idx); 3497 } 3498 3499 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3500 psp_usbc_pd_fw_sysfs_read, 3501 psp_usbc_pd_fw_sysfs_write); 3502 3503 int is_psp_fw_valid(struct psp_bin_desc bin) 3504 { 3505 return bin.size_bytes; 3506 } 3507 3508 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3509 struct bin_attribute *bin_attr, 3510 char *buffer, loff_t pos, size_t count) 3511 { 3512 struct device *dev = kobj_to_dev(kobj); 3513 struct drm_device *ddev = dev_get_drvdata(dev); 3514 struct amdgpu_device *adev = drm_to_adev(ddev); 3515 3516 adev->psp.vbflash_done = false; 3517 3518 /* Safeguard against memory drain */ 3519 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3520 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3521 kvfree(adev->psp.vbflash_tmp_buf); 3522 adev->psp.vbflash_tmp_buf = NULL; 3523 adev->psp.vbflash_image_size = 0; 3524 return -ENOMEM; 3525 } 3526 3527 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3528 if (!adev->psp.vbflash_tmp_buf) { 3529 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3530 if (!adev->psp.vbflash_tmp_buf) 3531 return -ENOMEM; 3532 } 3533 3534 mutex_lock(&adev->psp.mutex); 3535 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3536 adev->psp.vbflash_image_size += count; 3537 mutex_unlock(&adev->psp.mutex); 3538 3539 dev_info(adev->dev, "VBIOS flash write PSP done"); 3540 3541 return count; 3542 } 3543 3544 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3545 struct bin_attribute *bin_attr, char *buffer, 3546 loff_t pos, size_t count) 3547 { 3548 struct device *dev = kobj_to_dev(kobj); 3549 struct drm_device *ddev = dev_get_drvdata(dev); 3550 struct amdgpu_device *adev = drm_to_adev(ddev); 3551 struct amdgpu_bo *fw_buf_bo = NULL; 3552 uint64_t fw_pri_mc_addr; 3553 void *fw_pri_cpu_addr; 3554 int ret; 3555 3556 dev_info(adev->dev, "VBIOS flash to PSP started"); 3557 3558 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3559 AMDGPU_GPU_PAGE_SIZE, 3560 AMDGPU_GEM_DOMAIN_VRAM, 3561 &fw_buf_bo, 3562 &fw_pri_mc_addr, 3563 &fw_pri_cpu_addr); 3564 if (ret) 3565 goto rel_buf; 3566 3567 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3568 3569 mutex_lock(&adev->psp.mutex); 3570 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3571 mutex_unlock(&adev->psp.mutex); 3572 3573 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3574 3575 rel_buf: 3576 kvfree(adev->psp.vbflash_tmp_buf); 3577 adev->psp.vbflash_tmp_buf = NULL; 3578 adev->psp.vbflash_image_size = 0; 3579 3580 if (ret) { 3581 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret); 3582 return ret; 3583 } 3584 3585 dev_info(adev->dev, "VBIOS flash to PSP done"); 3586 return 0; 3587 } 3588 3589 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3590 struct device_attribute *attr, 3591 char *buf) 3592 { 3593 struct drm_device *ddev = dev_get_drvdata(dev); 3594 struct amdgpu_device *adev = drm_to_adev(ddev); 3595 uint32_t vbflash_status; 3596 3597 vbflash_status = psp_vbflash_status(&adev->psp); 3598 if (!adev->psp.vbflash_done) 3599 vbflash_status = 0; 3600 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3601 vbflash_status = 1; 3602 3603 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3604 } 3605 3606 static const struct bin_attribute psp_vbflash_bin_attr = { 3607 .attr = {.name = "psp_vbflash", .mode = 0664}, 3608 .size = 0, 3609 .write = amdgpu_psp_vbflash_write, 3610 .read = amdgpu_psp_vbflash_read, 3611 }; 3612 3613 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL); 3614 3615 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev) 3616 { 3617 int ret = 0; 3618 struct psp_context *psp = &adev->psp; 3619 3620 if (amdgpu_sriov_vf(adev)) 3621 return -EINVAL; 3622 3623 switch (adev->ip_versions[MP0_HWIP][0]) { 3624 case IP_VERSION(13, 0, 0): 3625 case IP_VERSION(13, 0, 7): 3626 if (!psp->adev) { 3627 psp->adev = adev; 3628 psp_v13_0_set_psp_funcs(psp); 3629 } 3630 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3631 if (ret) 3632 dev_err(adev->dev, "Failed to create device file psp_vbflash"); 3633 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status); 3634 if (ret) 3635 dev_err(adev->dev, "Failed to create device file psp_vbflash_status"); 3636 return ret; 3637 default: 3638 return 0; 3639 } 3640 } 3641 3642 const struct amd_ip_funcs psp_ip_funcs = { 3643 .name = "psp", 3644 .early_init = psp_early_init, 3645 .late_init = NULL, 3646 .sw_init = psp_sw_init, 3647 .sw_fini = psp_sw_fini, 3648 .hw_init = psp_hw_init, 3649 .hw_fini = psp_hw_fini, 3650 .suspend = psp_suspend, 3651 .resume = psp_resume, 3652 .is_idle = NULL, 3653 .check_soft_reset = NULL, 3654 .wait_for_idle = NULL, 3655 .soft_reset = NULL, 3656 .set_clockgating_state = psp_set_clockgating_state, 3657 .set_powergating_state = psp_set_powergating_state, 3658 }; 3659 3660 static int psp_sysfs_init(struct amdgpu_device *adev) 3661 { 3662 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3663 3664 if (ret) 3665 DRM_ERROR("Failed to create USBC PD FW control file!"); 3666 3667 return ret; 3668 } 3669 3670 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev) 3671 { 3672 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3673 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status); 3674 } 3675 3676 static void psp_sysfs_fini(struct amdgpu_device *adev) 3677 { 3678 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3679 } 3680 3681 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3682 { 3683 .type = AMD_IP_BLOCK_TYPE_PSP, 3684 .major = 3, 3685 .minor = 1, 3686 .rev = 0, 3687 .funcs = &psp_ip_funcs, 3688 }; 3689 3690 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3691 { 3692 .type = AMD_IP_BLOCK_TYPE_PSP, 3693 .major = 10, 3694 .minor = 0, 3695 .rev = 0, 3696 .funcs = &psp_ip_funcs, 3697 }; 3698 3699 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3700 { 3701 .type = AMD_IP_BLOCK_TYPE_PSP, 3702 .major = 11, 3703 .minor = 0, 3704 .rev = 0, 3705 .funcs = &psp_ip_funcs, 3706 }; 3707 3708 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3709 .type = AMD_IP_BLOCK_TYPE_PSP, 3710 .major = 11, 3711 .minor = 0, 3712 .rev = 8, 3713 .funcs = &psp_ip_funcs, 3714 }; 3715 3716 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3717 { 3718 .type = AMD_IP_BLOCK_TYPE_PSP, 3719 .major = 12, 3720 .minor = 0, 3721 .rev = 0, 3722 .funcs = &psp_ip_funcs, 3723 }; 3724 3725 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3726 .type = AMD_IP_BLOCK_TYPE_PSP, 3727 .major = 13, 3728 .minor = 0, 3729 .rev = 0, 3730 .funcs = &psp_ip_funcs, 3731 }; 3732 3733 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3734 .type = AMD_IP_BLOCK_TYPE_PSP, 3735 .major = 13, 3736 .minor = 0, 3737 .rev = 4, 3738 .funcs = &psp_ip_funcs, 3739 }; 3740