1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/dma-mapping.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v3_1.h" 34 #include "psp_v10_0.h" 35 #include "psp_v11_0.h" 36 #include "psp_v12_0.h" 37 #include "psp_v13_0.h" 38 39 #include "amdgpu_ras.h" 40 #include "amdgpu_securedisplay.h" 41 42 static int psp_sysfs_init(struct amdgpu_device *adev); 43 static void psp_sysfs_fini(struct amdgpu_device *adev); 44 45 static int psp_load_smu_fw(struct psp_context *psp); 46 47 /* 48 * Due to DF Cstate management centralized to PMFW, the firmware 49 * loading sequence will be updated as below: 50 * - Load KDB 51 * - Load SYS_DRV 52 * - Load tOS 53 * - Load PMFW 54 * - Setup TMR 55 * - Load other non-psp fw 56 * - Load ASD 57 * - Load XGMI/RAS/HDCP/DTM TA if any 58 * 59 * This new sequence is required for 60 * - Arcturus and onwards 61 * - Navi12 and onwards 62 */ 63 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 64 { 65 struct amdgpu_device *adev = psp->adev; 66 67 psp->pmfw_centralized_cstate_management = false; 68 69 if (amdgpu_sriov_vf(adev)) 70 return; 71 72 if (adev->flags & AMD_IS_APU) 73 return; 74 75 if ((adev->asic_type >= CHIP_ARCTURUS) || 76 (adev->asic_type >= CHIP_NAVI12)) 77 psp->pmfw_centralized_cstate_management = true; 78 } 79 80 static int psp_early_init(void *handle) 81 { 82 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 83 struct psp_context *psp = &adev->psp; 84 85 switch (adev->asic_type) { 86 case CHIP_VEGA10: 87 case CHIP_VEGA12: 88 psp_v3_1_set_psp_funcs(psp); 89 psp->autoload_supported = false; 90 break; 91 case CHIP_RAVEN: 92 psp_v10_0_set_psp_funcs(psp); 93 psp->autoload_supported = false; 94 break; 95 case CHIP_VEGA20: 96 case CHIP_ARCTURUS: 97 psp_v11_0_set_psp_funcs(psp); 98 psp->autoload_supported = false; 99 break; 100 case CHIP_NAVI10: 101 case CHIP_NAVI14: 102 case CHIP_NAVI12: 103 case CHIP_SIENNA_CICHLID: 104 case CHIP_NAVY_FLOUNDER: 105 case CHIP_VANGOGH: 106 case CHIP_DIMGREY_CAVEFISH: 107 psp_v11_0_set_psp_funcs(psp); 108 psp->autoload_supported = true; 109 break; 110 case CHIP_RENOIR: 111 psp_v12_0_set_psp_funcs(psp); 112 break; 113 case CHIP_ALDEBARAN: 114 psp_v13_0_set_psp_funcs(psp); 115 break; 116 default: 117 return -EINVAL; 118 } 119 120 psp->adev = adev; 121 122 psp_check_pmfw_centralized_cstate_management(psp); 123 124 return 0; 125 } 126 127 static void psp_memory_training_fini(struct psp_context *psp) 128 { 129 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 130 131 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 132 kfree(ctx->sys_cache); 133 ctx->sys_cache = NULL; 134 } 135 136 static int psp_memory_training_init(struct psp_context *psp) 137 { 138 int ret; 139 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 140 141 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 142 DRM_DEBUG("memory training is not supported!\n"); 143 return 0; 144 } 145 146 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 147 if (ctx->sys_cache == NULL) { 148 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 149 ret = -ENOMEM; 150 goto Err_out; 151 } 152 153 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 154 ctx->train_data_size, 155 ctx->p2c_train_data_offset, 156 ctx->c2p_train_data_offset); 157 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 158 return 0; 159 160 Err_out: 161 psp_memory_training_fini(psp); 162 return ret; 163 } 164 165 static int psp_sw_init(void *handle) 166 { 167 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 168 struct psp_context *psp = &adev->psp; 169 int ret; 170 171 if (!amdgpu_sriov_vf(adev)) { 172 ret = psp_init_microcode(psp); 173 if (ret) { 174 DRM_ERROR("Failed to load psp firmware!\n"); 175 return ret; 176 } 177 } 178 179 ret = psp_memory_training_init(psp); 180 if (ret) { 181 DRM_ERROR("Failed to initialize memory training!\n"); 182 return ret; 183 } 184 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 185 if (ret) { 186 DRM_ERROR("Failed to process memory training!\n"); 187 return ret; 188 } 189 190 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 191 ret= psp_sysfs_init(adev); 192 if (ret) { 193 return ret; 194 } 195 } 196 197 return 0; 198 } 199 200 static int psp_sw_fini(void *handle) 201 { 202 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 203 204 psp_memory_training_fini(&adev->psp); 205 if (adev->psp.sos_fw) { 206 release_firmware(adev->psp.sos_fw); 207 adev->psp.sos_fw = NULL; 208 } 209 if (adev->psp.asd_fw) { 210 release_firmware(adev->psp.asd_fw); 211 adev->psp.asd_fw = NULL; 212 } 213 if (adev->psp.ta_fw) { 214 release_firmware(adev->psp.ta_fw); 215 adev->psp.ta_fw = NULL; 216 } 217 218 if (adev->asic_type == CHIP_NAVI10 || 219 adev->asic_type == CHIP_SIENNA_CICHLID) 220 psp_sysfs_fini(adev); 221 222 return 0; 223 } 224 225 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 226 uint32_t reg_val, uint32_t mask, bool check_changed) 227 { 228 uint32_t val; 229 int i; 230 struct amdgpu_device *adev = psp->adev; 231 232 if (psp->adev->in_pci_err_recovery) 233 return 0; 234 235 for (i = 0; i < adev->usec_timeout; i++) { 236 val = RREG32(reg_index); 237 if (check_changed) { 238 if (val != reg_val) 239 return 0; 240 } else { 241 if ((val & mask) == reg_val) 242 return 0; 243 } 244 udelay(1); 245 } 246 247 return -ETIME; 248 } 249 250 static int 251 psp_cmd_submit_buf(struct psp_context *psp, 252 struct amdgpu_firmware_info *ucode, 253 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 254 { 255 int ret; 256 int index; 257 int timeout = 20000; 258 bool ras_intr = false; 259 bool skip_unsupport = false; 260 261 if (psp->adev->in_pci_err_recovery) 262 return 0; 263 264 mutex_lock(&psp->mutex); 265 266 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 267 268 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 269 270 index = atomic_inc_return(&psp->fence_value); 271 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 272 if (ret) { 273 atomic_dec(&psp->fence_value); 274 mutex_unlock(&psp->mutex); 275 return ret; 276 } 277 278 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 279 while (*((unsigned int *)psp->fence_buf) != index) { 280 if (--timeout == 0) 281 break; 282 /* 283 * Shouldn't wait for timeout when err_event_athub occurs, 284 * because gpu reset thread triggered and lock resource should 285 * be released for psp resume sequence. 286 */ 287 ras_intr = amdgpu_ras_intr_triggered(); 288 if (ras_intr) 289 break; 290 usleep_range(10, 100); 291 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 292 } 293 294 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 295 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 296 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 297 298 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 299 300 /* In some cases, psp response status is not 0 even there is no 301 * problem while the command is submitted. Some version of PSP FW 302 * doesn't write 0 to that field. 303 * So here we would like to only print a warning instead of an error 304 * during psp initialization to avoid breaking hw_init and it doesn't 305 * return -EINVAL. 306 */ 307 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 308 if (ucode) 309 DRM_WARN("failed to load ucode id (%d) ", 310 ucode->ucode_id); 311 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n", 312 psp->cmd_buf_mem->cmd_id, 313 psp->cmd_buf_mem->resp.status); 314 if (!timeout) { 315 mutex_unlock(&psp->mutex); 316 return -EINVAL; 317 } 318 } 319 320 if (ucode) { 321 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 322 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 323 } 324 mutex_unlock(&psp->mutex); 325 326 return ret; 327 } 328 329 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 330 struct psp_gfx_cmd_resp *cmd, 331 uint64_t tmr_mc, uint32_t size) 332 { 333 if (amdgpu_sriov_vf(psp->adev)) 334 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 335 else 336 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 337 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 338 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 339 cmd->cmd.cmd_setup_tmr.buf_size = size; 340 } 341 342 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 343 uint64_t pri_buf_mc, uint32_t size) 344 { 345 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 346 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 347 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 348 cmd->cmd.cmd_load_toc.toc_size = size; 349 } 350 351 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 352 static int psp_load_toc(struct psp_context *psp, 353 uint32_t *tmr_size) 354 { 355 int ret; 356 struct psp_gfx_cmd_resp *cmd; 357 358 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 359 if (!cmd) 360 return -ENOMEM; 361 /* Copy toc to psp firmware private buffer */ 362 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 363 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size); 364 365 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 366 367 ret = psp_cmd_submit_buf(psp, NULL, cmd, 368 psp->fence_buf_mc_addr); 369 if (!ret) 370 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 371 kfree(cmd); 372 return ret; 373 } 374 375 /* Set up Trusted Memory Region */ 376 static int psp_tmr_init(struct psp_context *psp) 377 { 378 int ret; 379 int tmr_size; 380 void *tmr_buf; 381 void **pptr; 382 383 /* 384 * According to HW engineer, they prefer the TMR address be "naturally 385 * aligned" , e.g. the start address be an integer divide of TMR size. 386 * 387 * Note: this memory need be reserved till the driver 388 * uninitializes. 389 */ 390 tmr_size = PSP_TMR_SIZE(psp->adev); 391 392 /* For ASICs support RLC autoload, psp will parse the toc 393 * and calculate the total size of TMR needed */ 394 if (!amdgpu_sriov_vf(psp->adev) && 395 psp->toc_start_addr && 396 psp->toc_bin_size && 397 psp->fw_pri_buf) { 398 ret = psp_load_toc(psp, &tmr_size); 399 if (ret) { 400 DRM_ERROR("Failed to load toc\n"); 401 return ret; 402 } 403 } 404 405 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 406 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 407 AMDGPU_GEM_DOMAIN_VRAM, 408 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 409 410 /* workaround the tmr_mc_addr: 411 * PSP requires an address in FB aperture. Right now driver produce 412 * tmr_mc_addr in the GART aperture. Convert it back to FB aperture 413 * for PSP. Will revert it after we get a fix from PSP FW. 414 */ 415 if (psp->adev->asic_type == CHIP_ALDEBARAN) { 416 psp->tmr_mc_addr -= psp->adev->gmc.fb_start; 417 psp->tmr_mc_addr += psp->adev->gmc.fb_start_original; 418 } 419 420 return ret; 421 } 422 423 static int psp_clear_vf_fw(struct psp_context *psp) 424 { 425 int ret; 426 struct psp_gfx_cmd_resp *cmd; 427 428 if (!amdgpu_sriov_vf(psp->adev) || psp->adev->asic_type != CHIP_NAVI12) 429 return 0; 430 431 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 432 if (!cmd) 433 return -ENOMEM; 434 435 cmd->cmd_id = GFX_CMD_ID_CLEAR_VF_FW; 436 437 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 438 kfree(cmd); 439 440 return ret; 441 } 442 443 static bool psp_skip_tmr(struct psp_context *psp) 444 { 445 switch (psp->adev->asic_type) { 446 case CHIP_NAVI12: 447 case CHIP_SIENNA_CICHLID: 448 return true; 449 default: 450 return false; 451 } 452 } 453 454 static int psp_tmr_load(struct psp_context *psp) 455 { 456 int ret; 457 struct psp_gfx_cmd_resp *cmd; 458 459 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 460 * Already set up by host driver. 461 */ 462 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 463 return 0; 464 465 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 466 if (!cmd) 467 return -ENOMEM; 468 469 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, 470 amdgpu_bo_size(psp->tmr_bo)); 471 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 472 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 473 474 ret = psp_cmd_submit_buf(psp, NULL, cmd, 475 psp->fence_buf_mc_addr); 476 477 kfree(cmd); 478 479 return ret; 480 } 481 482 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 483 struct psp_gfx_cmd_resp *cmd) 484 { 485 if (amdgpu_sriov_vf(psp->adev)) 486 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 487 else 488 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 489 } 490 491 static int psp_tmr_unload(struct psp_context *psp) 492 { 493 int ret; 494 struct psp_gfx_cmd_resp *cmd; 495 496 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 497 if (!cmd) 498 return -ENOMEM; 499 500 psp_prep_tmr_unload_cmd_buf(psp, cmd); 501 DRM_INFO("free PSP TMR buffer\n"); 502 503 ret = psp_cmd_submit_buf(psp, NULL, cmd, 504 psp->fence_buf_mc_addr); 505 506 kfree(cmd); 507 508 return ret; 509 } 510 511 static int psp_tmr_terminate(struct psp_context *psp) 512 { 513 int ret; 514 void *tmr_buf; 515 void **pptr; 516 517 ret = psp_tmr_unload(psp); 518 if (ret) 519 return ret; 520 521 /* free TMR memory buffer */ 522 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 523 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 524 525 return 0; 526 } 527 528 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 529 uint64_t *output_ptr) 530 { 531 int ret; 532 struct psp_gfx_cmd_resp *cmd; 533 534 if (!output_ptr) 535 return -EINVAL; 536 537 if (amdgpu_sriov_vf(psp->adev)) 538 return 0; 539 540 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 541 if (!cmd) 542 return -ENOMEM; 543 544 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 545 546 ret = psp_cmd_submit_buf(psp, NULL, cmd, 547 psp->fence_buf_mc_addr); 548 549 if (!ret) { 550 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 551 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 552 } 553 554 kfree(cmd); 555 556 return ret; 557 } 558 559 static int psp_rl_load(struct amdgpu_device *adev) 560 { 561 struct psp_context *psp = &adev->psp; 562 struct psp_gfx_cmd_resp *cmd = psp->cmd; 563 564 if (psp->rl_bin_size == 0) 565 return 0; 566 567 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 568 memcpy(psp->fw_pri_buf, psp->rl_start_addr, psp->rl_bin_size); 569 570 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 571 572 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 573 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 574 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 575 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl_bin_size; 576 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 577 578 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 579 } 580 581 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 582 uint64_t asd_mc, uint32_t size) 583 { 584 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 585 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 586 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 587 cmd->cmd.cmd_load_ta.app_len = size; 588 589 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 590 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 591 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 592 } 593 594 static int psp_asd_load(struct psp_context *psp) 595 { 596 int ret; 597 struct psp_gfx_cmd_resp *cmd; 598 599 /* If PSP version doesn't match ASD version, asd loading will be failed. 600 * add workaround to bypass it for sriov now. 601 * TODO: add version check to make it common 602 */ 603 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size) 604 return 0; 605 606 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 607 if (!cmd) 608 return -ENOMEM; 609 610 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 611 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 612 613 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 614 psp->asd_ucode_size); 615 616 ret = psp_cmd_submit_buf(psp, NULL, cmd, 617 psp->fence_buf_mc_addr); 618 if (!ret) { 619 psp->asd_context.asd_initialized = true; 620 psp->asd_context.session_id = cmd->resp.session_id; 621 } 622 623 kfree(cmd); 624 625 return ret; 626 } 627 628 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 629 uint32_t session_id) 630 { 631 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 632 cmd->cmd.cmd_unload_ta.session_id = session_id; 633 } 634 635 static int psp_asd_unload(struct psp_context *psp) 636 { 637 int ret; 638 struct psp_gfx_cmd_resp *cmd; 639 640 if (amdgpu_sriov_vf(psp->adev)) 641 return 0; 642 643 if (!psp->asd_context.asd_initialized) 644 return 0; 645 646 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 647 if (!cmd) 648 return -ENOMEM; 649 650 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 651 652 ret = psp_cmd_submit_buf(psp, NULL, cmd, 653 psp->fence_buf_mc_addr); 654 if (!ret) 655 psp->asd_context.asd_initialized = false; 656 657 kfree(cmd); 658 659 return ret; 660 } 661 662 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 663 uint32_t id, uint32_t value) 664 { 665 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 666 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 667 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 668 } 669 670 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 671 uint32_t value) 672 { 673 struct psp_gfx_cmd_resp *cmd = NULL; 674 int ret = 0; 675 676 if (reg >= PSP_REG_LAST) 677 return -EINVAL; 678 679 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 680 if (!cmd) 681 return -ENOMEM; 682 683 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 684 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 685 686 kfree(cmd); 687 return ret; 688 } 689 690 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 691 uint64_t ta_bin_mc, 692 uint32_t ta_bin_size, 693 uint64_t ta_shared_mc, 694 uint32_t ta_shared_size) 695 { 696 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 697 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 698 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 699 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 700 701 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 702 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 703 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 704 } 705 706 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 707 { 708 int ret; 709 710 /* 711 * Allocate 16k memory aligned to 4k from Frame Buffer (local 712 * physical) for xgmi ta <-> Driver 713 */ 714 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 715 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 716 &psp->xgmi_context.xgmi_shared_bo, 717 &psp->xgmi_context.xgmi_shared_mc_addr, 718 &psp->xgmi_context.xgmi_shared_buf); 719 720 return ret; 721 } 722 723 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 724 uint32_t ta_cmd_id, 725 uint32_t session_id) 726 { 727 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 728 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 729 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 730 } 731 732 static int psp_ta_invoke(struct psp_context *psp, 733 uint32_t ta_cmd_id, 734 uint32_t session_id) 735 { 736 int ret; 737 struct psp_gfx_cmd_resp *cmd; 738 739 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 740 if (!cmd) 741 return -ENOMEM; 742 743 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 744 745 ret = psp_cmd_submit_buf(psp, NULL, cmd, 746 psp->fence_buf_mc_addr); 747 748 kfree(cmd); 749 750 return ret; 751 } 752 753 static int psp_xgmi_load(struct psp_context *psp) 754 { 755 int ret; 756 struct psp_gfx_cmd_resp *cmd; 757 758 /* 759 * TODO: bypass the loading in sriov for now 760 */ 761 762 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 763 if (!cmd) 764 return -ENOMEM; 765 766 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 767 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 768 769 psp_prep_ta_load_cmd_buf(cmd, 770 psp->fw_pri_mc_addr, 771 psp->ta_xgmi_ucode_size, 772 psp->xgmi_context.xgmi_shared_mc_addr, 773 PSP_XGMI_SHARED_MEM_SIZE); 774 775 ret = psp_cmd_submit_buf(psp, NULL, cmd, 776 psp->fence_buf_mc_addr); 777 778 if (!ret) { 779 psp->xgmi_context.initialized = 1; 780 psp->xgmi_context.session_id = cmd->resp.session_id; 781 } 782 783 kfree(cmd); 784 785 return ret; 786 } 787 788 static int psp_xgmi_unload(struct psp_context *psp) 789 { 790 int ret; 791 struct psp_gfx_cmd_resp *cmd; 792 struct amdgpu_device *adev = psp->adev; 793 794 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 795 if (adev->asic_type == CHIP_ARCTURUS || 796 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu)) 797 return 0; 798 799 /* 800 * TODO: bypass the unloading in sriov for now 801 */ 802 803 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 804 if (!cmd) 805 return -ENOMEM; 806 807 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 808 809 ret = psp_cmd_submit_buf(psp, NULL, cmd, 810 psp->fence_buf_mc_addr); 811 812 kfree(cmd); 813 814 return ret; 815 } 816 817 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 818 { 819 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 820 } 821 822 int psp_xgmi_terminate(struct psp_context *psp) 823 { 824 int ret; 825 826 if (!psp->xgmi_context.initialized) 827 return 0; 828 829 ret = psp_xgmi_unload(psp); 830 if (ret) 831 return ret; 832 833 psp->xgmi_context.initialized = 0; 834 835 /* free xgmi shared memory */ 836 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 837 &psp->xgmi_context.xgmi_shared_mc_addr, 838 &psp->xgmi_context.xgmi_shared_buf); 839 840 return 0; 841 } 842 843 int psp_xgmi_initialize(struct psp_context *psp) 844 { 845 struct ta_xgmi_shared_memory *xgmi_cmd; 846 int ret; 847 848 if (!psp->adev->psp.ta_fw || 849 !psp->adev->psp.ta_xgmi_ucode_size || 850 !psp->adev->psp.ta_xgmi_start_addr) 851 return -ENOENT; 852 853 if (!psp->xgmi_context.initialized) { 854 ret = psp_xgmi_init_shared_buf(psp); 855 if (ret) 856 return ret; 857 } 858 859 /* Load XGMI TA */ 860 ret = psp_xgmi_load(psp); 861 if (ret) 862 return ret; 863 864 /* Initialize XGMI session */ 865 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 866 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 867 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 868 869 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 870 871 return ret; 872 } 873 874 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 875 { 876 struct ta_xgmi_shared_memory *xgmi_cmd; 877 int ret; 878 879 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 880 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 881 882 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 883 884 /* Invoke xgmi ta to get hive id */ 885 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 886 if (ret) 887 return ret; 888 889 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 890 891 return 0; 892 } 893 894 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 895 { 896 struct ta_xgmi_shared_memory *xgmi_cmd; 897 int ret; 898 899 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 900 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 901 902 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 903 904 /* Invoke xgmi ta to get the node id */ 905 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 906 if (ret) 907 return ret; 908 909 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 910 911 return 0; 912 } 913 914 int psp_xgmi_get_topology_info(struct psp_context *psp, 915 int number_devices, 916 struct psp_xgmi_topology_info *topology) 917 { 918 struct ta_xgmi_shared_memory *xgmi_cmd; 919 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 920 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 921 int i; 922 int ret; 923 924 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 925 return -EINVAL; 926 927 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 928 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 929 930 /* Fill in the shared memory with topology information as input */ 931 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 932 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 933 topology_info_input->num_nodes = number_devices; 934 935 for (i = 0; i < topology_info_input->num_nodes; i++) { 936 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 937 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 938 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 939 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 940 } 941 942 /* Invoke xgmi ta to get the topology information */ 943 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 944 if (ret) 945 return ret; 946 947 /* Read the output topology information from the shared memory */ 948 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 949 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 950 for (i = 0; i < topology->num_nodes; i++) { 951 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 952 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 953 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 954 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 955 } 956 957 return 0; 958 } 959 960 int psp_xgmi_set_topology_info(struct psp_context *psp, 961 int number_devices, 962 struct psp_xgmi_topology_info *topology) 963 { 964 struct ta_xgmi_shared_memory *xgmi_cmd; 965 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 966 int i; 967 968 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 969 return -EINVAL; 970 971 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 972 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 973 974 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 975 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 976 topology_info_input->num_nodes = number_devices; 977 978 for (i = 0; i < topology_info_input->num_nodes; i++) { 979 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 980 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 981 topology_info_input->nodes[i].is_sharing_enabled = 1; 982 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 983 } 984 985 /* Invoke xgmi ta to set topology information */ 986 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 987 } 988 989 // ras begin 990 static int psp_ras_init_shared_buf(struct psp_context *psp) 991 { 992 int ret; 993 994 /* 995 * Allocate 16k memory aligned to 4k from Frame Buffer (local 996 * physical) for ras ta <-> Driver 997 */ 998 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 999 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1000 &psp->ras.ras_shared_bo, 1001 &psp->ras.ras_shared_mc_addr, 1002 &psp->ras.ras_shared_buf); 1003 1004 return ret; 1005 } 1006 1007 static int psp_ras_load(struct psp_context *psp) 1008 { 1009 int ret; 1010 struct psp_gfx_cmd_resp *cmd; 1011 struct ta_ras_shared_memory *ras_cmd; 1012 1013 /* 1014 * TODO: bypass the loading in sriov for now 1015 */ 1016 if (amdgpu_sriov_vf(psp->adev)) 1017 return 0; 1018 1019 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1020 if (!cmd) 1021 return -ENOMEM; 1022 1023 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1024 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 1025 1026 psp_prep_ta_load_cmd_buf(cmd, 1027 psp->fw_pri_mc_addr, 1028 psp->ta_ras_ucode_size, 1029 psp->ras.ras_shared_mc_addr, 1030 PSP_RAS_SHARED_MEM_SIZE); 1031 1032 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1033 psp->fence_buf_mc_addr); 1034 1035 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1036 1037 if (!ret) { 1038 psp->ras.session_id = cmd->resp.session_id; 1039 1040 if (!ras_cmd->ras_status) 1041 psp->ras.ras_initialized = true; 1042 else 1043 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1044 } 1045 1046 if (ret || ras_cmd->ras_status) 1047 amdgpu_ras_fini(psp->adev); 1048 1049 kfree(cmd); 1050 1051 return ret; 1052 } 1053 1054 static int psp_ras_unload(struct psp_context *psp) 1055 { 1056 int ret; 1057 struct psp_gfx_cmd_resp *cmd; 1058 1059 /* 1060 * TODO: bypass the unloading in sriov for now 1061 */ 1062 if (amdgpu_sriov_vf(psp->adev)) 1063 return 0; 1064 1065 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1066 if (!cmd) 1067 return -ENOMEM; 1068 1069 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 1070 1071 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1072 psp->fence_buf_mc_addr); 1073 1074 kfree(cmd); 1075 1076 return ret; 1077 } 1078 1079 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1080 { 1081 struct ta_ras_shared_memory *ras_cmd; 1082 int ret; 1083 1084 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1085 1086 /* 1087 * TODO: bypass the loading in sriov for now 1088 */ 1089 if (amdgpu_sriov_vf(psp->adev)) 1090 return 0; 1091 1092 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 1093 1094 if (amdgpu_ras_intr_triggered()) 1095 return ret; 1096 1097 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1098 { 1099 DRM_WARN("RAS: Unsupported Interface"); 1100 return -EINVAL; 1101 } 1102 1103 if (!ret) { 1104 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1105 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1106 1107 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1108 } 1109 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1110 dev_warn(psp->adev->dev, 1111 "RAS internal register access blocked\n"); 1112 } 1113 1114 return ret; 1115 } 1116 1117 int psp_ras_enable_features(struct psp_context *psp, 1118 union ta_ras_cmd_input *info, bool enable) 1119 { 1120 struct ta_ras_shared_memory *ras_cmd; 1121 int ret; 1122 1123 if (!psp->ras.ras_initialized) 1124 return -EINVAL; 1125 1126 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1127 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1128 1129 if (enable) 1130 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1131 else 1132 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1133 1134 ras_cmd->ras_in_message = *info; 1135 1136 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1137 if (ret) 1138 return -EINVAL; 1139 1140 return ras_cmd->ras_status; 1141 } 1142 1143 static int psp_ras_terminate(struct psp_context *psp) 1144 { 1145 int ret; 1146 1147 /* 1148 * TODO: bypass the terminate in sriov for now 1149 */ 1150 if (amdgpu_sriov_vf(psp->adev)) 1151 return 0; 1152 1153 if (!psp->ras.ras_initialized) 1154 return 0; 1155 1156 ret = psp_ras_unload(psp); 1157 if (ret) 1158 return ret; 1159 1160 psp->ras.ras_initialized = false; 1161 1162 /* free ras shared memory */ 1163 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1164 &psp->ras.ras_shared_mc_addr, 1165 &psp->ras.ras_shared_buf); 1166 1167 return 0; 1168 } 1169 1170 static int psp_ras_initialize(struct psp_context *psp) 1171 { 1172 int ret; 1173 1174 /* 1175 * TODO: bypass the initialize in sriov for now 1176 */ 1177 if (amdgpu_sriov_vf(psp->adev)) 1178 return 0; 1179 1180 if (!psp->adev->psp.ta_ras_ucode_size || 1181 !psp->adev->psp.ta_ras_start_addr) { 1182 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n"); 1183 return 0; 1184 } 1185 1186 if (!psp->ras.ras_initialized) { 1187 ret = psp_ras_init_shared_buf(psp); 1188 if (ret) 1189 return ret; 1190 } 1191 1192 ret = psp_ras_load(psp); 1193 if (ret) 1194 return ret; 1195 1196 return 0; 1197 } 1198 1199 int psp_ras_trigger_error(struct psp_context *psp, 1200 struct ta_ras_trigger_error_input *info) 1201 { 1202 struct ta_ras_shared_memory *ras_cmd; 1203 int ret; 1204 1205 if (!psp->ras.ras_initialized) 1206 return -EINVAL; 1207 1208 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1209 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1210 1211 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1212 ras_cmd->ras_in_message.trigger_error = *info; 1213 1214 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1215 if (ret) 1216 return -EINVAL; 1217 1218 /* If err_event_athub occurs error inject was successful, however 1219 return status from TA is no long reliable */ 1220 if (amdgpu_ras_intr_triggered()) 1221 return 0; 1222 1223 return ras_cmd->ras_status; 1224 } 1225 // ras end 1226 1227 // HDCP start 1228 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1229 { 1230 int ret; 1231 1232 /* 1233 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1234 * physical) for hdcp ta <-> Driver 1235 */ 1236 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1237 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1238 &psp->hdcp_context.hdcp_shared_bo, 1239 &psp->hdcp_context.hdcp_shared_mc_addr, 1240 &psp->hdcp_context.hdcp_shared_buf); 1241 1242 return ret; 1243 } 1244 1245 static int psp_hdcp_load(struct psp_context *psp) 1246 { 1247 int ret; 1248 struct psp_gfx_cmd_resp *cmd; 1249 1250 /* 1251 * TODO: bypass the loading in sriov for now 1252 */ 1253 if (amdgpu_sriov_vf(psp->adev)) 1254 return 0; 1255 1256 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1257 if (!cmd) 1258 return -ENOMEM; 1259 1260 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1261 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr, 1262 psp->ta_hdcp_ucode_size); 1263 1264 psp_prep_ta_load_cmd_buf(cmd, 1265 psp->fw_pri_mc_addr, 1266 psp->ta_hdcp_ucode_size, 1267 psp->hdcp_context.hdcp_shared_mc_addr, 1268 PSP_HDCP_SHARED_MEM_SIZE); 1269 1270 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1271 1272 if (!ret) { 1273 psp->hdcp_context.hdcp_initialized = true; 1274 psp->hdcp_context.session_id = cmd->resp.session_id; 1275 mutex_init(&psp->hdcp_context.mutex); 1276 } 1277 1278 kfree(cmd); 1279 1280 return ret; 1281 } 1282 static int psp_hdcp_initialize(struct psp_context *psp) 1283 { 1284 int ret; 1285 1286 /* 1287 * TODO: bypass the initialize in sriov for now 1288 */ 1289 if (amdgpu_sriov_vf(psp->adev)) 1290 return 0; 1291 1292 if (!psp->adev->psp.ta_hdcp_ucode_size || 1293 !psp->adev->psp.ta_hdcp_start_addr) { 1294 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1295 return 0; 1296 } 1297 1298 if (!psp->hdcp_context.hdcp_initialized) { 1299 ret = psp_hdcp_init_shared_buf(psp); 1300 if (ret) 1301 return ret; 1302 } 1303 1304 ret = psp_hdcp_load(psp); 1305 if (ret) 1306 return ret; 1307 1308 return 0; 1309 } 1310 1311 static int psp_hdcp_unload(struct psp_context *psp) 1312 { 1313 int ret; 1314 struct psp_gfx_cmd_resp *cmd; 1315 1316 /* 1317 * TODO: bypass the unloading in sriov for now 1318 */ 1319 if (amdgpu_sriov_vf(psp->adev)) 1320 return 0; 1321 1322 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1323 if (!cmd) 1324 return -ENOMEM; 1325 1326 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1327 1328 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1329 1330 kfree(cmd); 1331 1332 return ret; 1333 } 1334 1335 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1336 { 1337 /* 1338 * TODO: bypass the loading in sriov for now 1339 */ 1340 if (amdgpu_sriov_vf(psp->adev)) 1341 return 0; 1342 1343 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1344 } 1345 1346 static int psp_hdcp_terminate(struct psp_context *psp) 1347 { 1348 int ret; 1349 1350 /* 1351 * TODO: bypass the terminate in sriov for now 1352 */ 1353 if (amdgpu_sriov_vf(psp->adev)) 1354 return 0; 1355 1356 if (!psp->hdcp_context.hdcp_initialized) { 1357 if (psp->hdcp_context.hdcp_shared_buf) 1358 goto out; 1359 else 1360 return 0; 1361 } 1362 1363 ret = psp_hdcp_unload(psp); 1364 if (ret) 1365 return ret; 1366 1367 psp->hdcp_context.hdcp_initialized = false; 1368 1369 out: 1370 /* free hdcp shared memory */ 1371 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1372 &psp->hdcp_context.hdcp_shared_mc_addr, 1373 &psp->hdcp_context.hdcp_shared_buf); 1374 1375 return 0; 1376 } 1377 // HDCP end 1378 1379 // DTM start 1380 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1381 { 1382 int ret; 1383 1384 /* 1385 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1386 * physical) for dtm ta <-> Driver 1387 */ 1388 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1389 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1390 &psp->dtm_context.dtm_shared_bo, 1391 &psp->dtm_context.dtm_shared_mc_addr, 1392 &psp->dtm_context.dtm_shared_buf); 1393 1394 return ret; 1395 } 1396 1397 static int psp_dtm_load(struct psp_context *psp) 1398 { 1399 int ret; 1400 struct psp_gfx_cmd_resp *cmd; 1401 1402 /* 1403 * TODO: bypass the loading in sriov for now 1404 */ 1405 if (amdgpu_sriov_vf(psp->adev)) 1406 return 0; 1407 1408 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1409 if (!cmd) 1410 return -ENOMEM; 1411 1412 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1413 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1414 1415 psp_prep_ta_load_cmd_buf(cmd, 1416 psp->fw_pri_mc_addr, 1417 psp->ta_dtm_ucode_size, 1418 psp->dtm_context.dtm_shared_mc_addr, 1419 PSP_DTM_SHARED_MEM_SIZE); 1420 1421 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1422 1423 if (!ret) { 1424 psp->dtm_context.dtm_initialized = true; 1425 psp->dtm_context.session_id = cmd->resp.session_id; 1426 mutex_init(&psp->dtm_context.mutex); 1427 } 1428 1429 kfree(cmd); 1430 1431 return ret; 1432 } 1433 1434 static int psp_dtm_initialize(struct psp_context *psp) 1435 { 1436 int ret; 1437 1438 /* 1439 * TODO: bypass the initialize in sriov for now 1440 */ 1441 if (amdgpu_sriov_vf(psp->adev)) 1442 return 0; 1443 1444 if (!psp->adev->psp.ta_dtm_ucode_size || 1445 !psp->adev->psp.ta_dtm_start_addr) { 1446 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1447 return 0; 1448 } 1449 1450 if (!psp->dtm_context.dtm_initialized) { 1451 ret = psp_dtm_init_shared_buf(psp); 1452 if (ret) 1453 return ret; 1454 } 1455 1456 ret = psp_dtm_load(psp); 1457 if (ret) 1458 return ret; 1459 1460 return 0; 1461 } 1462 1463 static int psp_dtm_unload(struct psp_context *psp) 1464 { 1465 int ret; 1466 struct psp_gfx_cmd_resp *cmd; 1467 1468 /* 1469 * TODO: bypass the unloading in sriov for now 1470 */ 1471 if (amdgpu_sriov_vf(psp->adev)) 1472 return 0; 1473 1474 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1475 if (!cmd) 1476 return -ENOMEM; 1477 1478 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1479 1480 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1481 1482 kfree(cmd); 1483 1484 return ret; 1485 } 1486 1487 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1488 { 1489 /* 1490 * TODO: bypass the loading in sriov for now 1491 */ 1492 if (amdgpu_sriov_vf(psp->adev)) 1493 return 0; 1494 1495 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1496 } 1497 1498 static int psp_dtm_terminate(struct psp_context *psp) 1499 { 1500 int ret; 1501 1502 /* 1503 * TODO: bypass the terminate in sriov for now 1504 */ 1505 if (amdgpu_sriov_vf(psp->adev)) 1506 return 0; 1507 1508 if (!psp->dtm_context.dtm_initialized) { 1509 if (psp->dtm_context.dtm_shared_buf) 1510 goto out; 1511 else 1512 return 0; 1513 } 1514 1515 ret = psp_dtm_unload(psp); 1516 if (ret) 1517 return ret; 1518 1519 psp->dtm_context.dtm_initialized = false; 1520 1521 out: 1522 /* free hdcp shared memory */ 1523 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1524 &psp->dtm_context.dtm_shared_mc_addr, 1525 &psp->dtm_context.dtm_shared_buf); 1526 1527 return 0; 1528 } 1529 // DTM end 1530 1531 // RAP start 1532 static int psp_rap_init_shared_buf(struct psp_context *psp) 1533 { 1534 int ret; 1535 1536 /* 1537 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1538 * physical) for rap ta <-> Driver 1539 */ 1540 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE, 1541 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1542 &psp->rap_context.rap_shared_bo, 1543 &psp->rap_context.rap_shared_mc_addr, 1544 &psp->rap_context.rap_shared_buf); 1545 1546 return ret; 1547 } 1548 1549 static int psp_rap_load(struct psp_context *psp) 1550 { 1551 int ret; 1552 struct psp_gfx_cmd_resp *cmd; 1553 1554 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1555 if (!cmd) 1556 return -ENOMEM; 1557 1558 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1559 memcpy(psp->fw_pri_buf, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); 1560 1561 psp_prep_ta_load_cmd_buf(cmd, 1562 psp->fw_pri_mc_addr, 1563 psp->ta_rap_ucode_size, 1564 psp->rap_context.rap_shared_mc_addr, 1565 PSP_RAP_SHARED_MEM_SIZE); 1566 1567 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1568 1569 if (!ret) { 1570 psp->rap_context.rap_initialized = true; 1571 psp->rap_context.session_id = cmd->resp.session_id; 1572 mutex_init(&psp->rap_context.mutex); 1573 } 1574 1575 kfree(cmd); 1576 1577 return ret; 1578 } 1579 1580 static int psp_rap_unload(struct psp_context *psp) 1581 { 1582 int ret; 1583 struct psp_gfx_cmd_resp *cmd; 1584 1585 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1586 if (!cmd) 1587 return -ENOMEM; 1588 1589 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id); 1590 1591 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1592 1593 kfree(cmd); 1594 1595 return ret; 1596 } 1597 1598 static int psp_rap_initialize(struct psp_context *psp) 1599 { 1600 int ret; 1601 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1602 1603 /* 1604 * TODO: bypass the initialize in sriov for now 1605 */ 1606 if (amdgpu_sriov_vf(psp->adev)) 1607 return 0; 1608 1609 if (!psp->adev->psp.ta_rap_ucode_size || 1610 !psp->adev->psp.ta_rap_start_addr) { 1611 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1612 return 0; 1613 } 1614 1615 if (!psp->rap_context.rap_initialized) { 1616 ret = psp_rap_init_shared_buf(psp); 1617 if (ret) 1618 return ret; 1619 } 1620 1621 ret = psp_rap_load(psp); 1622 if (ret) 1623 return ret; 1624 1625 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1626 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1627 psp_rap_unload(psp); 1628 1629 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1630 &psp->rap_context.rap_shared_mc_addr, 1631 &psp->rap_context.rap_shared_buf); 1632 1633 psp->rap_context.rap_initialized = false; 1634 1635 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1636 ret, status); 1637 1638 return ret; 1639 } 1640 1641 return 0; 1642 } 1643 1644 static int psp_rap_terminate(struct psp_context *psp) 1645 { 1646 int ret; 1647 1648 if (!psp->rap_context.rap_initialized) 1649 return 0; 1650 1651 ret = psp_rap_unload(psp); 1652 1653 psp->rap_context.rap_initialized = false; 1654 1655 /* free rap shared memory */ 1656 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1657 &psp->rap_context.rap_shared_mc_addr, 1658 &psp->rap_context.rap_shared_buf); 1659 1660 return ret; 1661 } 1662 1663 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1664 { 1665 struct ta_rap_shared_memory *rap_cmd; 1666 int ret = 0; 1667 1668 if (!psp->rap_context.rap_initialized) 1669 return 0; 1670 1671 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1672 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1673 return -EINVAL; 1674 1675 mutex_lock(&psp->rap_context.mutex); 1676 1677 rap_cmd = (struct ta_rap_shared_memory *) 1678 psp->rap_context.rap_shared_buf; 1679 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1680 1681 rap_cmd->cmd_id = ta_cmd_id; 1682 rap_cmd->validation_method_id = METHOD_A; 1683 1684 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id); 1685 if (ret) 1686 goto out_unlock; 1687 1688 if (status) 1689 *status = rap_cmd->rap_status; 1690 1691 out_unlock: 1692 mutex_unlock(&psp->rap_context.mutex); 1693 1694 return ret; 1695 } 1696 // RAP end 1697 1698 /* securedisplay start */ 1699 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1700 { 1701 int ret; 1702 1703 /* 1704 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1705 * physical) for sa ta <-> Driver 1706 */ 1707 ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE, 1708 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1709 &psp->securedisplay_context.securedisplay_shared_bo, 1710 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1711 &psp->securedisplay_context.securedisplay_shared_buf); 1712 1713 return ret; 1714 } 1715 1716 static int psp_securedisplay_load(struct psp_context *psp) 1717 { 1718 int ret; 1719 struct psp_gfx_cmd_resp *cmd; 1720 1721 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1722 if (!cmd) 1723 return -ENOMEM; 1724 1725 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1726 memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size); 1727 1728 psp_prep_ta_load_cmd_buf(cmd, 1729 psp->fw_pri_mc_addr, 1730 psp->ta_securedisplay_ucode_size, 1731 psp->securedisplay_context.securedisplay_shared_mc_addr, 1732 PSP_SECUREDISPLAY_SHARED_MEM_SIZE); 1733 1734 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1735 1736 if (ret) 1737 goto failed; 1738 1739 psp->securedisplay_context.securedisplay_initialized = true; 1740 psp->securedisplay_context.session_id = cmd->resp.session_id; 1741 mutex_init(&psp->securedisplay_context.mutex); 1742 1743 failed: 1744 kfree(cmd); 1745 return ret; 1746 } 1747 1748 static int psp_securedisplay_unload(struct psp_context *psp) 1749 { 1750 int ret; 1751 struct psp_gfx_cmd_resp *cmd; 1752 1753 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1754 if (!cmd) 1755 return -ENOMEM; 1756 1757 psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id); 1758 1759 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1760 1761 kfree(cmd); 1762 1763 return ret; 1764 } 1765 1766 static int psp_securedisplay_initialize(struct psp_context *psp) 1767 { 1768 int ret; 1769 struct securedisplay_cmd *securedisplay_cmd; 1770 1771 /* 1772 * TODO: bypass the initialize in sriov for now 1773 */ 1774 if (amdgpu_sriov_vf(psp->adev)) 1775 return 0; 1776 1777 if (!psp->adev->psp.ta_securedisplay_ucode_size || 1778 !psp->adev->psp.ta_securedisplay_start_addr) { 1779 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1780 return 0; 1781 } 1782 1783 if (!psp->securedisplay_context.securedisplay_initialized) { 1784 ret = psp_securedisplay_init_shared_buf(psp); 1785 if (ret) 1786 return ret; 1787 } 1788 1789 ret = psp_securedisplay_load(psp); 1790 if (ret) 1791 return ret; 1792 1793 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1794 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1795 1796 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1797 if (ret) { 1798 psp_securedisplay_unload(psp); 1799 1800 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 1801 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1802 &psp->securedisplay_context.securedisplay_shared_buf); 1803 1804 psp->securedisplay_context.securedisplay_initialized = false; 1805 1806 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1807 return -EINVAL; 1808 } 1809 1810 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1811 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1812 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1813 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1814 } 1815 1816 return 0; 1817 } 1818 1819 static int psp_securedisplay_terminate(struct psp_context *psp) 1820 { 1821 int ret; 1822 1823 /* 1824 * TODO:bypass the terminate in sriov for now 1825 */ 1826 if (amdgpu_sriov_vf(psp->adev)) 1827 return 0; 1828 1829 if (!psp->securedisplay_context.securedisplay_initialized) 1830 return 0; 1831 1832 ret = psp_securedisplay_unload(psp); 1833 if (ret) 1834 return ret; 1835 1836 psp->securedisplay_context.securedisplay_initialized = false; 1837 1838 /* free securedisplay shared memory */ 1839 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 1840 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1841 &psp->securedisplay_context.securedisplay_shared_buf); 1842 1843 return ret; 1844 } 1845 1846 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1847 { 1848 int ret; 1849 1850 if (!psp->securedisplay_context.securedisplay_initialized) 1851 return -EINVAL; 1852 1853 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1854 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1855 return -EINVAL; 1856 1857 mutex_lock(&psp->securedisplay_context.mutex); 1858 1859 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id); 1860 1861 mutex_unlock(&psp->securedisplay_context.mutex); 1862 1863 return ret; 1864 } 1865 /* SECUREDISPLAY end */ 1866 1867 static int psp_hw_start(struct psp_context *psp) 1868 { 1869 struct amdgpu_device *adev = psp->adev; 1870 int ret; 1871 1872 if (!amdgpu_sriov_vf(adev)) { 1873 if (psp->kdb_bin_size && 1874 (psp->funcs->bootloader_load_kdb != NULL)) { 1875 ret = psp_bootloader_load_kdb(psp); 1876 if (ret) { 1877 DRM_ERROR("PSP load kdb failed!\n"); 1878 return ret; 1879 } 1880 } 1881 1882 if (psp->spl_bin_size) { 1883 ret = psp_bootloader_load_spl(psp); 1884 if (ret) { 1885 DRM_ERROR("PSP load spl failed!\n"); 1886 return ret; 1887 } 1888 } 1889 1890 ret = psp_bootloader_load_sysdrv(psp); 1891 if (ret) { 1892 DRM_ERROR("PSP load sysdrv failed!\n"); 1893 return ret; 1894 } 1895 1896 ret = psp_bootloader_load_sos(psp); 1897 if (ret) { 1898 DRM_ERROR("PSP load sos failed!\n"); 1899 return ret; 1900 } 1901 } 1902 1903 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1904 if (ret) { 1905 DRM_ERROR("PSP create ring failed!\n"); 1906 return ret; 1907 } 1908 1909 ret = psp_clear_vf_fw(psp); 1910 if (ret) { 1911 DRM_ERROR("PSP clear vf fw!\n"); 1912 return ret; 1913 } 1914 1915 ret = psp_tmr_init(psp); 1916 if (ret) { 1917 DRM_ERROR("PSP tmr init failed!\n"); 1918 return ret; 1919 } 1920 1921 /* 1922 * For ASICs with DF Cstate management centralized 1923 * to PMFW, TMR setup should be performed after PMFW 1924 * loaded and before other non-psp firmware loaded. 1925 */ 1926 if (psp->pmfw_centralized_cstate_management) { 1927 ret = psp_load_smu_fw(psp); 1928 if (ret) 1929 return ret; 1930 } 1931 1932 ret = psp_tmr_load(psp); 1933 if (ret) { 1934 DRM_ERROR("PSP load tmr failed!\n"); 1935 return ret; 1936 } 1937 1938 return 0; 1939 } 1940 1941 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 1942 enum psp_gfx_fw_type *type) 1943 { 1944 switch (ucode->ucode_id) { 1945 case AMDGPU_UCODE_ID_SDMA0: 1946 *type = GFX_FW_TYPE_SDMA0; 1947 break; 1948 case AMDGPU_UCODE_ID_SDMA1: 1949 *type = GFX_FW_TYPE_SDMA1; 1950 break; 1951 case AMDGPU_UCODE_ID_SDMA2: 1952 *type = GFX_FW_TYPE_SDMA2; 1953 break; 1954 case AMDGPU_UCODE_ID_SDMA3: 1955 *type = GFX_FW_TYPE_SDMA3; 1956 break; 1957 case AMDGPU_UCODE_ID_SDMA4: 1958 *type = GFX_FW_TYPE_SDMA4; 1959 break; 1960 case AMDGPU_UCODE_ID_SDMA5: 1961 *type = GFX_FW_TYPE_SDMA5; 1962 break; 1963 case AMDGPU_UCODE_ID_SDMA6: 1964 *type = GFX_FW_TYPE_SDMA6; 1965 break; 1966 case AMDGPU_UCODE_ID_SDMA7: 1967 *type = GFX_FW_TYPE_SDMA7; 1968 break; 1969 case AMDGPU_UCODE_ID_CP_MES: 1970 *type = GFX_FW_TYPE_CP_MES; 1971 break; 1972 case AMDGPU_UCODE_ID_CP_MES_DATA: 1973 *type = GFX_FW_TYPE_MES_STACK; 1974 break; 1975 case AMDGPU_UCODE_ID_CP_CE: 1976 *type = GFX_FW_TYPE_CP_CE; 1977 break; 1978 case AMDGPU_UCODE_ID_CP_PFP: 1979 *type = GFX_FW_TYPE_CP_PFP; 1980 break; 1981 case AMDGPU_UCODE_ID_CP_ME: 1982 *type = GFX_FW_TYPE_CP_ME; 1983 break; 1984 case AMDGPU_UCODE_ID_CP_MEC1: 1985 *type = GFX_FW_TYPE_CP_MEC; 1986 break; 1987 case AMDGPU_UCODE_ID_CP_MEC1_JT: 1988 *type = GFX_FW_TYPE_CP_MEC_ME1; 1989 break; 1990 case AMDGPU_UCODE_ID_CP_MEC2: 1991 *type = GFX_FW_TYPE_CP_MEC; 1992 break; 1993 case AMDGPU_UCODE_ID_CP_MEC2_JT: 1994 *type = GFX_FW_TYPE_CP_MEC_ME2; 1995 break; 1996 case AMDGPU_UCODE_ID_RLC_G: 1997 *type = GFX_FW_TYPE_RLC_G; 1998 break; 1999 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2000 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2001 break; 2002 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2003 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2004 break; 2005 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2006 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2007 break; 2008 case AMDGPU_UCODE_ID_RLC_IRAM: 2009 *type = GFX_FW_TYPE_RLC_IRAM; 2010 break; 2011 case AMDGPU_UCODE_ID_RLC_DRAM: 2012 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2013 break; 2014 case AMDGPU_UCODE_ID_SMC: 2015 *type = GFX_FW_TYPE_SMU; 2016 break; 2017 case AMDGPU_UCODE_ID_UVD: 2018 *type = GFX_FW_TYPE_UVD; 2019 break; 2020 case AMDGPU_UCODE_ID_UVD1: 2021 *type = GFX_FW_TYPE_UVD1; 2022 break; 2023 case AMDGPU_UCODE_ID_VCE: 2024 *type = GFX_FW_TYPE_VCE; 2025 break; 2026 case AMDGPU_UCODE_ID_VCN: 2027 *type = GFX_FW_TYPE_VCN; 2028 break; 2029 case AMDGPU_UCODE_ID_VCN1: 2030 *type = GFX_FW_TYPE_VCN1; 2031 break; 2032 case AMDGPU_UCODE_ID_DMCU_ERAM: 2033 *type = GFX_FW_TYPE_DMCU_ERAM; 2034 break; 2035 case AMDGPU_UCODE_ID_DMCU_INTV: 2036 *type = GFX_FW_TYPE_DMCU_ISR; 2037 break; 2038 case AMDGPU_UCODE_ID_VCN0_RAM: 2039 *type = GFX_FW_TYPE_VCN0_RAM; 2040 break; 2041 case AMDGPU_UCODE_ID_VCN1_RAM: 2042 *type = GFX_FW_TYPE_VCN1_RAM; 2043 break; 2044 case AMDGPU_UCODE_ID_DMCUB: 2045 *type = GFX_FW_TYPE_DMUB; 2046 break; 2047 case AMDGPU_UCODE_ID_MAXIMUM: 2048 default: 2049 return -EINVAL; 2050 } 2051 2052 return 0; 2053 } 2054 2055 static void psp_print_fw_hdr(struct psp_context *psp, 2056 struct amdgpu_firmware_info *ucode) 2057 { 2058 struct amdgpu_device *adev = psp->adev; 2059 struct common_firmware_header *hdr; 2060 2061 switch (ucode->ucode_id) { 2062 case AMDGPU_UCODE_ID_SDMA0: 2063 case AMDGPU_UCODE_ID_SDMA1: 2064 case AMDGPU_UCODE_ID_SDMA2: 2065 case AMDGPU_UCODE_ID_SDMA3: 2066 case AMDGPU_UCODE_ID_SDMA4: 2067 case AMDGPU_UCODE_ID_SDMA5: 2068 case AMDGPU_UCODE_ID_SDMA6: 2069 case AMDGPU_UCODE_ID_SDMA7: 2070 hdr = (struct common_firmware_header *) 2071 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2072 amdgpu_ucode_print_sdma_hdr(hdr); 2073 break; 2074 case AMDGPU_UCODE_ID_CP_CE: 2075 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2076 amdgpu_ucode_print_gfx_hdr(hdr); 2077 break; 2078 case AMDGPU_UCODE_ID_CP_PFP: 2079 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2080 amdgpu_ucode_print_gfx_hdr(hdr); 2081 break; 2082 case AMDGPU_UCODE_ID_CP_ME: 2083 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2084 amdgpu_ucode_print_gfx_hdr(hdr); 2085 break; 2086 case AMDGPU_UCODE_ID_CP_MEC1: 2087 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2088 amdgpu_ucode_print_gfx_hdr(hdr); 2089 break; 2090 case AMDGPU_UCODE_ID_RLC_G: 2091 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2092 amdgpu_ucode_print_rlc_hdr(hdr); 2093 break; 2094 case AMDGPU_UCODE_ID_SMC: 2095 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2096 amdgpu_ucode_print_smc_hdr(hdr); 2097 break; 2098 default: 2099 break; 2100 } 2101 } 2102 2103 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2104 struct psp_gfx_cmd_resp *cmd) 2105 { 2106 int ret; 2107 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2108 2109 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 2110 2111 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2112 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2113 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2114 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2115 2116 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2117 if (ret) 2118 DRM_ERROR("Unknown firmware type\n"); 2119 2120 return ret; 2121 } 2122 2123 static int psp_execute_np_fw_load(struct psp_context *psp, 2124 struct amdgpu_firmware_info *ucode) 2125 { 2126 int ret = 0; 2127 2128 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 2129 if (ret) 2130 return ret; 2131 2132 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 2133 psp->fence_buf_mc_addr); 2134 2135 return ret; 2136 } 2137 2138 static int psp_load_smu_fw(struct psp_context *psp) 2139 { 2140 int ret; 2141 struct amdgpu_device *adev = psp->adev; 2142 struct amdgpu_firmware_info *ucode = 2143 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2144 struct amdgpu_ras *ras = psp->ras.ras; 2145 2146 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2147 return 0; 2148 2149 if ((amdgpu_in_reset(adev) && 2150 ras && ras->supported && 2151 adev->asic_type == CHIP_ARCTURUS) || 2152 (adev->in_runpm && 2153 adev->asic_type >= CHIP_NAVI10 && 2154 adev->asic_type <= CHIP_NAVI12)) { 2155 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2156 if (ret) { 2157 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2158 } 2159 } 2160 2161 ret = psp_execute_np_fw_load(psp, ucode); 2162 2163 if (ret) 2164 DRM_ERROR("PSP load smu failed!\n"); 2165 2166 return ret; 2167 } 2168 2169 static bool fw_load_skip_check(struct psp_context *psp, 2170 struct amdgpu_firmware_info *ucode) 2171 { 2172 if (!ucode->fw) 2173 return true; 2174 2175 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2176 (psp_smu_reload_quirk(psp) || 2177 psp->autoload_supported || 2178 psp->pmfw_centralized_cstate_management)) 2179 return true; 2180 2181 if (amdgpu_sriov_vf(psp->adev) && 2182 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2183 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2184 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2185 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2186 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2187 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2188 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2189 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2190 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2191 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2192 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2193 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2194 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2195 /*skip ucode loading in SRIOV VF */ 2196 return true; 2197 2198 if (psp->autoload_supported && 2199 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2200 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2201 /* skip mec JT when autoload is enabled */ 2202 return true; 2203 2204 return false; 2205 } 2206 2207 static int psp_np_fw_load(struct psp_context *psp) 2208 { 2209 int i, ret; 2210 struct amdgpu_firmware_info *ucode; 2211 struct amdgpu_device *adev = psp->adev; 2212 2213 if (psp->autoload_supported && 2214 !psp->pmfw_centralized_cstate_management) { 2215 ret = psp_load_smu_fw(psp); 2216 if (ret) 2217 return ret; 2218 } 2219 2220 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2221 ucode = &adev->firmware.ucode[i]; 2222 2223 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2224 !fw_load_skip_check(psp, ucode)) { 2225 ret = psp_load_smu_fw(psp); 2226 if (ret) 2227 return ret; 2228 continue; 2229 } 2230 2231 if (fw_load_skip_check(psp, ucode)) 2232 continue; 2233 2234 if (psp->autoload_supported && 2235 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2236 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2237 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2238 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2239 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2240 /* PSP only receive one SDMA fw for sienna_cichlid, 2241 * as all four sdma fw are same */ 2242 continue; 2243 2244 psp_print_fw_hdr(psp, ucode); 2245 2246 ret = psp_execute_np_fw_load(psp, ucode); 2247 if (ret) 2248 return ret; 2249 2250 /* Start rlc autoload after psp recieved all the gfx firmware */ 2251 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2252 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2253 ret = psp_rlc_autoload_start(psp); 2254 if (ret) { 2255 DRM_ERROR("Failed to start rlc autoload\n"); 2256 return ret; 2257 } 2258 } 2259 } 2260 2261 return 0; 2262 } 2263 2264 static int psp_load_fw(struct amdgpu_device *adev) 2265 { 2266 int ret; 2267 struct psp_context *psp = &adev->psp; 2268 2269 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2270 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2271 goto skip_memalloc; 2272 } 2273 2274 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2275 if (!psp->cmd) 2276 return -ENOMEM; 2277 2278 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2279 AMDGPU_GEM_DOMAIN_GTT, 2280 &psp->fw_pri_bo, 2281 &psp->fw_pri_mc_addr, 2282 &psp->fw_pri_buf); 2283 if (ret) 2284 goto failed; 2285 2286 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2287 AMDGPU_GEM_DOMAIN_VRAM, 2288 &psp->fence_buf_bo, 2289 &psp->fence_buf_mc_addr, 2290 &psp->fence_buf); 2291 if (ret) 2292 goto failed; 2293 2294 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2295 AMDGPU_GEM_DOMAIN_VRAM, 2296 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2297 (void **)&psp->cmd_buf_mem); 2298 if (ret) 2299 goto failed; 2300 2301 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2302 2303 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2304 if (ret) { 2305 DRM_ERROR("PSP ring init failed!\n"); 2306 goto failed; 2307 } 2308 2309 skip_memalloc: 2310 ret = psp_hw_start(psp); 2311 if (ret) 2312 goto failed; 2313 2314 ret = psp_np_fw_load(psp); 2315 if (ret) 2316 goto failed; 2317 2318 ret = psp_asd_load(psp); 2319 if (ret) { 2320 DRM_ERROR("PSP load asd failed!\n"); 2321 return ret; 2322 } 2323 2324 ret = psp_rl_load(adev); 2325 if (ret) { 2326 DRM_ERROR("PSP load RL failed!\n"); 2327 return ret; 2328 } 2329 2330 if (psp->adev->psp.ta_fw) { 2331 ret = psp_ras_initialize(psp); 2332 if (ret) 2333 dev_err(psp->adev->dev, 2334 "RAS: Failed to initialize RAS\n"); 2335 2336 ret = psp_hdcp_initialize(psp); 2337 if (ret) 2338 dev_err(psp->adev->dev, 2339 "HDCP: Failed to initialize HDCP\n"); 2340 2341 ret = psp_dtm_initialize(psp); 2342 if (ret) 2343 dev_err(psp->adev->dev, 2344 "DTM: Failed to initialize DTM\n"); 2345 2346 ret = psp_rap_initialize(psp); 2347 if (ret) 2348 dev_err(psp->adev->dev, 2349 "RAP: Failed to initialize RAP\n"); 2350 2351 ret = psp_securedisplay_initialize(psp); 2352 if (ret) 2353 dev_err(psp->adev->dev, 2354 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2355 } 2356 2357 return 0; 2358 2359 failed: 2360 /* 2361 * all cleanup jobs (xgmi terminate, ras terminate, 2362 * ring destroy, cmd/fence/fw buffers destory, 2363 * psp->cmd destory) are delayed to psp_hw_fini 2364 */ 2365 return ret; 2366 } 2367 2368 static int psp_hw_init(void *handle) 2369 { 2370 int ret; 2371 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2372 2373 mutex_lock(&adev->firmware.mutex); 2374 /* 2375 * This sequence is just used on hw_init only once, no need on 2376 * resume. 2377 */ 2378 ret = amdgpu_ucode_init_bo(adev); 2379 if (ret) 2380 goto failed; 2381 2382 ret = psp_load_fw(adev); 2383 if (ret) { 2384 DRM_ERROR("PSP firmware loading failed\n"); 2385 goto failed; 2386 } 2387 2388 mutex_unlock(&adev->firmware.mutex); 2389 return 0; 2390 2391 failed: 2392 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2393 mutex_unlock(&adev->firmware.mutex); 2394 return -EINVAL; 2395 } 2396 2397 static int psp_hw_fini(void *handle) 2398 { 2399 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2400 struct psp_context *psp = &adev->psp; 2401 int ret; 2402 2403 if (psp->adev->psp.ta_fw) { 2404 psp_ras_terminate(psp); 2405 psp_securedisplay_terminate(psp); 2406 psp_rap_terminate(psp); 2407 psp_dtm_terminate(psp); 2408 psp_hdcp_terminate(psp); 2409 } 2410 2411 psp_asd_unload(psp); 2412 ret = psp_clear_vf_fw(psp); 2413 if (ret) { 2414 DRM_ERROR("PSP clear vf fw!\n"); 2415 return ret; 2416 } 2417 2418 psp_tmr_terminate(psp); 2419 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2420 2421 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2422 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2423 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2424 &psp->fence_buf_mc_addr, &psp->fence_buf); 2425 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2426 (void **)&psp->cmd_buf_mem); 2427 2428 kfree(psp->cmd); 2429 psp->cmd = NULL; 2430 2431 return 0; 2432 } 2433 2434 static int psp_suspend(void *handle) 2435 { 2436 int ret; 2437 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2438 struct psp_context *psp = &adev->psp; 2439 2440 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2441 psp->xgmi_context.initialized == 1) { 2442 ret = psp_xgmi_terminate(psp); 2443 if (ret) { 2444 DRM_ERROR("Failed to terminate xgmi ta\n"); 2445 return ret; 2446 } 2447 } 2448 2449 if (psp->adev->psp.ta_fw) { 2450 ret = psp_ras_terminate(psp); 2451 if (ret) { 2452 DRM_ERROR("Failed to terminate ras ta\n"); 2453 return ret; 2454 } 2455 ret = psp_hdcp_terminate(psp); 2456 if (ret) { 2457 DRM_ERROR("Failed to terminate hdcp ta\n"); 2458 return ret; 2459 } 2460 ret = psp_dtm_terminate(psp); 2461 if (ret) { 2462 DRM_ERROR("Failed to terminate dtm ta\n"); 2463 return ret; 2464 } 2465 ret = psp_rap_terminate(psp); 2466 if (ret) { 2467 DRM_ERROR("Failed to terminate rap ta\n"); 2468 return ret; 2469 } 2470 ret = psp_securedisplay_terminate(psp); 2471 if (ret) { 2472 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2473 return ret; 2474 } 2475 } 2476 2477 ret = psp_asd_unload(psp); 2478 if (ret) { 2479 DRM_ERROR("Failed to unload asd\n"); 2480 return ret; 2481 } 2482 2483 ret = psp_tmr_terminate(psp); 2484 if (ret) { 2485 DRM_ERROR("Failed to terminate tmr\n"); 2486 return ret; 2487 } 2488 2489 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2490 if (ret) { 2491 DRM_ERROR("PSP ring stop failed\n"); 2492 return ret; 2493 } 2494 2495 return 0; 2496 } 2497 2498 static int psp_resume(void *handle) 2499 { 2500 int ret; 2501 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2502 struct psp_context *psp = &adev->psp; 2503 2504 DRM_INFO("PSP is resuming...\n"); 2505 2506 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2507 if (ret) { 2508 DRM_ERROR("Failed to process memory training!\n"); 2509 return ret; 2510 } 2511 2512 mutex_lock(&adev->firmware.mutex); 2513 2514 ret = psp_hw_start(psp); 2515 if (ret) 2516 goto failed; 2517 2518 ret = psp_np_fw_load(psp); 2519 if (ret) 2520 goto failed; 2521 2522 ret = psp_asd_load(psp); 2523 if (ret) { 2524 DRM_ERROR("PSP load asd failed!\n"); 2525 goto failed; 2526 } 2527 2528 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2529 ret = psp_xgmi_initialize(psp); 2530 /* Warning the XGMI seesion initialize failure 2531 * Instead of stop driver initialization 2532 */ 2533 if (ret) 2534 dev_err(psp->adev->dev, 2535 "XGMI: Failed to initialize XGMI session\n"); 2536 } 2537 2538 if (psp->adev->psp.ta_fw) { 2539 ret = psp_ras_initialize(psp); 2540 if (ret) 2541 dev_err(psp->adev->dev, 2542 "RAS: Failed to initialize RAS\n"); 2543 2544 ret = psp_hdcp_initialize(psp); 2545 if (ret) 2546 dev_err(psp->adev->dev, 2547 "HDCP: Failed to initialize HDCP\n"); 2548 2549 ret = psp_dtm_initialize(psp); 2550 if (ret) 2551 dev_err(psp->adev->dev, 2552 "DTM: Failed to initialize DTM\n"); 2553 2554 ret = psp_rap_initialize(psp); 2555 if (ret) 2556 dev_err(psp->adev->dev, 2557 "RAP: Failed to initialize RAP\n"); 2558 2559 ret = psp_securedisplay_initialize(psp); 2560 if (ret) 2561 dev_err(psp->adev->dev, 2562 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2563 } 2564 2565 mutex_unlock(&adev->firmware.mutex); 2566 2567 return 0; 2568 2569 failed: 2570 DRM_ERROR("PSP resume failed\n"); 2571 mutex_unlock(&adev->firmware.mutex); 2572 return ret; 2573 } 2574 2575 int psp_gpu_reset(struct amdgpu_device *adev) 2576 { 2577 int ret; 2578 2579 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2580 return 0; 2581 2582 mutex_lock(&adev->psp.mutex); 2583 ret = psp_mode1_reset(&adev->psp); 2584 mutex_unlock(&adev->psp.mutex); 2585 2586 return ret; 2587 } 2588 2589 int psp_rlc_autoload_start(struct psp_context *psp) 2590 { 2591 int ret; 2592 struct psp_gfx_cmd_resp *cmd; 2593 2594 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2595 if (!cmd) 2596 return -ENOMEM; 2597 2598 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2599 2600 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2601 psp->fence_buf_mc_addr); 2602 kfree(cmd); 2603 return ret; 2604 } 2605 2606 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2607 uint64_t cmd_gpu_addr, int cmd_size) 2608 { 2609 struct amdgpu_firmware_info ucode = {0}; 2610 2611 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2612 AMDGPU_UCODE_ID_VCN0_RAM; 2613 ucode.mc_addr = cmd_gpu_addr; 2614 ucode.ucode_size = cmd_size; 2615 2616 return psp_execute_np_fw_load(&adev->psp, &ucode); 2617 } 2618 2619 int psp_ring_cmd_submit(struct psp_context *psp, 2620 uint64_t cmd_buf_mc_addr, 2621 uint64_t fence_mc_addr, 2622 int index) 2623 { 2624 unsigned int psp_write_ptr_reg = 0; 2625 struct psp_gfx_rb_frame *write_frame; 2626 struct psp_ring *ring = &psp->km_ring; 2627 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2628 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2629 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2630 struct amdgpu_device *adev = psp->adev; 2631 uint32_t ring_size_dw = ring->ring_size / 4; 2632 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2633 2634 /* KM (GPCOM) prepare write pointer */ 2635 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2636 2637 /* Update KM RB frame pointer to new frame */ 2638 /* write_frame ptr increments by size of rb_frame in bytes */ 2639 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2640 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2641 write_frame = ring_buffer_start; 2642 else 2643 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2644 /* Check invalid write_frame ptr address */ 2645 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2646 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2647 ring_buffer_start, ring_buffer_end, write_frame); 2648 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2649 return -EINVAL; 2650 } 2651 2652 /* Initialize KM RB frame */ 2653 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2654 2655 /* Update KM RB frame */ 2656 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2657 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2658 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2659 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2660 write_frame->fence_value = index; 2661 amdgpu_asic_flush_hdp(adev, NULL); 2662 2663 /* Update the write Pointer in DWORDs */ 2664 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2665 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2666 return 0; 2667 } 2668 2669 int psp_init_asd_microcode(struct psp_context *psp, 2670 const char *chip_name) 2671 { 2672 struct amdgpu_device *adev = psp->adev; 2673 char fw_name[PSP_FW_NAME_LEN]; 2674 const struct psp_firmware_header_v1_0 *asd_hdr; 2675 int err = 0; 2676 2677 if (!chip_name) { 2678 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2679 return -EINVAL; 2680 } 2681 2682 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2683 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2684 if (err) 2685 goto out; 2686 2687 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2688 if (err) 2689 goto out; 2690 2691 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2692 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2693 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 2694 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2695 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2696 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2697 return 0; 2698 out: 2699 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2700 release_firmware(adev->psp.asd_fw); 2701 adev->psp.asd_fw = NULL; 2702 return err; 2703 } 2704 2705 int psp_init_toc_microcode(struct psp_context *psp, 2706 const char *chip_name) 2707 { 2708 struct amdgpu_device *adev = psp->adev; 2709 char fw_name[30]; 2710 const struct psp_firmware_header_v1_0 *toc_hdr; 2711 int err = 0; 2712 2713 if (!chip_name) { 2714 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2715 return -EINVAL; 2716 } 2717 2718 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2719 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2720 if (err) 2721 goto out; 2722 2723 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2724 if (err) 2725 goto out; 2726 2727 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2728 adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2729 adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version); 2730 adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2731 adev->psp.toc_start_addr = (uint8_t *)toc_hdr + 2732 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2733 return 0; 2734 out: 2735 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2736 release_firmware(adev->psp.toc_fw); 2737 adev->psp.toc_fw = NULL; 2738 return err; 2739 } 2740 2741 int psp_init_sos_microcode(struct psp_context *psp, 2742 const char *chip_name) 2743 { 2744 struct amdgpu_device *adev = psp->adev; 2745 char fw_name[PSP_FW_NAME_LEN]; 2746 const struct psp_firmware_header_v1_0 *sos_hdr; 2747 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 2748 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 2749 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2750 int err = 0; 2751 2752 if (!chip_name) { 2753 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 2754 return -EINVAL; 2755 } 2756 2757 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 2758 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 2759 if (err) 2760 goto out; 2761 2762 err = amdgpu_ucode_validate(adev->psp.sos_fw); 2763 if (err) 2764 goto out; 2765 2766 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2767 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 2768 2769 switch (sos_hdr->header.header_version_major) { 2770 case 1: 2771 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 2772 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 2773 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 2774 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 2775 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 2776 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2777 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2778 le32_to_cpu(sos_hdr->sos_offset_bytes); 2779 if (sos_hdr->header.header_version_minor == 1) { 2780 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 2781 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 2782 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2783 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 2784 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); 2785 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2786 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); 2787 } 2788 if (sos_hdr->header.header_version_minor == 2) { 2789 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 2790 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); 2791 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2792 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); 2793 } 2794 if (sos_hdr->header.header_version_minor == 3) { 2795 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 2796 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes); 2797 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2798 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes); 2799 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes); 2800 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2801 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes); 2802 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes); 2803 adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2804 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes); 2805 adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl_size_bytes); 2806 adev->psp.rl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2807 le32_to_cpu(sos_hdr_v1_3->rl_offset_bytes); 2808 } 2809 break; 2810 default: 2811 dev_err(adev->dev, 2812 "unsupported psp sos firmware\n"); 2813 err = -EINVAL; 2814 goto out; 2815 } 2816 2817 return 0; 2818 out: 2819 dev_err(adev->dev, 2820 "failed to init sos firmware\n"); 2821 release_firmware(adev->psp.sos_fw); 2822 adev->psp.sos_fw = NULL; 2823 2824 return err; 2825 } 2826 2827 static int parse_ta_bin_descriptor(struct psp_context *psp, 2828 const struct ta_fw_bin_desc *desc, 2829 const struct ta_firmware_header_v2_0 *ta_hdr) 2830 { 2831 uint8_t *ucode_start_addr = NULL; 2832 2833 if (!psp || !desc || !ta_hdr) 2834 return -EINVAL; 2835 2836 ucode_start_addr = (uint8_t *)ta_hdr + 2837 le32_to_cpu(desc->offset_bytes) + 2838 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 2839 2840 switch (desc->fw_type) { 2841 case TA_FW_TYPE_PSP_ASD: 2842 psp->asd_fw_version = le32_to_cpu(desc->fw_version); 2843 psp->asd_feature_version = le32_to_cpu(desc->fw_version); 2844 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 2845 psp->asd_start_addr = ucode_start_addr; 2846 break; 2847 case TA_FW_TYPE_PSP_XGMI: 2848 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 2849 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 2850 psp->ta_xgmi_start_addr = ucode_start_addr; 2851 break; 2852 case TA_FW_TYPE_PSP_RAS: 2853 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 2854 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 2855 psp->ta_ras_start_addr = ucode_start_addr; 2856 break; 2857 case TA_FW_TYPE_PSP_HDCP: 2858 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 2859 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 2860 psp->ta_hdcp_start_addr = ucode_start_addr; 2861 break; 2862 case TA_FW_TYPE_PSP_DTM: 2863 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 2864 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 2865 psp->ta_dtm_start_addr = ucode_start_addr; 2866 break; 2867 case TA_FW_TYPE_PSP_RAP: 2868 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version); 2869 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes); 2870 psp->ta_rap_start_addr = ucode_start_addr; 2871 break; 2872 case TA_FW_TYPE_PSP_SECUREDISPLAY: 2873 psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version); 2874 psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes); 2875 psp->ta_securedisplay_start_addr = ucode_start_addr; 2876 break; 2877 default: 2878 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 2879 break; 2880 } 2881 2882 return 0; 2883 } 2884 2885 int psp_init_ta_microcode(struct psp_context *psp, 2886 const char *chip_name) 2887 { 2888 struct amdgpu_device *adev = psp->adev; 2889 char fw_name[PSP_FW_NAME_LEN]; 2890 const struct ta_firmware_header_v2_0 *ta_hdr; 2891 int err = 0; 2892 int ta_index = 0; 2893 2894 if (!chip_name) { 2895 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 2896 return -EINVAL; 2897 } 2898 2899 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 2900 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 2901 if (err) 2902 goto out; 2903 2904 err = amdgpu_ucode_validate(adev->psp.ta_fw); 2905 if (err) 2906 goto out; 2907 2908 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 2909 2910 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 2911 dev_err(adev->dev, "unsupported TA header version\n"); 2912 err = -EINVAL; 2913 goto out; 2914 } 2915 2916 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) { 2917 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 2918 err = -EINVAL; 2919 goto out; 2920 } 2921 2922 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 2923 err = parse_ta_bin_descriptor(psp, 2924 &ta_hdr->ta_fw_bin[ta_index], 2925 ta_hdr); 2926 if (err) 2927 goto out; 2928 } 2929 2930 return 0; 2931 out: 2932 dev_err(adev->dev, "fail to initialize ta microcode\n"); 2933 release_firmware(adev->psp.ta_fw); 2934 adev->psp.ta_fw = NULL; 2935 return err; 2936 } 2937 2938 static int psp_set_clockgating_state(void *handle, 2939 enum amd_clockgating_state state) 2940 { 2941 return 0; 2942 } 2943 2944 static int psp_set_powergating_state(void *handle, 2945 enum amd_powergating_state state) 2946 { 2947 return 0; 2948 } 2949 2950 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 2951 struct device_attribute *attr, 2952 char *buf) 2953 { 2954 struct drm_device *ddev = dev_get_drvdata(dev); 2955 struct amdgpu_device *adev = drm_to_adev(ddev); 2956 uint32_t fw_ver; 2957 int ret; 2958 2959 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2960 DRM_INFO("PSP block is not ready yet."); 2961 return -EBUSY; 2962 } 2963 2964 mutex_lock(&adev->psp.mutex); 2965 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 2966 mutex_unlock(&adev->psp.mutex); 2967 2968 if (ret) { 2969 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 2970 return ret; 2971 } 2972 2973 return snprintf(buf, PAGE_SIZE, "%x\n", fw_ver); 2974 } 2975 2976 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 2977 struct device_attribute *attr, 2978 const char *buf, 2979 size_t count) 2980 { 2981 struct drm_device *ddev = dev_get_drvdata(dev); 2982 struct amdgpu_device *adev = drm_to_adev(ddev); 2983 void *cpu_addr; 2984 dma_addr_t dma_addr; 2985 int ret; 2986 char fw_name[100]; 2987 const struct firmware *usbc_pd_fw; 2988 2989 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2990 DRM_INFO("PSP block is not ready yet."); 2991 return -EBUSY; 2992 } 2993 2994 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 2995 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 2996 if (ret) 2997 goto fail; 2998 2999 /* We need contiguous physical mem to place the FW for psp to access */ 3000 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL); 3001 3002 ret = dma_mapping_error(adev->dev, dma_addr); 3003 if (ret) 3004 goto rel_buf; 3005 3006 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3007 3008 /* 3009 * x86 specific workaround. 3010 * Without it the buffer is invisible in PSP. 3011 * 3012 * TODO Remove once PSP starts snooping CPU cache 3013 */ 3014 #ifdef CONFIG_X86 3015 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1))); 3016 #endif 3017 3018 mutex_lock(&adev->psp.mutex); 3019 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr); 3020 mutex_unlock(&adev->psp.mutex); 3021 3022 rel_buf: 3023 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr); 3024 release_firmware(usbc_pd_fw); 3025 3026 fail: 3027 if (ret) { 3028 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3029 return ret; 3030 } 3031 3032 return count; 3033 } 3034 3035 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3036 psp_usbc_pd_fw_sysfs_read, 3037 psp_usbc_pd_fw_sysfs_write); 3038 3039 3040 3041 const struct amd_ip_funcs psp_ip_funcs = { 3042 .name = "psp", 3043 .early_init = psp_early_init, 3044 .late_init = NULL, 3045 .sw_init = psp_sw_init, 3046 .sw_fini = psp_sw_fini, 3047 .hw_init = psp_hw_init, 3048 .hw_fini = psp_hw_fini, 3049 .suspend = psp_suspend, 3050 .resume = psp_resume, 3051 .is_idle = NULL, 3052 .check_soft_reset = NULL, 3053 .wait_for_idle = NULL, 3054 .soft_reset = NULL, 3055 .set_clockgating_state = psp_set_clockgating_state, 3056 .set_powergating_state = psp_set_powergating_state, 3057 }; 3058 3059 static int psp_sysfs_init(struct amdgpu_device *adev) 3060 { 3061 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3062 3063 if (ret) 3064 DRM_ERROR("Failed to create USBC PD FW control file!"); 3065 3066 return ret; 3067 } 3068 3069 static void psp_sysfs_fini(struct amdgpu_device *adev) 3070 { 3071 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3072 } 3073 3074 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3075 { 3076 .type = AMD_IP_BLOCK_TYPE_PSP, 3077 .major = 3, 3078 .minor = 1, 3079 .rev = 0, 3080 .funcs = &psp_ip_funcs, 3081 }; 3082 3083 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3084 { 3085 .type = AMD_IP_BLOCK_TYPE_PSP, 3086 .major = 10, 3087 .minor = 0, 3088 .rev = 0, 3089 .funcs = &psp_ip_funcs, 3090 }; 3091 3092 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3093 { 3094 .type = AMD_IP_BLOCK_TYPE_PSP, 3095 .major = 11, 3096 .minor = 0, 3097 .rev = 0, 3098 .funcs = &psp_ip_funcs, 3099 }; 3100 3101 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3102 { 3103 .type = AMD_IP_BLOCK_TYPE_PSP, 3104 .major = 12, 3105 .minor = 0, 3106 .rev = 0, 3107 .funcs = &psp_ip_funcs, 3108 }; 3109 3110 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3111 .type = AMD_IP_BLOCK_TYPE_PSP, 3112 .major = 13, 3113 .minor = 0, 3114 .rev = 0, 3115 .funcs = &psp_ip_funcs, 3116 }; 3117