1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 42 #include "amdgpu_ras.h" 43 #include "amdgpu_securedisplay.h" 44 #include "amdgpu_atomfirmware.h" 45 46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 47 48 static int psp_sysfs_init(struct amdgpu_device *adev); 49 static void psp_sysfs_fini(struct amdgpu_device *adev); 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 /* 56 * Due to DF Cstate management centralized to PMFW, the firmware 57 * loading sequence will be updated as below: 58 * - Load KDB 59 * - Load SYS_DRV 60 * - Load tOS 61 * - Load PMFW 62 * - Setup TMR 63 * - Load other non-psp fw 64 * - Load ASD 65 * - Load XGMI/RAS/HDCP/DTM TA if any 66 * 67 * This new sequence is required for 68 * - Arcturus and onwards 69 */ 70 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 71 { 72 struct amdgpu_device *adev = psp->adev; 73 74 if (amdgpu_sriov_vf(adev)) { 75 psp->pmfw_centralized_cstate_management = false; 76 return; 77 } 78 79 switch (adev->ip_versions[MP0_HWIP][0]) { 80 case IP_VERSION(11, 0, 0): 81 case IP_VERSION(11, 0, 4): 82 case IP_VERSION(11, 0, 5): 83 case IP_VERSION(11, 0, 7): 84 case IP_VERSION(11, 0, 9): 85 case IP_VERSION(11, 0, 11): 86 case IP_VERSION(11, 0, 12): 87 case IP_VERSION(11, 0, 13): 88 case IP_VERSION(13, 0, 0): 89 case IP_VERSION(13, 0, 2): 90 case IP_VERSION(13, 0, 7): 91 psp->pmfw_centralized_cstate_management = true; 92 break; 93 default: 94 psp->pmfw_centralized_cstate_management = false; 95 break; 96 } 97 } 98 99 static int psp_early_init(void *handle) 100 { 101 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 102 struct psp_context *psp = &adev->psp; 103 104 switch (adev->ip_versions[MP0_HWIP][0]) { 105 case IP_VERSION(9, 0, 0): 106 psp_v3_1_set_psp_funcs(psp); 107 psp->autoload_supported = false; 108 break; 109 case IP_VERSION(10, 0, 0): 110 case IP_VERSION(10, 0, 1): 111 psp_v10_0_set_psp_funcs(psp); 112 psp->autoload_supported = false; 113 break; 114 case IP_VERSION(11, 0, 2): 115 case IP_VERSION(11, 0, 4): 116 psp_v11_0_set_psp_funcs(psp); 117 psp->autoload_supported = false; 118 break; 119 case IP_VERSION(11, 0, 0): 120 case IP_VERSION(11, 0, 5): 121 case IP_VERSION(11, 0, 9): 122 case IP_VERSION(11, 0, 7): 123 case IP_VERSION(11, 0, 11): 124 case IP_VERSION(11, 5, 0): 125 case IP_VERSION(11, 0, 12): 126 case IP_VERSION(11, 0, 13): 127 psp_v11_0_set_psp_funcs(psp); 128 psp->autoload_supported = true; 129 break; 130 case IP_VERSION(11, 0, 3): 131 case IP_VERSION(12, 0, 1): 132 psp_v12_0_set_psp_funcs(psp); 133 break; 134 case IP_VERSION(13, 0, 2): 135 psp_v13_0_set_psp_funcs(psp); 136 break; 137 case IP_VERSION(13, 0, 1): 138 case IP_VERSION(13, 0, 3): 139 case IP_VERSION(13, 0, 5): 140 case IP_VERSION(13, 0, 8): 141 case IP_VERSION(13, 0, 10): 142 psp_v13_0_set_psp_funcs(psp); 143 psp->autoload_supported = true; 144 break; 145 case IP_VERSION(11, 0, 8): 146 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 147 psp_v11_0_8_set_psp_funcs(psp); 148 psp->autoload_supported = false; 149 } 150 break; 151 case IP_VERSION(13, 0, 0): 152 case IP_VERSION(13, 0, 7): 153 psp_v13_0_set_psp_funcs(psp); 154 psp->autoload_supported = true; 155 break; 156 case IP_VERSION(13, 0, 4): 157 psp_v13_0_4_set_psp_funcs(psp); 158 psp->autoload_supported = true; 159 break; 160 default: 161 return -EINVAL; 162 } 163 164 psp->adev = adev; 165 166 psp_check_pmfw_centralized_cstate_management(psp); 167 168 return 0; 169 } 170 171 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 172 { 173 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 174 &mem_ctx->shared_buf); 175 } 176 177 static void psp_free_shared_bufs(struct psp_context *psp) 178 { 179 void *tmr_buf; 180 void **pptr; 181 182 /* free TMR memory buffer */ 183 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 184 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 185 186 /* free xgmi shared memory */ 187 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 188 189 /* free ras shared memory */ 190 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 191 192 /* free hdcp shared memory */ 193 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 194 195 /* free dtm shared memory */ 196 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 197 198 /* free rap shared memory */ 199 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 200 201 /* free securedisplay shared memory */ 202 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 203 204 205 } 206 207 static void psp_memory_training_fini(struct psp_context *psp) 208 { 209 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 210 211 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 212 kfree(ctx->sys_cache); 213 ctx->sys_cache = NULL; 214 } 215 216 static int psp_memory_training_init(struct psp_context *psp) 217 { 218 int ret; 219 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 220 221 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 222 DRM_DEBUG("memory training is not supported!\n"); 223 return 0; 224 } 225 226 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 227 if (ctx->sys_cache == NULL) { 228 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 229 ret = -ENOMEM; 230 goto Err_out; 231 } 232 233 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 234 ctx->train_data_size, 235 ctx->p2c_train_data_offset, 236 ctx->c2p_train_data_offset); 237 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 238 return 0; 239 240 Err_out: 241 psp_memory_training_fini(psp); 242 return ret; 243 } 244 245 /* 246 * Helper funciton to query psp runtime database entry 247 * 248 * @adev: amdgpu_device pointer 249 * @entry_type: the type of psp runtime database entry 250 * @db_entry: runtime database entry pointer 251 * 252 * Return false if runtime database doesn't exit or entry is invalid 253 * or true if the specific database entry is found, and copy to @db_entry 254 */ 255 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 256 enum psp_runtime_entry_type entry_type, 257 void *db_entry) 258 { 259 uint64_t db_header_pos, db_dir_pos; 260 struct psp_runtime_data_header db_header = {0}; 261 struct psp_runtime_data_directory db_dir = {0}; 262 bool ret = false; 263 int i; 264 265 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 266 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 267 268 /* read runtime db header from vram */ 269 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 270 sizeof(struct psp_runtime_data_header), false); 271 272 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 273 /* runtime db doesn't exist, exit */ 274 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 275 return false; 276 } 277 278 /* read runtime database entry from vram */ 279 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 280 sizeof(struct psp_runtime_data_directory), false); 281 282 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 283 /* invalid db entry count, exit */ 284 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 285 return false; 286 } 287 288 /* look up for requested entry type */ 289 for (i = 0; i < db_dir.entry_count && !ret; i++) { 290 if (db_dir.entry_list[i].entry_type == entry_type) { 291 switch (entry_type) { 292 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 293 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 294 /* invalid db entry size */ 295 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 296 return false; 297 } 298 /* read runtime database entry */ 299 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 300 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 301 ret = true; 302 break; 303 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 304 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 305 /* invalid db entry size */ 306 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 307 return false; 308 } 309 /* read runtime database entry */ 310 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 311 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 312 ret = true; 313 break; 314 default: 315 ret = false; 316 break; 317 } 318 } 319 } 320 321 return ret; 322 } 323 324 static int psp_init_sriov_microcode(struct psp_context *psp) 325 { 326 struct amdgpu_device *adev = psp->adev; 327 int ret = 0; 328 329 switch (adev->ip_versions[MP0_HWIP][0]) { 330 case IP_VERSION(9, 0, 0): 331 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 332 ret = psp_init_cap_microcode(psp, "vega10"); 333 break; 334 case IP_VERSION(11, 0, 9): 335 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 336 ret = psp_init_cap_microcode(psp, "navi12"); 337 break; 338 case IP_VERSION(11, 0, 7): 339 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 340 ret = psp_init_cap_microcode(psp, "sienna_cichlid"); 341 break; 342 case IP_VERSION(13, 0, 2): 343 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 344 ret = psp_init_cap_microcode(psp, "aldebaran"); 345 ret &= psp_init_ta_microcode(psp, "aldebaran"); 346 break; 347 case IP_VERSION(13, 0, 0): 348 adev->virt.autoload_ucode_id = 0; 349 break; 350 case IP_VERSION(13, 0, 10): 351 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 352 break; 353 default: 354 BUG(); 355 break; 356 } 357 return ret; 358 } 359 360 static int psp_sw_init(void *handle) 361 { 362 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 363 struct psp_context *psp = &adev->psp; 364 int ret; 365 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 366 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 367 struct psp_runtime_scpm_entry scpm_entry; 368 369 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 370 if (!psp->cmd) { 371 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 372 ret = -ENOMEM; 373 } 374 375 if (amdgpu_sriov_vf(adev)) 376 ret = psp_init_sriov_microcode(psp); 377 else 378 ret = psp_init_microcode(psp); 379 if (ret) { 380 DRM_ERROR("Failed to load psp firmware!\n"); 381 return ret; 382 } 383 384 adev->psp.xgmi_context.supports_extended_data = 385 !adev->gmc.xgmi.connected_to_cpu && 386 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 387 388 memset(&scpm_entry, 0, sizeof(scpm_entry)); 389 if ((psp_get_runtime_db_entry(adev, 390 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 391 &scpm_entry)) && 392 (SCPM_DISABLE != scpm_entry.scpm_status)) { 393 adev->scpm_enabled = true; 394 adev->scpm_status = scpm_entry.scpm_status; 395 } else { 396 adev->scpm_enabled = false; 397 adev->scpm_status = SCPM_DISABLE; 398 } 399 400 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 401 402 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 403 if (psp_get_runtime_db_entry(adev, 404 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 405 &boot_cfg_entry)) { 406 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 407 if ((psp->boot_cfg_bitmask) & 408 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 409 /* If psp runtime database exists, then 410 * only enable two stage memory training 411 * when TWO_STAGE_DRAM_TRAINING bit is set 412 * in runtime database */ 413 mem_training_ctx->enable_mem_training = true; 414 } 415 416 } else { 417 /* If psp runtime database doesn't exist or 418 * is invalid, force enable two stage memory 419 * training */ 420 mem_training_ctx->enable_mem_training = true; 421 } 422 423 if (mem_training_ctx->enable_mem_training) { 424 ret = psp_memory_training_init(psp); 425 if (ret) { 426 DRM_ERROR("Failed to initialize memory training!\n"); 427 return ret; 428 } 429 430 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 431 if (ret) { 432 DRM_ERROR("Failed to process memory training!\n"); 433 return ret; 434 } 435 } 436 437 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 438 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 439 ret= psp_sysfs_init(adev); 440 if (ret) { 441 return ret; 442 } 443 } 444 445 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 446 amdgpu_sriov_vf(adev) ? 447 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 448 &psp->fw_pri_bo, 449 &psp->fw_pri_mc_addr, 450 &psp->fw_pri_buf); 451 if (ret) 452 return ret; 453 454 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 455 AMDGPU_GEM_DOMAIN_VRAM, 456 &psp->fence_buf_bo, 457 &psp->fence_buf_mc_addr, 458 &psp->fence_buf); 459 if (ret) 460 goto failed1; 461 462 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 463 AMDGPU_GEM_DOMAIN_VRAM, 464 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 465 (void **)&psp->cmd_buf_mem); 466 if (ret) 467 goto failed2; 468 469 return 0; 470 471 failed2: 472 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 473 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 474 failed1: 475 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 476 &psp->fence_buf_mc_addr, &psp->fence_buf); 477 return ret; 478 } 479 480 static int psp_sw_fini(void *handle) 481 { 482 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 483 struct psp_context *psp = &adev->psp; 484 struct psp_gfx_cmd_resp *cmd = psp->cmd; 485 486 psp_memory_training_fini(psp); 487 if (psp->sos_fw) { 488 release_firmware(psp->sos_fw); 489 psp->sos_fw = NULL; 490 } 491 if (psp->asd_fw) { 492 release_firmware(psp->asd_fw); 493 psp->asd_fw = NULL; 494 } 495 if (psp->ta_fw) { 496 release_firmware(psp->ta_fw); 497 psp->ta_fw = NULL; 498 } 499 if (psp->cap_fw) { 500 release_firmware(psp->cap_fw); 501 psp->cap_fw = NULL; 502 } 503 if (psp->toc_fw) { 504 release_firmware(psp->toc_fw); 505 psp->toc_fw = NULL; 506 } 507 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 508 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 509 psp_sysfs_fini(adev); 510 511 kfree(cmd); 512 cmd = NULL; 513 514 if (psp->km_ring.ring_mem) 515 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 516 &psp->km_ring.ring_mem_mc_addr, 517 (void **)&psp->km_ring.ring_mem); 518 519 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 520 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 521 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 522 &psp->fence_buf_mc_addr, &psp->fence_buf); 523 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 524 (void **)&psp->cmd_buf_mem); 525 526 return 0; 527 } 528 529 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 530 uint32_t reg_val, uint32_t mask, bool check_changed) 531 { 532 uint32_t val; 533 int i; 534 struct amdgpu_device *adev = psp->adev; 535 536 if (psp->adev->no_hw_access) 537 return 0; 538 539 for (i = 0; i < adev->usec_timeout; i++) { 540 val = RREG32(reg_index); 541 if (check_changed) { 542 if (val != reg_val) 543 return 0; 544 } else { 545 if ((val & mask) == reg_val) 546 return 0; 547 } 548 udelay(1); 549 } 550 551 return -ETIME; 552 } 553 554 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 555 { 556 switch (cmd_id) { 557 case GFX_CMD_ID_LOAD_TA: 558 return "LOAD_TA"; 559 case GFX_CMD_ID_UNLOAD_TA: 560 return "UNLOAD_TA"; 561 case GFX_CMD_ID_INVOKE_CMD: 562 return "INVOKE_CMD"; 563 case GFX_CMD_ID_LOAD_ASD: 564 return "LOAD_ASD"; 565 case GFX_CMD_ID_SETUP_TMR: 566 return "SETUP_TMR"; 567 case GFX_CMD_ID_LOAD_IP_FW: 568 return "LOAD_IP_FW"; 569 case GFX_CMD_ID_DESTROY_TMR: 570 return "DESTROY_TMR"; 571 case GFX_CMD_ID_SAVE_RESTORE: 572 return "SAVE_RESTORE_IP_FW"; 573 case GFX_CMD_ID_SETUP_VMR: 574 return "SETUP_VMR"; 575 case GFX_CMD_ID_DESTROY_VMR: 576 return "DESTROY_VMR"; 577 case GFX_CMD_ID_PROG_REG: 578 return "PROG_REG"; 579 case GFX_CMD_ID_GET_FW_ATTESTATION: 580 return "GET_FW_ATTESTATION"; 581 case GFX_CMD_ID_LOAD_TOC: 582 return "ID_LOAD_TOC"; 583 case GFX_CMD_ID_AUTOLOAD_RLC: 584 return "AUTOLOAD_RLC"; 585 case GFX_CMD_ID_BOOT_CFG: 586 return "BOOT_CFG"; 587 default: 588 return "UNKNOWN CMD"; 589 } 590 } 591 592 static int 593 psp_cmd_submit_buf(struct psp_context *psp, 594 struct amdgpu_firmware_info *ucode, 595 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 596 { 597 int ret; 598 int index, idx; 599 int timeout = 20000; 600 bool ras_intr = false; 601 bool skip_unsupport = false; 602 603 if (psp->adev->no_hw_access) 604 return 0; 605 606 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 607 return 0; 608 609 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 610 611 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 612 613 index = atomic_inc_return(&psp->fence_value); 614 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 615 if (ret) { 616 atomic_dec(&psp->fence_value); 617 goto exit; 618 } 619 620 amdgpu_device_invalidate_hdp(psp->adev, NULL); 621 while (*((unsigned int *)psp->fence_buf) != index) { 622 if (--timeout == 0) 623 break; 624 /* 625 * Shouldn't wait for timeout when err_event_athub occurs, 626 * because gpu reset thread triggered and lock resource should 627 * be released for psp resume sequence. 628 */ 629 ras_intr = amdgpu_ras_intr_triggered(); 630 if (ras_intr) 631 break; 632 usleep_range(10, 100); 633 amdgpu_device_invalidate_hdp(psp->adev, NULL); 634 } 635 636 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 637 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 638 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 639 640 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 641 642 /* In some cases, psp response status is not 0 even there is no 643 * problem while the command is submitted. Some version of PSP FW 644 * doesn't write 0 to that field. 645 * So here we would like to only print a warning instead of an error 646 * during psp initialization to avoid breaking hw_init and it doesn't 647 * return -EINVAL. 648 */ 649 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 650 if (ucode) 651 DRM_WARN("failed to load ucode %s(0x%X) ", 652 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 653 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 654 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 655 psp->cmd_buf_mem->resp.status); 656 /* If any firmware (including CAP) load fails under SRIOV, it should 657 * return failure to stop the VF from initializing. 658 * Also return failure in case of timeout 659 */ 660 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 661 ret = -EINVAL; 662 goto exit; 663 } 664 } 665 666 if (ucode) { 667 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 668 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 669 } 670 671 exit: 672 drm_dev_exit(idx); 673 return ret; 674 } 675 676 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 677 { 678 struct psp_gfx_cmd_resp *cmd = psp->cmd; 679 680 mutex_lock(&psp->mutex); 681 682 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 683 684 return cmd; 685 } 686 687 static void release_psp_cmd_buf(struct psp_context *psp) 688 { 689 mutex_unlock(&psp->mutex); 690 } 691 692 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 693 struct psp_gfx_cmd_resp *cmd, 694 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 695 { 696 struct amdgpu_device *adev = psp->adev; 697 uint32_t size = amdgpu_bo_size(tmr_bo); 698 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 699 700 if (amdgpu_sriov_vf(psp->adev)) 701 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 702 else 703 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 704 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 705 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 706 cmd->cmd.cmd_setup_tmr.buf_size = size; 707 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 708 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 709 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 710 } 711 712 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 713 uint64_t pri_buf_mc, uint32_t size) 714 { 715 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 716 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 717 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 718 cmd->cmd.cmd_load_toc.toc_size = size; 719 } 720 721 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 722 static int psp_load_toc(struct psp_context *psp, 723 uint32_t *tmr_size) 724 { 725 int ret; 726 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 727 728 /* Copy toc to psp firmware private buffer */ 729 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 730 731 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 732 733 ret = psp_cmd_submit_buf(psp, NULL, cmd, 734 psp->fence_buf_mc_addr); 735 if (!ret) 736 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 737 738 release_psp_cmd_buf(psp); 739 740 return ret; 741 } 742 743 /* Set up Trusted Memory Region */ 744 static int psp_tmr_init(struct psp_context *psp) 745 { 746 int ret; 747 int tmr_size; 748 void *tmr_buf; 749 void **pptr; 750 751 /* 752 * According to HW engineer, they prefer the TMR address be "naturally 753 * aligned" , e.g. the start address be an integer divide of TMR size. 754 * 755 * Note: this memory need be reserved till the driver 756 * uninitializes. 757 */ 758 tmr_size = PSP_TMR_SIZE(psp->adev); 759 760 /* For ASICs support RLC autoload, psp will parse the toc 761 * and calculate the total size of TMR needed */ 762 if (!amdgpu_sriov_vf(psp->adev) && 763 psp->toc.start_addr && 764 psp->toc.size_bytes && 765 psp->fw_pri_buf) { 766 ret = psp_load_toc(psp, &tmr_size); 767 if (ret) { 768 DRM_ERROR("Failed to load toc\n"); 769 return ret; 770 } 771 } 772 773 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 774 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT, 775 AMDGPU_GEM_DOMAIN_VRAM, 776 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 777 778 return ret; 779 } 780 781 static bool psp_skip_tmr(struct psp_context *psp) 782 { 783 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 784 case IP_VERSION(11, 0, 9): 785 case IP_VERSION(11, 0, 7): 786 case IP_VERSION(13, 0, 2): 787 case IP_VERSION(13, 0, 10): 788 return true; 789 default: 790 return false; 791 } 792 } 793 794 static int psp_tmr_load(struct psp_context *psp) 795 { 796 int ret; 797 struct psp_gfx_cmd_resp *cmd; 798 799 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 800 * Already set up by host driver. 801 */ 802 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 803 return 0; 804 805 cmd = acquire_psp_cmd_buf(psp); 806 807 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 808 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 809 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 810 811 ret = psp_cmd_submit_buf(psp, NULL, cmd, 812 psp->fence_buf_mc_addr); 813 814 release_psp_cmd_buf(psp); 815 816 return ret; 817 } 818 819 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 820 struct psp_gfx_cmd_resp *cmd) 821 { 822 if (amdgpu_sriov_vf(psp->adev)) 823 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 824 else 825 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 826 } 827 828 static int psp_tmr_unload(struct psp_context *psp) 829 { 830 int ret; 831 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 832 833 psp_prep_tmr_unload_cmd_buf(psp, cmd); 834 dev_info(psp->adev->dev, "free PSP TMR buffer\n"); 835 836 ret = psp_cmd_submit_buf(psp, NULL, cmd, 837 psp->fence_buf_mc_addr); 838 839 release_psp_cmd_buf(psp); 840 841 return ret; 842 } 843 844 static int psp_tmr_terminate(struct psp_context *psp) 845 { 846 return psp_tmr_unload(psp); 847 } 848 849 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 850 uint64_t *output_ptr) 851 { 852 int ret; 853 struct psp_gfx_cmd_resp *cmd; 854 855 if (!output_ptr) 856 return -EINVAL; 857 858 if (amdgpu_sriov_vf(psp->adev)) 859 return 0; 860 861 cmd = acquire_psp_cmd_buf(psp); 862 863 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 864 865 ret = psp_cmd_submit_buf(psp, NULL, cmd, 866 psp->fence_buf_mc_addr); 867 868 if (!ret) { 869 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 870 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 871 } 872 873 release_psp_cmd_buf(psp); 874 875 return ret; 876 } 877 878 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 879 { 880 struct psp_context *psp = &adev->psp; 881 struct psp_gfx_cmd_resp *cmd; 882 int ret; 883 884 if (amdgpu_sriov_vf(adev)) 885 return 0; 886 887 cmd = acquire_psp_cmd_buf(psp); 888 889 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 890 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 891 892 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 893 if (!ret) { 894 *boot_cfg = 895 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 896 } 897 898 release_psp_cmd_buf(psp); 899 900 return ret; 901 } 902 903 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 904 { 905 int ret; 906 struct psp_context *psp = &adev->psp; 907 struct psp_gfx_cmd_resp *cmd; 908 909 if (amdgpu_sriov_vf(adev)) 910 return 0; 911 912 cmd = acquire_psp_cmd_buf(psp); 913 914 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 915 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 916 cmd->cmd.boot_cfg.boot_config = boot_cfg; 917 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 918 919 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 920 921 release_psp_cmd_buf(psp); 922 923 return ret; 924 } 925 926 static int psp_rl_load(struct amdgpu_device *adev) 927 { 928 int ret; 929 struct psp_context *psp = &adev->psp; 930 struct psp_gfx_cmd_resp *cmd; 931 932 if (!is_psp_fw_valid(psp->rl)) 933 return 0; 934 935 cmd = acquire_psp_cmd_buf(psp); 936 937 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 938 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 939 940 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 941 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 942 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 943 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 944 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 945 946 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 947 948 release_psp_cmd_buf(psp); 949 950 return ret; 951 } 952 953 static int psp_asd_initialize(struct psp_context *psp) 954 { 955 int ret; 956 957 /* If PSP version doesn't match ASD version, asd loading will be failed. 958 * add workaround to bypass it for sriov now. 959 * TODO: add version check to make it common 960 */ 961 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 962 return 0; 963 964 psp->asd_context.mem_context.shared_mc_addr = 0; 965 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 966 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 967 968 ret = psp_ta_load(psp, &psp->asd_context); 969 if (!ret) 970 psp->asd_context.initialized = true; 971 972 return ret; 973 } 974 975 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 976 uint32_t session_id) 977 { 978 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 979 cmd->cmd.cmd_unload_ta.session_id = session_id; 980 } 981 982 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 983 { 984 int ret; 985 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 986 987 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 988 989 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 990 991 context->resp_status = cmd->resp.status; 992 993 release_psp_cmd_buf(psp); 994 995 return ret; 996 } 997 998 static int psp_asd_terminate(struct psp_context *psp) 999 { 1000 int ret; 1001 1002 if (amdgpu_sriov_vf(psp->adev)) 1003 return 0; 1004 1005 if (!psp->asd_context.initialized) 1006 return 0; 1007 1008 ret = psp_ta_unload(psp, &psp->asd_context); 1009 if (!ret) 1010 psp->asd_context.initialized = false; 1011 1012 return ret; 1013 } 1014 1015 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1016 uint32_t id, uint32_t value) 1017 { 1018 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1019 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1020 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1021 } 1022 1023 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1024 uint32_t value) 1025 { 1026 struct psp_gfx_cmd_resp *cmd; 1027 int ret = 0; 1028 1029 if (reg >= PSP_REG_LAST) 1030 return -EINVAL; 1031 1032 cmd = acquire_psp_cmd_buf(psp); 1033 1034 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1035 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1036 if (ret) 1037 DRM_ERROR("PSP failed to program reg id %d", reg); 1038 1039 release_psp_cmd_buf(psp); 1040 1041 return ret; 1042 } 1043 1044 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1045 uint64_t ta_bin_mc, 1046 struct ta_context *context) 1047 { 1048 cmd->cmd_id = context->ta_load_type; 1049 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1050 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1051 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1052 1053 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1054 lower_32_bits(context->mem_context.shared_mc_addr); 1055 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1056 upper_32_bits(context->mem_context.shared_mc_addr); 1057 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1058 } 1059 1060 int psp_ta_init_shared_buf(struct psp_context *psp, 1061 struct ta_mem_context *mem_ctx) 1062 { 1063 /* 1064 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1065 * physical) for ta to host memory 1066 */ 1067 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1068 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1069 &mem_ctx->shared_bo, 1070 &mem_ctx->shared_mc_addr, 1071 &mem_ctx->shared_buf); 1072 } 1073 1074 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1075 uint32_t ta_cmd_id, 1076 uint32_t session_id) 1077 { 1078 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1079 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1080 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1081 } 1082 1083 int psp_ta_invoke(struct psp_context *psp, 1084 uint32_t ta_cmd_id, 1085 struct ta_context *context) 1086 { 1087 int ret; 1088 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1089 1090 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1091 1092 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1093 psp->fence_buf_mc_addr); 1094 1095 context->resp_status = cmd->resp.status; 1096 1097 release_psp_cmd_buf(psp); 1098 1099 return ret; 1100 } 1101 1102 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1103 { 1104 int ret; 1105 struct psp_gfx_cmd_resp *cmd; 1106 1107 cmd = acquire_psp_cmd_buf(psp); 1108 1109 psp_copy_fw(psp, context->bin_desc.start_addr, 1110 context->bin_desc.size_bytes); 1111 1112 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1113 1114 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1115 psp->fence_buf_mc_addr); 1116 1117 context->resp_status = cmd->resp.status; 1118 1119 if (!ret) { 1120 context->session_id = cmd->resp.session_id; 1121 } 1122 1123 release_psp_cmd_buf(psp); 1124 1125 return ret; 1126 } 1127 1128 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1129 { 1130 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1131 } 1132 1133 int psp_xgmi_terminate(struct psp_context *psp) 1134 { 1135 int ret; 1136 struct amdgpu_device *adev = psp->adev; 1137 1138 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1139 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1140 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1141 adev->gmc.xgmi.connected_to_cpu)) 1142 return 0; 1143 1144 if (!psp->xgmi_context.context.initialized) 1145 return 0; 1146 1147 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1148 1149 psp->xgmi_context.context.initialized = false; 1150 1151 return ret; 1152 } 1153 1154 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1155 { 1156 struct ta_xgmi_shared_memory *xgmi_cmd; 1157 int ret; 1158 1159 if (!psp->ta_fw || 1160 !psp->xgmi_context.context.bin_desc.size_bytes || 1161 !psp->xgmi_context.context.bin_desc.start_addr) 1162 return -ENOENT; 1163 1164 if (!load_ta) 1165 goto invoke; 1166 1167 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1168 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1169 1170 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1171 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1172 if (ret) 1173 return ret; 1174 } 1175 1176 /* Load XGMI TA */ 1177 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1178 if (!ret) 1179 psp->xgmi_context.context.initialized = true; 1180 else 1181 return ret; 1182 1183 invoke: 1184 /* Initialize XGMI session */ 1185 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1186 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1187 xgmi_cmd->flag_extend_link_record = set_extended_data; 1188 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1189 1190 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1191 1192 return ret; 1193 } 1194 1195 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1196 { 1197 struct ta_xgmi_shared_memory *xgmi_cmd; 1198 int ret; 1199 1200 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1201 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1202 1203 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1204 1205 /* Invoke xgmi ta to get hive id */ 1206 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1207 if (ret) 1208 return ret; 1209 1210 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1211 1212 return 0; 1213 } 1214 1215 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1216 { 1217 struct ta_xgmi_shared_memory *xgmi_cmd; 1218 int ret; 1219 1220 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1221 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1222 1223 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1224 1225 /* Invoke xgmi ta to get the node id */ 1226 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1227 if (ret) 1228 return ret; 1229 1230 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1231 1232 return 0; 1233 } 1234 1235 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1236 { 1237 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1238 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1239 } 1240 1241 /* 1242 * Chips that support extended topology information require the driver to 1243 * reflect topology information in the opposite direction. This is 1244 * because the TA has already exceeded its link record limit and if the 1245 * TA holds bi-directional information, the driver would have to do 1246 * multiple fetches instead of just two. 1247 */ 1248 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1249 struct psp_xgmi_node_info node_info) 1250 { 1251 struct amdgpu_device *mirror_adev; 1252 struct amdgpu_hive_info *hive; 1253 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1254 uint64_t dst_node_id = node_info.node_id; 1255 uint8_t dst_num_hops = node_info.num_hops; 1256 uint8_t dst_num_links = node_info.num_links; 1257 1258 hive = amdgpu_get_xgmi_hive(psp->adev); 1259 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1260 struct psp_xgmi_topology_info *mirror_top_info; 1261 int j; 1262 1263 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1264 continue; 1265 1266 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1267 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1268 if (mirror_top_info->nodes[j].node_id != src_node_id) 1269 continue; 1270 1271 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1272 /* 1273 * prevent 0 num_links value re-reflection since reflection 1274 * criteria is based on num_hops (direct or indirect). 1275 * 1276 */ 1277 if (dst_num_links) 1278 mirror_top_info->nodes[j].num_links = dst_num_links; 1279 1280 break; 1281 } 1282 1283 break; 1284 } 1285 1286 amdgpu_put_xgmi_hive(hive); 1287 } 1288 1289 int psp_xgmi_get_topology_info(struct psp_context *psp, 1290 int number_devices, 1291 struct psp_xgmi_topology_info *topology, 1292 bool get_extended_data) 1293 { 1294 struct ta_xgmi_shared_memory *xgmi_cmd; 1295 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1296 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1297 int i; 1298 int ret; 1299 1300 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1301 return -EINVAL; 1302 1303 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1304 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1305 xgmi_cmd->flag_extend_link_record = get_extended_data; 1306 1307 /* Fill in the shared memory with topology information as input */ 1308 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1309 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1310 topology_info_input->num_nodes = number_devices; 1311 1312 for (i = 0; i < topology_info_input->num_nodes; i++) { 1313 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1314 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1315 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1316 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1317 } 1318 1319 /* Invoke xgmi ta to get the topology information */ 1320 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1321 if (ret) 1322 return ret; 1323 1324 /* Read the output topology information from the shared memory */ 1325 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1326 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1327 for (i = 0; i < topology->num_nodes; i++) { 1328 /* extended data will either be 0 or equal to non-extended data */ 1329 if (topology_info_output->nodes[i].num_hops) 1330 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1331 1332 /* non-extended data gets everything here so no need to update */ 1333 if (!get_extended_data) { 1334 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1335 topology->nodes[i].is_sharing_enabled = 1336 topology_info_output->nodes[i].is_sharing_enabled; 1337 topology->nodes[i].sdma_engine = 1338 topology_info_output->nodes[i].sdma_engine; 1339 } 1340 1341 } 1342 1343 /* Invoke xgmi ta again to get the link information */ 1344 if (psp_xgmi_peer_link_info_supported(psp)) { 1345 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1346 1347 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1348 1349 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1350 1351 if (ret) 1352 return ret; 1353 1354 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1355 for (i = 0; i < topology->num_nodes; i++) { 1356 /* accumulate num_links on extended data */ 1357 topology->nodes[i].num_links = get_extended_data ? 1358 topology->nodes[i].num_links + 1359 link_info_output->nodes[i].num_links : 1360 link_info_output->nodes[i].num_links; 1361 1362 /* reflect the topology information for bi-directionality */ 1363 if (psp->xgmi_context.supports_extended_data && 1364 get_extended_data && topology->nodes[i].num_hops) 1365 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1366 } 1367 } 1368 1369 return 0; 1370 } 1371 1372 int psp_xgmi_set_topology_info(struct psp_context *psp, 1373 int number_devices, 1374 struct psp_xgmi_topology_info *topology) 1375 { 1376 struct ta_xgmi_shared_memory *xgmi_cmd; 1377 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1378 int i; 1379 1380 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1381 return -EINVAL; 1382 1383 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1384 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1385 1386 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1387 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1388 topology_info_input->num_nodes = number_devices; 1389 1390 for (i = 0; i < topology_info_input->num_nodes; i++) { 1391 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1392 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1393 topology_info_input->nodes[i].is_sharing_enabled = 1; 1394 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1395 } 1396 1397 /* Invoke xgmi ta to set topology information */ 1398 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1399 } 1400 1401 // ras begin 1402 static void psp_ras_ta_check_status(struct psp_context *psp) 1403 { 1404 struct ta_ras_shared_memory *ras_cmd = 1405 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1406 1407 switch (ras_cmd->ras_status) { 1408 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1409 dev_warn(psp->adev->dev, 1410 "RAS WARNING: cmd failed due to unsupported ip\n"); 1411 break; 1412 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1413 dev_warn(psp->adev->dev, 1414 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1415 break; 1416 case TA_RAS_STATUS__SUCCESS: 1417 break; 1418 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1419 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1420 dev_warn(psp->adev->dev, 1421 "RAS WARNING: Inject error to critical region is not allowed\n"); 1422 break; 1423 default: 1424 dev_warn(psp->adev->dev, 1425 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1426 break; 1427 } 1428 } 1429 1430 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1431 { 1432 struct ta_ras_shared_memory *ras_cmd; 1433 int ret; 1434 1435 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1436 1437 /* 1438 * TODO: bypass the loading in sriov for now 1439 */ 1440 if (amdgpu_sriov_vf(psp->adev)) 1441 return 0; 1442 1443 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1444 1445 if (amdgpu_ras_intr_triggered()) 1446 return ret; 1447 1448 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1449 { 1450 DRM_WARN("RAS: Unsupported Interface"); 1451 return -EINVAL; 1452 } 1453 1454 if (!ret) { 1455 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1456 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1457 1458 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1459 } 1460 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1461 dev_warn(psp->adev->dev, 1462 "RAS internal register access blocked\n"); 1463 1464 psp_ras_ta_check_status(psp); 1465 } 1466 1467 return ret; 1468 } 1469 1470 int psp_ras_enable_features(struct psp_context *psp, 1471 union ta_ras_cmd_input *info, bool enable) 1472 { 1473 struct ta_ras_shared_memory *ras_cmd; 1474 int ret; 1475 1476 if (!psp->ras_context.context.initialized) 1477 return -EINVAL; 1478 1479 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1480 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1481 1482 if (enable) 1483 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1484 else 1485 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1486 1487 ras_cmd->ras_in_message = *info; 1488 1489 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1490 if (ret) 1491 return -EINVAL; 1492 1493 return 0; 1494 } 1495 1496 int psp_ras_terminate(struct psp_context *psp) 1497 { 1498 int ret; 1499 1500 /* 1501 * TODO: bypass the terminate in sriov for now 1502 */ 1503 if (amdgpu_sriov_vf(psp->adev)) 1504 return 0; 1505 1506 if (!psp->ras_context.context.initialized) 1507 return 0; 1508 1509 ret = psp_ta_unload(psp, &psp->ras_context.context); 1510 1511 psp->ras_context.context.initialized = false; 1512 1513 return ret; 1514 } 1515 1516 int psp_ras_initialize(struct psp_context *psp) 1517 { 1518 int ret; 1519 uint32_t boot_cfg = 0xFF; 1520 struct amdgpu_device *adev = psp->adev; 1521 struct ta_ras_shared_memory *ras_cmd; 1522 1523 /* 1524 * TODO: bypass the initialize in sriov for now 1525 */ 1526 if (amdgpu_sriov_vf(adev)) 1527 return 0; 1528 1529 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1530 !adev->psp.ras_context.context.bin_desc.start_addr) { 1531 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1532 return 0; 1533 } 1534 1535 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1536 /* query GECC enablement status from boot config 1537 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1538 */ 1539 ret = psp_boot_config_get(adev, &boot_cfg); 1540 if (ret) 1541 dev_warn(adev->dev, "PSP get boot config failed\n"); 1542 1543 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1544 if (!boot_cfg) { 1545 dev_info(adev->dev, "GECC is disabled\n"); 1546 } else { 1547 /* disable GECC in next boot cycle if ras is 1548 * disabled by module parameter amdgpu_ras_enable 1549 * and/or amdgpu_ras_mask, or boot_config_get call 1550 * is failed 1551 */ 1552 ret = psp_boot_config_set(adev, 0); 1553 if (ret) 1554 dev_warn(adev->dev, "PSP set boot config failed\n"); 1555 else 1556 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1557 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1558 } 1559 } else { 1560 if (1 == boot_cfg) { 1561 dev_info(adev->dev, "GECC is enabled\n"); 1562 } else { 1563 /* enable GECC in next boot cycle if it is disabled 1564 * in boot config, or force enable GECC if failed to 1565 * get boot configuration 1566 */ 1567 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1568 if (ret) 1569 dev_warn(adev->dev, "PSP set boot config failed\n"); 1570 else 1571 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1572 } 1573 } 1574 } 1575 1576 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1577 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1578 1579 if (!psp->ras_context.context.mem_context.shared_buf) { 1580 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1581 if (ret) 1582 return ret; 1583 } 1584 1585 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1586 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1587 1588 if (amdgpu_ras_is_poison_mode_supported(adev)) 1589 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1590 if (!adev->gmc.xgmi.connected_to_cpu) 1591 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1592 1593 ret = psp_ta_load(psp, &psp->ras_context.context); 1594 1595 if (!ret && !ras_cmd->ras_status) 1596 psp->ras_context.context.initialized = true; 1597 else { 1598 if (ras_cmd->ras_status) 1599 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1600 1601 /* fail to load RAS TA */ 1602 psp->ras_context.context.initialized = false; 1603 } 1604 1605 return ret; 1606 } 1607 1608 int psp_ras_trigger_error(struct psp_context *psp, 1609 struct ta_ras_trigger_error_input *info) 1610 { 1611 struct ta_ras_shared_memory *ras_cmd; 1612 int ret; 1613 1614 if (!psp->ras_context.context.initialized) 1615 return -EINVAL; 1616 1617 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1618 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1619 1620 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1621 ras_cmd->ras_in_message.trigger_error = *info; 1622 1623 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1624 if (ret) 1625 return -EINVAL; 1626 1627 /* If err_event_athub occurs error inject was successful, however 1628 return status from TA is no long reliable */ 1629 if (amdgpu_ras_intr_triggered()) 1630 return 0; 1631 1632 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1633 return -EACCES; 1634 else if (ras_cmd->ras_status) 1635 return -EINVAL; 1636 1637 return 0; 1638 } 1639 // ras end 1640 1641 // HDCP start 1642 static int psp_hdcp_initialize(struct psp_context *psp) 1643 { 1644 int ret; 1645 1646 /* 1647 * TODO: bypass the initialize in sriov for now 1648 */ 1649 if (amdgpu_sriov_vf(psp->adev)) 1650 return 0; 1651 1652 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1653 !psp->hdcp_context.context.bin_desc.start_addr) { 1654 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1655 return 0; 1656 } 1657 1658 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1659 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1660 1661 if (!psp->hdcp_context.context.initialized) { 1662 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1663 if (ret) 1664 return ret; 1665 } 1666 1667 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1668 if (!ret) { 1669 psp->hdcp_context.context.initialized = true; 1670 mutex_init(&psp->hdcp_context.mutex); 1671 } 1672 1673 return ret; 1674 } 1675 1676 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1677 { 1678 /* 1679 * TODO: bypass the loading in sriov for now 1680 */ 1681 if (amdgpu_sriov_vf(psp->adev)) 1682 return 0; 1683 1684 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1685 } 1686 1687 static int psp_hdcp_terminate(struct psp_context *psp) 1688 { 1689 int ret; 1690 1691 /* 1692 * TODO: bypass the terminate in sriov for now 1693 */ 1694 if (amdgpu_sriov_vf(psp->adev)) 1695 return 0; 1696 1697 if (!psp->hdcp_context.context.initialized) 1698 return 0; 1699 1700 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1701 1702 psp->hdcp_context.context.initialized = false; 1703 1704 return ret; 1705 } 1706 // HDCP end 1707 1708 // DTM start 1709 static int psp_dtm_initialize(struct psp_context *psp) 1710 { 1711 int ret; 1712 1713 /* 1714 * TODO: bypass the initialize in sriov for now 1715 */ 1716 if (amdgpu_sriov_vf(psp->adev)) 1717 return 0; 1718 1719 if (!psp->dtm_context.context.bin_desc.size_bytes || 1720 !psp->dtm_context.context.bin_desc.start_addr) { 1721 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1722 return 0; 1723 } 1724 1725 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1726 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1727 1728 if (!psp->dtm_context.context.initialized) { 1729 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1730 if (ret) 1731 return ret; 1732 } 1733 1734 ret = psp_ta_load(psp, &psp->dtm_context.context); 1735 if (!ret) { 1736 psp->dtm_context.context.initialized = true; 1737 mutex_init(&psp->dtm_context.mutex); 1738 } 1739 1740 return ret; 1741 } 1742 1743 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1744 { 1745 /* 1746 * TODO: bypass the loading in sriov for now 1747 */ 1748 if (amdgpu_sriov_vf(psp->adev)) 1749 return 0; 1750 1751 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1752 } 1753 1754 static int psp_dtm_terminate(struct psp_context *psp) 1755 { 1756 int ret; 1757 1758 /* 1759 * TODO: bypass the terminate in sriov for now 1760 */ 1761 if (amdgpu_sriov_vf(psp->adev)) 1762 return 0; 1763 1764 if (!psp->dtm_context.context.initialized) 1765 return 0; 1766 1767 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1768 1769 psp->dtm_context.context.initialized = false; 1770 1771 return ret; 1772 } 1773 // DTM end 1774 1775 // RAP start 1776 static int psp_rap_initialize(struct psp_context *psp) 1777 { 1778 int ret; 1779 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1780 1781 /* 1782 * TODO: bypass the initialize in sriov for now 1783 */ 1784 if (amdgpu_sriov_vf(psp->adev)) 1785 return 0; 1786 1787 if (!psp->rap_context.context.bin_desc.size_bytes || 1788 !psp->rap_context.context.bin_desc.start_addr) { 1789 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1790 return 0; 1791 } 1792 1793 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1794 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1795 1796 if (!psp->rap_context.context.initialized) { 1797 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1798 if (ret) 1799 return ret; 1800 } 1801 1802 ret = psp_ta_load(psp, &psp->rap_context.context); 1803 if (!ret) { 1804 psp->rap_context.context.initialized = true; 1805 mutex_init(&psp->rap_context.mutex); 1806 } else 1807 return ret; 1808 1809 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1810 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1811 psp_rap_terminate(psp); 1812 /* free rap shared memory */ 1813 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1814 1815 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1816 ret, status); 1817 1818 return ret; 1819 } 1820 1821 return 0; 1822 } 1823 1824 static int psp_rap_terminate(struct psp_context *psp) 1825 { 1826 int ret; 1827 1828 if (!psp->rap_context.context.initialized) 1829 return 0; 1830 1831 ret = psp_ta_unload(psp, &psp->rap_context.context); 1832 1833 psp->rap_context.context.initialized = false; 1834 1835 return ret; 1836 } 1837 1838 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1839 { 1840 struct ta_rap_shared_memory *rap_cmd; 1841 int ret = 0; 1842 1843 if (!psp->rap_context.context.initialized) 1844 return 0; 1845 1846 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1847 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1848 return -EINVAL; 1849 1850 mutex_lock(&psp->rap_context.mutex); 1851 1852 rap_cmd = (struct ta_rap_shared_memory *) 1853 psp->rap_context.context.mem_context.shared_buf; 1854 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1855 1856 rap_cmd->cmd_id = ta_cmd_id; 1857 rap_cmd->validation_method_id = METHOD_A; 1858 1859 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1860 if (ret) 1861 goto out_unlock; 1862 1863 if (status) 1864 *status = rap_cmd->rap_status; 1865 1866 out_unlock: 1867 mutex_unlock(&psp->rap_context.mutex); 1868 1869 return ret; 1870 } 1871 // RAP end 1872 1873 /* securedisplay start */ 1874 static int psp_securedisplay_initialize(struct psp_context *psp) 1875 { 1876 int ret; 1877 struct securedisplay_cmd *securedisplay_cmd; 1878 1879 /* 1880 * TODO: bypass the initialize in sriov for now 1881 */ 1882 if (amdgpu_sriov_vf(psp->adev)) 1883 return 0; 1884 1885 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1886 !psp->securedisplay_context.context.bin_desc.start_addr) { 1887 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1888 return 0; 1889 } 1890 1891 psp->securedisplay_context.context.mem_context.shared_mem_size = 1892 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1893 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1894 1895 if (!psp->securedisplay_context.context.initialized) { 1896 ret = psp_ta_init_shared_buf(psp, 1897 &psp->securedisplay_context.context.mem_context); 1898 if (ret) 1899 return ret; 1900 } 1901 1902 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 1903 if (!ret) { 1904 psp->securedisplay_context.context.initialized = true; 1905 mutex_init(&psp->securedisplay_context.mutex); 1906 } else 1907 return ret; 1908 1909 mutex_lock(&psp->securedisplay_context.mutex); 1910 1911 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1912 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1913 1914 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1915 1916 mutex_unlock(&psp->securedisplay_context.mutex); 1917 1918 if (ret) { 1919 psp_securedisplay_terminate(psp); 1920 /* free securedisplay shared memory */ 1921 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1922 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1923 return -EINVAL; 1924 } 1925 1926 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1927 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1928 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1929 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1930 } 1931 1932 return 0; 1933 } 1934 1935 static int psp_securedisplay_terminate(struct psp_context *psp) 1936 { 1937 int ret; 1938 1939 /* 1940 * TODO:bypass the terminate in sriov for now 1941 */ 1942 if (amdgpu_sriov_vf(psp->adev)) 1943 return 0; 1944 1945 if (!psp->securedisplay_context.context.initialized) 1946 return 0; 1947 1948 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 1949 1950 psp->securedisplay_context.context.initialized = false; 1951 1952 return ret; 1953 } 1954 1955 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1956 { 1957 int ret; 1958 1959 if (!psp->securedisplay_context.context.initialized) 1960 return -EINVAL; 1961 1962 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1963 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1964 return -EINVAL; 1965 1966 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1967 1968 return ret; 1969 } 1970 /* SECUREDISPLAY end */ 1971 1972 static int psp_hw_start(struct psp_context *psp) 1973 { 1974 struct amdgpu_device *adev = psp->adev; 1975 int ret; 1976 1977 if (!amdgpu_sriov_vf(adev)) { 1978 if ((is_psp_fw_valid(psp->kdb)) && 1979 (psp->funcs->bootloader_load_kdb != NULL)) { 1980 ret = psp_bootloader_load_kdb(psp); 1981 if (ret) { 1982 DRM_ERROR("PSP load kdb failed!\n"); 1983 return ret; 1984 } 1985 } 1986 1987 if ((is_psp_fw_valid(psp->spl)) && 1988 (psp->funcs->bootloader_load_spl != NULL)) { 1989 ret = psp_bootloader_load_spl(psp); 1990 if (ret) { 1991 DRM_ERROR("PSP load spl failed!\n"); 1992 return ret; 1993 } 1994 } 1995 1996 if ((is_psp_fw_valid(psp->sys)) && 1997 (psp->funcs->bootloader_load_sysdrv != NULL)) { 1998 ret = psp_bootloader_load_sysdrv(psp); 1999 if (ret) { 2000 DRM_ERROR("PSP load sys drv failed!\n"); 2001 return ret; 2002 } 2003 } 2004 2005 if ((is_psp_fw_valid(psp->soc_drv)) && 2006 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2007 ret = psp_bootloader_load_soc_drv(psp); 2008 if (ret) { 2009 DRM_ERROR("PSP load soc drv failed!\n"); 2010 return ret; 2011 } 2012 } 2013 2014 if ((is_psp_fw_valid(psp->intf_drv)) && 2015 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2016 ret = psp_bootloader_load_intf_drv(psp); 2017 if (ret) { 2018 DRM_ERROR("PSP load intf drv failed!\n"); 2019 return ret; 2020 } 2021 } 2022 2023 if ((is_psp_fw_valid(psp->dbg_drv)) && 2024 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2025 ret = psp_bootloader_load_dbg_drv(psp); 2026 if (ret) { 2027 DRM_ERROR("PSP load dbg drv failed!\n"); 2028 return ret; 2029 } 2030 } 2031 2032 if ((is_psp_fw_valid(psp->ras_drv)) && 2033 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2034 ret = psp_bootloader_load_ras_drv(psp); 2035 if (ret) { 2036 DRM_ERROR("PSP load ras_drv failed!\n"); 2037 return ret; 2038 } 2039 } 2040 2041 if ((is_psp_fw_valid(psp->sos)) && 2042 (psp->funcs->bootloader_load_sos != NULL)) { 2043 ret = psp_bootloader_load_sos(psp); 2044 if (ret) { 2045 DRM_ERROR("PSP load sos failed!\n"); 2046 return ret; 2047 } 2048 } 2049 } 2050 2051 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2052 if (ret) { 2053 DRM_ERROR("PSP create ring failed!\n"); 2054 return ret; 2055 } 2056 2057 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2058 goto skip_pin_bo; 2059 2060 ret = psp_tmr_init(psp); 2061 if (ret) { 2062 DRM_ERROR("PSP tmr init failed!\n"); 2063 return ret; 2064 } 2065 2066 skip_pin_bo: 2067 /* 2068 * For ASICs with DF Cstate management centralized 2069 * to PMFW, TMR setup should be performed after PMFW 2070 * loaded and before other non-psp firmware loaded. 2071 */ 2072 if (psp->pmfw_centralized_cstate_management) { 2073 ret = psp_load_smu_fw(psp); 2074 if (ret) 2075 return ret; 2076 } 2077 2078 ret = psp_tmr_load(psp); 2079 if (ret) { 2080 DRM_ERROR("PSP load tmr failed!\n"); 2081 return ret; 2082 } 2083 2084 return 0; 2085 } 2086 2087 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2088 enum psp_gfx_fw_type *type) 2089 { 2090 switch (ucode->ucode_id) { 2091 case AMDGPU_UCODE_ID_CAP: 2092 *type = GFX_FW_TYPE_CAP; 2093 break; 2094 case AMDGPU_UCODE_ID_SDMA0: 2095 *type = GFX_FW_TYPE_SDMA0; 2096 break; 2097 case AMDGPU_UCODE_ID_SDMA1: 2098 *type = GFX_FW_TYPE_SDMA1; 2099 break; 2100 case AMDGPU_UCODE_ID_SDMA2: 2101 *type = GFX_FW_TYPE_SDMA2; 2102 break; 2103 case AMDGPU_UCODE_ID_SDMA3: 2104 *type = GFX_FW_TYPE_SDMA3; 2105 break; 2106 case AMDGPU_UCODE_ID_SDMA4: 2107 *type = GFX_FW_TYPE_SDMA4; 2108 break; 2109 case AMDGPU_UCODE_ID_SDMA5: 2110 *type = GFX_FW_TYPE_SDMA5; 2111 break; 2112 case AMDGPU_UCODE_ID_SDMA6: 2113 *type = GFX_FW_TYPE_SDMA6; 2114 break; 2115 case AMDGPU_UCODE_ID_SDMA7: 2116 *type = GFX_FW_TYPE_SDMA7; 2117 break; 2118 case AMDGPU_UCODE_ID_CP_MES: 2119 *type = GFX_FW_TYPE_CP_MES; 2120 break; 2121 case AMDGPU_UCODE_ID_CP_MES_DATA: 2122 *type = GFX_FW_TYPE_MES_STACK; 2123 break; 2124 case AMDGPU_UCODE_ID_CP_MES1: 2125 *type = GFX_FW_TYPE_CP_MES_KIQ; 2126 break; 2127 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2128 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2129 break; 2130 case AMDGPU_UCODE_ID_CP_CE: 2131 *type = GFX_FW_TYPE_CP_CE; 2132 break; 2133 case AMDGPU_UCODE_ID_CP_PFP: 2134 *type = GFX_FW_TYPE_CP_PFP; 2135 break; 2136 case AMDGPU_UCODE_ID_CP_ME: 2137 *type = GFX_FW_TYPE_CP_ME; 2138 break; 2139 case AMDGPU_UCODE_ID_CP_MEC1: 2140 *type = GFX_FW_TYPE_CP_MEC; 2141 break; 2142 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2143 *type = GFX_FW_TYPE_CP_MEC_ME1; 2144 break; 2145 case AMDGPU_UCODE_ID_CP_MEC2: 2146 *type = GFX_FW_TYPE_CP_MEC; 2147 break; 2148 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2149 *type = GFX_FW_TYPE_CP_MEC_ME2; 2150 break; 2151 case AMDGPU_UCODE_ID_RLC_P: 2152 *type = GFX_FW_TYPE_RLC_P; 2153 break; 2154 case AMDGPU_UCODE_ID_RLC_V: 2155 *type = GFX_FW_TYPE_RLC_V; 2156 break; 2157 case AMDGPU_UCODE_ID_RLC_G: 2158 *type = GFX_FW_TYPE_RLC_G; 2159 break; 2160 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2161 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2162 break; 2163 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2164 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2165 break; 2166 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2167 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2168 break; 2169 case AMDGPU_UCODE_ID_RLC_IRAM: 2170 *type = GFX_FW_TYPE_RLC_IRAM; 2171 break; 2172 case AMDGPU_UCODE_ID_RLC_DRAM: 2173 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2174 break; 2175 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2176 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2177 break; 2178 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2179 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2180 break; 2181 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2182 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2183 break; 2184 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2185 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2186 break; 2187 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2188 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2189 break; 2190 case AMDGPU_UCODE_ID_SMC: 2191 *type = GFX_FW_TYPE_SMU; 2192 break; 2193 case AMDGPU_UCODE_ID_PPTABLE: 2194 *type = GFX_FW_TYPE_PPTABLE; 2195 break; 2196 case AMDGPU_UCODE_ID_UVD: 2197 *type = GFX_FW_TYPE_UVD; 2198 break; 2199 case AMDGPU_UCODE_ID_UVD1: 2200 *type = GFX_FW_TYPE_UVD1; 2201 break; 2202 case AMDGPU_UCODE_ID_VCE: 2203 *type = GFX_FW_TYPE_VCE; 2204 break; 2205 case AMDGPU_UCODE_ID_VCN: 2206 *type = GFX_FW_TYPE_VCN; 2207 break; 2208 case AMDGPU_UCODE_ID_VCN1: 2209 *type = GFX_FW_TYPE_VCN1; 2210 break; 2211 case AMDGPU_UCODE_ID_DMCU_ERAM: 2212 *type = GFX_FW_TYPE_DMCU_ERAM; 2213 break; 2214 case AMDGPU_UCODE_ID_DMCU_INTV: 2215 *type = GFX_FW_TYPE_DMCU_ISR; 2216 break; 2217 case AMDGPU_UCODE_ID_VCN0_RAM: 2218 *type = GFX_FW_TYPE_VCN0_RAM; 2219 break; 2220 case AMDGPU_UCODE_ID_VCN1_RAM: 2221 *type = GFX_FW_TYPE_VCN1_RAM; 2222 break; 2223 case AMDGPU_UCODE_ID_DMCUB: 2224 *type = GFX_FW_TYPE_DMUB; 2225 break; 2226 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2227 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2228 break; 2229 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2230 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2231 break; 2232 case AMDGPU_UCODE_ID_IMU_I: 2233 *type = GFX_FW_TYPE_IMU_I; 2234 break; 2235 case AMDGPU_UCODE_ID_IMU_D: 2236 *type = GFX_FW_TYPE_IMU_D; 2237 break; 2238 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2239 *type = GFX_FW_TYPE_RS64_PFP; 2240 break; 2241 case AMDGPU_UCODE_ID_CP_RS64_ME: 2242 *type = GFX_FW_TYPE_RS64_ME; 2243 break; 2244 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2245 *type = GFX_FW_TYPE_RS64_MEC; 2246 break; 2247 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2248 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2249 break; 2250 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2251 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2252 break; 2253 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2254 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2255 break; 2256 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2257 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2258 break; 2259 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2260 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2261 break; 2262 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2263 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2264 break; 2265 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2266 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2267 break; 2268 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2269 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2270 break; 2271 case AMDGPU_UCODE_ID_MAXIMUM: 2272 default: 2273 return -EINVAL; 2274 } 2275 2276 return 0; 2277 } 2278 2279 static void psp_print_fw_hdr(struct psp_context *psp, 2280 struct amdgpu_firmware_info *ucode) 2281 { 2282 struct amdgpu_device *adev = psp->adev; 2283 struct common_firmware_header *hdr; 2284 2285 switch (ucode->ucode_id) { 2286 case AMDGPU_UCODE_ID_SDMA0: 2287 case AMDGPU_UCODE_ID_SDMA1: 2288 case AMDGPU_UCODE_ID_SDMA2: 2289 case AMDGPU_UCODE_ID_SDMA3: 2290 case AMDGPU_UCODE_ID_SDMA4: 2291 case AMDGPU_UCODE_ID_SDMA5: 2292 case AMDGPU_UCODE_ID_SDMA6: 2293 case AMDGPU_UCODE_ID_SDMA7: 2294 hdr = (struct common_firmware_header *) 2295 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2296 amdgpu_ucode_print_sdma_hdr(hdr); 2297 break; 2298 case AMDGPU_UCODE_ID_CP_CE: 2299 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2300 amdgpu_ucode_print_gfx_hdr(hdr); 2301 break; 2302 case AMDGPU_UCODE_ID_CP_PFP: 2303 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2304 amdgpu_ucode_print_gfx_hdr(hdr); 2305 break; 2306 case AMDGPU_UCODE_ID_CP_ME: 2307 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2308 amdgpu_ucode_print_gfx_hdr(hdr); 2309 break; 2310 case AMDGPU_UCODE_ID_CP_MEC1: 2311 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2312 amdgpu_ucode_print_gfx_hdr(hdr); 2313 break; 2314 case AMDGPU_UCODE_ID_RLC_G: 2315 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2316 amdgpu_ucode_print_rlc_hdr(hdr); 2317 break; 2318 case AMDGPU_UCODE_ID_SMC: 2319 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2320 amdgpu_ucode_print_smc_hdr(hdr); 2321 break; 2322 default: 2323 break; 2324 } 2325 } 2326 2327 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2328 struct psp_gfx_cmd_resp *cmd) 2329 { 2330 int ret; 2331 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2332 2333 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2334 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2335 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2336 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2337 2338 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2339 if (ret) 2340 DRM_ERROR("Unknown firmware type\n"); 2341 2342 return ret; 2343 } 2344 2345 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2346 struct amdgpu_firmware_info *ucode) 2347 { 2348 int ret = 0; 2349 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2350 2351 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2352 if (!ret) { 2353 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2354 psp->fence_buf_mc_addr); 2355 } 2356 2357 release_psp_cmd_buf(psp); 2358 2359 return ret; 2360 } 2361 2362 static int psp_load_smu_fw(struct psp_context *psp) 2363 { 2364 int ret; 2365 struct amdgpu_device *adev = psp->adev; 2366 struct amdgpu_firmware_info *ucode = 2367 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2368 struct amdgpu_ras *ras = psp->ras_context.ras; 2369 2370 /* 2371 * Skip SMU FW reloading in case of using BACO for runpm only, 2372 * as SMU is always alive. 2373 */ 2374 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2375 return 0; 2376 2377 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2378 return 0; 2379 2380 if ((amdgpu_in_reset(adev) && 2381 ras && adev->ras_enabled && 2382 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2383 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2384 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2385 if (ret) { 2386 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2387 } 2388 } 2389 2390 ret = psp_execute_non_psp_fw_load(psp, ucode); 2391 2392 if (ret) 2393 DRM_ERROR("PSP load smu failed!\n"); 2394 2395 return ret; 2396 } 2397 2398 static bool fw_load_skip_check(struct psp_context *psp, 2399 struct amdgpu_firmware_info *ucode) 2400 { 2401 if (!ucode->fw || !ucode->ucode_size) 2402 return true; 2403 2404 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2405 (psp_smu_reload_quirk(psp) || 2406 psp->autoload_supported || 2407 psp->pmfw_centralized_cstate_management)) 2408 return true; 2409 2410 if (amdgpu_sriov_vf(psp->adev) && 2411 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2412 return true; 2413 2414 if (psp->autoload_supported && 2415 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2416 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2417 /* skip mec JT when autoload is enabled */ 2418 return true; 2419 2420 return false; 2421 } 2422 2423 int psp_load_fw_list(struct psp_context *psp, 2424 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2425 { 2426 int ret = 0, i; 2427 struct amdgpu_firmware_info *ucode; 2428 2429 for (i = 0; i < ucode_count; ++i) { 2430 ucode = ucode_list[i]; 2431 psp_print_fw_hdr(psp, ucode); 2432 ret = psp_execute_non_psp_fw_load(psp, ucode); 2433 if (ret) 2434 return ret; 2435 } 2436 return ret; 2437 } 2438 2439 static int psp_load_non_psp_fw(struct psp_context *psp) 2440 { 2441 int i, ret; 2442 struct amdgpu_firmware_info *ucode; 2443 struct amdgpu_device *adev = psp->adev; 2444 2445 if (psp->autoload_supported && 2446 !psp->pmfw_centralized_cstate_management) { 2447 ret = psp_load_smu_fw(psp); 2448 if (ret) 2449 return ret; 2450 } 2451 2452 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2453 ucode = &adev->firmware.ucode[i]; 2454 2455 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2456 !fw_load_skip_check(psp, ucode)) { 2457 ret = psp_load_smu_fw(psp); 2458 if (ret) 2459 return ret; 2460 continue; 2461 } 2462 2463 if (fw_load_skip_check(psp, ucode)) 2464 continue; 2465 2466 if (psp->autoload_supported && 2467 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2468 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2469 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2470 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2471 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2472 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2473 /* PSP only receive one SDMA fw for sienna_cichlid, 2474 * as all four sdma fw are same */ 2475 continue; 2476 2477 psp_print_fw_hdr(psp, ucode); 2478 2479 ret = psp_execute_non_psp_fw_load(psp, ucode); 2480 if (ret) 2481 return ret; 2482 2483 /* Start rlc autoload after psp recieved all the gfx firmware */ 2484 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2485 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2486 ret = psp_rlc_autoload_start(psp); 2487 if (ret) { 2488 DRM_ERROR("Failed to start rlc autoload\n"); 2489 return ret; 2490 } 2491 } 2492 } 2493 2494 return 0; 2495 } 2496 2497 static int psp_load_fw(struct amdgpu_device *adev) 2498 { 2499 int ret; 2500 struct psp_context *psp = &adev->psp; 2501 2502 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2503 /* should not destroy ring, only stop */ 2504 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2505 } else { 2506 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2507 2508 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2509 if (ret) { 2510 DRM_ERROR("PSP ring init failed!\n"); 2511 goto failed; 2512 } 2513 } 2514 2515 ret = psp_hw_start(psp); 2516 if (ret) 2517 goto failed; 2518 2519 ret = psp_load_non_psp_fw(psp); 2520 if (ret) 2521 goto failed1; 2522 2523 ret = psp_asd_initialize(psp); 2524 if (ret) { 2525 DRM_ERROR("PSP load asd failed!\n"); 2526 goto failed1; 2527 } 2528 2529 ret = psp_rl_load(adev); 2530 if (ret) { 2531 DRM_ERROR("PSP load RL failed!\n"); 2532 goto failed1; 2533 } 2534 2535 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2536 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2537 ret = psp_xgmi_initialize(psp, false, true); 2538 /* Warning the XGMI seesion initialize failure 2539 * Instead of stop driver initialization 2540 */ 2541 if (ret) 2542 dev_err(psp->adev->dev, 2543 "XGMI: Failed to initialize XGMI session\n"); 2544 } 2545 } 2546 2547 if (psp->ta_fw) { 2548 ret = psp_ras_initialize(psp); 2549 if (ret) 2550 dev_err(psp->adev->dev, 2551 "RAS: Failed to initialize RAS\n"); 2552 2553 ret = psp_hdcp_initialize(psp); 2554 if (ret) 2555 dev_err(psp->adev->dev, 2556 "HDCP: Failed to initialize HDCP\n"); 2557 2558 ret = psp_dtm_initialize(psp); 2559 if (ret) 2560 dev_err(psp->adev->dev, 2561 "DTM: Failed to initialize DTM\n"); 2562 2563 ret = psp_rap_initialize(psp); 2564 if (ret) 2565 dev_err(psp->adev->dev, 2566 "RAP: Failed to initialize RAP\n"); 2567 2568 ret = psp_securedisplay_initialize(psp); 2569 if (ret) 2570 dev_err(psp->adev->dev, 2571 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2572 } 2573 2574 return 0; 2575 2576 failed1: 2577 psp_free_shared_bufs(psp); 2578 failed: 2579 /* 2580 * all cleanup jobs (xgmi terminate, ras terminate, 2581 * ring destroy, cmd/fence/fw buffers destory, 2582 * psp->cmd destory) are delayed to psp_hw_fini 2583 */ 2584 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2585 return ret; 2586 } 2587 2588 static int psp_hw_init(void *handle) 2589 { 2590 int ret; 2591 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2592 2593 mutex_lock(&adev->firmware.mutex); 2594 /* 2595 * This sequence is just used on hw_init only once, no need on 2596 * resume. 2597 */ 2598 ret = amdgpu_ucode_init_bo(adev); 2599 if (ret) 2600 goto failed; 2601 2602 ret = psp_load_fw(adev); 2603 if (ret) { 2604 DRM_ERROR("PSP firmware loading failed\n"); 2605 goto failed; 2606 } 2607 2608 mutex_unlock(&adev->firmware.mutex); 2609 return 0; 2610 2611 failed: 2612 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2613 mutex_unlock(&adev->firmware.mutex); 2614 return -EINVAL; 2615 } 2616 2617 static int psp_hw_fini(void *handle) 2618 { 2619 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2620 struct psp_context *psp = &adev->psp; 2621 2622 if (psp->ta_fw) { 2623 psp_ras_terminate(psp); 2624 psp_securedisplay_terminate(psp); 2625 psp_rap_terminate(psp); 2626 psp_dtm_terminate(psp); 2627 psp_hdcp_terminate(psp); 2628 2629 if (adev->gmc.xgmi.num_physical_nodes > 1) 2630 psp_xgmi_terminate(psp); 2631 } 2632 2633 psp_asd_terminate(psp); 2634 psp_tmr_terminate(psp); 2635 2636 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2637 2638 psp_free_shared_bufs(psp); 2639 2640 return 0; 2641 } 2642 2643 static int psp_suspend(void *handle) 2644 { 2645 int ret = 0; 2646 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2647 struct psp_context *psp = &adev->psp; 2648 2649 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2650 psp->xgmi_context.context.initialized) { 2651 ret = psp_xgmi_terminate(psp); 2652 if (ret) { 2653 DRM_ERROR("Failed to terminate xgmi ta\n"); 2654 goto out; 2655 } 2656 } 2657 2658 if (psp->ta_fw) { 2659 ret = psp_ras_terminate(psp); 2660 if (ret) { 2661 DRM_ERROR("Failed to terminate ras ta\n"); 2662 goto out; 2663 } 2664 ret = psp_hdcp_terminate(psp); 2665 if (ret) { 2666 DRM_ERROR("Failed to terminate hdcp ta\n"); 2667 goto out; 2668 } 2669 ret = psp_dtm_terminate(psp); 2670 if (ret) { 2671 DRM_ERROR("Failed to terminate dtm ta\n"); 2672 goto out; 2673 } 2674 ret = psp_rap_terminate(psp); 2675 if (ret) { 2676 DRM_ERROR("Failed to terminate rap ta\n"); 2677 goto out; 2678 } 2679 ret = psp_securedisplay_terminate(psp); 2680 if (ret) { 2681 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2682 goto out; 2683 } 2684 } 2685 2686 ret = psp_asd_terminate(psp); 2687 if (ret) { 2688 DRM_ERROR("Failed to terminate asd\n"); 2689 goto out; 2690 } 2691 2692 ret = psp_tmr_terminate(psp); 2693 if (ret) { 2694 DRM_ERROR("Failed to terminate tmr\n"); 2695 goto out; 2696 } 2697 2698 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2699 if (ret) { 2700 DRM_ERROR("PSP ring stop failed\n"); 2701 } 2702 2703 out: 2704 psp_free_shared_bufs(psp); 2705 2706 return ret; 2707 } 2708 2709 static int psp_resume(void *handle) 2710 { 2711 int ret; 2712 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2713 struct psp_context *psp = &adev->psp; 2714 2715 DRM_INFO("PSP is resuming...\n"); 2716 2717 if (psp->mem_train_ctx.enable_mem_training) { 2718 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2719 if (ret) { 2720 DRM_ERROR("Failed to process memory training!\n"); 2721 return ret; 2722 } 2723 } 2724 2725 mutex_lock(&adev->firmware.mutex); 2726 2727 ret = psp_hw_start(psp); 2728 if (ret) 2729 goto failed; 2730 2731 ret = psp_load_non_psp_fw(psp); 2732 if (ret) 2733 goto failed; 2734 2735 ret = psp_asd_initialize(psp); 2736 if (ret) { 2737 DRM_ERROR("PSP load asd failed!\n"); 2738 goto failed; 2739 } 2740 2741 ret = psp_rl_load(adev); 2742 if (ret) { 2743 dev_err(adev->dev, "PSP load RL failed!\n"); 2744 goto failed; 2745 } 2746 2747 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2748 ret = psp_xgmi_initialize(psp, false, true); 2749 /* Warning the XGMI seesion initialize failure 2750 * Instead of stop driver initialization 2751 */ 2752 if (ret) 2753 dev_err(psp->adev->dev, 2754 "XGMI: Failed to initialize XGMI session\n"); 2755 } 2756 2757 if (psp->ta_fw) { 2758 ret = psp_ras_initialize(psp); 2759 if (ret) 2760 dev_err(psp->adev->dev, 2761 "RAS: Failed to initialize RAS\n"); 2762 2763 ret = psp_hdcp_initialize(psp); 2764 if (ret) 2765 dev_err(psp->adev->dev, 2766 "HDCP: Failed to initialize HDCP\n"); 2767 2768 ret = psp_dtm_initialize(psp); 2769 if (ret) 2770 dev_err(psp->adev->dev, 2771 "DTM: Failed to initialize DTM\n"); 2772 2773 ret = psp_rap_initialize(psp); 2774 if (ret) 2775 dev_err(psp->adev->dev, 2776 "RAP: Failed to initialize RAP\n"); 2777 2778 ret = psp_securedisplay_initialize(psp); 2779 if (ret) 2780 dev_err(psp->adev->dev, 2781 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2782 } 2783 2784 mutex_unlock(&adev->firmware.mutex); 2785 2786 return 0; 2787 2788 failed: 2789 DRM_ERROR("PSP resume failed\n"); 2790 mutex_unlock(&adev->firmware.mutex); 2791 return ret; 2792 } 2793 2794 int psp_gpu_reset(struct amdgpu_device *adev) 2795 { 2796 int ret; 2797 2798 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2799 return 0; 2800 2801 mutex_lock(&adev->psp.mutex); 2802 ret = psp_mode1_reset(&adev->psp); 2803 mutex_unlock(&adev->psp.mutex); 2804 2805 return ret; 2806 } 2807 2808 int psp_rlc_autoload_start(struct psp_context *psp) 2809 { 2810 int ret; 2811 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2812 2813 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2814 2815 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2816 psp->fence_buf_mc_addr); 2817 2818 release_psp_cmd_buf(psp); 2819 2820 return ret; 2821 } 2822 2823 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2824 uint64_t cmd_gpu_addr, int cmd_size) 2825 { 2826 struct amdgpu_firmware_info ucode = {0}; 2827 2828 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2829 AMDGPU_UCODE_ID_VCN0_RAM; 2830 ucode.mc_addr = cmd_gpu_addr; 2831 ucode.ucode_size = cmd_size; 2832 2833 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2834 } 2835 2836 int psp_ring_cmd_submit(struct psp_context *psp, 2837 uint64_t cmd_buf_mc_addr, 2838 uint64_t fence_mc_addr, 2839 int index) 2840 { 2841 unsigned int psp_write_ptr_reg = 0; 2842 struct psp_gfx_rb_frame *write_frame; 2843 struct psp_ring *ring = &psp->km_ring; 2844 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2845 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2846 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2847 struct amdgpu_device *adev = psp->adev; 2848 uint32_t ring_size_dw = ring->ring_size / 4; 2849 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2850 2851 /* KM (GPCOM) prepare write pointer */ 2852 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2853 2854 /* Update KM RB frame pointer to new frame */ 2855 /* write_frame ptr increments by size of rb_frame in bytes */ 2856 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2857 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2858 write_frame = ring_buffer_start; 2859 else 2860 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2861 /* Check invalid write_frame ptr address */ 2862 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2863 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2864 ring_buffer_start, ring_buffer_end, write_frame); 2865 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2866 return -EINVAL; 2867 } 2868 2869 /* Initialize KM RB frame */ 2870 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2871 2872 /* Update KM RB frame */ 2873 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2874 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2875 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2876 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2877 write_frame->fence_value = index; 2878 amdgpu_device_flush_hdp(adev, NULL); 2879 2880 /* Update the write Pointer in DWORDs */ 2881 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2882 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2883 return 0; 2884 } 2885 2886 int psp_init_asd_microcode(struct psp_context *psp, 2887 const char *chip_name) 2888 { 2889 struct amdgpu_device *adev = psp->adev; 2890 char fw_name[PSP_FW_NAME_LEN]; 2891 const struct psp_firmware_header_v1_0 *asd_hdr; 2892 int err = 0; 2893 2894 if (!chip_name) { 2895 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2896 return -EINVAL; 2897 } 2898 2899 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2900 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2901 if (err) 2902 goto out; 2903 2904 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2905 if (err) 2906 goto out; 2907 2908 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2909 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2910 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2911 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2912 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2913 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2914 return 0; 2915 out: 2916 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2917 release_firmware(adev->psp.asd_fw); 2918 adev->psp.asd_fw = NULL; 2919 return err; 2920 } 2921 2922 int psp_init_toc_microcode(struct psp_context *psp, 2923 const char *chip_name) 2924 { 2925 struct amdgpu_device *adev = psp->adev; 2926 char fw_name[PSP_FW_NAME_LEN]; 2927 const struct psp_firmware_header_v1_0 *toc_hdr; 2928 int err = 0; 2929 2930 if (!chip_name) { 2931 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2932 return -EINVAL; 2933 } 2934 2935 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2936 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2937 if (err) 2938 goto out; 2939 2940 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2941 if (err) 2942 goto out; 2943 2944 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2945 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2946 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2947 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2948 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2949 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2950 return 0; 2951 out: 2952 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2953 release_firmware(adev->psp.toc_fw); 2954 adev->psp.toc_fw = NULL; 2955 return err; 2956 } 2957 2958 static int parse_sos_bin_descriptor(struct psp_context *psp, 2959 const struct psp_fw_bin_desc *desc, 2960 const struct psp_firmware_header_v2_0 *sos_hdr) 2961 { 2962 uint8_t *ucode_start_addr = NULL; 2963 2964 if (!psp || !desc || !sos_hdr) 2965 return -EINVAL; 2966 2967 ucode_start_addr = (uint8_t *)sos_hdr + 2968 le32_to_cpu(desc->offset_bytes) + 2969 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2970 2971 switch (desc->fw_type) { 2972 case PSP_FW_TYPE_PSP_SOS: 2973 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2974 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2975 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2976 psp->sos.start_addr = ucode_start_addr; 2977 break; 2978 case PSP_FW_TYPE_PSP_SYS_DRV: 2979 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2980 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2981 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2982 psp->sys.start_addr = ucode_start_addr; 2983 break; 2984 case PSP_FW_TYPE_PSP_KDB: 2985 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2986 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2987 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2988 psp->kdb.start_addr = ucode_start_addr; 2989 break; 2990 case PSP_FW_TYPE_PSP_TOC: 2991 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2992 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2993 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 2994 psp->toc.start_addr = ucode_start_addr; 2995 break; 2996 case PSP_FW_TYPE_PSP_SPL: 2997 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 2998 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 2999 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3000 psp->spl.start_addr = ucode_start_addr; 3001 break; 3002 case PSP_FW_TYPE_PSP_RL: 3003 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3004 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3005 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3006 psp->rl.start_addr = ucode_start_addr; 3007 break; 3008 case PSP_FW_TYPE_PSP_SOC_DRV: 3009 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3010 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3011 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3012 psp->soc_drv.start_addr = ucode_start_addr; 3013 break; 3014 case PSP_FW_TYPE_PSP_INTF_DRV: 3015 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3016 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3017 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3018 psp->intf_drv.start_addr = ucode_start_addr; 3019 break; 3020 case PSP_FW_TYPE_PSP_DBG_DRV: 3021 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3022 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3023 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3024 psp->dbg_drv.start_addr = ucode_start_addr; 3025 break; 3026 case PSP_FW_TYPE_PSP_RAS_DRV: 3027 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3028 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3029 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3030 psp->ras_drv.start_addr = ucode_start_addr; 3031 break; 3032 default: 3033 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3034 break; 3035 } 3036 3037 return 0; 3038 } 3039 3040 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3041 { 3042 const struct psp_firmware_header_v1_0 *sos_hdr; 3043 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3044 uint8_t *ucode_array_start_addr; 3045 3046 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3047 ucode_array_start_addr = (uint8_t *)sos_hdr + 3048 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3049 3050 if (adev->gmc.xgmi.connected_to_cpu || 3051 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3052 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3053 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3054 3055 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3056 adev->psp.sys.start_addr = ucode_array_start_addr; 3057 3058 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3059 adev->psp.sos.start_addr = ucode_array_start_addr + 3060 le32_to_cpu(sos_hdr->sos.offset_bytes); 3061 } else { 3062 /* Load alternate PSP SOS FW */ 3063 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3064 3065 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3066 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3067 3068 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3069 adev->psp.sys.start_addr = ucode_array_start_addr + 3070 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3071 3072 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3073 adev->psp.sos.start_addr = ucode_array_start_addr + 3074 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3075 } 3076 3077 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3078 dev_warn(adev->dev, "PSP SOS FW not available"); 3079 return -EINVAL; 3080 } 3081 3082 return 0; 3083 } 3084 3085 int psp_init_sos_microcode(struct psp_context *psp, 3086 const char *chip_name) 3087 { 3088 struct amdgpu_device *adev = psp->adev; 3089 char fw_name[PSP_FW_NAME_LEN]; 3090 const struct psp_firmware_header_v1_0 *sos_hdr; 3091 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3092 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3093 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3094 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3095 int err = 0; 3096 uint8_t *ucode_array_start_addr; 3097 int fw_index = 0; 3098 3099 if (!chip_name) { 3100 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3101 return -EINVAL; 3102 } 3103 3104 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3105 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3106 if (err) 3107 goto out; 3108 3109 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3110 if (err) 3111 goto out; 3112 3113 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3114 ucode_array_start_addr = (uint8_t *)sos_hdr + 3115 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3116 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3117 3118 switch (sos_hdr->header.header_version_major) { 3119 case 1: 3120 err = psp_init_sos_base_fw(adev); 3121 if (err) 3122 goto out; 3123 3124 if (sos_hdr->header.header_version_minor == 1) { 3125 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3126 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3127 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3128 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3129 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3130 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3131 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3132 } 3133 if (sos_hdr->header.header_version_minor == 2) { 3134 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3135 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3136 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3137 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3138 } 3139 if (sos_hdr->header.header_version_minor == 3) { 3140 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3141 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3142 adev->psp.toc.start_addr = ucode_array_start_addr + 3143 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3144 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3145 adev->psp.kdb.start_addr = ucode_array_start_addr + 3146 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3147 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3148 adev->psp.spl.start_addr = ucode_array_start_addr + 3149 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3150 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3151 adev->psp.rl.start_addr = ucode_array_start_addr + 3152 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3153 } 3154 break; 3155 case 2: 3156 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3157 3158 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3159 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3160 err = -EINVAL; 3161 goto out; 3162 } 3163 3164 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3165 err = parse_sos_bin_descriptor(psp, 3166 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3167 sos_hdr_v2_0); 3168 if (err) 3169 goto out; 3170 } 3171 break; 3172 default: 3173 dev_err(adev->dev, 3174 "unsupported psp sos firmware\n"); 3175 err = -EINVAL; 3176 goto out; 3177 } 3178 3179 return 0; 3180 out: 3181 dev_err(adev->dev, 3182 "failed to init sos firmware\n"); 3183 release_firmware(adev->psp.sos_fw); 3184 adev->psp.sos_fw = NULL; 3185 3186 return err; 3187 } 3188 3189 static int parse_ta_bin_descriptor(struct psp_context *psp, 3190 const struct psp_fw_bin_desc *desc, 3191 const struct ta_firmware_header_v2_0 *ta_hdr) 3192 { 3193 uint8_t *ucode_start_addr = NULL; 3194 3195 if (!psp || !desc || !ta_hdr) 3196 return -EINVAL; 3197 3198 ucode_start_addr = (uint8_t *)ta_hdr + 3199 le32_to_cpu(desc->offset_bytes) + 3200 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3201 3202 switch (desc->fw_type) { 3203 case TA_FW_TYPE_PSP_ASD: 3204 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3205 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3206 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3207 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3208 break; 3209 case TA_FW_TYPE_PSP_XGMI: 3210 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3211 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3212 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3213 break; 3214 case TA_FW_TYPE_PSP_RAS: 3215 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3216 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3217 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3218 break; 3219 case TA_FW_TYPE_PSP_HDCP: 3220 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3221 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3222 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3223 break; 3224 case TA_FW_TYPE_PSP_DTM: 3225 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3226 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3227 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3228 break; 3229 case TA_FW_TYPE_PSP_RAP: 3230 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3231 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3232 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3233 break; 3234 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3235 psp->securedisplay_context.context.bin_desc.fw_version = 3236 le32_to_cpu(desc->fw_version); 3237 psp->securedisplay_context.context.bin_desc.size_bytes = 3238 le32_to_cpu(desc->size_bytes); 3239 psp->securedisplay_context.context.bin_desc.start_addr = 3240 ucode_start_addr; 3241 break; 3242 default: 3243 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3244 break; 3245 } 3246 3247 return 0; 3248 } 3249 3250 int psp_init_ta_microcode(struct psp_context *psp, 3251 const char *chip_name) 3252 { 3253 struct amdgpu_device *adev = psp->adev; 3254 char fw_name[PSP_FW_NAME_LEN]; 3255 const struct ta_firmware_header_v2_0 *ta_hdr; 3256 int err = 0; 3257 int ta_index = 0; 3258 3259 if (!chip_name) { 3260 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3261 return -EINVAL; 3262 } 3263 3264 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3265 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3266 if (err) 3267 goto out; 3268 3269 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3270 if (err) 3271 goto out; 3272 3273 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3274 3275 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3276 dev_err(adev->dev, "unsupported TA header version\n"); 3277 err = -EINVAL; 3278 goto out; 3279 } 3280 3281 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3282 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3283 err = -EINVAL; 3284 goto out; 3285 } 3286 3287 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3288 err = parse_ta_bin_descriptor(psp, 3289 &ta_hdr->ta_fw_bin[ta_index], 3290 ta_hdr); 3291 if (err) 3292 goto out; 3293 } 3294 3295 return 0; 3296 out: 3297 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3298 release_firmware(adev->psp.ta_fw); 3299 adev->psp.ta_fw = NULL; 3300 return err; 3301 } 3302 3303 int psp_init_cap_microcode(struct psp_context *psp, 3304 const char *chip_name) 3305 { 3306 struct amdgpu_device *adev = psp->adev; 3307 char fw_name[PSP_FW_NAME_LEN]; 3308 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3309 struct amdgpu_firmware_info *info = NULL; 3310 int err = 0; 3311 3312 if (!chip_name) { 3313 dev_err(adev->dev, "invalid chip name for cap microcode\n"); 3314 return -EINVAL; 3315 } 3316 3317 if (!amdgpu_sriov_vf(adev)) { 3318 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3319 return -EINVAL; 3320 } 3321 3322 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3323 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev); 3324 if (err) { 3325 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3326 err = 0; 3327 goto out; 3328 } 3329 3330 err = amdgpu_ucode_validate(adev->psp.cap_fw); 3331 if (err) { 3332 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3333 goto out; 3334 } 3335 3336 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3337 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3338 info->fw = adev->psp.cap_fw; 3339 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3340 adev->psp.cap_fw->data; 3341 adev->firmware.fw_size += ALIGN( 3342 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3343 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3344 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3345 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3346 3347 return 0; 3348 3349 out: 3350 release_firmware(adev->psp.cap_fw); 3351 adev->psp.cap_fw = NULL; 3352 return err; 3353 } 3354 3355 static int psp_set_clockgating_state(void *handle, 3356 enum amd_clockgating_state state) 3357 { 3358 return 0; 3359 } 3360 3361 static int psp_set_powergating_state(void *handle, 3362 enum amd_powergating_state state) 3363 { 3364 return 0; 3365 } 3366 3367 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3368 struct device_attribute *attr, 3369 char *buf) 3370 { 3371 struct drm_device *ddev = dev_get_drvdata(dev); 3372 struct amdgpu_device *adev = drm_to_adev(ddev); 3373 uint32_t fw_ver; 3374 int ret; 3375 3376 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3377 DRM_INFO("PSP block is not ready yet."); 3378 return -EBUSY; 3379 } 3380 3381 mutex_lock(&adev->psp.mutex); 3382 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3383 mutex_unlock(&adev->psp.mutex); 3384 3385 if (ret) { 3386 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3387 return ret; 3388 } 3389 3390 return sysfs_emit(buf, "%x\n", fw_ver); 3391 } 3392 3393 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3394 struct device_attribute *attr, 3395 const char *buf, 3396 size_t count) 3397 { 3398 struct drm_device *ddev = dev_get_drvdata(dev); 3399 struct amdgpu_device *adev = drm_to_adev(ddev); 3400 int ret, idx; 3401 char fw_name[100]; 3402 const struct firmware *usbc_pd_fw; 3403 struct amdgpu_bo *fw_buf_bo = NULL; 3404 uint64_t fw_pri_mc_addr; 3405 void *fw_pri_cpu_addr; 3406 3407 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3408 DRM_INFO("PSP block is not ready yet."); 3409 return -EBUSY; 3410 } 3411 3412 if (!drm_dev_enter(ddev, &idx)) 3413 return -ENODEV; 3414 3415 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3416 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3417 if (ret) 3418 goto fail; 3419 3420 /* LFB address which is aligned to 1MB boundary per PSP request */ 3421 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3422 AMDGPU_GEM_DOMAIN_VRAM, 3423 &fw_buf_bo, 3424 &fw_pri_mc_addr, 3425 &fw_pri_cpu_addr); 3426 if (ret) 3427 goto rel_buf; 3428 3429 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3430 3431 mutex_lock(&adev->psp.mutex); 3432 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3433 mutex_unlock(&adev->psp.mutex); 3434 3435 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3436 3437 rel_buf: 3438 release_firmware(usbc_pd_fw); 3439 fail: 3440 if (ret) { 3441 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3442 count = ret; 3443 } 3444 3445 drm_dev_exit(idx); 3446 return count; 3447 } 3448 3449 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3450 { 3451 int idx; 3452 3453 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3454 return; 3455 3456 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3457 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3458 3459 drm_dev_exit(idx); 3460 } 3461 3462 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3463 psp_usbc_pd_fw_sysfs_read, 3464 psp_usbc_pd_fw_sysfs_write); 3465 3466 int is_psp_fw_valid(struct psp_bin_desc bin) 3467 { 3468 return bin.size_bytes; 3469 } 3470 3471 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3472 struct bin_attribute *bin_attr, 3473 char *buffer, loff_t pos, size_t count) 3474 { 3475 struct device *dev = kobj_to_dev(kobj); 3476 struct drm_device *ddev = dev_get_drvdata(dev); 3477 struct amdgpu_device *adev = drm_to_adev(ddev); 3478 3479 adev->psp.vbflash_done = false; 3480 3481 /* Safeguard against memory drain */ 3482 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3483 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3484 kvfree(adev->psp.vbflash_tmp_buf); 3485 adev->psp.vbflash_tmp_buf = NULL; 3486 adev->psp.vbflash_image_size = 0; 3487 return -ENOMEM; 3488 } 3489 3490 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3491 if (!adev->psp.vbflash_tmp_buf) { 3492 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3493 if (!adev->psp.vbflash_tmp_buf) 3494 return -ENOMEM; 3495 } 3496 3497 mutex_lock(&adev->psp.mutex); 3498 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3499 adev->psp.vbflash_image_size += count; 3500 mutex_unlock(&adev->psp.mutex); 3501 3502 dev_info(adev->dev, "VBIOS flash write PSP done"); 3503 3504 return count; 3505 } 3506 3507 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3508 struct bin_attribute *bin_attr, char *buffer, 3509 loff_t pos, size_t count) 3510 { 3511 struct device *dev = kobj_to_dev(kobj); 3512 struct drm_device *ddev = dev_get_drvdata(dev); 3513 struct amdgpu_device *adev = drm_to_adev(ddev); 3514 struct amdgpu_bo *fw_buf_bo = NULL; 3515 uint64_t fw_pri_mc_addr; 3516 void *fw_pri_cpu_addr; 3517 int ret; 3518 3519 dev_info(adev->dev, "VBIOS flash to PSP started"); 3520 3521 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3522 AMDGPU_GPU_PAGE_SIZE, 3523 AMDGPU_GEM_DOMAIN_VRAM, 3524 &fw_buf_bo, 3525 &fw_pri_mc_addr, 3526 &fw_pri_cpu_addr); 3527 if (ret) 3528 goto rel_buf; 3529 3530 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3531 3532 mutex_lock(&adev->psp.mutex); 3533 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3534 mutex_unlock(&adev->psp.mutex); 3535 3536 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3537 3538 rel_buf: 3539 kvfree(adev->psp.vbflash_tmp_buf); 3540 adev->psp.vbflash_tmp_buf = NULL; 3541 adev->psp.vbflash_image_size = 0; 3542 3543 if (ret) { 3544 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret); 3545 return ret; 3546 } 3547 3548 dev_info(adev->dev, "VBIOS flash to PSP done"); 3549 return 0; 3550 } 3551 3552 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3553 struct device_attribute *attr, 3554 char *buf) 3555 { 3556 struct drm_device *ddev = dev_get_drvdata(dev); 3557 struct amdgpu_device *adev = drm_to_adev(ddev); 3558 uint32_t vbflash_status; 3559 3560 vbflash_status = psp_vbflash_status(&adev->psp); 3561 if (!adev->psp.vbflash_done) 3562 vbflash_status = 0; 3563 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3564 vbflash_status = 1; 3565 3566 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3567 } 3568 3569 static const struct bin_attribute psp_vbflash_bin_attr = { 3570 .attr = {.name = "psp_vbflash", .mode = 0664}, 3571 .size = 0, 3572 .write = amdgpu_psp_vbflash_write, 3573 .read = amdgpu_psp_vbflash_read, 3574 }; 3575 3576 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL); 3577 3578 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev) 3579 { 3580 int ret = 0; 3581 struct psp_context *psp = &adev->psp; 3582 3583 if (amdgpu_sriov_vf(adev)) 3584 return -EINVAL; 3585 3586 switch (adev->ip_versions[MP0_HWIP][0]) { 3587 case IP_VERSION(13, 0, 0): 3588 case IP_VERSION(13, 0, 7): 3589 if (!psp->adev) { 3590 psp->adev = adev; 3591 psp_v13_0_set_psp_funcs(psp); 3592 } 3593 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3594 if (ret) 3595 dev_err(adev->dev, "Failed to create device file psp_vbflash"); 3596 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status); 3597 if (ret) 3598 dev_err(adev->dev, "Failed to create device file psp_vbflash_status"); 3599 return ret; 3600 default: 3601 return 0; 3602 } 3603 } 3604 3605 const struct amd_ip_funcs psp_ip_funcs = { 3606 .name = "psp", 3607 .early_init = psp_early_init, 3608 .late_init = NULL, 3609 .sw_init = psp_sw_init, 3610 .sw_fini = psp_sw_fini, 3611 .hw_init = psp_hw_init, 3612 .hw_fini = psp_hw_fini, 3613 .suspend = psp_suspend, 3614 .resume = psp_resume, 3615 .is_idle = NULL, 3616 .check_soft_reset = NULL, 3617 .wait_for_idle = NULL, 3618 .soft_reset = NULL, 3619 .set_clockgating_state = psp_set_clockgating_state, 3620 .set_powergating_state = psp_set_powergating_state, 3621 }; 3622 3623 static int psp_sysfs_init(struct amdgpu_device *adev) 3624 { 3625 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3626 3627 if (ret) 3628 DRM_ERROR("Failed to create USBC PD FW control file!"); 3629 3630 return ret; 3631 } 3632 3633 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev) 3634 { 3635 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3636 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status); 3637 } 3638 3639 static void psp_sysfs_fini(struct amdgpu_device *adev) 3640 { 3641 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3642 } 3643 3644 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3645 { 3646 .type = AMD_IP_BLOCK_TYPE_PSP, 3647 .major = 3, 3648 .minor = 1, 3649 .rev = 0, 3650 .funcs = &psp_ip_funcs, 3651 }; 3652 3653 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3654 { 3655 .type = AMD_IP_BLOCK_TYPE_PSP, 3656 .major = 10, 3657 .minor = 0, 3658 .rev = 0, 3659 .funcs = &psp_ip_funcs, 3660 }; 3661 3662 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3663 { 3664 .type = AMD_IP_BLOCK_TYPE_PSP, 3665 .major = 11, 3666 .minor = 0, 3667 .rev = 0, 3668 .funcs = &psp_ip_funcs, 3669 }; 3670 3671 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3672 .type = AMD_IP_BLOCK_TYPE_PSP, 3673 .major = 11, 3674 .minor = 0, 3675 .rev = 8, 3676 .funcs = &psp_ip_funcs, 3677 }; 3678 3679 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3680 { 3681 .type = AMD_IP_BLOCK_TYPE_PSP, 3682 .major = 12, 3683 .minor = 0, 3684 .rev = 0, 3685 .funcs = &psp_ip_funcs, 3686 }; 3687 3688 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3689 .type = AMD_IP_BLOCK_TYPE_PSP, 3690 .major = 13, 3691 .minor = 0, 3692 .rev = 0, 3693 .funcs = &psp_ip_funcs, 3694 }; 3695 3696 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3697 .type = AMD_IP_BLOCK_TYPE_PSP, 3698 .major = 13, 3699 .minor = 0, 3700 .rev = 4, 3701 .funcs = &psp_ip_funcs, 3702 }; 3703