1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 42 #include "amdgpu_ras.h" 43 #include "amdgpu_securedisplay.h" 44 #include "amdgpu_atomfirmware.h" 45 46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 47 48 static int psp_sysfs_init(struct amdgpu_device *adev); 49 static void psp_sysfs_fini(struct amdgpu_device *adev); 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 static int psp_ring_init(struct psp_context *psp, 56 enum psp_ring_type ring_type) 57 { 58 int ret = 0; 59 struct psp_ring *ring; 60 struct amdgpu_device *adev = psp->adev; 61 62 ring = &psp->km_ring; 63 64 ring->ring_type = ring_type; 65 66 /* allocate 4k Page of Local Frame Buffer memory for ring */ 67 ring->ring_size = 0x1000; 68 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 69 AMDGPU_GEM_DOMAIN_VRAM | 70 AMDGPU_GEM_DOMAIN_GTT, 71 &adev->firmware.rbuf, 72 &ring->ring_mem_mc_addr, 73 (void **)&ring->ring_mem); 74 if (ret) { 75 ring->ring_size = 0; 76 return ret; 77 } 78 79 return 0; 80 } 81 82 /* 83 * Due to DF Cstate management centralized to PMFW, the firmware 84 * loading sequence will be updated as below: 85 * - Load KDB 86 * - Load SYS_DRV 87 * - Load tOS 88 * - Load PMFW 89 * - Setup TMR 90 * - Load other non-psp fw 91 * - Load ASD 92 * - Load XGMI/RAS/HDCP/DTM TA if any 93 * 94 * This new sequence is required for 95 * - Arcturus and onwards 96 */ 97 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 98 { 99 struct amdgpu_device *adev = psp->adev; 100 101 if (amdgpu_sriov_vf(adev)) { 102 psp->pmfw_centralized_cstate_management = false; 103 return; 104 } 105 106 switch (adev->ip_versions[MP0_HWIP][0]) { 107 case IP_VERSION(11, 0, 0): 108 case IP_VERSION(11, 0, 4): 109 case IP_VERSION(11, 0, 5): 110 case IP_VERSION(11, 0, 7): 111 case IP_VERSION(11, 0, 9): 112 case IP_VERSION(11, 0, 11): 113 case IP_VERSION(11, 0, 12): 114 case IP_VERSION(11, 0, 13): 115 case IP_VERSION(13, 0, 0): 116 case IP_VERSION(13, 0, 2): 117 case IP_VERSION(13, 0, 7): 118 psp->pmfw_centralized_cstate_management = true; 119 break; 120 default: 121 psp->pmfw_centralized_cstate_management = false; 122 break; 123 } 124 } 125 126 static int psp_init_sriov_microcode(struct psp_context *psp) 127 { 128 struct amdgpu_device *adev = psp->adev; 129 char ucode_prefix[30]; 130 int ret = 0; 131 132 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 133 134 switch (adev->ip_versions[MP0_HWIP][0]) { 135 case IP_VERSION(9, 0, 0): 136 case IP_VERSION(11, 0, 7): 137 case IP_VERSION(11, 0, 9): 138 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 139 ret = psp_init_cap_microcode(psp, ucode_prefix); 140 break; 141 case IP_VERSION(13, 0, 2): 142 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 143 ret = psp_init_cap_microcode(psp, ucode_prefix); 144 ret &= psp_init_ta_microcode(psp, ucode_prefix); 145 break; 146 case IP_VERSION(13, 0, 0): 147 adev->virt.autoload_ucode_id = 0; 148 break; 149 case IP_VERSION(13, 0, 10): 150 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 151 break; 152 default: 153 return -EINVAL; 154 } 155 return ret; 156 } 157 158 static int psp_early_init(void *handle) 159 { 160 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 161 struct psp_context *psp = &adev->psp; 162 163 switch (adev->ip_versions[MP0_HWIP][0]) { 164 case IP_VERSION(9, 0, 0): 165 psp_v3_1_set_psp_funcs(psp); 166 psp->autoload_supported = false; 167 break; 168 case IP_VERSION(10, 0, 0): 169 case IP_VERSION(10, 0, 1): 170 psp_v10_0_set_psp_funcs(psp); 171 psp->autoload_supported = false; 172 break; 173 case IP_VERSION(11, 0, 2): 174 case IP_VERSION(11, 0, 4): 175 psp_v11_0_set_psp_funcs(psp); 176 psp->autoload_supported = false; 177 break; 178 case IP_VERSION(11, 0, 0): 179 case IP_VERSION(11, 0, 5): 180 case IP_VERSION(11, 0, 9): 181 case IP_VERSION(11, 0, 7): 182 case IP_VERSION(11, 0, 11): 183 case IP_VERSION(11, 5, 0): 184 case IP_VERSION(11, 0, 12): 185 case IP_VERSION(11, 0, 13): 186 psp_v11_0_set_psp_funcs(psp); 187 psp->autoload_supported = true; 188 break; 189 case IP_VERSION(11, 0, 3): 190 case IP_VERSION(12, 0, 1): 191 psp_v12_0_set_psp_funcs(psp); 192 break; 193 case IP_VERSION(13, 0, 2): 194 psp_v13_0_set_psp_funcs(psp); 195 break; 196 case IP_VERSION(13, 0, 1): 197 case IP_VERSION(13, 0, 3): 198 case IP_VERSION(13, 0, 5): 199 case IP_VERSION(13, 0, 8): 200 case IP_VERSION(13, 0, 10): 201 case IP_VERSION(13, 0, 11): 202 psp_v13_0_set_psp_funcs(psp); 203 psp->autoload_supported = true; 204 break; 205 case IP_VERSION(11, 0, 8): 206 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 207 psp_v11_0_8_set_psp_funcs(psp); 208 psp->autoload_supported = false; 209 } 210 break; 211 case IP_VERSION(13, 0, 0): 212 case IP_VERSION(13, 0, 7): 213 psp_v13_0_set_psp_funcs(psp); 214 psp->autoload_supported = true; 215 break; 216 case IP_VERSION(13, 0, 4): 217 psp_v13_0_4_set_psp_funcs(psp); 218 psp->autoload_supported = true; 219 break; 220 default: 221 return -EINVAL; 222 } 223 224 psp->adev = adev; 225 226 psp_check_pmfw_centralized_cstate_management(psp); 227 228 if (amdgpu_sriov_vf(adev)) 229 return psp_init_sriov_microcode(psp); 230 else 231 return psp_init_microcode(psp); 232 } 233 234 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 235 { 236 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 237 &mem_ctx->shared_buf); 238 mem_ctx->shared_bo = NULL; 239 } 240 241 static void psp_free_shared_bufs(struct psp_context *psp) 242 { 243 void *tmr_buf; 244 void **pptr; 245 246 /* free TMR memory buffer */ 247 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 248 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 249 psp->tmr_bo = NULL; 250 251 /* free xgmi shared memory */ 252 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 253 254 /* free ras shared memory */ 255 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 256 257 /* free hdcp shared memory */ 258 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 259 260 /* free dtm shared memory */ 261 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 262 263 /* free rap shared memory */ 264 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 265 266 /* free securedisplay shared memory */ 267 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 268 269 270 } 271 272 static void psp_memory_training_fini(struct psp_context *psp) 273 { 274 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 275 276 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 277 kfree(ctx->sys_cache); 278 ctx->sys_cache = NULL; 279 } 280 281 static int psp_memory_training_init(struct psp_context *psp) 282 { 283 int ret; 284 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 285 286 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 287 DRM_DEBUG("memory training is not supported!\n"); 288 return 0; 289 } 290 291 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 292 if (ctx->sys_cache == NULL) { 293 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 294 ret = -ENOMEM; 295 goto Err_out; 296 } 297 298 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 299 ctx->train_data_size, 300 ctx->p2c_train_data_offset, 301 ctx->c2p_train_data_offset); 302 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 303 return 0; 304 305 Err_out: 306 psp_memory_training_fini(psp); 307 return ret; 308 } 309 310 /* 311 * Helper funciton to query psp runtime database entry 312 * 313 * @adev: amdgpu_device pointer 314 * @entry_type: the type of psp runtime database entry 315 * @db_entry: runtime database entry pointer 316 * 317 * Return false if runtime database doesn't exit or entry is invalid 318 * or true if the specific database entry is found, and copy to @db_entry 319 */ 320 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 321 enum psp_runtime_entry_type entry_type, 322 void *db_entry) 323 { 324 uint64_t db_header_pos, db_dir_pos; 325 struct psp_runtime_data_header db_header = {0}; 326 struct psp_runtime_data_directory db_dir = {0}; 327 bool ret = false; 328 int i; 329 330 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 331 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 332 333 /* read runtime db header from vram */ 334 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 335 sizeof(struct psp_runtime_data_header), false); 336 337 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 338 /* runtime db doesn't exist, exit */ 339 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 340 return false; 341 } 342 343 /* read runtime database entry from vram */ 344 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 345 sizeof(struct psp_runtime_data_directory), false); 346 347 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 348 /* invalid db entry count, exit */ 349 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 350 return false; 351 } 352 353 /* look up for requested entry type */ 354 for (i = 0; i < db_dir.entry_count && !ret; i++) { 355 if (db_dir.entry_list[i].entry_type == entry_type) { 356 switch (entry_type) { 357 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 358 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 359 /* invalid db entry size */ 360 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 361 return false; 362 } 363 /* read runtime database entry */ 364 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 365 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 366 ret = true; 367 break; 368 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 369 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 370 /* invalid db entry size */ 371 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 372 return false; 373 } 374 /* read runtime database entry */ 375 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 376 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 377 ret = true; 378 break; 379 default: 380 ret = false; 381 break; 382 } 383 } 384 } 385 386 return ret; 387 } 388 389 static int psp_sw_init(void *handle) 390 { 391 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 392 struct psp_context *psp = &adev->psp; 393 int ret; 394 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 395 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 396 struct psp_runtime_scpm_entry scpm_entry; 397 398 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 399 if (!psp->cmd) { 400 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 401 ret = -ENOMEM; 402 } 403 404 adev->psp.xgmi_context.supports_extended_data = 405 !adev->gmc.xgmi.connected_to_cpu && 406 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 407 408 memset(&scpm_entry, 0, sizeof(scpm_entry)); 409 if ((psp_get_runtime_db_entry(adev, 410 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 411 &scpm_entry)) && 412 (SCPM_DISABLE != scpm_entry.scpm_status)) { 413 adev->scpm_enabled = true; 414 adev->scpm_status = scpm_entry.scpm_status; 415 } else { 416 adev->scpm_enabled = false; 417 adev->scpm_status = SCPM_DISABLE; 418 } 419 420 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 421 422 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 423 if (psp_get_runtime_db_entry(adev, 424 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 425 &boot_cfg_entry)) { 426 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 427 if ((psp->boot_cfg_bitmask) & 428 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 429 /* If psp runtime database exists, then 430 * only enable two stage memory training 431 * when TWO_STAGE_DRAM_TRAINING bit is set 432 * in runtime database */ 433 mem_training_ctx->enable_mem_training = true; 434 } 435 436 } else { 437 /* If psp runtime database doesn't exist or 438 * is invalid, force enable two stage memory 439 * training */ 440 mem_training_ctx->enable_mem_training = true; 441 } 442 443 if (mem_training_ctx->enable_mem_training) { 444 ret = psp_memory_training_init(psp); 445 if (ret) { 446 DRM_ERROR("Failed to initialize memory training!\n"); 447 return ret; 448 } 449 450 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 451 if (ret) { 452 DRM_ERROR("Failed to process memory training!\n"); 453 return ret; 454 } 455 } 456 457 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 458 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 459 ret= psp_sysfs_init(adev); 460 if (ret) { 461 return ret; 462 } 463 } 464 465 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 466 amdgpu_sriov_vf(adev) ? 467 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 468 &psp->fw_pri_bo, 469 &psp->fw_pri_mc_addr, 470 &psp->fw_pri_buf); 471 if (ret) 472 return ret; 473 474 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 475 AMDGPU_GEM_DOMAIN_VRAM, 476 &psp->fence_buf_bo, 477 &psp->fence_buf_mc_addr, 478 &psp->fence_buf); 479 if (ret) 480 goto failed1; 481 482 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 483 AMDGPU_GEM_DOMAIN_VRAM, 484 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 485 (void **)&psp->cmd_buf_mem); 486 if (ret) 487 goto failed2; 488 489 return 0; 490 491 failed2: 492 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 493 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 494 failed1: 495 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 496 &psp->fence_buf_mc_addr, &psp->fence_buf); 497 return ret; 498 } 499 500 static int psp_sw_fini(void *handle) 501 { 502 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 503 struct psp_context *psp = &adev->psp; 504 struct psp_gfx_cmd_resp *cmd = psp->cmd; 505 506 psp_memory_training_fini(psp); 507 508 amdgpu_ucode_release(&psp->sos_fw); 509 amdgpu_ucode_release(&psp->asd_fw); 510 amdgpu_ucode_release(&psp->ta_fw); 511 amdgpu_ucode_release(&psp->cap_fw); 512 amdgpu_ucode_release(&psp->toc_fw); 513 514 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 515 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 516 psp_sysfs_fini(adev); 517 518 kfree(cmd); 519 cmd = NULL; 520 521 if (psp->km_ring.ring_mem) 522 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 523 &psp->km_ring.ring_mem_mc_addr, 524 (void **)&psp->km_ring.ring_mem); 525 526 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 527 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 528 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 529 &psp->fence_buf_mc_addr, &psp->fence_buf); 530 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 531 (void **)&psp->cmd_buf_mem); 532 533 return 0; 534 } 535 536 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 537 uint32_t reg_val, uint32_t mask, bool check_changed) 538 { 539 uint32_t val; 540 int i; 541 struct amdgpu_device *adev = psp->adev; 542 543 if (psp->adev->no_hw_access) 544 return 0; 545 546 for (i = 0; i < adev->usec_timeout; i++) { 547 val = RREG32(reg_index); 548 if (check_changed) { 549 if (val != reg_val) 550 return 0; 551 } else { 552 if ((val & mask) == reg_val) 553 return 0; 554 } 555 udelay(1); 556 } 557 558 return -ETIME; 559 } 560 561 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 562 { 563 switch (cmd_id) { 564 case GFX_CMD_ID_LOAD_TA: 565 return "LOAD_TA"; 566 case GFX_CMD_ID_UNLOAD_TA: 567 return "UNLOAD_TA"; 568 case GFX_CMD_ID_INVOKE_CMD: 569 return "INVOKE_CMD"; 570 case GFX_CMD_ID_LOAD_ASD: 571 return "LOAD_ASD"; 572 case GFX_CMD_ID_SETUP_TMR: 573 return "SETUP_TMR"; 574 case GFX_CMD_ID_LOAD_IP_FW: 575 return "LOAD_IP_FW"; 576 case GFX_CMD_ID_DESTROY_TMR: 577 return "DESTROY_TMR"; 578 case GFX_CMD_ID_SAVE_RESTORE: 579 return "SAVE_RESTORE_IP_FW"; 580 case GFX_CMD_ID_SETUP_VMR: 581 return "SETUP_VMR"; 582 case GFX_CMD_ID_DESTROY_VMR: 583 return "DESTROY_VMR"; 584 case GFX_CMD_ID_PROG_REG: 585 return "PROG_REG"; 586 case GFX_CMD_ID_GET_FW_ATTESTATION: 587 return "GET_FW_ATTESTATION"; 588 case GFX_CMD_ID_LOAD_TOC: 589 return "ID_LOAD_TOC"; 590 case GFX_CMD_ID_AUTOLOAD_RLC: 591 return "AUTOLOAD_RLC"; 592 case GFX_CMD_ID_BOOT_CFG: 593 return "BOOT_CFG"; 594 default: 595 return "UNKNOWN CMD"; 596 } 597 } 598 599 static int 600 psp_cmd_submit_buf(struct psp_context *psp, 601 struct amdgpu_firmware_info *ucode, 602 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 603 { 604 int ret; 605 int index, idx; 606 int timeout = 20000; 607 bool ras_intr = false; 608 bool skip_unsupport = false; 609 bool dev_entered; 610 611 if (psp->adev->no_hw_access) 612 return 0; 613 614 dev_entered = drm_dev_enter(adev_to_drm(psp->adev), &idx); 615 /* 616 * We allow sending PSP messages LOAD_ASD and UNLOAD_TA without acquiring 617 * a lock in drm_dev_enter during driver unload because we must call 618 * drm_dev_unplug as the beginning of unload driver sequence . It is very 619 * crucial that userspace can't access device instances anymore. 620 */ 621 if (!dev_entered) 622 WARN_ON(psp->cmd_buf_mem->cmd_id != GFX_CMD_ID_LOAD_ASD && 623 psp->cmd_buf_mem->cmd_id != GFX_CMD_ID_UNLOAD_TA); 624 625 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 626 627 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 628 629 index = atomic_inc_return(&psp->fence_value); 630 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 631 if (ret) { 632 atomic_dec(&psp->fence_value); 633 goto exit; 634 } 635 636 amdgpu_device_invalidate_hdp(psp->adev, NULL); 637 while (*((unsigned int *)psp->fence_buf) != index) { 638 if (--timeout == 0) 639 break; 640 /* 641 * Shouldn't wait for timeout when err_event_athub occurs, 642 * because gpu reset thread triggered and lock resource should 643 * be released for psp resume sequence. 644 */ 645 ras_intr = amdgpu_ras_intr_triggered(); 646 if (ras_intr) 647 break; 648 usleep_range(10, 100); 649 amdgpu_device_invalidate_hdp(psp->adev, NULL); 650 } 651 652 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 653 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 654 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 655 656 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 657 658 /* In some cases, psp response status is not 0 even there is no 659 * problem while the command is submitted. Some version of PSP FW 660 * doesn't write 0 to that field. 661 * So here we would like to only print a warning instead of an error 662 * during psp initialization to avoid breaking hw_init and it doesn't 663 * return -EINVAL. 664 */ 665 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 666 if (ucode) 667 DRM_WARN("failed to load ucode %s(0x%X) ", 668 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 669 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 670 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 671 psp->cmd_buf_mem->resp.status); 672 /* If any firmware (including CAP) load fails under SRIOV, it should 673 * return failure to stop the VF from initializing. 674 * Also return failure in case of timeout 675 */ 676 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 677 ret = -EINVAL; 678 goto exit; 679 } 680 } 681 682 if (ucode) { 683 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 684 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 685 } 686 687 exit: 688 if (dev_entered) 689 drm_dev_exit(idx); 690 return ret; 691 } 692 693 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 694 { 695 struct psp_gfx_cmd_resp *cmd = psp->cmd; 696 697 mutex_lock(&psp->mutex); 698 699 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 700 701 return cmd; 702 } 703 704 static void release_psp_cmd_buf(struct psp_context *psp) 705 { 706 mutex_unlock(&psp->mutex); 707 } 708 709 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 710 struct psp_gfx_cmd_resp *cmd, 711 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 712 { 713 struct amdgpu_device *adev = psp->adev; 714 uint32_t size = amdgpu_bo_size(tmr_bo); 715 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 716 717 if (amdgpu_sriov_vf(psp->adev)) 718 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 719 else 720 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 721 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 722 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 723 cmd->cmd.cmd_setup_tmr.buf_size = size; 724 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 725 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 726 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 727 } 728 729 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 730 uint64_t pri_buf_mc, uint32_t size) 731 { 732 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 733 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 734 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 735 cmd->cmd.cmd_load_toc.toc_size = size; 736 } 737 738 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 739 static int psp_load_toc(struct psp_context *psp, 740 uint32_t *tmr_size) 741 { 742 int ret; 743 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 744 745 /* Copy toc to psp firmware private buffer */ 746 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 747 748 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 749 750 ret = psp_cmd_submit_buf(psp, NULL, cmd, 751 psp->fence_buf_mc_addr); 752 if (!ret) 753 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 754 755 release_psp_cmd_buf(psp); 756 757 return ret; 758 } 759 760 /* Set up Trusted Memory Region */ 761 static int psp_tmr_init(struct psp_context *psp) 762 { 763 int ret = 0; 764 int tmr_size; 765 void *tmr_buf; 766 void **pptr; 767 768 /* 769 * According to HW engineer, they prefer the TMR address be "naturally 770 * aligned" , e.g. the start address be an integer divide of TMR size. 771 * 772 * Note: this memory need be reserved till the driver 773 * uninitializes. 774 */ 775 tmr_size = PSP_TMR_SIZE(psp->adev); 776 777 /* For ASICs support RLC autoload, psp will parse the toc 778 * and calculate the total size of TMR needed */ 779 if (!amdgpu_sriov_vf(psp->adev) && 780 psp->toc.start_addr && 781 psp->toc.size_bytes && 782 psp->fw_pri_buf) { 783 ret = psp_load_toc(psp, &tmr_size); 784 if (ret) { 785 DRM_ERROR("Failed to load toc\n"); 786 return ret; 787 } 788 } 789 790 if (!psp->tmr_bo) { 791 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 792 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 793 PSP_TMR_ALIGNMENT, 794 AMDGPU_HAS_VRAM(psp->adev) ? 795 AMDGPU_GEM_DOMAIN_VRAM : 796 AMDGPU_GEM_DOMAIN_GTT, 797 &psp->tmr_bo, &psp->tmr_mc_addr, 798 pptr); 799 } 800 801 return ret; 802 } 803 804 static bool psp_skip_tmr(struct psp_context *psp) 805 { 806 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 807 case IP_VERSION(11, 0, 9): 808 case IP_VERSION(11, 0, 7): 809 case IP_VERSION(13, 0, 2): 810 case IP_VERSION(13, 0, 10): 811 return true; 812 default: 813 return false; 814 } 815 } 816 817 static int psp_tmr_load(struct psp_context *psp) 818 { 819 int ret; 820 struct psp_gfx_cmd_resp *cmd; 821 822 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 823 * Already set up by host driver. 824 */ 825 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 826 return 0; 827 828 cmd = acquire_psp_cmd_buf(psp); 829 830 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 831 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 832 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 833 834 ret = psp_cmd_submit_buf(psp, NULL, cmd, 835 psp->fence_buf_mc_addr); 836 837 release_psp_cmd_buf(psp); 838 839 return ret; 840 } 841 842 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 843 struct psp_gfx_cmd_resp *cmd) 844 { 845 if (amdgpu_sriov_vf(psp->adev)) 846 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 847 else 848 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 849 } 850 851 static int psp_tmr_unload(struct psp_context *psp) 852 { 853 int ret; 854 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 855 856 psp_prep_tmr_unload_cmd_buf(psp, cmd); 857 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 858 859 ret = psp_cmd_submit_buf(psp, NULL, cmd, 860 psp->fence_buf_mc_addr); 861 862 release_psp_cmd_buf(psp); 863 864 return ret; 865 } 866 867 static int psp_tmr_terminate(struct psp_context *psp) 868 { 869 return psp_tmr_unload(psp); 870 } 871 872 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 873 uint64_t *output_ptr) 874 { 875 int ret; 876 struct psp_gfx_cmd_resp *cmd; 877 878 if (!output_ptr) 879 return -EINVAL; 880 881 if (amdgpu_sriov_vf(psp->adev)) 882 return 0; 883 884 cmd = acquire_psp_cmd_buf(psp); 885 886 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 887 888 ret = psp_cmd_submit_buf(psp, NULL, cmd, 889 psp->fence_buf_mc_addr); 890 891 if (!ret) { 892 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 893 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 894 } 895 896 release_psp_cmd_buf(psp); 897 898 return ret; 899 } 900 901 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 902 { 903 struct psp_context *psp = &adev->psp; 904 struct psp_gfx_cmd_resp *cmd; 905 int ret; 906 907 if (amdgpu_sriov_vf(adev)) 908 return 0; 909 910 cmd = acquire_psp_cmd_buf(psp); 911 912 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 913 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 914 915 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 916 if (!ret) { 917 *boot_cfg = 918 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 919 } 920 921 release_psp_cmd_buf(psp); 922 923 return ret; 924 } 925 926 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 927 { 928 int ret; 929 struct psp_context *psp = &adev->psp; 930 struct psp_gfx_cmd_resp *cmd; 931 932 if (amdgpu_sriov_vf(adev)) 933 return 0; 934 935 cmd = acquire_psp_cmd_buf(psp); 936 937 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 938 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 939 cmd->cmd.boot_cfg.boot_config = boot_cfg; 940 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 941 942 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 943 944 release_psp_cmd_buf(psp); 945 946 return ret; 947 } 948 949 static int psp_rl_load(struct amdgpu_device *adev) 950 { 951 int ret; 952 struct psp_context *psp = &adev->psp; 953 struct psp_gfx_cmd_resp *cmd; 954 955 if (!is_psp_fw_valid(psp->rl)) 956 return 0; 957 958 cmd = acquire_psp_cmd_buf(psp); 959 960 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 961 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 962 963 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 964 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 965 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 966 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 967 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 968 969 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 970 971 release_psp_cmd_buf(psp); 972 973 return ret; 974 } 975 976 static int psp_asd_initialize(struct psp_context *psp) 977 { 978 int ret; 979 980 /* If PSP version doesn't match ASD version, asd loading will be failed. 981 * add workaround to bypass it for sriov now. 982 * TODO: add version check to make it common 983 */ 984 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 985 return 0; 986 987 psp->asd_context.mem_context.shared_mc_addr = 0; 988 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 989 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 990 991 ret = psp_ta_load(psp, &psp->asd_context); 992 if (!ret) 993 psp->asd_context.initialized = true; 994 995 return ret; 996 } 997 998 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 999 uint32_t session_id) 1000 { 1001 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1002 cmd->cmd.cmd_unload_ta.session_id = session_id; 1003 } 1004 1005 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1006 { 1007 int ret; 1008 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1009 1010 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1011 1012 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1013 1014 context->resp_status = cmd->resp.status; 1015 1016 release_psp_cmd_buf(psp); 1017 1018 return ret; 1019 } 1020 1021 static int psp_asd_terminate(struct psp_context *psp) 1022 { 1023 int ret; 1024 1025 if (amdgpu_sriov_vf(psp->adev)) 1026 return 0; 1027 1028 if (!psp->asd_context.initialized) 1029 return 0; 1030 1031 ret = psp_ta_unload(psp, &psp->asd_context); 1032 if (!ret) 1033 psp->asd_context.initialized = false; 1034 1035 return ret; 1036 } 1037 1038 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1039 uint32_t id, uint32_t value) 1040 { 1041 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1042 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1043 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1044 } 1045 1046 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1047 uint32_t value) 1048 { 1049 struct psp_gfx_cmd_resp *cmd; 1050 int ret = 0; 1051 1052 if (reg >= PSP_REG_LAST) 1053 return -EINVAL; 1054 1055 cmd = acquire_psp_cmd_buf(psp); 1056 1057 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1058 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1059 if (ret) 1060 DRM_ERROR("PSP failed to program reg id %d", reg); 1061 1062 release_psp_cmd_buf(psp); 1063 1064 return ret; 1065 } 1066 1067 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1068 uint64_t ta_bin_mc, 1069 struct ta_context *context) 1070 { 1071 cmd->cmd_id = context->ta_load_type; 1072 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1073 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1074 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1075 1076 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1077 lower_32_bits(context->mem_context.shared_mc_addr); 1078 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1079 upper_32_bits(context->mem_context.shared_mc_addr); 1080 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1081 } 1082 1083 int psp_ta_init_shared_buf(struct psp_context *psp, 1084 struct ta_mem_context *mem_ctx) 1085 { 1086 /* 1087 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1088 * physical) for ta to host memory 1089 */ 1090 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1091 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1092 AMDGPU_GEM_DOMAIN_GTT, 1093 &mem_ctx->shared_bo, 1094 &mem_ctx->shared_mc_addr, 1095 &mem_ctx->shared_buf); 1096 } 1097 1098 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1099 uint32_t ta_cmd_id, 1100 uint32_t session_id) 1101 { 1102 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1103 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1104 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1105 } 1106 1107 int psp_ta_invoke(struct psp_context *psp, 1108 uint32_t ta_cmd_id, 1109 struct ta_context *context) 1110 { 1111 int ret; 1112 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1113 1114 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1115 1116 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1117 psp->fence_buf_mc_addr); 1118 1119 context->resp_status = cmd->resp.status; 1120 1121 release_psp_cmd_buf(psp); 1122 1123 return ret; 1124 } 1125 1126 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1127 { 1128 int ret; 1129 struct psp_gfx_cmd_resp *cmd; 1130 1131 cmd = acquire_psp_cmd_buf(psp); 1132 1133 psp_copy_fw(psp, context->bin_desc.start_addr, 1134 context->bin_desc.size_bytes); 1135 1136 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1137 1138 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1139 psp->fence_buf_mc_addr); 1140 1141 context->resp_status = cmd->resp.status; 1142 1143 if (!ret) { 1144 context->session_id = cmd->resp.session_id; 1145 } 1146 1147 release_psp_cmd_buf(psp); 1148 1149 return ret; 1150 } 1151 1152 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1153 { 1154 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1155 } 1156 1157 int psp_xgmi_terminate(struct psp_context *psp) 1158 { 1159 int ret; 1160 struct amdgpu_device *adev = psp->adev; 1161 1162 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1163 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1164 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1165 adev->gmc.xgmi.connected_to_cpu)) 1166 return 0; 1167 1168 if (!psp->xgmi_context.context.initialized) 1169 return 0; 1170 1171 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1172 1173 psp->xgmi_context.context.initialized = false; 1174 1175 return ret; 1176 } 1177 1178 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1179 { 1180 struct ta_xgmi_shared_memory *xgmi_cmd; 1181 int ret; 1182 1183 if (!psp->ta_fw || 1184 !psp->xgmi_context.context.bin_desc.size_bytes || 1185 !psp->xgmi_context.context.bin_desc.start_addr) 1186 return -ENOENT; 1187 1188 if (!load_ta) 1189 goto invoke; 1190 1191 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1192 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1193 1194 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1195 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1196 if (ret) 1197 return ret; 1198 } 1199 1200 /* Load XGMI TA */ 1201 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1202 if (!ret) 1203 psp->xgmi_context.context.initialized = true; 1204 else 1205 return ret; 1206 1207 invoke: 1208 /* Initialize XGMI session */ 1209 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1210 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1211 xgmi_cmd->flag_extend_link_record = set_extended_data; 1212 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1213 1214 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1215 1216 return ret; 1217 } 1218 1219 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1220 { 1221 struct ta_xgmi_shared_memory *xgmi_cmd; 1222 int ret; 1223 1224 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1225 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1226 1227 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1228 1229 /* Invoke xgmi ta to get hive id */ 1230 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1231 if (ret) 1232 return ret; 1233 1234 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1235 1236 return 0; 1237 } 1238 1239 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1240 { 1241 struct ta_xgmi_shared_memory *xgmi_cmd; 1242 int ret; 1243 1244 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1245 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1246 1247 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1248 1249 /* Invoke xgmi ta to get the node id */ 1250 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1251 if (ret) 1252 return ret; 1253 1254 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1255 1256 return 0; 1257 } 1258 1259 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1260 { 1261 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1262 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1263 } 1264 1265 /* 1266 * Chips that support extended topology information require the driver to 1267 * reflect topology information in the opposite direction. This is 1268 * because the TA has already exceeded its link record limit and if the 1269 * TA holds bi-directional information, the driver would have to do 1270 * multiple fetches instead of just two. 1271 */ 1272 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1273 struct psp_xgmi_node_info node_info) 1274 { 1275 struct amdgpu_device *mirror_adev; 1276 struct amdgpu_hive_info *hive; 1277 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1278 uint64_t dst_node_id = node_info.node_id; 1279 uint8_t dst_num_hops = node_info.num_hops; 1280 uint8_t dst_num_links = node_info.num_links; 1281 1282 hive = amdgpu_get_xgmi_hive(psp->adev); 1283 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1284 struct psp_xgmi_topology_info *mirror_top_info; 1285 int j; 1286 1287 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1288 continue; 1289 1290 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1291 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1292 if (mirror_top_info->nodes[j].node_id != src_node_id) 1293 continue; 1294 1295 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1296 /* 1297 * prevent 0 num_links value re-reflection since reflection 1298 * criteria is based on num_hops (direct or indirect). 1299 * 1300 */ 1301 if (dst_num_links) 1302 mirror_top_info->nodes[j].num_links = dst_num_links; 1303 1304 break; 1305 } 1306 1307 break; 1308 } 1309 1310 amdgpu_put_xgmi_hive(hive); 1311 } 1312 1313 int psp_xgmi_get_topology_info(struct psp_context *psp, 1314 int number_devices, 1315 struct psp_xgmi_topology_info *topology, 1316 bool get_extended_data) 1317 { 1318 struct ta_xgmi_shared_memory *xgmi_cmd; 1319 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1320 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1321 int i; 1322 int ret; 1323 1324 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1325 return -EINVAL; 1326 1327 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1328 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1329 xgmi_cmd->flag_extend_link_record = get_extended_data; 1330 1331 /* Fill in the shared memory with topology information as input */ 1332 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1333 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1334 topology_info_input->num_nodes = number_devices; 1335 1336 for (i = 0; i < topology_info_input->num_nodes; i++) { 1337 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1338 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1339 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1340 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1341 } 1342 1343 /* Invoke xgmi ta to get the topology information */ 1344 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1345 if (ret) 1346 return ret; 1347 1348 /* Read the output topology information from the shared memory */ 1349 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1350 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1351 for (i = 0; i < topology->num_nodes; i++) { 1352 /* extended data will either be 0 or equal to non-extended data */ 1353 if (topology_info_output->nodes[i].num_hops) 1354 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1355 1356 /* non-extended data gets everything here so no need to update */ 1357 if (!get_extended_data) { 1358 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1359 topology->nodes[i].is_sharing_enabled = 1360 topology_info_output->nodes[i].is_sharing_enabled; 1361 topology->nodes[i].sdma_engine = 1362 topology_info_output->nodes[i].sdma_engine; 1363 } 1364 1365 } 1366 1367 /* Invoke xgmi ta again to get the link information */ 1368 if (psp_xgmi_peer_link_info_supported(psp)) { 1369 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1370 1371 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1372 1373 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1374 1375 if (ret) 1376 return ret; 1377 1378 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1379 for (i = 0; i < topology->num_nodes; i++) { 1380 /* accumulate num_links on extended data */ 1381 topology->nodes[i].num_links = get_extended_data ? 1382 topology->nodes[i].num_links + 1383 link_info_output->nodes[i].num_links : 1384 link_info_output->nodes[i].num_links; 1385 1386 /* reflect the topology information for bi-directionality */ 1387 if (psp->xgmi_context.supports_extended_data && 1388 get_extended_data && topology->nodes[i].num_hops) 1389 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1390 } 1391 } 1392 1393 return 0; 1394 } 1395 1396 int psp_xgmi_set_topology_info(struct psp_context *psp, 1397 int number_devices, 1398 struct psp_xgmi_topology_info *topology) 1399 { 1400 struct ta_xgmi_shared_memory *xgmi_cmd; 1401 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1402 int i; 1403 1404 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1405 return -EINVAL; 1406 1407 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1408 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1409 1410 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1411 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1412 topology_info_input->num_nodes = number_devices; 1413 1414 for (i = 0; i < topology_info_input->num_nodes; i++) { 1415 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1416 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1417 topology_info_input->nodes[i].is_sharing_enabled = 1; 1418 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1419 } 1420 1421 /* Invoke xgmi ta to set topology information */ 1422 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1423 } 1424 1425 // ras begin 1426 static void psp_ras_ta_check_status(struct psp_context *psp) 1427 { 1428 struct ta_ras_shared_memory *ras_cmd = 1429 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1430 1431 switch (ras_cmd->ras_status) { 1432 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1433 dev_warn(psp->adev->dev, 1434 "RAS WARNING: cmd failed due to unsupported ip\n"); 1435 break; 1436 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1437 dev_warn(psp->adev->dev, 1438 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1439 break; 1440 case TA_RAS_STATUS__SUCCESS: 1441 break; 1442 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1443 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1444 dev_warn(psp->adev->dev, 1445 "RAS WARNING: Inject error to critical region is not allowed\n"); 1446 break; 1447 default: 1448 dev_warn(psp->adev->dev, 1449 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1450 break; 1451 } 1452 } 1453 1454 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1455 { 1456 struct ta_ras_shared_memory *ras_cmd; 1457 int ret; 1458 1459 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1460 1461 /* 1462 * TODO: bypass the loading in sriov for now 1463 */ 1464 if (amdgpu_sriov_vf(psp->adev)) 1465 return 0; 1466 1467 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1468 1469 if (amdgpu_ras_intr_triggered()) 1470 return ret; 1471 1472 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1473 { 1474 DRM_WARN("RAS: Unsupported Interface"); 1475 return -EINVAL; 1476 } 1477 1478 if (!ret) { 1479 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1480 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1481 1482 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1483 } 1484 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1485 dev_warn(psp->adev->dev, 1486 "RAS internal register access blocked\n"); 1487 1488 psp_ras_ta_check_status(psp); 1489 } 1490 1491 return ret; 1492 } 1493 1494 int psp_ras_enable_features(struct psp_context *psp, 1495 union ta_ras_cmd_input *info, bool enable) 1496 { 1497 struct ta_ras_shared_memory *ras_cmd; 1498 int ret; 1499 1500 if (!psp->ras_context.context.initialized) 1501 return -EINVAL; 1502 1503 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1504 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1505 1506 if (enable) 1507 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1508 else 1509 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1510 1511 ras_cmd->ras_in_message = *info; 1512 1513 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1514 if (ret) 1515 return -EINVAL; 1516 1517 return 0; 1518 } 1519 1520 int psp_ras_terminate(struct psp_context *psp) 1521 { 1522 int ret; 1523 1524 /* 1525 * TODO: bypass the terminate in sriov for now 1526 */ 1527 if (amdgpu_sriov_vf(psp->adev)) 1528 return 0; 1529 1530 if (!psp->ras_context.context.initialized) 1531 return 0; 1532 1533 ret = psp_ta_unload(psp, &psp->ras_context.context); 1534 1535 psp->ras_context.context.initialized = false; 1536 1537 return ret; 1538 } 1539 1540 int psp_ras_initialize(struct psp_context *psp) 1541 { 1542 int ret; 1543 uint32_t boot_cfg = 0xFF; 1544 struct amdgpu_device *adev = psp->adev; 1545 struct ta_ras_shared_memory *ras_cmd; 1546 1547 /* 1548 * TODO: bypass the initialize in sriov for now 1549 */ 1550 if (amdgpu_sriov_vf(adev)) 1551 return 0; 1552 1553 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1554 !adev->psp.ras_context.context.bin_desc.start_addr) { 1555 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1556 return 0; 1557 } 1558 1559 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1560 /* query GECC enablement status from boot config 1561 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1562 */ 1563 ret = psp_boot_config_get(adev, &boot_cfg); 1564 if (ret) 1565 dev_warn(adev->dev, "PSP get boot config failed\n"); 1566 1567 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1568 if (!boot_cfg) { 1569 dev_info(adev->dev, "GECC is disabled\n"); 1570 } else { 1571 /* disable GECC in next boot cycle if ras is 1572 * disabled by module parameter amdgpu_ras_enable 1573 * and/or amdgpu_ras_mask, or boot_config_get call 1574 * is failed 1575 */ 1576 ret = psp_boot_config_set(adev, 0); 1577 if (ret) 1578 dev_warn(adev->dev, "PSP set boot config failed\n"); 1579 else 1580 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1581 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1582 } 1583 } else { 1584 if (1 == boot_cfg) { 1585 dev_info(adev->dev, "GECC is enabled\n"); 1586 } else { 1587 /* enable GECC in next boot cycle if it is disabled 1588 * in boot config, or force enable GECC if failed to 1589 * get boot configuration 1590 */ 1591 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1592 if (ret) 1593 dev_warn(adev->dev, "PSP set boot config failed\n"); 1594 else 1595 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1596 } 1597 } 1598 } 1599 1600 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1601 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1602 1603 if (!psp->ras_context.context.mem_context.shared_buf) { 1604 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1605 if (ret) 1606 return ret; 1607 } 1608 1609 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1610 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1611 1612 if (amdgpu_ras_is_poison_mode_supported(adev)) 1613 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1614 if (!adev->gmc.xgmi.connected_to_cpu) 1615 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1616 1617 ret = psp_ta_load(psp, &psp->ras_context.context); 1618 1619 if (!ret && !ras_cmd->ras_status) 1620 psp->ras_context.context.initialized = true; 1621 else { 1622 if (ras_cmd->ras_status) 1623 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1624 1625 /* fail to load RAS TA */ 1626 psp->ras_context.context.initialized = false; 1627 } 1628 1629 return ret; 1630 } 1631 1632 int psp_ras_trigger_error(struct psp_context *psp, 1633 struct ta_ras_trigger_error_input *info) 1634 { 1635 struct ta_ras_shared_memory *ras_cmd; 1636 int ret; 1637 1638 if (!psp->ras_context.context.initialized) 1639 return -EINVAL; 1640 1641 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1642 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1643 1644 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1645 ras_cmd->ras_in_message.trigger_error = *info; 1646 1647 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1648 if (ret) 1649 return -EINVAL; 1650 1651 /* If err_event_athub occurs error inject was successful, however 1652 return status from TA is no long reliable */ 1653 if (amdgpu_ras_intr_triggered()) 1654 return 0; 1655 1656 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1657 return -EACCES; 1658 else if (ras_cmd->ras_status) 1659 return -EINVAL; 1660 1661 return 0; 1662 } 1663 // ras end 1664 1665 // HDCP start 1666 static int psp_hdcp_initialize(struct psp_context *psp) 1667 { 1668 int ret; 1669 1670 /* 1671 * TODO: bypass the initialize in sriov for now 1672 */ 1673 if (amdgpu_sriov_vf(psp->adev)) 1674 return 0; 1675 1676 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1677 !psp->hdcp_context.context.bin_desc.start_addr) { 1678 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1679 return 0; 1680 } 1681 1682 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1683 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1684 1685 if (!psp->hdcp_context.context.initialized) { 1686 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1687 if (ret) 1688 return ret; 1689 } 1690 1691 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1692 if (!ret) { 1693 psp->hdcp_context.context.initialized = true; 1694 mutex_init(&psp->hdcp_context.mutex); 1695 } 1696 1697 return ret; 1698 } 1699 1700 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1701 { 1702 /* 1703 * TODO: bypass the loading in sriov for now 1704 */ 1705 if (amdgpu_sriov_vf(psp->adev)) 1706 return 0; 1707 1708 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1709 } 1710 1711 static int psp_hdcp_terminate(struct psp_context *psp) 1712 { 1713 int ret; 1714 1715 /* 1716 * TODO: bypass the terminate in sriov for now 1717 */ 1718 if (amdgpu_sriov_vf(psp->adev)) 1719 return 0; 1720 1721 if (!psp->hdcp_context.context.initialized) 1722 return 0; 1723 1724 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1725 1726 psp->hdcp_context.context.initialized = false; 1727 1728 return ret; 1729 } 1730 // HDCP end 1731 1732 // DTM start 1733 static int psp_dtm_initialize(struct psp_context *psp) 1734 { 1735 int ret; 1736 1737 /* 1738 * TODO: bypass the initialize in sriov for now 1739 */ 1740 if (amdgpu_sriov_vf(psp->adev)) 1741 return 0; 1742 1743 if (!psp->dtm_context.context.bin_desc.size_bytes || 1744 !psp->dtm_context.context.bin_desc.start_addr) { 1745 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1746 return 0; 1747 } 1748 1749 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1750 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1751 1752 if (!psp->dtm_context.context.initialized) { 1753 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1754 if (ret) 1755 return ret; 1756 } 1757 1758 ret = psp_ta_load(psp, &psp->dtm_context.context); 1759 if (!ret) { 1760 psp->dtm_context.context.initialized = true; 1761 mutex_init(&psp->dtm_context.mutex); 1762 } 1763 1764 return ret; 1765 } 1766 1767 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1768 { 1769 /* 1770 * TODO: bypass the loading in sriov for now 1771 */ 1772 if (amdgpu_sriov_vf(psp->adev)) 1773 return 0; 1774 1775 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1776 } 1777 1778 static int psp_dtm_terminate(struct psp_context *psp) 1779 { 1780 int ret; 1781 1782 /* 1783 * TODO: bypass the terminate in sriov for now 1784 */ 1785 if (amdgpu_sriov_vf(psp->adev)) 1786 return 0; 1787 1788 if (!psp->dtm_context.context.initialized) 1789 return 0; 1790 1791 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1792 1793 psp->dtm_context.context.initialized = false; 1794 1795 return ret; 1796 } 1797 // DTM end 1798 1799 // RAP start 1800 static int psp_rap_initialize(struct psp_context *psp) 1801 { 1802 int ret; 1803 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1804 1805 /* 1806 * TODO: bypass the initialize in sriov for now 1807 */ 1808 if (amdgpu_sriov_vf(psp->adev)) 1809 return 0; 1810 1811 if (!psp->rap_context.context.bin_desc.size_bytes || 1812 !psp->rap_context.context.bin_desc.start_addr) { 1813 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1814 return 0; 1815 } 1816 1817 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1818 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1819 1820 if (!psp->rap_context.context.initialized) { 1821 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1822 if (ret) 1823 return ret; 1824 } 1825 1826 ret = psp_ta_load(psp, &psp->rap_context.context); 1827 if (!ret) { 1828 psp->rap_context.context.initialized = true; 1829 mutex_init(&psp->rap_context.mutex); 1830 } else 1831 return ret; 1832 1833 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1834 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1835 psp_rap_terminate(psp); 1836 /* free rap shared memory */ 1837 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1838 1839 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1840 ret, status); 1841 1842 return ret; 1843 } 1844 1845 return 0; 1846 } 1847 1848 static int psp_rap_terminate(struct psp_context *psp) 1849 { 1850 int ret; 1851 1852 if (!psp->rap_context.context.initialized) 1853 return 0; 1854 1855 ret = psp_ta_unload(psp, &psp->rap_context.context); 1856 1857 psp->rap_context.context.initialized = false; 1858 1859 return ret; 1860 } 1861 1862 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1863 { 1864 struct ta_rap_shared_memory *rap_cmd; 1865 int ret = 0; 1866 1867 if (!psp->rap_context.context.initialized) 1868 return 0; 1869 1870 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1871 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1872 return -EINVAL; 1873 1874 mutex_lock(&psp->rap_context.mutex); 1875 1876 rap_cmd = (struct ta_rap_shared_memory *) 1877 psp->rap_context.context.mem_context.shared_buf; 1878 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1879 1880 rap_cmd->cmd_id = ta_cmd_id; 1881 rap_cmd->validation_method_id = METHOD_A; 1882 1883 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1884 if (ret) 1885 goto out_unlock; 1886 1887 if (status) 1888 *status = rap_cmd->rap_status; 1889 1890 out_unlock: 1891 mutex_unlock(&psp->rap_context.mutex); 1892 1893 return ret; 1894 } 1895 // RAP end 1896 1897 /* securedisplay start */ 1898 static int psp_securedisplay_initialize(struct psp_context *psp) 1899 { 1900 int ret; 1901 struct ta_securedisplay_cmd *securedisplay_cmd; 1902 1903 /* 1904 * TODO: bypass the initialize in sriov for now 1905 */ 1906 if (amdgpu_sriov_vf(psp->adev)) 1907 return 0; 1908 1909 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1910 !psp->securedisplay_context.context.bin_desc.start_addr) { 1911 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1912 return 0; 1913 } 1914 1915 psp->securedisplay_context.context.mem_context.shared_mem_size = 1916 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1917 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1918 1919 if (!psp->securedisplay_context.context.initialized) { 1920 ret = psp_ta_init_shared_buf(psp, 1921 &psp->securedisplay_context.context.mem_context); 1922 if (ret) 1923 return ret; 1924 } 1925 1926 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 1927 if (!ret) { 1928 psp->securedisplay_context.context.initialized = true; 1929 mutex_init(&psp->securedisplay_context.mutex); 1930 } else 1931 return ret; 1932 1933 mutex_lock(&psp->securedisplay_context.mutex); 1934 1935 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1936 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1937 1938 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1939 1940 mutex_unlock(&psp->securedisplay_context.mutex); 1941 1942 if (ret) { 1943 psp_securedisplay_terminate(psp); 1944 /* free securedisplay shared memory */ 1945 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1946 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1947 return -EINVAL; 1948 } 1949 1950 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1951 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1952 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1953 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1954 } 1955 1956 return 0; 1957 } 1958 1959 static int psp_securedisplay_terminate(struct psp_context *psp) 1960 { 1961 int ret; 1962 1963 /* 1964 * TODO:bypass the terminate in sriov for now 1965 */ 1966 if (amdgpu_sriov_vf(psp->adev)) 1967 return 0; 1968 1969 if (!psp->securedisplay_context.context.initialized) 1970 return 0; 1971 1972 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 1973 1974 psp->securedisplay_context.context.initialized = false; 1975 1976 return ret; 1977 } 1978 1979 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1980 { 1981 int ret; 1982 1983 if (!psp->securedisplay_context.context.initialized) 1984 return -EINVAL; 1985 1986 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1987 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1988 return -EINVAL; 1989 1990 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1991 1992 return ret; 1993 } 1994 /* SECUREDISPLAY end */ 1995 1996 static int psp_hw_start(struct psp_context *psp) 1997 { 1998 struct amdgpu_device *adev = psp->adev; 1999 int ret; 2000 2001 if (!amdgpu_sriov_vf(adev)) { 2002 if ((is_psp_fw_valid(psp->kdb)) && 2003 (psp->funcs->bootloader_load_kdb != NULL)) { 2004 ret = psp_bootloader_load_kdb(psp); 2005 if (ret) { 2006 DRM_ERROR("PSP load kdb failed!\n"); 2007 return ret; 2008 } 2009 } 2010 2011 if ((is_psp_fw_valid(psp->spl)) && 2012 (psp->funcs->bootloader_load_spl != NULL)) { 2013 ret = psp_bootloader_load_spl(psp); 2014 if (ret) { 2015 DRM_ERROR("PSP load spl failed!\n"); 2016 return ret; 2017 } 2018 } 2019 2020 if ((is_psp_fw_valid(psp->sys)) && 2021 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2022 ret = psp_bootloader_load_sysdrv(psp); 2023 if (ret) { 2024 DRM_ERROR("PSP load sys drv failed!\n"); 2025 return ret; 2026 } 2027 } 2028 2029 if ((is_psp_fw_valid(psp->soc_drv)) && 2030 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2031 ret = psp_bootloader_load_soc_drv(psp); 2032 if (ret) { 2033 DRM_ERROR("PSP load soc drv failed!\n"); 2034 return ret; 2035 } 2036 } 2037 2038 if ((is_psp_fw_valid(psp->intf_drv)) && 2039 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2040 ret = psp_bootloader_load_intf_drv(psp); 2041 if (ret) { 2042 DRM_ERROR("PSP load intf drv failed!\n"); 2043 return ret; 2044 } 2045 } 2046 2047 if ((is_psp_fw_valid(psp->dbg_drv)) && 2048 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2049 ret = psp_bootloader_load_dbg_drv(psp); 2050 if (ret) { 2051 DRM_ERROR("PSP load dbg drv failed!\n"); 2052 return ret; 2053 } 2054 } 2055 2056 if ((is_psp_fw_valid(psp->ras_drv)) && 2057 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2058 ret = psp_bootloader_load_ras_drv(psp); 2059 if (ret) { 2060 DRM_ERROR("PSP load ras_drv failed!\n"); 2061 return ret; 2062 } 2063 } 2064 2065 if ((is_psp_fw_valid(psp->sos)) && 2066 (psp->funcs->bootloader_load_sos != NULL)) { 2067 ret = psp_bootloader_load_sos(psp); 2068 if (ret) { 2069 DRM_ERROR("PSP load sos failed!\n"); 2070 return ret; 2071 } 2072 } 2073 } 2074 2075 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2076 if (ret) { 2077 DRM_ERROR("PSP create ring failed!\n"); 2078 return ret; 2079 } 2080 2081 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2082 goto skip_pin_bo; 2083 2084 ret = psp_tmr_init(psp); 2085 if (ret) { 2086 DRM_ERROR("PSP tmr init failed!\n"); 2087 return ret; 2088 } 2089 2090 skip_pin_bo: 2091 /* 2092 * For ASICs with DF Cstate management centralized 2093 * to PMFW, TMR setup should be performed after PMFW 2094 * loaded and before other non-psp firmware loaded. 2095 */ 2096 if (psp->pmfw_centralized_cstate_management) { 2097 ret = psp_load_smu_fw(psp); 2098 if (ret) 2099 return ret; 2100 } 2101 2102 ret = psp_tmr_load(psp); 2103 if (ret) { 2104 DRM_ERROR("PSP load tmr failed!\n"); 2105 return ret; 2106 } 2107 2108 return 0; 2109 } 2110 2111 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2112 enum psp_gfx_fw_type *type) 2113 { 2114 switch (ucode->ucode_id) { 2115 case AMDGPU_UCODE_ID_CAP: 2116 *type = GFX_FW_TYPE_CAP; 2117 break; 2118 case AMDGPU_UCODE_ID_SDMA0: 2119 *type = GFX_FW_TYPE_SDMA0; 2120 break; 2121 case AMDGPU_UCODE_ID_SDMA1: 2122 *type = GFX_FW_TYPE_SDMA1; 2123 break; 2124 case AMDGPU_UCODE_ID_SDMA2: 2125 *type = GFX_FW_TYPE_SDMA2; 2126 break; 2127 case AMDGPU_UCODE_ID_SDMA3: 2128 *type = GFX_FW_TYPE_SDMA3; 2129 break; 2130 case AMDGPU_UCODE_ID_SDMA4: 2131 *type = GFX_FW_TYPE_SDMA4; 2132 break; 2133 case AMDGPU_UCODE_ID_SDMA5: 2134 *type = GFX_FW_TYPE_SDMA5; 2135 break; 2136 case AMDGPU_UCODE_ID_SDMA6: 2137 *type = GFX_FW_TYPE_SDMA6; 2138 break; 2139 case AMDGPU_UCODE_ID_SDMA7: 2140 *type = GFX_FW_TYPE_SDMA7; 2141 break; 2142 case AMDGPU_UCODE_ID_CP_MES: 2143 *type = GFX_FW_TYPE_CP_MES; 2144 break; 2145 case AMDGPU_UCODE_ID_CP_MES_DATA: 2146 *type = GFX_FW_TYPE_MES_STACK; 2147 break; 2148 case AMDGPU_UCODE_ID_CP_MES1: 2149 *type = GFX_FW_TYPE_CP_MES_KIQ; 2150 break; 2151 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2152 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2153 break; 2154 case AMDGPU_UCODE_ID_CP_CE: 2155 *type = GFX_FW_TYPE_CP_CE; 2156 break; 2157 case AMDGPU_UCODE_ID_CP_PFP: 2158 *type = GFX_FW_TYPE_CP_PFP; 2159 break; 2160 case AMDGPU_UCODE_ID_CP_ME: 2161 *type = GFX_FW_TYPE_CP_ME; 2162 break; 2163 case AMDGPU_UCODE_ID_CP_MEC1: 2164 *type = GFX_FW_TYPE_CP_MEC; 2165 break; 2166 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2167 *type = GFX_FW_TYPE_CP_MEC_ME1; 2168 break; 2169 case AMDGPU_UCODE_ID_CP_MEC2: 2170 *type = GFX_FW_TYPE_CP_MEC; 2171 break; 2172 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2173 *type = GFX_FW_TYPE_CP_MEC_ME2; 2174 break; 2175 case AMDGPU_UCODE_ID_RLC_P: 2176 *type = GFX_FW_TYPE_RLC_P; 2177 break; 2178 case AMDGPU_UCODE_ID_RLC_V: 2179 *type = GFX_FW_TYPE_RLC_V; 2180 break; 2181 case AMDGPU_UCODE_ID_RLC_G: 2182 *type = GFX_FW_TYPE_RLC_G; 2183 break; 2184 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2185 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2186 break; 2187 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2188 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2189 break; 2190 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2191 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2192 break; 2193 case AMDGPU_UCODE_ID_RLC_IRAM: 2194 *type = GFX_FW_TYPE_RLC_IRAM; 2195 break; 2196 case AMDGPU_UCODE_ID_RLC_DRAM: 2197 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2198 break; 2199 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2200 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2201 break; 2202 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2203 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2204 break; 2205 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2206 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2207 break; 2208 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2209 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2210 break; 2211 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2212 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2213 break; 2214 case AMDGPU_UCODE_ID_SMC: 2215 *type = GFX_FW_TYPE_SMU; 2216 break; 2217 case AMDGPU_UCODE_ID_PPTABLE: 2218 *type = GFX_FW_TYPE_PPTABLE; 2219 break; 2220 case AMDGPU_UCODE_ID_UVD: 2221 *type = GFX_FW_TYPE_UVD; 2222 break; 2223 case AMDGPU_UCODE_ID_UVD1: 2224 *type = GFX_FW_TYPE_UVD1; 2225 break; 2226 case AMDGPU_UCODE_ID_VCE: 2227 *type = GFX_FW_TYPE_VCE; 2228 break; 2229 case AMDGPU_UCODE_ID_VCN: 2230 *type = GFX_FW_TYPE_VCN; 2231 break; 2232 case AMDGPU_UCODE_ID_VCN1: 2233 *type = GFX_FW_TYPE_VCN1; 2234 break; 2235 case AMDGPU_UCODE_ID_DMCU_ERAM: 2236 *type = GFX_FW_TYPE_DMCU_ERAM; 2237 break; 2238 case AMDGPU_UCODE_ID_DMCU_INTV: 2239 *type = GFX_FW_TYPE_DMCU_ISR; 2240 break; 2241 case AMDGPU_UCODE_ID_VCN0_RAM: 2242 *type = GFX_FW_TYPE_VCN0_RAM; 2243 break; 2244 case AMDGPU_UCODE_ID_VCN1_RAM: 2245 *type = GFX_FW_TYPE_VCN1_RAM; 2246 break; 2247 case AMDGPU_UCODE_ID_DMCUB: 2248 *type = GFX_FW_TYPE_DMUB; 2249 break; 2250 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2251 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2252 break; 2253 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2254 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2255 break; 2256 case AMDGPU_UCODE_ID_IMU_I: 2257 *type = GFX_FW_TYPE_IMU_I; 2258 break; 2259 case AMDGPU_UCODE_ID_IMU_D: 2260 *type = GFX_FW_TYPE_IMU_D; 2261 break; 2262 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2263 *type = GFX_FW_TYPE_RS64_PFP; 2264 break; 2265 case AMDGPU_UCODE_ID_CP_RS64_ME: 2266 *type = GFX_FW_TYPE_RS64_ME; 2267 break; 2268 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2269 *type = GFX_FW_TYPE_RS64_MEC; 2270 break; 2271 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2272 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2273 break; 2274 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2275 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2276 break; 2277 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2278 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2279 break; 2280 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2281 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2282 break; 2283 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2284 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2285 break; 2286 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2287 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2288 break; 2289 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2290 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2291 break; 2292 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2293 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2294 break; 2295 case AMDGPU_UCODE_ID_MAXIMUM: 2296 default: 2297 return -EINVAL; 2298 } 2299 2300 return 0; 2301 } 2302 2303 static void psp_print_fw_hdr(struct psp_context *psp, 2304 struct amdgpu_firmware_info *ucode) 2305 { 2306 struct amdgpu_device *adev = psp->adev; 2307 struct common_firmware_header *hdr; 2308 2309 switch (ucode->ucode_id) { 2310 case AMDGPU_UCODE_ID_SDMA0: 2311 case AMDGPU_UCODE_ID_SDMA1: 2312 case AMDGPU_UCODE_ID_SDMA2: 2313 case AMDGPU_UCODE_ID_SDMA3: 2314 case AMDGPU_UCODE_ID_SDMA4: 2315 case AMDGPU_UCODE_ID_SDMA5: 2316 case AMDGPU_UCODE_ID_SDMA6: 2317 case AMDGPU_UCODE_ID_SDMA7: 2318 hdr = (struct common_firmware_header *) 2319 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2320 amdgpu_ucode_print_sdma_hdr(hdr); 2321 break; 2322 case AMDGPU_UCODE_ID_CP_CE: 2323 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2324 amdgpu_ucode_print_gfx_hdr(hdr); 2325 break; 2326 case AMDGPU_UCODE_ID_CP_PFP: 2327 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2328 amdgpu_ucode_print_gfx_hdr(hdr); 2329 break; 2330 case AMDGPU_UCODE_ID_CP_ME: 2331 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2332 amdgpu_ucode_print_gfx_hdr(hdr); 2333 break; 2334 case AMDGPU_UCODE_ID_CP_MEC1: 2335 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2336 amdgpu_ucode_print_gfx_hdr(hdr); 2337 break; 2338 case AMDGPU_UCODE_ID_RLC_G: 2339 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2340 amdgpu_ucode_print_rlc_hdr(hdr); 2341 break; 2342 case AMDGPU_UCODE_ID_SMC: 2343 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2344 amdgpu_ucode_print_smc_hdr(hdr); 2345 break; 2346 default: 2347 break; 2348 } 2349 } 2350 2351 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2352 struct psp_gfx_cmd_resp *cmd) 2353 { 2354 int ret; 2355 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2356 2357 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2358 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2359 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2360 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2361 2362 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2363 if (ret) 2364 DRM_ERROR("Unknown firmware type\n"); 2365 2366 return ret; 2367 } 2368 2369 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2370 struct amdgpu_firmware_info *ucode) 2371 { 2372 int ret = 0; 2373 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2374 2375 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2376 if (!ret) { 2377 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2378 psp->fence_buf_mc_addr); 2379 } 2380 2381 release_psp_cmd_buf(psp); 2382 2383 return ret; 2384 } 2385 2386 static int psp_load_smu_fw(struct psp_context *psp) 2387 { 2388 int ret; 2389 struct amdgpu_device *adev = psp->adev; 2390 struct amdgpu_firmware_info *ucode = 2391 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2392 struct amdgpu_ras *ras = psp->ras_context.ras; 2393 2394 /* 2395 * Skip SMU FW reloading in case of using BACO for runpm only, 2396 * as SMU is always alive. 2397 */ 2398 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2399 return 0; 2400 2401 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2402 return 0; 2403 2404 if ((amdgpu_in_reset(adev) && 2405 ras && adev->ras_enabled && 2406 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2407 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2408 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2409 if (ret) { 2410 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2411 } 2412 } 2413 2414 ret = psp_execute_non_psp_fw_load(psp, ucode); 2415 2416 if (ret) 2417 DRM_ERROR("PSP load smu failed!\n"); 2418 2419 return ret; 2420 } 2421 2422 static bool fw_load_skip_check(struct psp_context *psp, 2423 struct amdgpu_firmware_info *ucode) 2424 { 2425 if (!ucode->fw || !ucode->ucode_size) 2426 return true; 2427 2428 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2429 (psp_smu_reload_quirk(psp) || 2430 psp->autoload_supported || 2431 psp->pmfw_centralized_cstate_management)) 2432 return true; 2433 2434 if (amdgpu_sriov_vf(psp->adev) && 2435 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2436 return true; 2437 2438 if (psp->autoload_supported && 2439 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2440 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2441 /* skip mec JT when autoload is enabled */ 2442 return true; 2443 2444 return false; 2445 } 2446 2447 int psp_load_fw_list(struct psp_context *psp, 2448 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2449 { 2450 int ret = 0, i; 2451 struct amdgpu_firmware_info *ucode; 2452 2453 for (i = 0; i < ucode_count; ++i) { 2454 ucode = ucode_list[i]; 2455 psp_print_fw_hdr(psp, ucode); 2456 ret = psp_execute_non_psp_fw_load(psp, ucode); 2457 if (ret) 2458 return ret; 2459 } 2460 return ret; 2461 } 2462 2463 static int psp_load_non_psp_fw(struct psp_context *psp) 2464 { 2465 int i, ret; 2466 struct amdgpu_firmware_info *ucode; 2467 struct amdgpu_device *adev = psp->adev; 2468 2469 if (psp->autoload_supported && 2470 !psp->pmfw_centralized_cstate_management) { 2471 ret = psp_load_smu_fw(psp); 2472 if (ret) 2473 return ret; 2474 } 2475 2476 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2477 ucode = &adev->firmware.ucode[i]; 2478 2479 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2480 !fw_load_skip_check(psp, ucode)) { 2481 ret = psp_load_smu_fw(psp); 2482 if (ret) 2483 return ret; 2484 continue; 2485 } 2486 2487 if (fw_load_skip_check(psp, ucode)) 2488 continue; 2489 2490 if (psp->autoload_supported && 2491 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2492 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2493 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2494 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2495 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2496 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2497 /* PSP only receive one SDMA fw for sienna_cichlid, 2498 * as all four sdma fw are same */ 2499 continue; 2500 2501 psp_print_fw_hdr(psp, ucode); 2502 2503 ret = psp_execute_non_psp_fw_load(psp, ucode); 2504 if (ret) 2505 return ret; 2506 2507 /* Start rlc autoload after psp recieved all the gfx firmware */ 2508 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2509 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2510 ret = psp_rlc_autoload_start(psp); 2511 if (ret) { 2512 DRM_ERROR("Failed to start rlc autoload\n"); 2513 return ret; 2514 } 2515 } 2516 } 2517 2518 return 0; 2519 } 2520 2521 static int psp_load_fw(struct amdgpu_device *adev) 2522 { 2523 int ret; 2524 struct psp_context *psp = &adev->psp; 2525 2526 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2527 /* should not destroy ring, only stop */ 2528 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2529 } else { 2530 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2531 2532 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2533 if (ret) { 2534 DRM_ERROR("PSP ring init failed!\n"); 2535 goto failed; 2536 } 2537 } 2538 2539 ret = psp_hw_start(psp); 2540 if (ret) 2541 goto failed; 2542 2543 ret = psp_load_non_psp_fw(psp); 2544 if (ret) 2545 goto failed1; 2546 2547 ret = psp_asd_initialize(psp); 2548 if (ret) { 2549 DRM_ERROR("PSP load asd failed!\n"); 2550 goto failed1; 2551 } 2552 2553 ret = psp_rl_load(adev); 2554 if (ret) { 2555 DRM_ERROR("PSP load RL failed!\n"); 2556 goto failed1; 2557 } 2558 2559 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2560 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2561 ret = psp_xgmi_initialize(psp, false, true); 2562 /* Warning the XGMI seesion initialize failure 2563 * Instead of stop driver initialization 2564 */ 2565 if (ret) 2566 dev_err(psp->adev->dev, 2567 "XGMI: Failed to initialize XGMI session\n"); 2568 } 2569 } 2570 2571 if (psp->ta_fw) { 2572 ret = psp_ras_initialize(psp); 2573 if (ret) 2574 dev_err(psp->adev->dev, 2575 "RAS: Failed to initialize RAS\n"); 2576 2577 ret = psp_hdcp_initialize(psp); 2578 if (ret) 2579 dev_err(psp->adev->dev, 2580 "HDCP: Failed to initialize HDCP\n"); 2581 2582 ret = psp_dtm_initialize(psp); 2583 if (ret) 2584 dev_err(psp->adev->dev, 2585 "DTM: Failed to initialize DTM\n"); 2586 2587 ret = psp_rap_initialize(psp); 2588 if (ret) 2589 dev_err(psp->adev->dev, 2590 "RAP: Failed to initialize RAP\n"); 2591 2592 ret = psp_securedisplay_initialize(psp); 2593 if (ret) 2594 dev_err(psp->adev->dev, 2595 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2596 } 2597 2598 return 0; 2599 2600 failed1: 2601 psp_free_shared_bufs(psp); 2602 failed: 2603 /* 2604 * all cleanup jobs (xgmi terminate, ras terminate, 2605 * ring destroy, cmd/fence/fw buffers destory, 2606 * psp->cmd destory) are delayed to psp_hw_fini 2607 */ 2608 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2609 return ret; 2610 } 2611 2612 static int psp_hw_init(void *handle) 2613 { 2614 int ret; 2615 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2616 2617 mutex_lock(&adev->firmware.mutex); 2618 /* 2619 * This sequence is just used on hw_init only once, no need on 2620 * resume. 2621 */ 2622 ret = amdgpu_ucode_init_bo(adev); 2623 if (ret) 2624 goto failed; 2625 2626 ret = psp_load_fw(adev); 2627 if (ret) { 2628 DRM_ERROR("PSP firmware loading failed\n"); 2629 goto failed; 2630 } 2631 2632 mutex_unlock(&adev->firmware.mutex); 2633 return 0; 2634 2635 failed: 2636 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2637 mutex_unlock(&adev->firmware.mutex); 2638 return -EINVAL; 2639 } 2640 2641 static int psp_hw_fini(void *handle) 2642 { 2643 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2644 struct psp_context *psp = &adev->psp; 2645 2646 if (psp->ta_fw) { 2647 psp_ras_terminate(psp); 2648 psp_securedisplay_terminate(psp); 2649 psp_rap_terminate(psp); 2650 psp_dtm_terminate(psp); 2651 psp_hdcp_terminate(psp); 2652 2653 if (adev->gmc.xgmi.num_physical_nodes > 1) 2654 psp_xgmi_terminate(psp); 2655 } 2656 2657 psp_asd_terminate(psp); 2658 psp_tmr_terminate(psp); 2659 2660 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2661 2662 psp_free_shared_bufs(psp); 2663 2664 return 0; 2665 } 2666 2667 static int psp_suspend(void *handle) 2668 { 2669 int ret = 0; 2670 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2671 struct psp_context *psp = &adev->psp; 2672 2673 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2674 psp->xgmi_context.context.initialized) { 2675 ret = psp_xgmi_terminate(psp); 2676 if (ret) { 2677 DRM_ERROR("Failed to terminate xgmi ta\n"); 2678 goto out; 2679 } 2680 } 2681 2682 if (psp->ta_fw) { 2683 ret = psp_ras_terminate(psp); 2684 if (ret) { 2685 DRM_ERROR("Failed to terminate ras ta\n"); 2686 goto out; 2687 } 2688 ret = psp_hdcp_terminate(psp); 2689 if (ret) { 2690 DRM_ERROR("Failed to terminate hdcp ta\n"); 2691 goto out; 2692 } 2693 ret = psp_dtm_terminate(psp); 2694 if (ret) { 2695 DRM_ERROR("Failed to terminate dtm ta\n"); 2696 goto out; 2697 } 2698 ret = psp_rap_terminate(psp); 2699 if (ret) { 2700 DRM_ERROR("Failed to terminate rap ta\n"); 2701 goto out; 2702 } 2703 ret = psp_securedisplay_terminate(psp); 2704 if (ret) { 2705 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2706 goto out; 2707 } 2708 } 2709 2710 ret = psp_asd_terminate(psp); 2711 if (ret) { 2712 DRM_ERROR("Failed to terminate asd\n"); 2713 goto out; 2714 } 2715 2716 ret = psp_tmr_terminate(psp); 2717 if (ret) { 2718 DRM_ERROR("Failed to terminate tmr\n"); 2719 goto out; 2720 } 2721 2722 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2723 if (ret) { 2724 DRM_ERROR("PSP ring stop failed\n"); 2725 } 2726 2727 out: 2728 return ret; 2729 } 2730 2731 static int psp_resume(void *handle) 2732 { 2733 int ret; 2734 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2735 struct psp_context *psp = &adev->psp; 2736 2737 DRM_INFO("PSP is resuming...\n"); 2738 2739 if (psp->mem_train_ctx.enable_mem_training) { 2740 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2741 if (ret) { 2742 DRM_ERROR("Failed to process memory training!\n"); 2743 return ret; 2744 } 2745 } 2746 2747 mutex_lock(&adev->firmware.mutex); 2748 2749 ret = psp_hw_start(psp); 2750 if (ret) 2751 goto failed; 2752 2753 ret = psp_load_non_psp_fw(psp); 2754 if (ret) 2755 goto failed; 2756 2757 ret = psp_asd_initialize(psp); 2758 if (ret) { 2759 DRM_ERROR("PSP load asd failed!\n"); 2760 goto failed; 2761 } 2762 2763 ret = psp_rl_load(adev); 2764 if (ret) { 2765 dev_err(adev->dev, "PSP load RL failed!\n"); 2766 goto failed; 2767 } 2768 2769 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2770 ret = psp_xgmi_initialize(psp, false, true); 2771 /* Warning the XGMI seesion initialize failure 2772 * Instead of stop driver initialization 2773 */ 2774 if (ret) 2775 dev_err(psp->adev->dev, 2776 "XGMI: Failed to initialize XGMI session\n"); 2777 } 2778 2779 if (psp->ta_fw) { 2780 ret = psp_ras_initialize(psp); 2781 if (ret) 2782 dev_err(psp->adev->dev, 2783 "RAS: Failed to initialize RAS\n"); 2784 2785 ret = psp_hdcp_initialize(psp); 2786 if (ret) 2787 dev_err(psp->adev->dev, 2788 "HDCP: Failed to initialize HDCP\n"); 2789 2790 ret = psp_dtm_initialize(psp); 2791 if (ret) 2792 dev_err(psp->adev->dev, 2793 "DTM: Failed to initialize DTM\n"); 2794 2795 ret = psp_rap_initialize(psp); 2796 if (ret) 2797 dev_err(psp->adev->dev, 2798 "RAP: Failed to initialize RAP\n"); 2799 2800 ret = psp_securedisplay_initialize(psp); 2801 if (ret) 2802 dev_err(psp->adev->dev, 2803 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2804 } 2805 2806 mutex_unlock(&adev->firmware.mutex); 2807 2808 return 0; 2809 2810 failed: 2811 DRM_ERROR("PSP resume failed\n"); 2812 mutex_unlock(&adev->firmware.mutex); 2813 return ret; 2814 } 2815 2816 int psp_gpu_reset(struct amdgpu_device *adev) 2817 { 2818 int ret; 2819 2820 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2821 return 0; 2822 2823 mutex_lock(&adev->psp.mutex); 2824 ret = psp_mode1_reset(&adev->psp); 2825 mutex_unlock(&adev->psp.mutex); 2826 2827 return ret; 2828 } 2829 2830 int psp_rlc_autoload_start(struct psp_context *psp) 2831 { 2832 int ret; 2833 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2834 2835 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2836 2837 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2838 psp->fence_buf_mc_addr); 2839 2840 release_psp_cmd_buf(psp); 2841 2842 return ret; 2843 } 2844 2845 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2846 uint64_t cmd_gpu_addr, int cmd_size) 2847 { 2848 struct amdgpu_firmware_info ucode = {0}; 2849 2850 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2851 AMDGPU_UCODE_ID_VCN0_RAM; 2852 ucode.mc_addr = cmd_gpu_addr; 2853 ucode.ucode_size = cmd_size; 2854 2855 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2856 } 2857 2858 int psp_ring_cmd_submit(struct psp_context *psp, 2859 uint64_t cmd_buf_mc_addr, 2860 uint64_t fence_mc_addr, 2861 int index) 2862 { 2863 unsigned int psp_write_ptr_reg = 0; 2864 struct psp_gfx_rb_frame *write_frame; 2865 struct psp_ring *ring = &psp->km_ring; 2866 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2867 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2868 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2869 struct amdgpu_device *adev = psp->adev; 2870 uint32_t ring_size_dw = ring->ring_size / 4; 2871 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2872 2873 /* KM (GPCOM) prepare write pointer */ 2874 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2875 2876 /* Update KM RB frame pointer to new frame */ 2877 /* write_frame ptr increments by size of rb_frame in bytes */ 2878 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2879 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2880 write_frame = ring_buffer_start; 2881 else 2882 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2883 /* Check invalid write_frame ptr address */ 2884 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2885 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2886 ring_buffer_start, ring_buffer_end, write_frame); 2887 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2888 return -EINVAL; 2889 } 2890 2891 /* Initialize KM RB frame */ 2892 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2893 2894 /* Update KM RB frame */ 2895 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2896 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2897 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2898 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2899 write_frame->fence_value = index; 2900 amdgpu_device_flush_hdp(adev, NULL); 2901 2902 /* Update the write Pointer in DWORDs */ 2903 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2904 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2905 return 0; 2906 } 2907 2908 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 2909 { 2910 struct amdgpu_device *adev = psp->adev; 2911 char fw_name[PSP_FW_NAME_LEN]; 2912 const struct psp_firmware_header_v1_0 *asd_hdr; 2913 int err = 0; 2914 2915 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2916 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name); 2917 if (err) 2918 goto out; 2919 2920 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2921 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2922 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2923 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2924 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2925 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2926 return 0; 2927 out: 2928 amdgpu_ucode_release(&adev->psp.asd_fw); 2929 return err; 2930 } 2931 2932 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 2933 { 2934 struct amdgpu_device *adev = psp->adev; 2935 char fw_name[PSP_FW_NAME_LEN]; 2936 const struct psp_firmware_header_v1_0 *toc_hdr; 2937 int err = 0; 2938 2939 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2940 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 2941 if (err) 2942 goto out; 2943 2944 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2945 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2946 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2947 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2948 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2949 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2950 return 0; 2951 out: 2952 amdgpu_ucode_release(&adev->psp.toc_fw); 2953 return err; 2954 } 2955 2956 static int parse_sos_bin_descriptor(struct psp_context *psp, 2957 const struct psp_fw_bin_desc *desc, 2958 const struct psp_firmware_header_v2_0 *sos_hdr) 2959 { 2960 uint8_t *ucode_start_addr = NULL; 2961 2962 if (!psp || !desc || !sos_hdr) 2963 return -EINVAL; 2964 2965 ucode_start_addr = (uint8_t *)sos_hdr + 2966 le32_to_cpu(desc->offset_bytes) + 2967 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2968 2969 switch (desc->fw_type) { 2970 case PSP_FW_TYPE_PSP_SOS: 2971 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2972 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2973 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2974 psp->sos.start_addr = ucode_start_addr; 2975 break; 2976 case PSP_FW_TYPE_PSP_SYS_DRV: 2977 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2978 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2979 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2980 psp->sys.start_addr = ucode_start_addr; 2981 break; 2982 case PSP_FW_TYPE_PSP_KDB: 2983 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2984 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2985 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2986 psp->kdb.start_addr = ucode_start_addr; 2987 break; 2988 case PSP_FW_TYPE_PSP_TOC: 2989 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2990 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2991 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 2992 psp->toc.start_addr = ucode_start_addr; 2993 break; 2994 case PSP_FW_TYPE_PSP_SPL: 2995 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 2996 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 2997 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 2998 psp->spl.start_addr = ucode_start_addr; 2999 break; 3000 case PSP_FW_TYPE_PSP_RL: 3001 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3002 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3003 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3004 psp->rl.start_addr = ucode_start_addr; 3005 break; 3006 case PSP_FW_TYPE_PSP_SOC_DRV: 3007 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3008 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3009 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3010 psp->soc_drv.start_addr = ucode_start_addr; 3011 break; 3012 case PSP_FW_TYPE_PSP_INTF_DRV: 3013 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3014 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3015 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3016 psp->intf_drv.start_addr = ucode_start_addr; 3017 break; 3018 case PSP_FW_TYPE_PSP_DBG_DRV: 3019 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3020 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3021 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3022 psp->dbg_drv.start_addr = ucode_start_addr; 3023 break; 3024 case PSP_FW_TYPE_PSP_RAS_DRV: 3025 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3026 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3027 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3028 psp->ras_drv.start_addr = ucode_start_addr; 3029 break; 3030 default: 3031 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3032 break; 3033 } 3034 3035 return 0; 3036 } 3037 3038 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3039 { 3040 const struct psp_firmware_header_v1_0 *sos_hdr; 3041 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3042 uint8_t *ucode_array_start_addr; 3043 3044 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3045 ucode_array_start_addr = (uint8_t *)sos_hdr + 3046 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3047 3048 if (adev->gmc.xgmi.connected_to_cpu || 3049 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3050 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3051 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3052 3053 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3054 adev->psp.sys.start_addr = ucode_array_start_addr; 3055 3056 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3057 adev->psp.sos.start_addr = ucode_array_start_addr + 3058 le32_to_cpu(sos_hdr->sos.offset_bytes); 3059 } else { 3060 /* Load alternate PSP SOS FW */ 3061 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3062 3063 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3064 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3065 3066 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3067 adev->psp.sys.start_addr = ucode_array_start_addr + 3068 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3069 3070 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3071 adev->psp.sos.start_addr = ucode_array_start_addr + 3072 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3073 } 3074 3075 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3076 dev_warn(adev->dev, "PSP SOS FW not available"); 3077 return -EINVAL; 3078 } 3079 3080 return 0; 3081 } 3082 3083 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3084 { 3085 struct amdgpu_device *adev = psp->adev; 3086 char fw_name[PSP_FW_NAME_LEN]; 3087 const struct psp_firmware_header_v1_0 *sos_hdr; 3088 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3089 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3090 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3091 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3092 int err = 0; 3093 uint8_t *ucode_array_start_addr; 3094 int fw_index = 0; 3095 3096 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3097 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name); 3098 if (err) 3099 goto out; 3100 3101 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3102 ucode_array_start_addr = (uint8_t *)sos_hdr + 3103 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3104 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3105 3106 switch (sos_hdr->header.header_version_major) { 3107 case 1: 3108 err = psp_init_sos_base_fw(adev); 3109 if (err) 3110 goto out; 3111 3112 if (sos_hdr->header.header_version_minor == 1) { 3113 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3114 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3115 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3116 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3117 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3118 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3119 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3120 } 3121 if (sos_hdr->header.header_version_minor == 2) { 3122 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3123 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3124 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3125 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3126 } 3127 if (sos_hdr->header.header_version_minor == 3) { 3128 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3129 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3130 adev->psp.toc.start_addr = ucode_array_start_addr + 3131 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3132 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3133 adev->psp.kdb.start_addr = ucode_array_start_addr + 3134 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3135 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3136 adev->psp.spl.start_addr = ucode_array_start_addr + 3137 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3138 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3139 adev->psp.rl.start_addr = ucode_array_start_addr + 3140 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3141 } 3142 break; 3143 case 2: 3144 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3145 3146 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3147 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3148 err = -EINVAL; 3149 goto out; 3150 } 3151 3152 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3153 err = parse_sos_bin_descriptor(psp, 3154 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3155 sos_hdr_v2_0); 3156 if (err) 3157 goto out; 3158 } 3159 break; 3160 default: 3161 dev_err(adev->dev, 3162 "unsupported psp sos firmware\n"); 3163 err = -EINVAL; 3164 goto out; 3165 } 3166 3167 return 0; 3168 out: 3169 amdgpu_ucode_release(&adev->psp.sos_fw); 3170 3171 return err; 3172 } 3173 3174 static int parse_ta_bin_descriptor(struct psp_context *psp, 3175 const struct psp_fw_bin_desc *desc, 3176 const struct ta_firmware_header_v2_0 *ta_hdr) 3177 { 3178 uint8_t *ucode_start_addr = NULL; 3179 3180 if (!psp || !desc || !ta_hdr) 3181 return -EINVAL; 3182 3183 ucode_start_addr = (uint8_t *)ta_hdr + 3184 le32_to_cpu(desc->offset_bytes) + 3185 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3186 3187 switch (desc->fw_type) { 3188 case TA_FW_TYPE_PSP_ASD: 3189 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3190 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3191 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3192 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3193 break; 3194 case TA_FW_TYPE_PSP_XGMI: 3195 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3196 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3197 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3198 break; 3199 case TA_FW_TYPE_PSP_RAS: 3200 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3201 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3202 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3203 break; 3204 case TA_FW_TYPE_PSP_HDCP: 3205 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3206 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3207 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3208 break; 3209 case TA_FW_TYPE_PSP_DTM: 3210 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3211 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3212 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3213 break; 3214 case TA_FW_TYPE_PSP_RAP: 3215 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3216 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3217 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3218 break; 3219 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3220 psp->securedisplay_context.context.bin_desc.fw_version = 3221 le32_to_cpu(desc->fw_version); 3222 psp->securedisplay_context.context.bin_desc.size_bytes = 3223 le32_to_cpu(desc->size_bytes); 3224 psp->securedisplay_context.context.bin_desc.start_addr = 3225 ucode_start_addr; 3226 break; 3227 default: 3228 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3229 break; 3230 } 3231 3232 return 0; 3233 } 3234 3235 static int parse_ta_v1_microcode(struct psp_context *psp) 3236 { 3237 const struct ta_firmware_header_v1_0 *ta_hdr; 3238 struct amdgpu_device *adev = psp->adev; 3239 3240 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3241 3242 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3243 return -EINVAL; 3244 3245 adev->psp.xgmi_context.context.bin_desc.fw_version = 3246 le32_to_cpu(ta_hdr->xgmi.fw_version); 3247 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3248 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3249 adev->psp.xgmi_context.context.bin_desc.start_addr = 3250 (uint8_t *)ta_hdr + 3251 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3252 3253 adev->psp.ras_context.context.bin_desc.fw_version = 3254 le32_to_cpu(ta_hdr->ras.fw_version); 3255 adev->psp.ras_context.context.bin_desc.size_bytes = 3256 le32_to_cpu(ta_hdr->ras.size_bytes); 3257 adev->psp.ras_context.context.bin_desc.start_addr = 3258 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3259 le32_to_cpu(ta_hdr->ras.offset_bytes); 3260 3261 adev->psp.hdcp_context.context.bin_desc.fw_version = 3262 le32_to_cpu(ta_hdr->hdcp.fw_version); 3263 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3264 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3265 adev->psp.hdcp_context.context.bin_desc.start_addr = 3266 (uint8_t *)ta_hdr + 3267 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3268 3269 adev->psp.dtm_context.context.bin_desc.fw_version = 3270 le32_to_cpu(ta_hdr->dtm.fw_version); 3271 adev->psp.dtm_context.context.bin_desc.size_bytes = 3272 le32_to_cpu(ta_hdr->dtm.size_bytes); 3273 adev->psp.dtm_context.context.bin_desc.start_addr = 3274 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3275 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3276 3277 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3278 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3279 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3280 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3281 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3282 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3283 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3284 3285 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3286 3287 return 0; 3288 } 3289 3290 static int parse_ta_v2_microcode(struct psp_context *psp) 3291 { 3292 const struct ta_firmware_header_v2_0 *ta_hdr; 3293 struct amdgpu_device *adev = psp->adev; 3294 int err = 0; 3295 int ta_index = 0; 3296 3297 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3298 3299 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3300 return -EINVAL; 3301 3302 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3303 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3304 return -EINVAL; 3305 } 3306 3307 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3308 err = parse_ta_bin_descriptor(psp, 3309 &ta_hdr->ta_fw_bin[ta_index], 3310 ta_hdr); 3311 if (err) 3312 return err; 3313 } 3314 3315 return 0; 3316 } 3317 3318 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3319 { 3320 const struct common_firmware_header *hdr; 3321 struct amdgpu_device *adev = psp->adev; 3322 char fw_name[PSP_FW_NAME_LEN]; 3323 int err; 3324 3325 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3326 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name); 3327 if (err) 3328 return err; 3329 3330 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3331 switch (le16_to_cpu(hdr->header_version_major)) { 3332 case 1: 3333 err = parse_ta_v1_microcode(psp); 3334 break; 3335 case 2: 3336 err = parse_ta_v2_microcode(psp); 3337 break; 3338 default: 3339 dev_err(adev->dev, "unsupported TA header version\n"); 3340 err = -EINVAL; 3341 } 3342 3343 if (err) 3344 amdgpu_ucode_release(&adev->psp.ta_fw); 3345 3346 return err; 3347 } 3348 3349 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 3350 { 3351 struct amdgpu_device *adev = psp->adev; 3352 char fw_name[PSP_FW_NAME_LEN]; 3353 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3354 struct amdgpu_firmware_info *info = NULL; 3355 int err = 0; 3356 3357 if (!amdgpu_sriov_vf(adev)) { 3358 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3359 return -EINVAL; 3360 } 3361 3362 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3363 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name); 3364 if (err) { 3365 if (err == -ENODEV) { 3366 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3367 err = 0; 3368 goto out; 3369 } 3370 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3371 } 3372 3373 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3374 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3375 info->fw = adev->psp.cap_fw; 3376 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3377 adev->psp.cap_fw->data; 3378 adev->firmware.fw_size += ALIGN( 3379 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3380 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3381 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3382 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3383 3384 return 0; 3385 3386 out: 3387 amdgpu_ucode_release(&adev->psp.cap_fw); 3388 return err; 3389 } 3390 3391 static int psp_set_clockgating_state(void *handle, 3392 enum amd_clockgating_state state) 3393 { 3394 return 0; 3395 } 3396 3397 static int psp_set_powergating_state(void *handle, 3398 enum amd_powergating_state state) 3399 { 3400 return 0; 3401 } 3402 3403 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3404 struct device_attribute *attr, 3405 char *buf) 3406 { 3407 struct drm_device *ddev = dev_get_drvdata(dev); 3408 struct amdgpu_device *adev = drm_to_adev(ddev); 3409 uint32_t fw_ver; 3410 int ret; 3411 3412 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3413 DRM_INFO("PSP block is not ready yet."); 3414 return -EBUSY; 3415 } 3416 3417 mutex_lock(&adev->psp.mutex); 3418 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3419 mutex_unlock(&adev->psp.mutex); 3420 3421 if (ret) { 3422 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3423 return ret; 3424 } 3425 3426 return sysfs_emit(buf, "%x\n", fw_ver); 3427 } 3428 3429 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3430 struct device_attribute *attr, 3431 const char *buf, 3432 size_t count) 3433 { 3434 struct drm_device *ddev = dev_get_drvdata(dev); 3435 struct amdgpu_device *adev = drm_to_adev(ddev); 3436 int ret, idx; 3437 char fw_name[100]; 3438 const struct firmware *usbc_pd_fw; 3439 struct amdgpu_bo *fw_buf_bo = NULL; 3440 uint64_t fw_pri_mc_addr; 3441 void *fw_pri_cpu_addr; 3442 3443 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3444 DRM_INFO("PSP block is not ready yet."); 3445 return -EBUSY; 3446 } 3447 3448 if (!drm_dev_enter(ddev, &idx)) 3449 return -ENODEV; 3450 3451 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3452 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3453 if (ret) 3454 goto fail; 3455 3456 /* LFB address which is aligned to 1MB boundary per PSP request */ 3457 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3458 AMDGPU_GEM_DOMAIN_VRAM | 3459 AMDGPU_GEM_DOMAIN_GTT, 3460 &fw_buf_bo, &fw_pri_mc_addr, 3461 &fw_pri_cpu_addr); 3462 if (ret) 3463 goto rel_buf; 3464 3465 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3466 3467 mutex_lock(&adev->psp.mutex); 3468 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3469 mutex_unlock(&adev->psp.mutex); 3470 3471 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3472 3473 rel_buf: 3474 release_firmware(usbc_pd_fw); 3475 fail: 3476 if (ret) { 3477 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3478 count = ret; 3479 } 3480 3481 drm_dev_exit(idx); 3482 return count; 3483 } 3484 3485 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3486 { 3487 int idx; 3488 3489 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3490 return; 3491 3492 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3493 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3494 3495 drm_dev_exit(idx); 3496 } 3497 3498 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3499 psp_usbc_pd_fw_sysfs_read, 3500 psp_usbc_pd_fw_sysfs_write); 3501 3502 int is_psp_fw_valid(struct psp_bin_desc bin) 3503 { 3504 return bin.size_bytes; 3505 } 3506 3507 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3508 struct bin_attribute *bin_attr, 3509 char *buffer, loff_t pos, size_t count) 3510 { 3511 struct device *dev = kobj_to_dev(kobj); 3512 struct drm_device *ddev = dev_get_drvdata(dev); 3513 struct amdgpu_device *adev = drm_to_adev(ddev); 3514 3515 adev->psp.vbflash_done = false; 3516 3517 /* Safeguard against memory drain */ 3518 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3519 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3520 kvfree(adev->psp.vbflash_tmp_buf); 3521 adev->psp.vbflash_tmp_buf = NULL; 3522 adev->psp.vbflash_image_size = 0; 3523 return -ENOMEM; 3524 } 3525 3526 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3527 if (!adev->psp.vbflash_tmp_buf) { 3528 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3529 if (!adev->psp.vbflash_tmp_buf) 3530 return -ENOMEM; 3531 } 3532 3533 mutex_lock(&adev->psp.mutex); 3534 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3535 adev->psp.vbflash_image_size += count; 3536 mutex_unlock(&adev->psp.mutex); 3537 3538 dev_info(adev->dev, "VBIOS flash write PSP done"); 3539 3540 return count; 3541 } 3542 3543 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3544 struct bin_attribute *bin_attr, char *buffer, 3545 loff_t pos, size_t count) 3546 { 3547 struct device *dev = kobj_to_dev(kobj); 3548 struct drm_device *ddev = dev_get_drvdata(dev); 3549 struct amdgpu_device *adev = drm_to_adev(ddev); 3550 struct amdgpu_bo *fw_buf_bo = NULL; 3551 uint64_t fw_pri_mc_addr; 3552 void *fw_pri_cpu_addr; 3553 int ret; 3554 3555 dev_info(adev->dev, "VBIOS flash to PSP started"); 3556 3557 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3558 AMDGPU_GPU_PAGE_SIZE, 3559 AMDGPU_GEM_DOMAIN_VRAM, 3560 &fw_buf_bo, 3561 &fw_pri_mc_addr, 3562 &fw_pri_cpu_addr); 3563 if (ret) 3564 goto rel_buf; 3565 3566 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3567 3568 mutex_lock(&adev->psp.mutex); 3569 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3570 mutex_unlock(&adev->psp.mutex); 3571 3572 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3573 3574 rel_buf: 3575 kvfree(adev->psp.vbflash_tmp_buf); 3576 adev->psp.vbflash_tmp_buf = NULL; 3577 adev->psp.vbflash_image_size = 0; 3578 3579 if (ret) { 3580 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret); 3581 return ret; 3582 } 3583 3584 dev_info(adev->dev, "VBIOS flash to PSP done"); 3585 return 0; 3586 } 3587 3588 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3589 struct device_attribute *attr, 3590 char *buf) 3591 { 3592 struct drm_device *ddev = dev_get_drvdata(dev); 3593 struct amdgpu_device *adev = drm_to_adev(ddev); 3594 uint32_t vbflash_status; 3595 3596 vbflash_status = psp_vbflash_status(&adev->psp); 3597 if (!adev->psp.vbflash_done) 3598 vbflash_status = 0; 3599 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3600 vbflash_status = 1; 3601 3602 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3603 } 3604 3605 static const struct bin_attribute psp_vbflash_bin_attr = { 3606 .attr = {.name = "psp_vbflash", .mode = 0664}, 3607 .size = 0, 3608 .write = amdgpu_psp_vbflash_write, 3609 .read = amdgpu_psp_vbflash_read, 3610 }; 3611 3612 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL); 3613 3614 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev) 3615 { 3616 int ret = 0; 3617 struct psp_context *psp = &adev->psp; 3618 3619 if (amdgpu_sriov_vf(adev)) 3620 return -EINVAL; 3621 3622 switch (adev->ip_versions[MP0_HWIP][0]) { 3623 case IP_VERSION(13, 0, 0): 3624 case IP_VERSION(13, 0, 7): 3625 if (!psp->adev) { 3626 psp->adev = adev; 3627 psp_v13_0_set_psp_funcs(psp); 3628 } 3629 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3630 if (ret) 3631 dev_err(adev->dev, "Failed to create device file psp_vbflash"); 3632 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status); 3633 if (ret) 3634 dev_err(adev->dev, "Failed to create device file psp_vbflash_status"); 3635 return ret; 3636 default: 3637 return 0; 3638 } 3639 } 3640 3641 const struct amd_ip_funcs psp_ip_funcs = { 3642 .name = "psp", 3643 .early_init = psp_early_init, 3644 .late_init = NULL, 3645 .sw_init = psp_sw_init, 3646 .sw_fini = psp_sw_fini, 3647 .hw_init = psp_hw_init, 3648 .hw_fini = psp_hw_fini, 3649 .suspend = psp_suspend, 3650 .resume = psp_resume, 3651 .is_idle = NULL, 3652 .check_soft_reset = NULL, 3653 .wait_for_idle = NULL, 3654 .soft_reset = NULL, 3655 .set_clockgating_state = psp_set_clockgating_state, 3656 .set_powergating_state = psp_set_powergating_state, 3657 }; 3658 3659 static int psp_sysfs_init(struct amdgpu_device *adev) 3660 { 3661 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3662 3663 if (ret) 3664 DRM_ERROR("Failed to create USBC PD FW control file!"); 3665 3666 return ret; 3667 } 3668 3669 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev) 3670 { 3671 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3672 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status); 3673 } 3674 3675 static void psp_sysfs_fini(struct amdgpu_device *adev) 3676 { 3677 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3678 } 3679 3680 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3681 { 3682 .type = AMD_IP_BLOCK_TYPE_PSP, 3683 .major = 3, 3684 .minor = 1, 3685 .rev = 0, 3686 .funcs = &psp_ip_funcs, 3687 }; 3688 3689 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3690 { 3691 .type = AMD_IP_BLOCK_TYPE_PSP, 3692 .major = 10, 3693 .minor = 0, 3694 .rev = 0, 3695 .funcs = &psp_ip_funcs, 3696 }; 3697 3698 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3699 { 3700 .type = AMD_IP_BLOCK_TYPE_PSP, 3701 .major = 11, 3702 .minor = 0, 3703 .rev = 0, 3704 .funcs = &psp_ip_funcs, 3705 }; 3706 3707 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3708 .type = AMD_IP_BLOCK_TYPE_PSP, 3709 .major = 11, 3710 .minor = 0, 3711 .rev = 8, 3712 .funcs = &psp_ip_funcs, 3713 }; 3714 3715 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3716 { 3717 .type = AMD_IP_BLOCK_TYPE_PSP, 3718 .major = 12, 3719 .minor = 0, 3720 .rev = 0, 3721 .funcs = &psp_ip_funcs, 3722 }; 3723 3724 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3725 .type = AMD_IP_BLOCK_TYPE_PSP, 3726 .major = 13, 3727 .minor = 0, 3728 .rev = 0, 3729 .funcs = &psp_ip_funcs, 3730 }; 3731 3732 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3733 .type = AMD_IP_BLOCK_TYPE_PSP, 3734 .major = 13, 3735 .minor = 0, 3736 .rev = 4, 3737 .funcs = &psp_ip_funcs, 3738 }; 3739