1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 #include "psp_v10_0.h" 34 #include "psp_v11_0.h" 35 36 static void psp_set_funcs(struct amdgpu_device *adev); 37 38 static int psp_early_init(void *handle) 39 { 40 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 41 struct psp_context *psp = &adev->psp; 42 43 psp_set_funcs(adev); 44 45 switch (adev->asic_type) { 46 case CHIP_VEGA10: 47 case CHIP_VEGA12: 48 psp_v3_1_set_psp_funcs(psp); 49 psp->autoload_supported = false; 50 break; 51 case CHIP_RAVEN: 52 psp_v10_0_set_psp_funcs(psp); 53 psp->autoload_supported = false; 54 break; 55 case CHIP_VEGA20: 56 psp_v11_0_set_psp_funcs(psp); 57 psp->autoload_supported = false; 58 break; 59 case CHIP_NAVI10: 60 case CHIP_NAVI14: 61 psp_v11_0_set_psp_funcs(psp); 62 psp->autoload_supported = true; 63 break; 64 default: 65 return -EINVAL; 66 } 67 68 psp->adev = adev; 69 70 return 0; 71 } 72 73 static int psp_sw_init(void *handle) 74 { 75 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 76 struct psp_context *psp = &adev->psp; 77 int ret; 78 79 ret = psp_init_microcode(psp); 80 if (ret) { 81 DRM_ERROR("Failed to load psp firmware!\n"); 82 return ret; 83 } 84 85 return 0; 86 } 87 88 static int psp_sw_fini(void *handle) 89 { 90 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 91 92 release_firmware(adev->psp.sos_fw); 93 adev->psp.sos_fw = NULL; 94 release_firmware(adev->psp.asd_fw); 95 adev->psp.asd_fw = NULL; 96 if (adev->psp.ta_fw) { 97 release_firmware(adev->psp.ta_fw); 98 adev->psp.ta_fw = NULL; 99 } 100 return 0; 101 } 102 103 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 104 uint32_t reg_val, uint32_t mask, bool check_changed) 105 { 106 uint32_t val; 107 int i; 108 struct amdgpu_device *adev = psp->adev; 109 110 for (i = 0; i < adev->usec_timeout; i++) { 111 val = RREG32(reg_index); 112 if (check_changed) { 113 if (val != reg_val) 114 return 0; 115 } else { 116 if ((val & mask) == reg_val) 117 return 0; 118 } 119 udelay(1); 120 } 121 122 return -ETIME; 123 } 124 125 static int 126 psp_cmd_submit_buf(struct psp_context *psp, 127 struct amdgpu_firmware_info *ucode, 128 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 129 { 130 int ret; 131 int index; 132 int timeout = 2000; 133 134 mutex_lock(&psp->mutex); 135 136 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 137 138 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 139 140 index = atomic_inc_return(&psp->fence_value); 141 ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr, 142 fence_mc_addr, index); 143 if (ret) { 144 atomic_dec(&psp->fence_value); 145 mutex_unlock(&psp->mutex); 146 return ret; 147 } 148 149 while (*((unsigned int *)psp->fence_buf) != index) { 150 if (--timeout == 0) 151 break; 152 msleep(1); 153 } 154 155 /* In some cases, psp response status is not 0 even there is no 156 * problem while the command is submitted. Some version of PSP FW 157 * doesn't write 0 to that field. 158 * So here we would like to only print a warning instead of an error 159 * during psp initialization to avoid breaking hw_init and it doesn't 160 * return -EINVAL. 161 */ 162 if (psp->cmd_buf_mem->resp.status || !timeout) { 163 if (ucode) 164 DRM_WARN("failed to load ucode id (%d) ", 165 ucode->ucode_id); 166 DRM_WARN("psp command failed and response status is (%d)\n", 167 psp->cmd_buf_mem->resp.status); 168 if (!timeout) { 169 mutex_unlock(&psp->mutex); 170 return -EINVAL; 171 } 172 } 173 174 /* get xGMI session id from response buffer */ 175 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id; 176 177 if (ucode) { 178 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 179 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 180 } 181 mutex_unlock(&psp->mutex); 182 183 return ret; 184 } 185 186 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 187 struct psp_gfx_cmd_resp *cmd, 188 uint64_t tmr_mc, uint32_t size) 189 { 190 if (psp_support_vmr_ring(psp)) 191 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 192 else 193 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 194 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 195 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 196 cmd->cmd.cmd_setup_tmr.buf_size = size; 197 } 198 199 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 200 uint64_t pri_buf_mc, uint32_t size) 201 { 202 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 203 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 204 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 205 cmd->cmd.cmd_load_toc.toc_size = size; 206 } 207 208 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 209 static int psp_load_toc(struct psp_context *psp, 210 uint32_t *tmr_size) 211 { 212 int ret; 213 struct psp_gfx_cmd_resp *cmd; 214 215 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 216 if (!cmd) 217 return -ENOMEM; 218 /* Copy toc to psp firmware private buffer */ 219 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 220 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size); 221 222 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 223 224 ret = psp_cmd_submit_buf(psp, NULL, cmd, 225 psp->fence_buf_mc_addr); 226 if (!ret) 227 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 228 kfree(cmd); 229 return ret; 230 } 231 232 /* Set up Trusted Memory Region */ 233 static int psp_tmr_init(struct psp_context *psp) 234 { 235 int ret; 236 int tmr_size; 237 238 /* 239 * According to HW engineer, they prefer the TMR address be "naturally 240 * aligned" , e.g. the start address be an integer divide of TMR size. 241 * 242 * Note: this memory need be reserved till the driver 243 * uninitializes. 244 */ 245 tmr_size = PSP_TMR_SIZE; 246 247 /* For ASICs support RLC autoload, psp will parse the toc 248 * and calculate the total size of TMR needed */ 249 if (psp->toc_start_addr && 250 psp->toc_bin_size && 251 psp->fw_pri_buf) { 252 ret = psp_load_toc(psp, &tmr_size); 253 if (ret) { 254 DRM_ERROR("Failed to load toc\n"); 255 return ret; 256 } 257 } 258 259 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE, 260 AMDGPU_GEM_DOMAIN_VRAM, 261 &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 262 263 return ret; 264 } 265 266 static int psp_tmr_load(struct psp_context *psp) 267 { 268 int ret; 269 struct psp_gfx_cmd_resp *cmd; 270 271 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 272 if (!cmd) 273 return -ENOMEM; 274 275 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, 276 amdgpu_bo_size(psp->tmr_bo)); 277 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 278 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 279 280 ret = psp_cmd_submit_buf(psp, NULL, cmd, 281 psp->fence_buf_mc_addr); 282 if (ret) 283 goto failed; 284 285 kfree(cmd); 286 287 return 0; 288 289 failed: 290 kfree(cmd); 291 return ret; 292 } 293 294 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd, 295 uint64_t asd_mc, uint64_t asd_mc_shared, 296 uint32_t size, uint32_t shared_size) 297 { 298 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 299 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 300 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 301 cmd->cmd.cmd_load_ta.app_len = size; 302 303 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared); 304 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared); 305 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 306 } 307 308 static int psp_asd_init(struct psp_context *psp) 309 { 310 int ret; 311 312 /* 313 * Allocate 16k memory aligned to 4k from Frame Buffer (local 314 * physical) for shared ASD <-> Driver 315 */ 316 ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE, 317 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 318 &psp->asd_shared_bo, 319 &psp->asd_shared_mc_addr, 320 &psp->asd_shared_buf); 321 322 return ret; 323 } 324 325 static int psp_asd_load(struct psp_context *psp) 326 { 327 int ret; 328 struct psp_gfx_cmd_resp *cmd; 329 330 /* If PSP version doesn't match ASD version, asd loading will be failed. 331 * add workaround to bypass it for sriov now. 332 * TODO: add version check to make it common 333 */ 334 if (amdgpu_sriov_vf(psp->adev)) 335 return 0; 336 337 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 338 if (!cmd) 339 return -ENOMEM; 340 341 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 342 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 343 344 psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr, 345 psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE); 346 347 ret = psp_cmd_submit_buf(psp, NULL, cmd, 348 psp->fence_buf_mc_addr); 349 350 kfree(cmd); 351 352 return ret; 353 } 354 355 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 356 uint32_t id, uint32_t value) 357 { 358 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 359 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 360 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 361 } 362 363 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 364 uint32_t value) 365 { 366 struct psp_gfx_cmd_resp *cmd = NULL; 367 int ret = 0; 368 369 if (reg >= PSP_REG_LAST) 370 return -EINVAL; 371 372 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 373 if (!cmd) 374 return -ENOMEM; 375 376 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 377 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 378 379 kfree(cmd); 380 return ret; 381 } 382 383 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 384 uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared, 385 uint32_t xgmi_ta_size, uint32_t shared_size) 386 { 387 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 388 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc); 389 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc); 390 cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size; 391 392 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared); 393 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared); 394 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 395 } 396 397 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 398 { 399 int ret; 400 401 /* 402 * Allocate 16k memory aligned to 4k from Frame Buffer (local 403 * physical) for xgmi ta <-> Driver 404 */ 405 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 406 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 407 &psp->xgmi_context.xgmi_shared_bo, 408 &psp->xgmi_context.xgmi_shared_mc_addr, 409 &psp->xgmi_context.xgmi_shared_buf); 410 411 return ret; 412 } 413 414 static int psp_xgmi_load(struct psp_context *psp) 415 { 416 int ret; 417 struct psp_gfx_cmd_resp *cmd; 418 419 /* 420 * TODO: bypass the loading in sriov for now 421 */ 422 if (amdgpu_sriov_vf(psp->adev)) 423 return 0; 424 425 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 426 if (!cmd) 427 return -ENOMEM; 428 429 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 430 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 431 432 psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 433 psp->xgmi_context.xgmi_shared_mc_addr, 434 psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE); 435 436 ret = psp_cmd_submit_buf(psp, NULL, cmd, 437 psp->fence_buf_mc_addr); 438 439 if (!ret) { 440 psp->xgmi_context.initialized = 1; 441 psp->xgmi_context.session_id = cmd->resp.session_id; 442 } 443 444 kfree(cmd); 445 446 return ret; 447 } 448 449 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 450 uint32_t xgmi_session_id) 451 { 452 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 453 cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id; 454 } 455 456 static int psp_xgmi_unload(struct psp_context *psp) 457 { 458 int ret; 459 struct psp_gfx_cmd_resp *cmd; 460 461 /* 462 * TODO: bypass the unloading in sriov for now 463 */ 464 if (amdgpu_sriov_vf(psp->adev)) 465 return 0; 466 467 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 468 if (!cmd) 469 return -ENOMEM; 470 471 psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 472 473 ret = psp_cmd_submit_buf(psp, NULL, cmd, 474 psp->fence_buf_mc_addr); 475 476 kfree(cmd); 477 478 return ret; 479 } 480 481 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 482 uint32_t ta_cmd_id, 483 uint32_t xgmi_session_id) 484 { 485 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 486 cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id; 487 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 488 /* Note: cmd_invoke_cmd.buf is not used for now */ 489 } 490 491 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 492 { 493 int ret; 494 struct psp_gfx_cmd_resp *cmd; 495 496 /* 497 * TODO: bypass the loading in sriov for now 498 */ 499 if (amdgpu_sriov_vf(psp->adev)) 500 return 0; 501 502 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 503 if (!cmd) 504 return -ENOMEM; 505 506 psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id, 507 psp->xgmi_context.session_id); 508 509 ret = psp_cmd_submit_buf(psp, NULL, cmd, 510 psp->fence_buf_mc_addr); 511 512 kfree(cmd); 513 514 return ret; 515 } 516 517 static int psp_xgmi_terminate(struct psp_context *psp) 518 { 519 int ret; 520 521 if (!psp->xgmi_context.initialized) 522 return 0; 523 524 ret = psp_xgmi_unload(psp); 525 if (ret) 526 return ret; 527 528 psp->xgmi_context.initialized = 0; 529 530 /* free xgmi shared memory */ 531 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 532 &psp->xgmi_context.xgmi_shared_mc_addr, 533 &psp->xgmi_context.xgmi_shared_buf); 534 535 return 0; 536 } 537 538 static int psp_xgmi_initialize(struct psp_context *psp) 539 { 540 struct ta_xgmi_shared_memory *xgmi_cmd; 541 int ret; 542 543 if (!psp->adev->psp.ta_fw) 544 return -ENOENT; 545 546 if (!psp->xgmi_context.initialized) { 547 ret = psp_xgmi_init_shared_buf(psp); 548 if (ret) 549 return ret; 550 } 551 552 /* Load XGMI TA */ 553 ret = psp_xgmi_load(psp); 554 if (ret) 555 return ret; 556 557 /* Initialize XGMI session */ 558 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 559 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 560 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 561 562 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 563 564 return ret; 565 } 566 567 // ras begin 568 static void psp_prep_ras_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 569 uint64_t ras_ta_mc, uint64_t ras_mc_shared, 570 uint32_t ras_ta_size, uint32_t shared_size) 571 { 572 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 573 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ras_ta_mc); 574 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ras_ta_mc); 575 cmd->cmd.cmd_load_ta.app_len = ras_ta_size; 576 577 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ras_mc_shared); 578 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ras_mc_shared); 579 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 580 } 581 582 static int psp_ras_init_shared_buf(struct psp_context *psp) 583 { 584 int ret; 585 586 /* 587 * Allocate 16k memory aligned to 4k from Frame Buffer (local 588 * physical) for ras ta <-> Driver 589 */ 590 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 591 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 592 &psp->ras.ras_shared_bo, 593 &psp->ras.ras_shared_mc_addr, 594 &psp->ras.ras_shared_buf); 595 596 return ret; 597 } 598 599 static int psp_ras_load(struct psp_context *psp) 600 { 601 int ret; 602 struct psp_gfx_cmd_resp *cmd; 603 604 /* 605 * TODO: bypass the loading in sriov for now 606 */ 607 if (amdgpu_sriov_vf(psp->adev)) 608 return 0; 609 610 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 611 if (!cmd) 612 return -ENOMEM; 613 614 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 615 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 616 617 psp_prep_ras_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 618 psp->ras.ras_shared_mc_addr, 619 psp->ta_ras_ucode_size, PSP_RAS_SHARED_MEM_SIZE); 620 621 ret = psp_cmd_submit_buf(psp, NULL, cmd, 622 psp->fence_buf_mc_addr); 623 624 if (!ret) { 625 psp->ras.ras_initialized = 1; 626 psp->ras.session_id = cmd->resp.session_id; 627 } 628 629 kfree(cmd); 630 631 return ret; 632 } 633 634 static void psp_prep_ras_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 635 uint32_t ras_session_id) 636 { 637 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 638 cmd->cmd.cmd_unload_ta.session_id = ras_session_id; 639 } 640 641 static int psp_ras_unload(struct psp_context *psp) 642 { 643 int ret; 644 struct psp_gfx_cmd_resp *cmd; 645 646 /* 647 * TODO: bypass the unloading in sriov for now 648 */ 649 if (amdgpu_sriov_vf(psp->adev)) 650 return 0; 651 652 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 653 if (!cmd) 654 return -ENOMEM; 655 656 psp_prep_ras_ta_unload_cmd_buf(cmd, psp->ras.session_id); 657 658 ret = psp_cmd_submit_buf(psp, NULL, cmd, 659 psp->fence_buf_mc_addr); 660 661 kfree(cmd); 662 663 return ret; 664 } 665 666 static void psp_prep_ras_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 667 uint32_t ta_cmd_id, 668 uint32_t ras_session_id) 669 { 670 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 671 cmd->cmd.cmd_invoke_cmd.session_id = ras_session_id; 672 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 673 /* Note: cmd_invoke_cmd.buf is not used for now */ 674 } 675 676 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 677 { 678 int ret; 679 struct psp_gfx_cmd_resp *cmd; 680 681 /* 682 * TODO: bypass the loading in sriov for now 683 */ 684 if (amdgpu_sriov_vf(psp->adev)) 685 return 0; 686 687 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 688 if (!cmd) 689 return -ENOMEM; 690 691 psp_prep_ras_ta_invoke_cmd_buf(cmd, ta_cmd_id, 692 psp->ras.session_id); 693 694 ret = psp_cmd_submit_buf(psp, NULL, cmd, 695 psp->fence_buf_mc_addr); 696 697 kfree(cmd); 698 699 return ret; 700 } 701 702 int psp_ras_enable_features(struct psp_context *psp, 703 union ta_ras_cmd_input *info, bool enable) 704 { 705 struct ta_ras_shared_memory *ras_cmd; 706 int ret; 707 708 if (!psp->ras.ras_initialized) 709 return -EINVAL; 710 711 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 712 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 713 714 if (enable) 715 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 716 else 717 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 718 719 ras_cmd->ras_in_message = *info; 720 721 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 722 if (ret) 723 return -EINVAL; 724 725 return ras_cmd->ras_status; 726 } 727 728 static int psp_ras_terminate(struct psp_context *psp) 729 { 730 int ret; 731 732 if (!psp->ras.ras_initialized) 733 return 0; 734 735 ret = psp_ras_unload(psp); 736 if (ret) 737 return ret; 738 739 psp->ras.ras_initialized = 0; 740 741 /* free ras shared memory */ 742 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 743 &psp->ras.ras_shared_mc_addr, 744 &psp->ras.ras_shared_buf); 745 746 return 0; 747 } 748 749 static int psp_ras_initialize(struct psp_context *psp) 750 { 751 int ret; 752 753 if (!psp->ras.ras_initialized) { 754 ret = psp_ras_init_shared_buf(psp); 755 if (ret) 756 return ret; 757 } 758 759 ret = psp_ras_load(psp); 760 if (ret) 761 return ret; 762 763 return 0; 764 } 765 // ras end 766 767 static int psp_hw_start(struct psp_context *psp) 768 { 769 struct amdgpu_device *adev = psp->adev; 770 int ret; 771 772 if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) { 773 if (psp->kdb_bin_size && 774 (psp->funcs->bootloader_load_kdb != NULL)) { 775 ret = psp_bootloader_load_kdb(psp); 776 if (ret) { 777 DRM_ERROR("PSP load kdb failed!\n"); 778 return ret; 779 } 780 } 781 782 ret = psp_bootloader_load_sysdrv(psp); 783 if (ret) { 784 DRM_ERROR("PSP load sysdrv failed!\n"); 785 return ret; 786 } 787 788 ret = psp_bootloader_load_sos(psp); 789 if (ret) { 790 DRM_ERROR("PSP load sos failed!\n"); 791 return ret; 792 } 793 } 794 795 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 796 if (ret) { 797 DRM_ERROR("PSP create ring failed!\n"); 798 return ret; 799 } 800 801 ret = psp_tmr_init(psp); 802 if (ret) { 803 DRM_ERROR("PSP tmr init failed!\n"); 804 return ret; 805 } 806 807 ret = psp_tmr_load(psp); 808 if (ret) { 809 DRM_ERROR("PSP load tmr failed!\n"); 810 return ret; 811 } 812 813 ret = psp_asd_init(psp); 814 if (ret) { 815 DRM_ERROR("PSP asd init failed!\n"); 816 return ret; 817 } 818 819 ret = psp_asd_load(psp); 820 if (ret) { 821 DRM_ERROR("PSP load asd failed!\n"); 822 return ret; 823 } 824 825 if (adev->gmc.xgmi.num_physical_nodes > 1) { 826 ret = psp_xgmi_initialize(psp); 827 /* Warning the XGMI seesion initialize failure 828 * Instead of stop driver initialization 829 */ 830 if (ret) 831 dev_err(psp->adev->dev, 832 "XGMI: Failed to initialize XGMI session\n"); 833 } 834 835 836 if (psp->adev->psp.ta_fw) { 837 ret = psp_ras_initialize(psp); 838 if (ret) 839 dev_err(psp->adev->dev, 840 "RAS: Failed to initialize RAS\n"); 841 } 842 843 return 0; 844 } 845 846 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 847 enum psp_gfx_fw_type *type) 848 { 849 switch (ucode->ucode_id) { 850 case AMDGPU_UCODE_ID_SDMA0: 851 *type = GFX_FW_TYPE_SDMA0; 852 break; 853 case AMDGPU_UCODE_ID_SDMA1: 854 *type = GFX_FW_TYPE_SDMA1; 855 break; 856 case AMDGPU_UCODE_ID_CP_CE: 857 *type = GFX_FW_TYPE_CP_CE; 858 break; 859 case AMDGPU_UCODE_ID_CP_PFP: 860 *type = GFX_FW_TYPE_CP_PFP; 861 break; 862 case AMDGPU_UCODE_ID_CP_ME: 863 *type = GFX_FW_TYPE_CP_ME; 864 break; 865 case AMDGPU_UCODE_ID_CP_MEC1: 866 *type = GFX_FW_TYPE_CP_MEC; 867 break; 868 case AMDGPU_UCODE_ID_CP_MEC1_JT: 869 *type = GFX_FW_TYPE_CP_MEC_ME1; 870 break; 871 case AMDGPU_UCODE_ID_CP_MEC2: 872 *type = GFX_FW_TYPE_CP_MEC; 873 break; 874 case AMDGPU_UCODE_ID_CP_MEC2_JT: 875 *type = GFX_FW_TYPE_CP_MEC_ME2; 876 break; 877 case AMDGPU_UCODE_ID_RLC_G: 878 *type = GFX_FW_TYPE_RLC_G; 879 break; 880 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 881 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 882 break; 883 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 884 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 885 break; 886 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 887 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 888 break; 889 case AMDGPU_UCODE_ID_SMC: 890 *type = GFX_FW_TYPE_SMU; 891 break; 892 case AMDGPU_UCODE_ID_UVD: 893 *type = GFX_FW_TYPE_UVD; 894 break; 895 case AMDGPU_UCODE_ID_UVD1: 896 *type = GFX_FW_TYPE_UVD1; 897 break; 898 case AMDGPU_UCODE_ID_VCE: 899 *type = GFX_FW_TYPE_VCE; 900 break; 901 case AMDGPU_UCODE_ID_VCN: 902 *type = GFX_FW_TYPE_VCN; 903 break; 904 case AMDGPU_UCODE_ID_DMCU_ERAM: 905 *type = GFX_FW_TYPE_DMCU_ERAM; 906 break; 907 case AMDGPU_UCODE_ID_DMCU_INTV: 908 *type = GFX_FW_TYPE_DMCU_ISR; 909 break; 910 case AMDGPU_UCODE_ID_VCN0_RAM: 911 *type = GFX_FW_TYPE_VCN0_RAM; 912 break; 913 case AMDGPU_UCODE_ID_VCN1_RAM: 914 *type = GFX_FW_TYPE_VCN1_RAM; 915 break; 916 case AMDGPU_UCODE_ID_MAXIMUM: 917 default: 918 return -EINVAL; 919 } 920 921 return 0; 922 } 923 924 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 925 struct psp_gfx_cmd_resp *cmd) 926 { 927 int ret; 928 uint64_t fw_mem_mc_addr = ucode->mc_addr; 929 930 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 931 932 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 933 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 934 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 935 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 936 937 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 938 if (ret) 939 DRM_ERROR("Unknown firmware type\n"); 940 941 return ret; 942 } 943 944 static int psp_execute_np_fw_load(struct psp_context *psp, 945 struct amdgpu_firmware_info *ucode) 946 { 947 int ret = 0; 948 949 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 950 if (ret) 951 return ret; 952 953 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 954 psp->fence_buf_mc_addr); 955 956 return ret; 957 } 958 959 static int psp_np_fw_load(struct psp_context *psp) 960 { 961 int i, ret; 962 struct amdgpu_firmware_info *ucode; 963 struct amdgpu_device* adev = psp->adev; 964 965 if (psp->autoload_supported) { 966 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 967 if (!ucode->fw) 968 goto out; 969 970 ret = psp_execute_np_fw_load(psp, ucode); 971 if (ret) 972 return ret; 973 } 974 975 out: 976 for (i = 0; i < adev->firmware.max_ucodes; i++) { 977 ucode = &adev->firmware.ucode[i]; 978 if (!ucode->fw) 979 continue; 980 981 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 982 (psp_smu_reload_quirk(psp) || psp->autoload_supported)) 983 continue; 984 if (amdgpu_sriov_vf(adev) && 985 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 986 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 987 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) 988 /*skip ucode loading in SRIOV VF */ 989 continue; 990 if (psp->autoload_supported && 991 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 992 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 993 /* skip mec JT when autoload is enabled */ 994 continue; 995 996 ret = psp_execute_np_fw_load(psp, ucode); 997 if (ret) 998 return ret; 999 1000 /* Start rlc autoload after psp recieved all the gfx firmware */ 1001 if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) { 1002 ret = psp_rlc_autoload(psp); 1003 if (ret) { 1004 DRM_ERROR("Failed to start rlc autoload\n"); 1005 return ret; 1006 } 1007 } 1008 #if 0 1009 /* check if firmware loaded sucessfully */ 1010 if (!amdgpu_psp_check_fw_loading_status(adev, i)) 1011 return -EINVAL; 1012 #endif 1013 } 1014 1015 return 0; 1016 } 1017 1018 static int psp_load_fw(struct amdgpu_device *adev) 1019 { 1020 int ret; 1021 struct psp_context *psp = &adev->psp; 1022 1023 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) { 1024 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 1025 goto skip_memalloc; 1026 } 1027 1028 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1029 if (!psp->cmd) 1030 return -ENOMEM; 1031 1032 /* this fw pri bo is not used under SRIOV */ 1033 if (!amdgpu_sriov_vf(psp->adev)) { 1034 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 1035 AMDGPU_GEM_DOMAIN_GTT, 1036 &psp->fw_pri_bo, 1037 &psp->fw_pri_mc_addr, 1038 &psp->fw_pri_buf); 1039 if (ret) 1040 goto failed; 1041 } 1042 1043 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 1044 AMDGPU_GEM_DOMAIN_VRAM, 1045 &psp->fence_buf_bo, 1046 &psp->fence_buf_mc_addr, 1047 &psp->fence_buf); 1048 if (ret) 1049 goto failed; 1050 1051 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 1052 AMDGPU_GEM_DOMAIN_VRAM, 1053 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 1054 (void **)&psp->cmd_buf_mem); 1055 if (ret) 1056 goto failed; 1057 1058 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 1059 1060 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 1061 if (ret) { 1062 DRM_ERROR("PSP ring init failed!\n"); 1063 goto failed; 1064 } 1065 1066 skip_memalloc: 1067 ret = psp_hw_start(psp); 1068 if (ret) 1069 goto failed; 1070 1071 ret = psp_np_fw_load(psp); 1072 if (ret) 1073 goto failed; 1074 1075 return 0; 1076 1077 failed: 1078 /* 1079 * all cleanup jobs (xgmi terminate, ras terminate, 1080 * ring destroy, cmd/fence/fw buffers destory, 1081 * psp->cmd destory) are delayed to psp_hw_fini 1082 */ 1083 return ret; 1084 } 1085 1086 static int psp_hw_init(void *handle) 1087 { 1088 int ret; 1089 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1090 1091 mutex_lock(&adev->firmware.mutex); 1092 /* 1093 * This sequence is just used on hw_init only once, no need on 1094 * resume. 1095 */ 1096 ret = amdgpu_ucode_init_bo(adev); 1097 if (ret) 1098 goto failed; 1099 1100 ret = psp_load_fw(adev); 1101 if (ret) { 1102 DRM_ERROR("PSP firmware loading failed\n"); 1103 goto failed; 1104 } 1105 1106 mutex_unlock(&adev->firmware.mutex); 1107 return 0; 1108 1109 failed: 1110 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 1111 mutex_unlock(&adev->firmware.mutex); 1112 return -EINVAL; 1113 } 1114 1115 static int psp_hw_fini(void *handle) 1116 { 1117 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1118 struct psp_context *psp = &adev->psp; 1119 1120 if (adev->gmc.xgmi.num_physical_nodes > 1 && 1121 psp->xgmi_context.initialized == 1) 1122 psp_xgmi_terminate(psp); 1123 1124 if (psp->adev->psp.ta_fw) 1125 psp_ras_terminate(psp); 1126 1127 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 1128 1129 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 1130 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 1131 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 1132 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 1133 &psp->fence_buf_mc_addr, &psp->fence_buf); 1134 amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr, 1135 &psp->asd_shared_buf); 1136 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 1137 (void **)&psp->cmd_buf_mem); 1138 1139 kfree(psp->cmd); 1140 psp->cmd = NULL; 1141 1142 return 0; 1143 } 1144 1145 static int psp_suspend(void *handle) 1146 { 1147 int ret; 1148 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1149 struct psp_context *psp = &adev->psp; 1150 1151 if (adev->gmc.xgmi.num_physical_nodes > 1 && 1152 psp->xgmi_context.initialized == 1) { 1153 ret = psp_xgmi_terminate(psp); 1154 if (ret) { 1155 DRM_ERROR("Failed to terminate xgmi ta\n"); 1156 return ret; 1157 } 1158 } 1159 1160 if (psp->adev->psp.ta_fw) { 1161 ret = psp_ras_terminate(psp); 1162 if (ret) { 1163 DRM_ERROR("Failed to terminate ras ta\n"); 1164 return ret; 1165 } 1166 } 1167 1168 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 1169 if (ret) { 1170 DRM_ERROR("PSP ring stop failed\n"); 1171 return ret; 1172 } 1173 1174 return 0; 1175 } 1176 1177 static int psp_resume(void *handle) 1178 { 1179 int ret; 1180 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1181 struct psp_context *psp = &adev->psp; 1182 1183 DRM_INFO("PSP is resuming...\n"); 1184 1185 mutex_lock(&adev->firmware.mutex); 1186 1187 ret = psp_hw_start(psp); 1188 if (ret) 1189 goto failed; 1190 1191 ret = psp_np_fw_load(psp); 1192 if (ret) 1193 goto failed; 1194 1195 mutex_unlock(&adev->firmware.mutex); 1196 1197 return 0; 1198 1199 failed: 1200 DRM_ERROR("PSP resume failed\n"); 1201 mutex_unlock(&adev->firmware.mutex); 1202 return ret; 1203 } 1204 1205 int psp_gpu_reset(struct amdgpu_device *adev) 1206 { 1207 int ret; 1208 1209 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 1210 return 0; 1211 1212 mutex_lock(&adev->psp.mutex); 1213 ret = psp_mode1_reset(&adev->psp); 1214 mutex_unlock(&adev->psp.mutex); 1215 1216 return ret; 1217 } 1218 1219 int psp_rlc_autoload_start(struct psp_context *psp) 1220 { 1221 int ret; 1222 struct psp_gfx_cmd_resp *cmd; 1223 1224 if (amdgpu_sriov_vf(psp->adev)) 1225 return 0; 1226 1227 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1228 if (!cmd) 1229 return -ENOMEM; 1230 1231 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 1232 1233 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1234 psp->fence_buf_mc_addr); 1235 kfree(cmd); 1236 return ret; 1237 } 1238 1239 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 1240 uint64_t cmd_gpu_addr, int cmd_size) 1241 { 1242 struct amdgpu_firmware_info ucode = {0}; 1243 1244 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 1245 AMDGPU_UCODE_ID_VCN0_RAM; 1246 ucode.mc_addr = cmd_gpu_addr; 1247 ucode.ucode_size = cmd_size; 1248 1249 return psp_execute_np_fw_load(&adev->psp, &ucode); 1250 } 1251 1252 static bool psp_check_fw_loading_status(struct amdgpu_device *adev, 1253 enum AMDGPU_UCODE_ID ucode_type) 1254 { 1255 struct amdgpu_firmware_info *ucode = NULL; 1256 1257 if (!adev->firmware.fw_size) 1258 return false; 1259 1260 ucode = &adev->firmware.ucode[ucode_type]; 1261 if (!ucode->fw || !ucode->ucode_size) 1262 return false; 1263 1264 return psp_compare_sram_data(&adev->psp, ucode, ucode_type); 1265 } 1266 1267 static int psp_set_clockgating_state(void *handle, 1268 enum amd_clockgating_state state) 1269 { 1270 return 0; 1271 } 1272 1273 static int psp_set_powergating_state(void *handle, 1274 enum amd_powergating_state state) 1275 { 1276 return 0; 1277 } 1278 1279 const struct amd_ip_funcs psp_ip_funcs = { 1280 .name = "psp", 1281 .early_init = psp_early_init, 1282 .late_init = NULL, 1283 .sw_init = psp_sw_init, 1284 .sw_fini = psp_sw_fini, 1285 .hw_init = psp_hw_init, 1286 .hw_fini = psp_hw_fini, 1287 .suspend = psp_suspend, 1288 .resume = psp_resume, 1289 .is_idle = NULL, 1290 .check_soft_reset = NULL, 1291 .wait_for_idle = NULL, 1292 .soft_reset = NULL, 1293 .set_clockgating_state = psp_set_clockgating_state, 1294 .set_powergating_state = psp_set_powergating_state, 1295 }; 1296 1297 static const struct amdgpu_psp_funcs psp_funcs = { 1298 .check_fw_loading_status = psp_check_fw_loading_status, 1299 }; 1300 1301 static void psp_set_funcs(struct amdgpu_device *adev) 1302 { 1303 if (NULL == adev->firmware.funcs) 1304 adev->firmware.funcs = &psp_funcs; 1305 } 1306 1307 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 1308 { 1309 .type = AMD_IP_BLOCK_TYPE_PSP, 1310 .major = 3, 1311 .minor = 1, 1312 .rev = 0, 1313 .funcs = &psp_ip_funcs, 1314 }; 1315 1316 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 1317 { 1318 .type = AMD_IP_BLOCK_TYPE_PSP, 1319 .major = 10, 1320 .minor = 0, 1321 .rev = 0, 1322 .funcs = &psp_ip_funcs, 1323 }; 1324 1325 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 1326 { 1327 .type = AMD_IP_BLOCK_TYPE_PSP, 1328 .major = 11, 1329 .minor = 0, 1330 .rev = 0, 1331 .funcs = &psp_ip_funcs, 1332 }; 1333