1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 41 #include "amdgpu_ras.h" 42 #include "amdgpu_securedisplay.h" 43 #include "amdgpu_atomfirmware.h" 44 45 static int psp_sysfs_init(struct amdgpu_device *adev); 46 static void psp_sysfs_fini(struct amdgpu_device *adev); 47 48 static int psp_load_smu_fw(struct psp_context *psp); 49 static int psp_ta_unload(struct psp_context *psp, struct ta_context *context); 50 static int psp_ta_load(struct psp_context *psp, struct ta_context *context); 51 static int psp_rap_terminate(struct psp_context *psp); 52 static int psp_securedisplay_terminate(struct psp_context *psp); 53 54 /* 55 * Due to DF Cstate management centralized to PMFW, the firmware 56 * loading sequence will be updated as below: 57 * - Load KDB 58 * - Load SYS_DRV 59 * - Load tOS 60 * - Load PMFW 61 * - Setup TMR 62 * - Load other non-psp fw 63 * - Load ASD 64 * - Load XGMI/RAS/HDCP/DTM TA if any 65 * 66 * This new sequence is required for 67 * - Arcturus and onwards 68 */ 69 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 70 { 71 struct amdgpu_device *adev = psp->adev; 72 73 if (amdgpu_sriov_vf(adev)) { 74 psp->pmfw_centralized_cstate_management = false; 75 return; 76 } 77 78 switch (adev->ip_versions[MP0_HWIP][0]) { 79 case IP_VERSION(11, 0, 0): 80 case IP_VERSION(11, 0, 4): 81 case IP_VERSION(11, 0, 5): 82 case IP_VERSION(11, 0, 7): 83 case IP_VERSION(11, 0, 9): 84 case IP_VERSION(11, 0, 11): 85 case IP_VERSION(11, 0, 12): 86 case IP_VERSION(11, 0, 13): 87 case IP_VERSION(13, 0, 2): 88 psp->pmfw_centralized_cstate_management = true; 89 break; 90 default: 91 psp->pmfw_centralized_cstate_management = false; 92 break; 93 } 94 } 95 96 static int psp_early_init(void *handle) 97 { 98 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 99 struct psp_context *psp = &adev->psp; 100 101 switch (adev->ip_versions[MP0_HWIP][0]) { 102 case IP_VERSION(9, 0, 0): 103 psp_v3_1_set_psp_funcs(psp); 104 psp->autoload_supported = false; 105 break; 106 case IP_VERSION(10, 0, 0): 107 case IP_VERSION(10, 0, 1): 108 psp_v10_0_set_psp_funcs(psp); 109 psp->autoload_supported = false; 110 break; 111 case IP_VERSION(11, 0, 2): 112 case IP_VERSION(11, 0, 4): 113 psp_v11_0_set_psp_funcs(psp); 114 psp->autoload_supported = false; 115 break; 116 case IP_VERSION(11, 0, 0): 117 case IP_VERSION(11, 0, 5): 118 case IP_VERSION(11, 0, 9): 119 case IP_VERSION(11, 0, 7): 120 case IP_VERSION(11, 0, 11): 121 case IP_VERSION(11, 5, 0): 122 case IP_VERSION(11, 0, 12): 123 case IP_VERSION(11, 0, 13): 124 psp_v11_0_set_psp_funcs(psp); 125 psp->autoload_supported = true; 126 break; 127 case IP_VERSION(11, 0, 3): 128 case IP_VERSION(12, 0, 1): 129 psp_v12_0_set_psp_funcs(psp); 130 break; 131 case IP_VERSION(13, 0, 2): 132 psp_v13_0_set_psp_funcs(psp); 133 break; 134 case IP_VERSION(13, 0, 1): 135 case IP_VERSION(13, 0, 3): 136 case IP_VERSION(13, 0, 5): 137 case IP_VERSION(13, 0, 8): 138 psp_v13_0_set_psp_funcs(psp); 139 psp->autoload_supported = true; 140 break; 141 case IP_VERSION(11, 0, 8): 142 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 143 psp_v11_0_8_set_psp_funcs(psp); 144 psp->autoload_supported = false; 145 } 146 break; 147 default: 148 return -EINVAL; 149 } 150 151 psp->adev = adev; 152 153 psp_check_pmfw_centralized_cstate_management(psp); 154 155 return 0; 156 } 157 158 static void psp_memory_training_fini(struct psp_context *psp) 159 { 160 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 161 162 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 163 kfree(ctx->sys_cache); 164 ctx->sys_cache = NULL; 165 } 166 167 static int psp_memory_training_init(struct psp_context *psp) 168 { 169 int ret; 170 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 171 172 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 173 DRM_DEBUG("memory training is not supported!\n"); 174 return 0; 175 } 176 177 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 178 if (ctx->sys_cache == NULL) { 179 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 180 ret = -ENOMEM; 181 goto Err_out; 182 } 183 184 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 185 ctx->train_data_size, 186 ctx->p2c_train_data_offset, 187 ctx->c2p_train_data_offset); 188 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 189 return 0; 190 191 Err_out: 192 psp_memory_training_fini(psp); 193 return ret; 194 } 195 196 /* 197 * Helper funciton to query psp runtime database entry 198 * 199 * @adev: amdgpu_device pointer 200 * @entry_type: the type of psp runtime database entry 201 * @db_entry: runtime database entry pointer 202 * 203 * Return false if runtime database doesn't exit or entry is invalid 204 * or true if the specific database entry is found, and copy to @db_entry 205 */ 206 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 207 enum psp_runtime_entry_type entry_type, 208 void *db_entry) 209 { 210 uint64_t db_header_pos, db_dir_pos; 211 struct psp_runtime_data_header db_header = {0}; 212 struct psp_runtime_data_directory db_dir = {0}; 213 bool ret = false; 214 int i; 215 216 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 217 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 218 219 /* read runtime db header from vram */ 220 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 221 sizeof(struct psp_runtime_data_header), false); 222 223 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 224 /* runtime db doesn't exist, exit */ 225 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 226 return false; 227 } 228 229 /* read runtime database entry from vram */ 230 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 231 sizeof(struct psp_runtime_data_directory), false); 232 233 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 234 /* invalid db entry count, exit */ 235 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 236 return false; 237 } 238 239 /* look up for requested entry type */ 240 for (i = 0; i < db_dir.entry_count && !ret; i++) { 241 if (db_dir.entry_list[i].entry_type == entry_type) { 242 switch (entry_type) { 243 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 244 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 245 /* invalid db entry size */ 246 dev_warn(adev->dev, "Invalid PSP runtime database entry size\n"); 247 return false; 248 } 249 /* read runtime database entry */ 250 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 251 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 252 ret = true; 253 break; 254 default: 255 ret = false; 256 break; 257 } 258 } 259 } 260 261 return ret; 262 } 263 264 static int psp_init_sriov_microcode(struct psp_context *psp) 265 { 266 struct amdgpu_device *adev = psp->adev; 267 int ret = 0; 268 269 switch (adev->ip_versions[MP0_HWIP][0]) { 270 case IP_VERSION(9, 0, 0): 271 ret = psp_init_cap_microcode(psp, "vega10"); 272 break; 273 case IP_VERSION(11, 0, 9): 274 ret = psp_init_cap_microcode(psp, "navi12"); 275 break; 276 case IP_VERSION(11, 0, 7): 277 ret = psp_init_cap_microcode(psp, "sienna_cichlid"); 278 break; 279 case IP_VERSION(13, 0, 2): 280 ret = psp_init_cap_microcode(psp, "aldebaran"); 281 break; 282 default: 283 BUG(); 284 break; 285 } 286 287 return ret; 288 } 289 290 static int psp_sw_init(void *handle) 291 { 292 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 293 struct psp_context *psp = &adev->psp; 294 int ret; 295 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 296 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 297 298 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 299 if (!psp->cmd) { 300 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 301 ret = -ENOMEM; 302 } 303 304 if (amdgpu_sriov_vf(adev)) 305 ret = psp_init_sriov_microcode(psp); 306 else 307 ret = psp_init_microcode(psp); 308 if (ret) { 309 DRM_ERROR("Failed to load psp firmware!\n"); 310 return ret; 311 } 312 313 adev->psp.xgmi_context.supports_extended_data = 314 !adev->gmc.xgmi.connected_to_cpu && 315 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 316 317 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 318 if (psp_get_runtime_db_entry(adev, 319 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 320 &boot_cfg_entry)) { 321 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 322 if ((psp->boot_cfg_bitmask) & 323 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 324 /* If psp runtime database exists, then 325 * only enable two stage memory training 326 * when TWO_STAGE_DRAM_TRAINING bit is set 327 * in runtime database */ 328 mem_training_ctx->enable_mem_training = true; 329 } 330 331 } else { 332 /* If psp runtime database doesn't exist or 333 * is invalid, force enable two stage memory 334 * training */ 335 mem_training_ctx->enable_mem_training = true; 336 } 337 338 if (mem_training_ctx->enable_mem_training) { 339 ret = psp_memory_training_init(psp); 340 if (ret) { 341 DRM_ERROR("Failed to initialize memory training!\n"); 342 return ret; 343 } 344 345 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 346 if (ret) { 347 DRM_ERROR("Failed to process memory training!\n"); 348 return ret; 349 } 350 } 351 352 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 353 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 354 ret= psp_sysfs_init(adev); 355 if (ret) { 356 return ret; 357 } 358 } 359 360 return 0; 361 } 362 363 static int psp_sw_fini(void *handle) 364 { 365 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 366 struct psp_context *psp = &adev->psp; 367 struct psp_gfx_cmd_resp *cmd = psp->cmd; 368 369 psp_memory_training_fini(psp); 370 if (psp->sos_fw) { 371 release_firmware(psp->sos_fw); 372 psp->sos_fw = NULL; 373 } 374 if (psp->asd_fw) { 375 release_firmware(psp->asd_fw); 376 psp->asd_fw = NULL; 377 } 378 if (psp->ta_fw) { 379 release_firmware(psp->ta_fw); 380 psp->ta_fw = NULL; 381 } 382 if (adev->psp.cap_fw) { 383 release_firmware(psp->cap_fw); 384 psp->cap_fw = NULL; 385 } 386 387 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 388 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 389 psp_sysfs_fini(adev); 390 391 kfree(cmd); 392 cmd = NULL; 393 394 return 0; 395 } 396 397 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 398 uint32_t reg_val, uint32_t mask, bool check_changed) 399 { 400 uint32_t val; 401 int i; 402 struct amdgpu_device *adev = psp->adev; 403 404 if (psp->adev->no_hw_access) 405 return 0; 406 407 for (i = 0; i < adev->usec_timeout; i++) { 408 val = RREG32(reg_index); 409 if (check_changed) { 410 if (val != reg_val) 411 return 0; 412 } else { 413 if ((val & mask) == reg_val) 414 return 0; 415 } 416 udelay(1); 417 } 418 419 return -ETIME; 420 } 421 422 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 423 { 424 switch (cmd_id) { 425 case GFX_CMD_ID_LOAD_TA: 426 return "LOAD_TA"; 427 case GFX_CMD_ID_UNLOAD_TA: 428 return "UNLOAD_TA"; 429 case GFX_CMD_ID_INVOKE_CMD: 430 return "INVOKE_CMD"; 431 case GFX_CMD_ID_LOAD_ASD: 432 return "LOAD_ASD"; 433 case GFX_CMD_ID_SETUP_TMR: 434 return "SETUP_TMR"; 435 case GFX_CMD_ID_LOAD_IP_FW: 436 return "LOAD_IP_FW"; 437 case GFX_CMD_ID_DESTROY_TMR: 438 return "DESTROY_TMR"; 439 case GFX_CMD_ID_SAVE_RESTORE: 440 return "SAVE_RESTORE_IP_FW"; 441 case GFX_CMD_ID_SETUP_VMR: 442 return "SETUP_VMR"; 443 case GFX_CMD_ID_DESTROY_VMR: 444 return "DESTROY_VMR"; 445 case GFX_CMD_ID_PROG_REG: 446 return "PROG_REG"; 447 case GFX_CMD_ID_GET_FW_ATTESTATION: 448 return "GET_FW_ATTESTATION"; 449 case GFX_CMD_ID_LOAD_TOC: 450 return "ID_LOAD_TOC"; 451 case GFX_CMD_ID_AUTOLOAD_RLC: 452 return "AUTOLOAD_RLC"; 453 case GFX_CMD_ID_BOOT_CFG: 454 return "BOOT_CFG"; 455 default: 456 return "UNKNOWN CMD"; 457 } 458 } 459 460 static int 461 psp_cmd_submit_buf(struct psp_context *psp, 462 struct amdgpu_firmware_info *ucode, 463 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 464 { 465 int ret; 466 int index, idx; 467 int timeout = 20000; 468 bool ras_intr = false; 469 bool skip_unsupport = false; 470 471 if (psp->adev->no_hw_access) 472 return 0; 473 474 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 475 return 0; 476 477 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 478 479 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 480 481 index = atomic_inc_return(&psp->fence_value); 482 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 483 if (ret) { 484 atomic_dec(&psp->fence_value); 485 goto exit; 486 } 487 488 amdgpu_device_invalidate_hdp(psp->adev, NULL); 489 while (*((unsigned int *)psp->fence_buf) != index) { 490 if (--timeout == 0) 491 break; 492 /* 493 * Shouldn't wait for timeout when err_event_athub occurs, 494 * because gpu reset thread triggered and lock resource should 495 * be released for psp resume sequence. 496 */ 497 ras_intr = amdgpu_ras_intr_triggered(); 498 if (ras_intr) 499 break; 500 usleep_range(10, 100); 501 amdgpu_device_invalidate_hdp(psp->adev, NULL); 502 } 503 504 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 505 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 506 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 507 508 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 509 510 /* In some cases, psp response status is not 0 even there is no 511 * problem while the command is submitted. Some version of PSP FW 512 * doesn't write 0 to that field. 513 * So here we would like to only print a warning instead of an error 514 * during psp initialization to avoid breaking hw_init and it doesn't 515 * return -EINVAL. 516 */ 517 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 518 if (ucode) 519 DRM_WARN("failed to load ucode %s(0x%X) ", 520 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 521 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 522 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 523 psp->cmd_buf_mem->resp.status); 524 /* If we load CAP FW, PSP must return 0 under SRIOV 525 * also return failure in case of timeout 526 */ 527 if ((ucode && (ucode->ucode_id == AMDGPU_UCODE_ID_CAP)) || !timeout) { 528 ret = -EINVAL; 529 goto exit; 530 } 531 } 532 533 if (ucode) { 534 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 535 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 536 } 537 538 exit: 539 drm_dev_exit(idx); 540 return ret; 541 } 542 543 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 544 { 545 struct psp_gfx_cmd_resp *cmd = psp->cmd; 546 547 mutex_lock(&psp->mutex); 548 549 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 550 551 return cmd; 552 } 553 554 static void release_psp_cmd_buf(struct psp_context *psp) 555 { 556 mutex_unlock(&psp->mutex); 557 } 558 559 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 560 struct psp_gfx_cmd_resp *cmd, 561 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 562 { 563 struct amdgpu_device *adev = psp->adev; 564 uint32_t size = amdgpu_bo_size(tmr_bo); 565 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 566 567 if (amdgpu_sriov_vf(psp->adev)) 568 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 569 else 570 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 571 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 572 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 573 cmd->cmd.cmd_setup_tmr.buf_size = size; 574 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 575 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 576 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 577 } 578 579 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 580 uint64_t pri_buf_mc, uint32_t size) 581 { 582 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 583 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 584 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 585 cmd->cmd.cmd_load_toc.toc_size = size; 586 } 587 588 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 589 static int psp_load_toc(struct psp_context *psp, 590 uint32_t *tmr_size) 591 { 592 int ret; 593 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 594 595 /* Copy toc to psp firmware private buffer */ 596 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 597 598 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 599 600 ret = psp_cmd_submit_buf(psp, NULL, cmd, 601 psp->fence_buf_mc_addr); 602 if (!ret) 603 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 604 605 release_psp_cmd_buf(psp); 606 607 return ret; 608 } 609 610 /* Set up Trusted Memory Region */ 611 static int psp_tmr_init(struct psp_context *psp) 612 { 613 int ret; 614 int tmr_size; 615 void *tmr_buf; 616 void **pptr; 617 618 /* 619 * According to HW engineer, they prefer the TMR address be "naturally 620 * aligned" , e.g. the start address be an integer divide of TMR size. 621 * 622 * Note: this memory need be reserved till the driver 623 * uninitializes. 624 */ 625 tmr_size = PSP_TMR_SIZE(psp->adev); 626 627 /* For ASICs support RLC autoload, psp will parse the toc 628 * and calculate the total size of TMR needed */ 629 if (!amdgpu_sriov_vf(psp->adev) && 630 psp->toc.start_addr && 631 psp->toc.size_bytes && 632 psp->fw_pri_buf) { 633 ret = psp_load_toc(psp, &tmr_size); 634 if (ret) { 635 DRM_ERROR("Failed to load toc\n"); 636 return ret; 637 } 638 } 639 640 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 641 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 642 AMDGPU_GEM_DOMAIN_VRAM, 643 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 644 645 return ret; 646 } 647 648 static bool psp_skip_tmr(struct psp_context *psp) 649 { 650 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 651 case IP_VERSION(11, 0, 9): 652 case IP_VERSION(11, 0, 7): 653 case IP_VERSION(13, 0, 2): 654 return true; 655 default: 656 return false; 657 } 658 } 659 660 static int psp_tmr_load(struct psp_context *psp) 661 { 662 int ret; 663 struct psp_gfx_cmd_resp *cmd; 664 665 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 666 * Already set up by host driver. 667 */ 668 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 669 return 0; 670 671 cmd = acquire_psp_cmd_buf(psp); 672 673 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 674 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 675 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 676 677 ret = psp_cmd_submit_buf(psp, NULL, cmd, 678 psp->fence_buf_mc_addr); 679 680 release_psp_cmd_buf(psp); 681 682 return ret; 683 } 684 685 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 686 struct psp_gfx_cmd_resp *cmd) 687 { 688 if (amdgpu_sriov_vf(psp->adev)) 689 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 690 else 691 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 692 } 693 694 static int psp_tmr_unload(struct psp_context *psp) 695 { 696 int ret; 697 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 698 699 psp_prep_tmr_unload_cmd_buf(psp, cmd); 700 DRM_INFO("free PSP TMR buffer\n"); 701 702 ret = psp_cmd_submit_buf(psp, NULL, cmd, 703 psp->fence_buf_mc_addr); 704 705 release_psp_cmd_buf(psp); 706 707 return ret; 708 } 709 710 static int psp_tmr_terminate(struct psp_context *psp) 711 { 712 int ret; 713 void *tmr_buf; 714 void **pptr; 715 716 ret = psp_tmr_unload(psp); 717 if (ret) 718 return ret; 719 720 /* free TMR memory buffer */ 721 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 722 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 723 724 return 0; 725 } 726 727 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 728 uint64_t *output_ptr) 729 { 730 int ret; 731 struct psp_gfx_cmd_resp *cmd; 732 733 if (!output_ptr) 734 return -EINVAL; 735 736 if (amdgpu_sriov_vf(psp->adev)) 737 return 0; 738 739 cmd = acquire_psp_cmd_buf(psp); 740 741 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 742 743 ret = psp_cmd_submit_buf(psp, NULL, cmd, 744 psp->fence_buf_mc_addr); 745 746 if (!ret) { 747 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 748 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 749 } 750 751 release_psp_cmd_buf(psp); 752 753 return ret; 754 } 755 756 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 757 { 758 struct psp_context *psp = &adev->psp; 759 struct psp_gfx_cmd_resp *cmd; 760 int ret; 761 762 if (amdgpu_sriov_vf(adev)) 763 return 0; 764 765 cmd = acquire_psp_cmd_buf(psp); 766 767 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 768 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 769 770 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 771 if (!ret) { 772 *boot_cfg = 773 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 774 } 775 776 release_psp_cmd_buf(psp); 777 778 return ret; 779 } 780 781 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 782 { 783 int ret; 784 struct psp_context *psp = &adev->psp; 785 struct psp_gfx_cmd_resp *cmd; 786 787 if (amdgpu_sriov_vf(adev)) 788 return 0; 789 790 cmd = acquire_psp_cmd_buf(psp); 791 792 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 793 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 794 cmd->cmd.boot_cfg.boot_config = boot_cfg; 795 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 796 797 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 798 799 release_psp_cmd_buf(psp); 800 801 return ret; 802 } 803 804 static int psp_rl_load(struct amdgpu_device *adev) 805 { 806 int ret; 807 struct psp_context *psp = &adev->psp; 808 struct psp_gfx_cmd_resp *cmd; 809 810 if (!is_psp_fw_valid(psp->rl)) 811 return 0; 812 813 cmd = acquire_psp_cmd_buf(psp); 814 815 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 816 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 817 818 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 819 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 820 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 821 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 822 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 823 824 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 825 826 release_psp_cmd_buf(psp); 827 828 return ret; 829 } 830 831 static int psp_asd_load(struct psp_context *psp) 832 { 833 return psp_ta_load(psp, &psp->asd_context); 834 } 835 836 static int psp_asd_initialize(struct psp_context *psp) 837 { 838 int ret; 839 840 /* If PSP version doesn't match ASD version, asd loading will be failed. 841 * add workaround to bypass it for sriov now. 842 * TODO: add version check to make it common 843 */ 844 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 845 return 0; 846 847 psp->asd_context.mem_context.shared_mc_addr = 0; 848 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 849 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 850 851 ret = psp_asd_load(psp); 852 if (!ret) 853 psp->asd_context.initialized = true; 854 855 return ret; 856 } 857 858 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 859 uint32_t session_id) 860 { 861 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 862 cmd->cmd.cmd_unload_ta.session_id = session_id; 863 } 864 865 static int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 866 { 867 int ret; 868 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 869 870 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 871 872 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 873 874 release_psp_cmd_buf(psp); 875 876 return ret; 877 } 878 879 static int psp_asd_unload(struct psp_context *psp) 880 { 881 return psp_ta_unload(psp, &psp->asd_context); 882 } 883 884 static int psp_asd_terminate(struct psp_context *psp) 885 { 886 int ret; 887 888 if (amdgpu_sriov_vf(psp->adev)) 889 return 0; 890 891 if (!psp->asd_context.initialized) 892 return 0; 893 894 ret = psp_asd_unload(psp); 895 896 if (!ret) 897 psp->asd_context.initialized = false; 898 899 return ret; 900 } 901 902 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 903 uint32_t id, uint32_t value) 904 { 905 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 906 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 907 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 908 } 909 910 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 911 uint32_t value) 912 { 913 struct psp_gfx_cmd_resp *cmd; 914 int ret = 0; 915 916 if (reg >= PSP_REG_LAST) 917 return -EINVAL; 918 919 cmd = acquire_psp_cmd_buf(psp); 920 921 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 922 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 923 if (ret) 924 DRM_ERROR("PSP failed to program reg id %d", reg); 925 926 release_psp_cmd_buf(psp); 927 928 return ret; 929 } 930 931 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 932 uint64_t ta_bin_mc, 933 struct ta_context *context) 934 { 935 cmd->cmd_id = context->ta_load_type; 936 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 937 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 938 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 939 940 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 941 lower_32_bits(context->mem_context.shared_mc_addr); 942 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 943 upper_32_bits(context->mem_context.shared_mc_addr); 944 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 945 } 946 947 static int psp_ta_init_shared_buf(struct psp_context *psp, 948 struct ta_mem_context *mem_ctx) 949 { 950 /* 951 * Allocate 16k memory aligned to 4k from Frame Buffer (local 952 * physical) for ta to host memory 953 */ 954 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 955 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 956 &mem_ctx->shared_bo, 957 &mem_ctx->shared_mc_addr, 958 &mem_ctx->shared_buf); 959 } 960 961 static void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 962 { 963 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 964 &mem_ctx->shared_buf); 965 } 966 967 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 968 { 969 return psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 970 } 971 972 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 973 uint32_t ta_cmd_id, 974 uint32_t session_id) 975 { 976 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 977 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 978 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 979 } 980 981 static int psp_ta_invoke(struct psp_context *psp, 982 uint32_t ta_cmd_id, 983 struct ta_context *context) 984 { 985 int ret; 986 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 987 988 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 989 990 ret = psp_cmd_submit_buf(psp, NULL, cmd, 991 psp->fence_buf_mc_addr); 992 993 release_psp_cmd_buf(psp); 994 995 return ret; 996 } 997 998 static int psp_ta_load(struct psp_context *psp, struct ta_context *context) 999 { 1000 int ret; 1001 struct psp_gfx_cmd_resp *cmd; 1002 1003 cmd = acquire_psp_cmd_buf(psp); 1004 1005 psp_copy_fw(psp, context->bin_desc.start_addr, 1006 context->bin_desc.size_bytes); 1007 1008 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1009 1010 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1011 psp->fence_buf_mc_addr); 1012 1013 if (!ret) { 1014 context->session_id = cmd->resp.session_id; 1015 } 1016 1017 release_psp_cmd_buf(psp); 1018 1019 return ret; 1020 } 1021 1022 static int psp_xgmi_load(struct psp_context *psp) 1023 { 1024 return psp_ta_load(psp, &psp->xgmi_context.context); 1025 } 1026 1027 static int psp_xgmi_unload(struct psp_context *psp) 1028 { 1029 return psp_ta_unload(psp, &psp->xgmi_context.context); 1030 } 1031 1032 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1033 { 1034 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1035 } 1036 1037 int psp_xgmi_terminate(struct psp_context *psp) 1038 { 1039 int ret; 1040 struct amdgpu_device *adev = psp->adev; 1041 1042 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1043 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1044 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1045 adev->gmc.xgmi.connected_to_cpu)) 1046 return 0; 1047 1048 if (!psp->xgmi_context.context.initialized) 1049 return 0; 1050 1051 ret = psp_xgmi_unload(psp); 1052 if (ret) 1053 return ret; 1054 1055 psp->xgmi_context.context.initialized = false; 1056 1057 /* free xgmi shared memory */ 1058 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 1059 1060 return 0; 1061 } 1062 1063 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1064 { 1065 struct ta_xgmi_shared_memory *xgmi_cmd; 1066 int ret; 1067 1068 if (!psp->ta_fw || 1069 !psp->xgmi_context.context.bin_desc.size_bytes || 1070 !psp->xgmi_context.context.bin_desc.start_addr) 1071 return -ENOENT; 1072 1073 if (!load_ta) 1074 goto invoke; 1075 1076 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1077 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1078 1079 if (!psp->xgmi_context.context.initialized) { 1080 ret = psp_xgmi_init_shared_buf(psp); 1081 if (ret) 1082 return ret; 1083 } 1084 1085 /* Load XGMI TA */ 1086 ret = psp_xgmi_load(psp); 1087 if (!ret) 1088 psp->xgmi_context.context.initialized = true; 1089 else 1090 return ret; 1091 1092 invoke: 1093 /* Initialize XGMI session */ 1094 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1095 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1096 xgmi_cmd->flag_extend_link_record = set_extended_data; 1097 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1098 1099 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1100 1101 return ret; 1102 } 1103 1104 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1105 { 1106 struct ta_xgmi_shared_memory *xgmi_cmd; 1107 int ret; 1108 1109 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1110 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1111 1112 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1113 1114 /* Invoke xgmi ta to get hive id */ 1115 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1116 if (ret) 1117 return ret; 1118 1119 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1120 1121 return 0; 1122 } 1123 1124 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1125 { 1126 struct ta_xgmi_shared_memory *xgmi_cmd; 1127 int ret; 1128 1129 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1130 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1131 1132 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1133 1134 /* Invoke xgmi ta to get the node id */ 1135 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1136 if (ret) 1137 return ret; 1138 1139 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1140 1141 return 0; 1142 } 1143 1144 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1145 { 1146 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1147 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1148 } 1149 1150 /* 1151 * Chips that support extended topology information require the driver to 1152 * reflect topology information in the opposite direction. This is 1153 * because the TA has already exceeded its link record limit and if the 1154 * TA holds bi-directional information, the driver would have to do 1155 * multiple fetches instead of just two. 1156 */ 1157 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1158 struct psp_xgmi_node_info node_info) 1159 { 1160 struct amdgpu_device *mirror_adev; 1161 struct amdgpu_hive_info *hive; 1162 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1163 uint64_t dst_node_id = node_info.node_id; 1164 uint8_t dst_num_hops = node_info.num_hops; 1165 uint8_t dst_num_links = node_info.num_links; 1166 1167 hive = amdgpu_get_xgmi_hive(psp->adev); 1168 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1169 struct psp_xgmi_topology_info *mirror_top_info; 1170 int j; 1171 1172 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1173 continue; 1174 1175 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1176 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1177 if (mirror_top_info->nodes[j].node_id != src_node_id) 1178 continue; 1179 1180 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1181 /* 1182 * prevent 0 num_links value re-reflection since reflection 1183 * criteria is based on num_hops (direct or indirect). 1184 * 1185 */ 1186 if (dst_num_links) 1187 mirror_top_info->nodes[j].num_links = dst_num_links; 1188 1189 break; 1190 } 1191 1192 break; 1193 } 1194 } 1195 1196 int psp_xgmi_get_topology_info(struct psp_context *psp, 1197 int number_devices, 1198 struct psp_xgmi_topology_info *topology, 1199 bool get_extended_data) 1200 { 1201 struct ta_xgmi_shared_memory *xgmi_cmd; 1202 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1203 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1204 int i; 1205 int ret; 1206 1207 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1208 return -EINVAL; 1209 1210 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1211 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1212 xgmi_cmd->flag_extend_link_record = get_extended_data; 1213 1214 /* Fill in the shared memory with topology information as input */ 1215 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1216 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1217 topology_info_input->num_nodes = number_devices; 1218 1219 for (i = 0; i < topology_info_input->num_nodes; i++) { 1220 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1221 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1222 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1223 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1224 } 1225 1226 /* Invoke xgmi ta to get the topology information */ 1227 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1228 if (ret) 1229 return ret; 1230 1231 /* Read the output topology information from the shared memory */ 1232 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1233 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1234 for (i = 0; i < topology->num_nodes; i++) { 1235 /* extended data will either be 0 or equal to non-extended data */ 1236 if (topology_info_output->nodes[i].num_hops) 1237 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1238 1239 /* non-extended data gets everything here so no need to update */ 1240 if (!get_extended_data) { 1241 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1242 topology->nodes[i].is_sharing_enabled = 1243 topology_info_output->nodes[i].is_sharing_enabled; 1244 topology->nodes[i].sdma_engine = 1245 topology_info_output->nodes[i].sdma_engine; 1246 } 1247 1248 } 1249 1250 /* Invoke xgmi ta again to get the link information */ 1251 if (psp_xgmi_peer_link_info_supported(psp)) { 1252 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1253 1254 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1255 1256 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1257 1258 if (ret) 1259 return ret; 1260 1261 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1262 for (i = 0; i < topology->num_nodes; i++) { 1263 /* accumulate num_links on extended data */ 1264 topology->nodes[i].num_links = get_extended_data ? 1265 topology->nodes[i].num_links + 1266 link_info_output->nodes[i].num_links : 1267 link_info_output->nodes[i].num_links; 1268 1269 /* reflect the topology information for bi-directionality */ 1270 if (psp->xgmi_context.supports_extended_data && 1271 get_extended_data && topology->nodes[i].num_hops) 1272 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1273 } 1274 } 1275 1276 return 0; 1277 } 1278 1279 int psp_xgmi_set_topology_info(struct psp_context *psp, 1280 int number_devices, 1281 struct psp_xgmi_topology_info *topology) 1282 { 1283 struct ta_xgmi_shared_memory *xgmi_cmd; 1284 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1285 int i; 1286 1287 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1288 return -EINVAL; 1289 1290 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1291 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1292 1293 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1294 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1295 topology_info_input->num_nodes = number_devices; 1296 1297 for (i = 0; i < topology_info_input->num_nodes; i++) { 1298 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1299 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1300 topology_info_input->nodes[i].is_sharing_enabled = 1; 1301 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1302 } 1303 1304 /* Invoke xgmi ta to set topology information */ 1305 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1306 } 1307 1308 // ras begin 1309 static int psp_ras_init_shared_buf(struct psp_context *psp) 1310 { 1311 return psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1312 } 1313 1314 static int psp_ras_load(struct psp_context *psp) 1315 { 1316 return psp_ta_load(psp, &psp->ras_context.context); 1317 } 1318 1319 static int psp_ras_unload(struct psp_context *psp) 1320 { 1321 return psp_ta_unload(psp, &psp->ras_context.context); 1322 } 1323 1324 static void psp_ras_ta_check_status(struct psp_context *psp) 1325 { 1326 struct ta_ras_shared_memory *ras_cmd = 1327 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1328 1329 switch (ras_cmd->ras_status) { 1330 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1331 dev_warn(psp->adev->dev, 1332 "RAS WARNING: cmd failed due to unsupported ip\n"); 1333 break; 1334 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1335 dev_warn(psp->adev->dev, 1336 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1337 break; 1338 case TA_RAS_STATUS__SUCCESS: 1339 break; 1340 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1341 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1342 dev_warn(psp->adev->dev, 1343 "RAS WARNING: Inject error to critical region is not allowed\n"); 1344 break; 1345 default: 1346 dev_warn(psp->adev->dev, 1347 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1348 break; 1349 } 1350 } 1351 1352 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1353 { 1354 struct ta_ras_shared_memory *ras_cmd; 1355 int ret; 1356 1357 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1358 1359 /* 1360 * TODO: bypass the loading in sriov for now 1361 */ 1362 if (amdgpu_sriov_vf(psp->adev)) 1363 return 0; 1364 1365 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1366 1367 if (amdgpu_ras_intr_triggered()) 1368 return ret; 1369 1370 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1371 { 1372 DRM_WARN("RAS: Unsupported Interface"); 1373 return -EINVAL; 1374 } 1375 1376 if (!ret) { 1377 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1378 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1379 1380 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1381 } 1382 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1383 dev_warn(psp->adev->dev, 1384 "RAS internal register access blocked\n"); 1385 1386 psp_ras_ta_check_status(psp); 1387 } 1388 1389 return ret; 1390 } 1391 1392 int psp_ras_enable_features(struct psp_context *psp, 1393 union ta_ras_cmd_input *info, bool enable) 1394 { 1395 struct ta_ras_shared_memory *ras_cmd; 1396 int ret; 1397 1398 if (!psp->ras_context.context.initialized) 1399 return -EINVAL; 1400 1401 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1402 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1403 1404 if (enable) 1405 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1406 else 1407 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1408 1409 ras_cmd->ras_in_message = *info; 1410 1411 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1412 if (ret) 1413 return -EINVAL; 1414 1415 return 0; 1416 } 1417 1418 static int psp_ras_terminate(struct psp_context *psp) 1419 { 1420 int ret; 1421 1422 /* 1423 * TODO: bypass the terminate in sriov for now 1424 */ 1425 if (amdgpu_sriov_vf(psp->adev)) 1426 return 0; 1427 1428 if (!psp->ras_context.context.initialized) 1429 return 0; 1430 1431 ret = psp_ras_unload(psp); 1432 if (ret) 1433 return ret; 1434 1435 psp->ras_context.context.initialized = false; 1436 1437 /* free ras shared memory */ 1438 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 1439 1440 return 0; 1441 } 1442 1443 static int psp_ras_initialize(struct psp_context *psp) 1444 { 1445 int ret; 1446 uint32_t boot_cfg = 0xFF; 1447 struct amdgpu_device *adev = psp->adev; 1448 struct ta_ras_shared_memory *ras_cmd; 1449 1450 /* 1451 * TODO: bypass the initialize in sriov for now 1452 */ 1453 if (amdgpu_sriov_vf(adev)) 1454 return 0; 1455 1456 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1457 !adev->psp.ras_context.context.bin_desc.start_addr) { 1458 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1459 return 0; 1460 } 1461 1462 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1463 /* query GECC enablement status from boot config 1464 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1465 */ 1466 ret = psp_boot_config_get(adev, &boot_cfg); 1467 if (ret) 1468 dev_warn(adev->dev, "PSP get boot config failed\n"); 1469 1470 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1471 if (!boot_cfg) { 1472 dev_info(adev->dev, "GECC is disabled\n"); 1473 } else { 1474 /* disable GECC in next boot cycle if ras is 1475 * disabled by module parameter amdgpu_ras_enable 1476 * and/or amdgpu_ras_mask, or boot_config_get call 1477 * is failed 1478 */ 1479 ret = psp_boot_config_set(adev, 0); 1480 if (ret) 1481 dev_warn(adev->dev, "PSP set boot config failed\n"); 1482 else 1483 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1484 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1485 } 1486 } else { 1487 if (1 == boot_cfg) { 1488 dev_info(adev->dev, "GECC is enabled\n"); 1489 } else { 1490 /* enable GECC in next boot cycle if it is disabled 1491 * in boot config, or force enable GECC if failed to 1492 * get boot configuration 1493 */ 1494 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1495 if (ret) 1496 dev_warn(adev->dev, "PSP set boot config failed\n"); 1497 else 1498 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1499 } 1500 } 1501 } 1502 1503 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1504 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1505 1506 if (!psp->ras_context.context.initialized) { 1507 ret = psp_ras_init_shared_buf(psp); 1508 if (ret) 1509 return ret; 1510 } 1511 1512 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1513 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1514 1515 if (amdgpu_ras_is_poison_mode_supported(adev)) 1516 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1517 if (!adev->gmc.xgmi.connected_to_cpu) 1518 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1519 1520 ret = psp_ras_load(psp); 1521 1522 if (!ret && !ras_cmd->ras_status) 1523 psp->ras_context.context.initialized = true; 1524 else { 1525 if (ras_cmd->ras_status) 1526 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1527 amdgpu_ras_fini(psp->adev); 1528 } 1529 1530 return ret; 1531 } 1532 1533 int psp_ras_trigger_error(struct psp_context *psp, 1534 struct ta_ras_trigger_error_input *info) 1535 { 1536 struct ta_ras_shared_memory *ras_cmd; 1537 int ret; 1538 1539 if (!psp->ras_context.context.initialized) 1540 return -EINVAL; 1541 1542 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1543 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1544 1545 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1546 ras_cmd->ras_in_message.trigger_error = *info; 1547 1548 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1549 if (ret) 1550 return -EINVAL; 1551 1552 /* If err_event_athub occurs error inject was successful, however 1553 return status from TA is no long reliable */ 1554 if (amdgpu_ras_intr_triggered()) 1555 return 0; 1556 1557 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1558 return -EACCES; 1559 else if (ras_cmd->ras_status) 1560 return -EINVAL; 1561 1562 return 0; 1563 } 1564 // ras end 1565 1566 // HDCP start 1567 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1568 { 1569 return psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1570 } 1571 1572 static int psp_hdcp_load(struct psp_context *psp) 1573 { 1574 return psp_ta_load(psp, &psp->hdcp_context.context); 1575 } 1576 1577 static int psp_hdcp_initialize(struct psp_context *psp) 1578 { 1579 int ret; 1580 1581 /* 1582 * TODO: bypass the initialize in sriov for now 1583 */ 1584 if (amdgpu_sriov_vf(psp->adev)) 1585 return 0; 1586 1587 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1588 !psp->hdcp_context.context.bin_desc.start_addr) { 1589 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1590 return 0; 1591 } 1592 1593 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1594 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1595 1596 if (!psp->hdcp_context.context.initialized) { 1597 ret = psp_hdcp_init_shared_buf(psp); 1598 if (ret) 1599 return ret; 1600 } 1601 1602 ret = psp_hdcp_load(psp); 1603 if (!ret) { 1604 psp->hdcp_context.context.initialized = true; 1605 mutex_init(&psp->hdcp_context.mutex); 1606 } 1607 1608 return ret; 1609 } 1610 1611 static int psp_hdcp_unload(struct psp_context *psp) 1612 { 1613 return psp_ta_unload(psp, &psp->hdcp_context.context); 1614 } 1615 1616 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1617 { 1618 /* 1619 * TODO: bypass the loading in sriov for now 1620 */ 1621 if (amdgpu_sriov_vf(psp->adev)) 1622 return 0; 1623 1624 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1625 } 1626 1627 static int psp_hdcp_terminate(struct psp_context *psp) 1628 { 1629 int ret; 1630 1631 /* 1632 * TODO: bypass the terminate in sriov for now 1633 */ 1634 if (amdgpu_sriov_vf(psp->adev)) 1635 return 0; 1636 1637 if (!psp->hdcp_context.context.initialized) { 1638 if (psp->hdcp_context.context.mem_context.shared_buf) 1639 goto out; 1640 else 1641 return 0; 1642 } 1643 1644 ret = psp_hdcp_unload(psp); 1645 if (ret) 1646 return ret; 1647 1648 psp->hdcp_context.context.initialized = false; 1649 1650 out: 1651 /* free hdcp shared memory */ 1652 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 1653 1654 return 0; 1655 } 1656 // HDCP end 1657 1658 // DTM start 1659 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1660 { 1661 return psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1662 } 1663 1664 static int psp_dtm_load(struct psp_context *psp) 1665 { 1666 return psp_ta_load(psp, &psp->dtm_context.context); 1667 } 1668 1669 static int psp_dtm_initialize(struct psp_context *psp) 1670 { 1671 int ret; 1672 1673 /* 1674 * TODO: bypass the initialize in sriov for now 1675 */ 1676 if (amdgpu_sriov_vf(psp->adev)) 1677 return 0; 1678 1679 if (!psp->dtm_context.context.bin_desc.size_bytes || 1680 !psp->dtm_context.context.bin_desc.start_addr) { 1681 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1682 return 0; 1683 } 1684 1685 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1686 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1687 1688 if (!psp->dtm_context.context.initialized) { 1689 ret = psp_dtm_init_shared_buf(psp); 1690 if (ret) 1691 return ret; 1692 } 1693 1694 ret = psp_dtm_load(psp); 1695 if (!ret) { 1696 psp->dtm_context.context.initialized = true; 1697 mutex_init(&psp->dtm_context.mutex); 1698 } 1699 1700 return ret; 1701 } 1702 1703 static int psp_dtm_unload(struct psp_context *psp) 1704 { 1705 return psp_ta_unload(psp, &psp->dtm_context.context); 1706 } 1707 1708 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1709 { 1710 /* 1711 * TODO: bypass the loading in sriov for now 1712 */ 1713 if (amdgpu_sriov_vf(psp->adev)) 1714 return 0; 1715 1716 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1717 } 1718 1719 static int psp_dtm_terminate(struct psp_context *psp) 1720 { 1721 int ret; 1722 1723 /* 1724 * TODO: bypass the terminate in sriov for now 1725 */ 1726 if (amdgpu_sriov_vf(psp->adev)) 1727 return 0; 1728 1729 if (!psp->dtm_context.context.initialized) { 1730 if (psp->dtm_context.context.mem_context.shared_buf) 1731 goto out; 1732 else 1733 return 0; 1734 } 1735 1736 ret = psp_dtm_unload(psp); 1737 if (ret) 1738 return ret; 1739 1740 psp->dtm_context.context.initialized = false; 1741 1742 out: 1743 /* free dtm shared memory */ 1744 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 1745 1746 return 0; 1747 } 1748 // DTM end 1749 1750 // RAP start 1751 static int psp_rap_init_shared_buf(struct psp_context *psp) 1752 { 1753 return psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1754 } 1755 1756 static int psp_rap_load(struct psp_context *psp) 1757 { 1758 return psp_ta_load(psp, &psp->rap_context.context); 1759 } 1760 1761 static int psp_rap_unload(struct psp_context *psp) 1762 { 1763 return psp_ta_unload(psp, &psp->rap_context.context); 1764 } 1765 1766 static int psp_rap_initialize(struct psp_context *psp) 1767 { 1768 int ret; 1769 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1770 1771 /* 1772 * TODO: bypass the initialize in sriov for now 1773 */ 1774 if (amdgpu_sriov_vf(psp->adev)) 1775 return 0; 1776 1777 if (!psp->rap_context.context.bin_desc.size_bytes || 1778 !psp->rap_context.context.bin_desc.start_addr) { 1779 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1780 return 0; 1781 } 1782 1783 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1784 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1785 1786 if (!psp->rap_context.context.initialized) { 1787 ret = psp_rap_init_shared_buf(psp); 1788 if (ret) 1789 return ret; 1790 } 1791 1792 ret = psp_rap_load(psp); 1793 if (!ret) { 1794 psp->rap_context.context.initialized = true; 1795 mutex_init(&psp->rap_context.mutex); 1796 } else 1797 return ret; 1798 1799 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1800 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1801 psp_rap_terminate(psp); 1802 1803 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1804 ret, status); 1805 1806 return ret; 1807 } 1808 1809 return 0; 1810 } 1811 1812 static int psp_rap_terminate(struct psp_context *psp) 1813 { 1814 int ret; 1815 1816 if (!psp->rap_context.context.initialized) 1817 return 0; 1818 1819 ret = psp_rap_unload(psp); 1820 1821 psp->rap_context.context.initialized = false; 1822 1823 /* free rap shared memory */ 1824 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1825 1826 return ret; 1827 } 1828 1829 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1830 { 1831 struct ta_rap_shared_memory *rap_cmd; 1832 int ret = 0; 1833 1834 if (!psp->rap_context.context.initialized) 1835 return 0; 1836 1837 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1838 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1839 return -EINVAL; 1840 1841 mutex_lock(&psp->rap_context.mutex); 1842 1843 rap_cmd = (struct ta_rap_shared_memory *) 1844 psp->rap_context.context.mem_context.shared_buf; 1845 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1846 1847 rap_cmd->cmd_id = ta_cmd_id; 1848 rap_cmd->validation_method_id = METHOD_A; 1849 1850 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1851 if (ret) 1852 goto out_unlock; 1853 1854 if (status) 1855 *status = rap_cmd->rap_status; 1856 1857 out_unlock: 1858 mutex_unlock(&psp->rap_context.mutex); 1859 1860 return ret; 1861 } 1862 // RAP end 1863 1864 /* securedisplay start */ 1865 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1866 { 1867 return psp_ta_init_shared_buf( 1868 psp, &psp->securedisplay_context.context.mem_context); 1869 } 1870 1871 static int psp_securedisplay_load(struct psp_context *psp) 1872 { 1873 return psp_ta_load(psp, &psp->securedisplay_context.context); 1874 } 1875 1876 static int psp_securedisplay_unload(struct psp_context *psp) 1877 { 1878 return psp_ta_unload(psp, &psp->securedisplay_context.context); 1879 } 1880 1881 static int psp_securedisplay_initialize(struct psp_context *psp) 1882 { 1883 int ret; 1884 struct securedisplay_cmd *securedisplay_cmd; 1885 1886 /* 1887 * TODO: bypass the initialize in sriov for now 1888 */ 1889 if (amdgpu_sriov_vf(psp->adev)) 1890 return 0; 1891 1892 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1893 !psp->securedisplay_context.context.bin_desc.start_addr) { 1894 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1895 return 0; 1896 } 1897 1898 psp->securedisplay_context.context.mem_context.shared_mem_size = 1899 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1900 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1901 1902 if (!psp->securedisplay_context.context.initialized) { 1903 ret = psp_securedisplay_init_shared_buf(psp); 1904 if (ret) 1905 return ret; 1906 } 1907 1908 ret = psp_securedisplay_load(psp); 1909 if (!ret) { 1910 psp->securedisplay_context.context.initialized = true; 1911 mutex_init(&psp->securedisplay_context.mutex); 1912 } else 1913 return ret; 1914 1915 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1916 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1917 1918 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1919 if (ret) { 1920 psp_securedisplay_terminate(psp); 1921 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1922 return -EINVAL; 1923 } 1924 1925 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1926 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1927 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1928 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1929 } 1930 1931 return 0; 1932 } 1933 1934 static int psp_securedisplay_terminate(struct psp_context *psp) 1935 { 1936 int ret; 1937 1938 /* 1939 * TODO:bypass the terminate in sriov for now 1940 */ 1941 if (amdgpu_sriov_vf(psp->adev)) 1942 return 0; 1943 1944 if (!psp->securedisplay_context.context.initialized) 1945 return 0; 1946 1947 ret = psp_securedisplay_unload(psp); 1948 if (ret) 1949 return ret; 1950 1951 psp->securedisplay_context.context.initialized = false; 1952 1953 /* free securedisplay shared memory */ 1954 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1955 1956 return ret; 1957 } 1958 1959 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1960 { 1961 int ret; 1962 1963 if (!psp->securedisplay_context.context.initialized) 1964 return -EINVAL; 1965 1966 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1967 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1968 return -EINVAL; 1969 1970 mutex_lock(&psp->securedisplay_context.mutex); 1971 1972 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1973 1974 mutex_unlock(&psp->securedisplay_context.mutex); 1975 1976 return ret; 1977 } 1978 /* SECUREDISPLAY end */ 1979 1980 static int psp_hw_start(struct psp_context *psp) 1981 { 1982 struct amdgpu_device *adev = psp->adev; 1983 int ret; 1984 1985 if (!amdgpu_sriov_vf(adev)) { 1986 if ((is_psp_fw_valid(psp->kdb)) && 1987 (psp->funcs->bootloader_load_kdb != NULL)) { 1988 ret = psp_bootloader_load_kdb(psp); 1989 if (ret) { 1990 DRM_ERROR("PSP load kdb failed!\n"); 1991 return ret; 1992 } 1993 } 1994 1995 if ((is_psp_fw_valid(psp->spl)) && 1996 (psp->funcs->bootloader_load_spl != NULL)) { 1997 ret = psp_bootloader_load_spl(psp); 1998 if (ret) { 1999 DRM_ERROR("PSP load spl failed!\n"); 2000 return ret; 2001 } 2002 } 2003 2004 if ((is_psp_fw_valid(psp->sys)) && 2005 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2006 ret = psp_bootloader_load_sysdrv(psp); 2007 if (ret) { 2008 DRM_ERROR("PSP load sys drv failed!\n"); 2009 return ret; 2010 } 2011 } 2012 2013 if ((is_psp_fw_valid(psp->soc_drv)) && 2014 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2015 ret = psp_bootloader_load_soc_drv(psp); 2016 if (ret) { 2017 DRM_ERROR("PSP load soc drv failed!\n"); 2018 return ret; 2019 } 2020 } 2021 2022 if ((is_psp_fw_valid(psp->intf_drv)) && 2023 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2024 ret = psp_bootloader_load_intf_drv(psp); 2025 if (ret) { 2026 DRM_ERROR("PSP load intf drv failed!\n"); 2027 return ret; 2028 } 2029 } 2030 2031 if ((is_psp_fw_valid(psp->dbg_drv)) && 2032 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2033 ret = psp_bootloader_load_dbg_drv(psp); 2034 if (ret) { 2035 DRM_ERROR("PSP load dbg drv failed!\n"); 2036 return ret; 2037 } 2038 } 2039 2040 if ((is_psp_fw_valid(psp->sos)) && 2041 (psp->funcs->bootloader_load_sos != NULL)) { 2042 ret = psp_bootloader_load_sos(psp); 2043 if (ret) { 2044 DRM_ERROR("PSP load sos failed!\n"); 2045 return ret; 2046 } 2047 } 2048 } 2049 2050 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2051 if (ret) { 2052 DRM_ERROR("PSP create ring failed!\n"); 2053 return ret; 2054 } 2055 2056 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2057 goto skip_pin_bo; 2058 2059 ret = psp_tmr_init(psp); 2060 if (ret) { 2061 DRM_ERROR("PSP tmr init failed!\n"); 2062 return ret; 2063 } 2064 2065 skip_pin_bo: 2066 /* 2067 * For ASICs with DF Cstate management centralized 2068 * to PMFW, TMR setup should be performed after PMFW 2069 * loaded and before other non-psp firmware loaded. 2070 */ 2071 if (psp->pmfw_centralized_cstate_management) { 2072 ret = psp_load_smu_fw(psp); 2073 if (ret) 2074 return ret; 2075 } 2076 2077 ret = psp_tmr_load(psp); 2078 if (ret) { 2079 DRM_ERROR("PSP load tmr failed!\n"); 2080 return ret; 2081 } 2082 2083 return 0; 2084 } 2085 2086 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2087 enum psp_gfx_fw_type *type) 2088 { 2089 switch (ucode->ucode_id) { 2090 case AMDGPU_UCODE_ID_CAP: 2091 *type = GFX_FW_TYPE_CAP; 2092 break; 2093 case AMDGPU_UCODE_ID_SDMA0: 2094 *type = GFX_FW_TYPE_SDMA0; 2095 break; 2096 case AMDGPU_UCODE_ID_SDMA1: 2097 *type = GFX_FW_TYPE_SDMA1; 2098 break; 2099 case AMDGPU_UCODE_ID_SDMA2: 2100 *type = GFX_FW_TYPE_SDMA2; 2101 break; 2102 case AMDGPU_UCODE_ID_SDMA3: 2103 *type = GFX_FW_TYPE_SDMA3; 2104 break; 2105 case AMDGPU_UCODE_ID_SDMA4: 2106 *type = GFX_FW_TYPE_SDMA4; 2107 break; 2108 case AMDGPU_UCODE_ID_SDMA5: 2109 *type = GFX_FW_TYPE_SDMA5; 2110 break; 2111 case AMDGPU_UCODE_ID_SDMA6: 2112 *type = GFX_FW_TYPE_SDMA6; 2113 break; 2114 case AMDGPU_UCODE_ID_SDMA7: 2115 *type = GFX_FW_TYPE_SDMA7; 2116 break; 2117 case AMDGPU_UCODE_ID_CP_MES: 2118 *type = GFX_FW_TYPE_CP_MES; 2119 break; 2120 case AMDGPU_UCODE_ID_CP_MES_DATA: 2121 *type = GFX_FW_TYPE_MES_STACK; 2122 break; 2123 case AMDGPU_UCODE_ID_CP_CE: 2124 *type = GFX_FW_TYPE_CP_CE; 2125 break; 2126 case AMDGPU_UCODE_ID_CP_PFP: 2127 *type = GFX_FW_TYPE_CP_PFP; 2128 break; 2129 case AMDGPU_UCODE_ID_CP_ME: 2130 *type = GFX_FW_TYPE_CP_ME; 2131 break; 2132 case AMDGPU_UCODE_ID_CP_MEC1: 2133 *type = GFX_FW_TYPE_CP_MEC; 2134 break; 2135 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2136 *type = GFX_FW_TYPE_CP_MEC_ME1; 2137 break; 2138 case AMDGPU_UCODE_ID_CP_MEC2: 2139 *type = GFX_FW_TYPE_CP_MEC; 2140 break; 2141 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2142 *type = GFX_FW_TYPE_CP_MEC_ME2; 2143 break; 2144 case AMDGPU_UCODE_ID_RLC_G: 2145 *type = GFX_FW_TYPE_RLC_G; 2146 break; 2147 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2148 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2149 break; 2150 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2151 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2152 break; 2153 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2154 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2155 break; 2156 case AMDGPU_UCODE_ID_RLC_IRAM: 2157 *type = GFX_FW_TYPE_RLC_IRAM; 2158 break; 2159 case AMDGPU_UCODE_ID_RLC_DRAM: 2160 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2161 break; 2162 case AMDGPU_UCODE_ID_SMC: 2163 *type = GFX_FW_TYPE_SMU; 2164 break; 2165 case AMDGPU_UCODE_ID_UVD: 2166 *type = GFX_FW_TYPE_UVD; 2167 break; 2168 case AMDGPU_UCODE_ID_UVD1: 2169 *type = GFX_FW_TYPE_UVD1; 2170 break; 2171 case AMDGPU_UCODE_ID_VCE: 2172 *type = GFX_FW_TYPE_VCE; 2173 break; 2174 case AMDGPU_UCODE_ID_VCN: 2175 *type = GFX_FW_TYPE_VCN; 2176 break; 2177 case AMDGPU_UCODE_ID_VCN1: 2178 *type = GFX_FW_TYPE_VCN1; 2179 break; 2180 case AMDGPU_UCODE_ID_DMCU_ERAM: 2181 *type = GFX_FW_TYPE_DMCU_ERAM; 2182 break; 2183 case AMDGPU_UCODE_ID_DMCU_INTV: 2184 *type = GFX_FW_TYPE_DMCU_ISR; 2185 break; 2186 case AMDGPU_UCODE_ID_VCN0_RAM: 2187 *type = GFX_FW_TYPE_VCN0_RAM; 2188 break; 2189 case AMDGPU_UCODE_ID_VCN1_RAM: 2190 *type = GFX_FW_TYPE_VCN1_RAM; 2191 break; 2192 case AMDGPU_UCODE_ID_DMCUB: 2193 *type = GFX_FW_TYPE_DMUB; 2194 break; 2195 case AMDGPU_UCODE_ID_MAXIMUM: 2196 default: 2197 return -EINVAL; 2198 } 2199 2200 return 0; 2201 } 2202 2203 static void psp_print_fw_hdr(struct psp_context *psp, 2204 struct amdgpu_firmware_info *ucode) 2205 { 2206 struct amdgpu_device *adev = psp->adev; 2207 struct common_firmware_header *hdr; 2208 2209 switch (ucode->ucode_id) { 2210 case AMDGPU_UCODE_ID_SDMA0: 2211 case AMDGPU_UCODE_ID_SDMA1: 2212 case AMDGPU_UCODE_ID_SDMA2: 2213 case AMDGPU_UCODE_ID_SDMA3: 2214 case AMDGPU_UCODE_ID_SDMA4: 2215 case AMDGPU_UCODE_ID_SDMA5: 2216 case AMDGPU_UCODE_ID_SDMA6: 2217 case AMDGPU_UCODE_ID_SDMA7: 2218 hdr = (struct common_firmware_header *) 2219 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2220 amdgpu_ucode_print_sdma_hdr(hdr); 2221 break; 2222 case AMDGPU_UCODE_ID_CP_CE: 2223 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2224 amdgpu_ucode_print_gfx_hdr(hdr); 2225 break; 2226 case AMDGPU_UCODE_ID_CP_PFP: 2227 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2228 amdgpu_ucode_print_gfx_hdr(hdr); 2229 break; 2230 case AMDGPU_UCODE_ID_CP_ME: 2231 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2232 amdgpu_ucode_print_gfx_hdr(hdr); 2233 break; 2234 case AMDGPU_UCODE_ID_CP_MEC1: 2235 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2236 amdgpu_ucode_print_gfx_hdr(hdr); 2237 break; 2238 case AMDGPU_UCODE_ID_RLC_G: 2239 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2240 amdgpu_ucode_print_rlc_hdr(hdr); 2241 break; 2242 case AMDGPU_UCODE_ID_SMC: 2243 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2244 amdgpu_ucode_print_smc_hdr(hdr); 2245 break; 2246 default: 2247 break; 2248 } 2249 } 2250 2251 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2252 struct psp_gfx_cmd_resp *cmd) 2253 { 2254 int ret; 2255 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2256 2257 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2258 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2259 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2260 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2261 2262 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2263 if (ret) 2264 DRM_ERROR("Unknown firmware type\n"); 2265 2266 return ret; 2267 } 2268 2269 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2270 struct amdgpu_firmware_info *ucode) 2271 { 2272 int ret = 0; 2273 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2274 2275 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2276 if (!ret) { 2277 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2278 psp->fence_buf_mc_addr); 2279 } 2280 2281 release_psp_cmd_buf(psp); 2282 2283 return ret; 2284 } 2285 2286 static int psp_load_smu_fw(struct psp_context *psp) 2287 { 2288 int ret; 2289 struct amdgpu_device *adev = psp->adev; 2290 struct amdgpu_firmware_info *ucode = 2291 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2292 struct amdgpu_ras *ras = psp->ras_context.ras; 2293 2294 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2295 return 0; 2296 2297 if ((amdgpu_in_reset(adev) && 2298 ras && adev->ras_enabled && 2299 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2300 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2301 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2302 if (ret) { 2303 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2304 } 2305 } 2306 2307 ret = psp_execute_non_psp_fw_load(psp, ucode); 2308 2309 if (ret) 2310 DRM_ERROR("PSP load smu failed!\n"); 2311 2312 return ret; 2313 } 2314 2315 static bool fw_load_skip_check(struct psp_context *psp, 2316 struct amdgpu_firmware_info *ucode) 2317 { 2318 if (!ucode->fw) 2319 return true; 2320 2321 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2322 (psp_smu_reload_quirk(psp) || 2323 psp->autoload_supported || 2324 psp->pmfw_centralized_cstate_management)) 2325 return true; 2326 2327 if (amdgpu_sriov_vf(psp->adev) && 2328 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2329 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2330 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2331 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2332 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2333 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2334 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2335 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2336 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2337 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2338 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2339 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2340 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2341 /*skip ucode loading in SRIOV VF */ 2342 return true; 2343 2344 if (psp->autoload_supported && 2345 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2346 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2347 /* skip mec JT when autoload is enabled */ 2348 return true; 2349 2350 return false; 2351 } 2352 2353 int psp_load_fw_list(struct psp_context *psp, 2354 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2355 { 2356 int ret = 0, i; 2357 struct amdgpu_firmware_info *ucode; 2358 2359 for (i = 0; i < ucode_count; ++i) { 2360 ucode = ucode_list[i]; 2361 psp_print_fw_hdr(psp, ucode); 2362 ret = psp_execute_non_psp_fw_load(psp, ucode); 2363 if (ret) 2364 return ret; 2365 } 2366 return ret; 2367 } 2368 2369 static int psp_load_non_psp_fw(struct psp_context *psp) 2370 { 2371 int i, ret; 2372 struct amdgpu_firmware_info *ucode; 2373 struct amdgpu_device *adev = psp->adev; 2374 2375 if (psp->autoload_supported && 2376 !psp->pmfw_centralized_cstate_management) { 2377 ret = psp_load_smu_fw(psp); 2378 if (ret) 2379 return ret; 2380 } 2381 2382 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2383 ucode = &adev->firmware.ucode[i]; 2384 2385 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2386 !fw_load_skip_check(psp, ucode)) { 2387 ret = psp_load_smu_fw(psp); 2388 if (ret) 2389 return ret; 2390 continue; 2391 } 2392 2393 if (fw_load_skip_check(psp, ucode)) 2394 continue; 2395 2396 if (psp->autoload_supported && 2397 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2398 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2399 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2400 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2401 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2402 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2403 /* PSP only receive one SDMA fw for sienna_cichlid, 2404 * as all four sdma fw are same */ 2405 continue; 2406 2407 psp_print_fw_hdr(psp, ucode); 2408 2409 ret = psp_execute_non_psp_fw_load(psp, ucode); 2410 if (ret) 2411 return ret; 2412 2413 /* Start rlc autoload after psp recieved all the gfx firmware */ 2414 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2415 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2416 ret = psp_rlc_autoload_start(psp); 2417 if (ret) { 2418 DRM_ERROR("Failed to start rlc autoload\n"); 2419 return ret; 2420 } 2421 } 2422 } 2423 2424 return 0; 2425 } 2426 2427 static int psp_load_fw(struct amdgpu_device *adev) 2428 { 2429 int ret; 2430 struct psp_context *psp = &adev->psp; 2431 2432 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2433 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2434 goto skip_memalloc; 2435 } 2436 2437 if (amdgpu_sriov_vf(adev)) { 2438 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2439 AMDGPU_GEM_DOMAIN_VRAM, 2440 &psp->fw_pri_bo, 2441 &psp->fw_pri_mc_addr, 2442 &psp->fw_pri_buf); 2443 } else { 2444 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2445 AMDGPU_GEM_DOMAIN_GTT, 2446 &psp->fw_pri_bo, 2447 &psp->fw_pri_mc_addr, 2448 &psp->fw_pri_buf); 2449 } 2450 2451 if (ret) 2452 goto failed; 2453 2454 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2455 AMDGPU_GEM_DOMAIN_VRAM, 2456 &psp->fence_buf_bo, 2457 &psp->fence_buf_mc_addr, 2458 &psp->fence_buf); 2459 if (ret) 2460 goto failed; 2461 2462 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2463 AMDGPU_GEM_DOMAIN_VRAM, 2464 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2465 (void **)&psp->cmd_buf_mem); 2466 if (ret) 2467 goto failed; 2468 2469 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2470 2471 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2472 if (ret) { 2473 DRM_ERROR("PSP ring init failed!\n"); 2474 goto failed; 2475 } 2476 2477 skip_memalloc: 2478 ret = psp_hw_start(psp); 2479 if (ret) 2480 goto failed; 2481 2482 ret = psp_load_non_psp_fw(psp); 2483 if (ret) 2484 goto failed; 2485 2486 ret = psp_asd_initialize(psp); 2487 if (ret) { 2488 DRM_ERROR("PSP load asd failed!\n"); 2489 return ret; 2490 } 2491 2492 ret = psp_rl_load(adev); 2493 if (ret) { 2494 DRM_ERROR("PSP load RL failed!\n"); 2495 return ret; 2496 } 2497 2498 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2499 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2500 ret = psp_xgmi_initialize(psp, false, true); 2501 /* Warning the XGMI seesion initialize failure 2502 * Instead of stop driver initialization 2503 */ 2504 if (ret) 2505 dev_err(psp->adev->dev, 2506 "XGMI: Failed to initialize XGMI session\n"); 2507 } 2508 } 2509 2510 if (psp->ta_fw) { 2511 ret = psp_ras_initialize(psp); 2512 if (ret) 2513 dev_err(psp->adev->dev, 2514 "RAS: Failed to initialize RAS\n"); 2515 2516 ret = psp_hdcp_initialize(psp); 2517 if (ret) 2518 dev_err(psp->adev->dev, 2519 "HDCP: Failed to initialize HDCP\n"); 2520 2521 ret = psp_dtm_initialize(psp); 2522 if (ret) 2523 dev_err(psp->adev->dev, 2524 "DTM: Failed to initialize DTM\n"); 2525 2526 ret = psp_rap_initialize(psp); 2527 if (ret) 2528 dev_err(psp->adev->dev, 2529 "RAP: Failed to initialize RAP\n"); 2530 2531 ret = psp_securedisplay_initialize(psp); 2532 if (ret) 2533 dev_err(psp->adev->dev, 2534 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2535 } 2536 2537 return 0; 2538 2539 failed: 2540 /* 2541 * all cleanup jobs (xgmi terminate, ras terminate, 2542 * ring destroy, cmd/fence/fw buffers destory, 2543 * psp->cmd destory) are delayed to psp_hw_fini 2544 */ 2545 return ret; 2546 } 2547 2548 static int psp_hw_init(void *handle) 2549 { 2550 int ret; 2551 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2552 2553 mutex_lock(&adev->firmware.mutex); 2554 /* 2555 * This sequence is just used on hw_init only once, no need on 2556 * resume. 2557 */ 2558 ret = amdgpu_ucode_init_bo(adev); 2559 if (ret) 2560 goto failed; 2561 2562 ret = psp_load_fw(adev); 2563 if (ret) { 2564 DRM_ERROR("PSP firmware loading failed\n"); 2565 goto failed; 2566 } 2567 2568 mutex_unlock(&adev->firmware.mutex); 2569 return 0; 2570 2571 failed: 2572 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2573 mutex_unlock(&adev->firmware.mutex); 2574 return -EINVAL; 2575 } 2576 2577 static int psp_hw_fini(void *handle) 2578 { 2579 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2580 struct psp_context *psp = &adev->psp; 2581 2582 if (psp->ta_fw) { 2583 psp_ras_terminate(psp); 2584 psp_securedisplay_terminate(psp); 2585 psp_rap_terminate(psp); 2586 psp_dtm_terminate(psp); 2587 psp_hdcp_terminate(psp); 2588 } 2589 2590 psp_asd_terminate(psp); 2591 2592 psp_tmr_terminate(psp); 2593 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2594 2595 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2596 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2597 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2598 &psp->fence_buf_mc_addr, &psp->fence_buf); 2599 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2600 (void **)&psp->cmd_buf_mem); 2601 2602 return 0; 2603 } 2604 2605 static int psp_suspend(void *handle) 2606 { 2607 int ret; 2608 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2609 struct psp_context *psp = &adev->psp; 2610 2611 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2612 psp->xgmi_context.context.initialized) { 2613 ret = psp_xgmi_terminate(psp); 2614 if (ret) { 2615 DRM_ERROR("Failed to terminate xgmi ta\n"); 2616 return ret; 2617 } 2618 } 2619 2620 if (psp->ta_fw) { 2621 ret = psp_ras_terminate(psp); 2622 if (ret) { 2623 DRM_ERROR("Failed to terminate ras ta\n"); 2624 return ret; 2625 } 2626 ret = psp_hdcp_terminate(psp); 2627 if (ret) { 2628 DRM_ERROR("Failed to terminate hdcp ta\n"); 2629 return ret; 2630 } 2631 ret = psp_dtm_terminate(psp); 2632 if (ret) { 2633 DRM_ERROR("Failed to terminate dtm ta\n"); 2634 return ret; 2635 } 2636 ret = psp_rap_terminate(psp); 2637 if (ret) { 2638 DRM_ERROR("Failed to terminate rap ta\n"); 2639 return ret; 2640 } 2641 ret = psp_securedisplay_terminate(psp); 2642 if (ret) { 2643 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2644 return ret; 2645 } 2646 } 2647 2648 ret = psp_asd_terminate(psp); 2649 if (ret) { 2650 DRM_ERROR("Failed to terminate asd\n"); 2651 return ret; 2652 } 2653 2654 ret = psp_tmr_terminate(psp); 2655 if (ret) { 2656 DRM_ERROR("Failed to terminate tmr\n"); 2657 return ret; 2658 } 2659 2660 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2661 if (ret) { 2662 DRM_ERROR("PSP ring stop failed\n"); 2663 return ret; 2664 } 2665 2666 return 0; 2667 } 2668 2669 static int psp_resume(void *handle) 2670 { 2671 int ret; 2672 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2673 struct psp_context *psp = &adev->psp; 2674 2675 DRM_INFO("PSP is resuming...\n"); 2676 2677 if (psp->mem_train_ctx.enable_mem_training) { 2678 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2679 if (ret) { 2680 DRM_ERROR("Failed to process memory training!\n"); 2681 return ret; 2682 } 2683 } 2684 2685 mutex_lock(&adev->firmware.mutex); 2686 2687 ret = psp_hw_start(psp); 2688 if (ret) 2689 goto failed; 2690 2691 ret = psp_load_non_psp_fw(psp); 2692 if (ret) 2693 goto failed; 2694 2695 ret = psp_asd_initialize(psp); 2696 if (ret) { 2697 DRM_ERROR("PSP load asd failed!\n"); 2698 goto failed; 2699 } 2700 2701 ret = psp_rl_load(adev); 2702 if (ret) { 2703 dev_err(adev->dev, "PSP load RL failed!\n"); 2704 goto failed; 2705 } 2706 2707 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2708 ret = psp_xgmi_initialize(psp, false, true); 2709 /* Warning the XGMI seesion initialize failure 2710 * Instead of stop driver initialization 2711 */ 2712 if (ret) 2713 dev_err(psp->adev->dev, 2714 "XGMI: Failed to initialize XGMI session\n"); 2715 } 2716 2717 if (psp->ta_fw) { 2718 ret = psp_ras_initialize(psp); 2719 if (ret) 2720 dev_err(psp->adev->dev, 2721 "RAS: Failed to initialize RAS\n"); 2722 2723 ret = psp_hdcp_initialize(psp); 2724 if (ret) 2725 dev_err(psp->adev->dev, 2726 "HDCP: Failed to initialize HDCP\n"); 2727 2728 ret = psp_dtm_initialize(psp); 2729 if (ret) 2730 dev_err(psp->adev->dev, 2731 "DTM: Failed to initialize DTM\n"); 2732 2733 ret = psp_rap_initialize(psp); 2734 if (ret) 2735 dev_err(psp->adev->dev, 2736 "RAP: Failed to initialize RAP\n"); 2737 2738 ret = psp_securedisplay_initialize(psp); 2739 if (ret) 2740 dev_err(psp->adev->dev, 2741 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2742 } 2743 2744 mutex_unlock(&adev->firmware.mutex); 2745 2746 return 0; 2747 2748 failed: 2749 DRM_ERROR("PSP resume failed\n"); 2750 mutex_unlock(&adev->firmware.mutex); 2751 return ret; 2752 } 2753 2754 int psp_gpu_reset(struct amdgpu_device *adev) 2755 { 2756 int ret; 2757 2758 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2759 return 0; 2760 2761 mutex_lock(&adev->psp.mutex); 2762 ret = psp_mode1_reset(&adev->psp); 2763 mutex_unlock(&adev->psp.mutex); 2764 2765 return ret; 2766 } 2767 2768 int psp_rlc_autoload_start(struct psp_context *psp) 2769 { 2770 int ret; 2771 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2772 2773 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2774 2775 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2776 psp->fence_buf_mc_addr); 2777 2778 release_psp_cmd_buf(psp); 2779 2780 return ret; 2781 } 2782 2783 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2784 uint64_t cmd_gpu_addr, int cmd_size) 2785 { 2786 struct amdgpu_firmware_info ucode = {0}; 2787 2788 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2789 AMDGPU_UCODE_ID_VCN0_RAM; 2790 ucode.mc_addr = cmd_gpu_addr; 2791 ucode.ucode_size = cmd_size; 2792 2793 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2794 } 2795 2796 int psp_ring_cmd_submit(struct psp_context *psp, 2797 uint64_t cmd_buf_mc_addr, 2798 uint64_t fence_mc_addr, 2799 int index) 2800 { 2801 unsigned int psp_write_ptr_reg = 0; 2802 struct psp_gfx_rb_frame *write_frame; 2803 struct psp_ring *ring = &psp->km_ring; 2804 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2805 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2806 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2807 struct amdgpu_device *adev = psp->adev; 2808 uint32_t ring_size_dw = ring->ring_size / 4; 2809 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2810 2811 /* KM (GPCOM) prepare write pointer */ 2812 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2813 2814 /* Update KM RB frame pointer to new frame */ 2815 /* write_frame ptr increments by size of rb_frame in bytes */ 2816 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2817 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2818 write_frame = ring_buffer_start; 2819 else 2820 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2821 /* Check invalid write_frame ptr address */ 2822 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2823 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2824 ring_buffer_start, ring_buffer_end, write_frame); 2825 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2826 return -EINVAL; 2827 } 2828 2829 /* Initialize KM RB frame */ 2830 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2831 2832 /* Update KM RB frame */ 2833 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2834 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2835 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2836 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2837 write_frame->fence_value = index; 2838 amdgpu_device_flush_hdp(adev, NULL); 2839 2840 /* Update the write Pointer in DWORDs */ 2841 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2842 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2843 return 0; 2844 } 2845 2846 int psp_init_asd_microcode(struct psp_context *psp, 2847 const char *chip_name) 2848 { 2849 struct amdgpu_device *adev = psp->adev; 2850 char fw_name[PSP_FW_NAME_LEN]; 2851 const struct psp_firmware_header_v1_0 *asd_hdr; 2852 int err = 0; 2853 2854 if (!chip_name) { 2855 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2856 return -EINVAL; 2857 } 2858 2859 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2860 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2861 if (err) 2862 goto out; 2863 2864 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2865 if (err) 2866 goto out; 2867 2868 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2869 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2870 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2871 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2872 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2873 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2874 return 0; 2875 out: 2876 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2877 release_firmware(adev->psp.asd_fw); 2878 adev->psp.asd_fw = NULL; 2879 return err; 2880 } 2881 2882 int psp_init_toc_microcode(struct psp_context *psp, 2883 const char *chip_name) 2884 { 2885 struct amdgpu_device *adev = psp->adev; 2886 char fw_name[PSP_FW_NAME_LEN]; 2887 const struct psp_firmware_header_v1_0 *toc_hdr; 2888 int err = 0; 2889 2890 if (!chip_name) { 2891 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2892 return -EINVAL; 2893 } 2894 2895 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2896 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2897 if (err) 2898 goto out; 2899 2900 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2901 if (err) 2902 goto out; 2903 2904 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2905 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2906 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2907 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2908 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2909 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2910 return 0; 2911 out: 2912 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2913 release_firmware(adev->psp.toc_fw); 2914 adev->psp.toc_fw = NULL; 2915 return err; 2916 } 2917 2918 static int parse_sos_bin_descriptor(struct psp_context *psp, 2919 const struct psp_fw_bin_desc *desc, 2920 const struct psp_firmware_header_v2_0 *sos_hdr) 2921 { 2922 uint8_t *ucode_start_addr = NULL; 2923 2924 if (!psp || !desc || !sos_hdr) 2925 return -EINVAL; 2926 2927 ucode_start_addr = (uint8_t *)sos_hdr + 2928 le32_to_cpu(desc->offset_bytes) + 2929 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2930 2931 switch (desc->fw_type) { 2932 case PSP_FW_TYPE_PSP_SOS: 2933 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2934 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2935 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2936 psp->sos.start_addr = ucode_start_addr; 2937 break; 2938 case PSP_FW_TYPE_PSP_SYS_DRV: 2939 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2940 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2941 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2942 psp->sys.start_addr = ucode_start_addr; 2943 break; 2944 case PSP_FW_TYPE_PSP_KDB: 2945 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2946 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2947 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2948 psp->kdb.start_addr = ucode_start_addr; 2949 break; 2950 case PSP_FW_TYPE_PSP_TOC: 2951 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2952 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2953 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 2954 psp->toc.start_addr = ucode_start_addr; 2955 break; 2956 case PSP_FW_TYPE_PSP_SPL: 2957 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 2958 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 2959 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 2960 psp->spl.start_addr = ucode_start_addr; 2961 break; 2962 case PSP_FW_TYPE_PSP_RL: 2963 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 2964 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 2965 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 2966 psp->rl.start_addr = ucode_start_addr; 2967 break; 2968 case PSP_FW_TYPE_PSP_SOC_DRV: 2969 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 2970 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 2971 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2972 psp->soc_drv.start_addr = ucode_start_addr; 2973 break; 2974 case PSP_FW_TYPE_PSP_INTF_DRV: 2975 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 2976 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 2977 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2978 psp->intf_drv.start_addr = ucode_start_addr; 2979 break; 2980 case PSP_FW_TYPE_PSP_DBG_DRV: 2981 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 2982 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 2983 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2984 psp->dbg_drv.start_addr = ucode_start_addr; 2985 break; 2986 default: 2987 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 2988 break; 2989 } 2990 2991 return 0; 2992 } 2993 2994 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 2995 { 2996 const struct psp_firmware_header_v1_0 *sos_hdr; 2997 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2998 uint8_t *ucode_array_start_addr; 2999 3000 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3001 ucode_array_start_addr = (uint8_t *)sos_hdr + 3002 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3003 3004 if (adev->gmc.xgmi.connected_to_cpu || 3005 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3006 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3007 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3008 3009 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3010 adev->psp.sys.start_addr = ucode_array_start_addr; 3011 3012 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3013 adev->psp.sos.start_addr = ucode_array_start_addr + 3014 le32_to_cpu(sos_hdr->sos.offset_bytes); 3015 } else { 3016 /* Load alternate PSP SOS FW */ 3017 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3018 3019 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3020 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3021 3022 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3023 adev->psp.sys.start_addr = ucode_array_start_addr + 3024 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3025 3026 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3027 adev->psp.sos.start_addr = ucode_array_start_addr + 3028 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3029 } 3030 3031 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3032 dev_warn(adev->dev, "PSP SOS FW not available"); 3033 return -EINVAL; 3034 } 3035 3036 return 0; 3037 } 3038 3039 int psp_init_sos_microcode(struct psp_context *psp, 3040 const char *chip_name) 3041 { 3042 struct amdgpu_device *adev = psp->adev; 3043 char fw_name[PSP_FW_NAME_LEN]; 3044 const struct psp_firmware_header_v1_0 *sos_hdr; 3045 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3046 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3047 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3048 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3049 int err = 0; 3050 uint8_t *ucode_array_start_addr; 3051 int fw_index = 0; 3052 3053 if (!chip_name) { 3054 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3055 return -EINVAL; 3056 } 3057 3058 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3059 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3060 if (err) 3061 goto out; 3062 3063 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3064 if (err) 3065 goto out; 3066 3067 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3068 ucode_array_start_addr = (uint8_t *)sos_hdr + 3069 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3070 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3071 3072 switch (sos_hdr->header.header_version_major) { 3073 case 1: 3074 err = psp_init_sos_base_fw(adev); 3075 if (err) 3076 goto out; 3077 3078 if (sos_hdr->header.header_version_minor == 1) { 3079 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3080 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3081 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3082 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3083 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3084 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3085 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3086 } 3087 if (sos_hdr->header.header_version_minor == 2) { 3088 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3089 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3090 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3091 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3092 } 3093 if (sos_hdr->header.header_version_minor == 3) { 3094 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3095 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3096 adev->psp.toc.start_addr = ucode_array_start_addr + 3097 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3098 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3099 adev->psp.kdb.start_addr = ucode_array_start_addr + 3100 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3101 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3102 adev->psp.spl.start_addr = ucode_array_start_addr + 3103 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3104 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3105 adev->psp.rl.start_addr = ucode_array_start_addr + 3106 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3107 } 3108 break; 3109 case 2: 3110 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3111 3112 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3113 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3114 err = -EINVAL; 3115 goto out; 3116 } 3117 3118 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3119 err = parse_sos_bin_descriptor(psp, 3120 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3121 sos_hdr_v2_0); 3122 if (err) 3123 goto out; 3124 } 3125 break; 3126 default: 3127 dev_err(adev->dev, 3128 "unsupported psp sos firmware\n"); 3129 err = -EINVAL; 3130 goto out; 3131 } 3132 3133 return 0; 3134 out: 3135 dev_err(adev->dev, 3136 "failed to init sos firmware\n"); 3137 release_firmware(adev->psp.sos_fw); 3138 adev->psp.sos_fw = NULL; 3139 3140 return err; 3141 } 3142 3143 static int parse_ta_bin_descriptor(struct psp_context *psp, 3144 const struct psp_fw_bin_desc *desc, 3145 const struct ta_firmware_header_v2_0 *ta_hdr) 3146 { 3147 uint8_t *ucode_start_addr = NULL; 3148 3149 if (!psp || !desc || !ta_hdr) 3150 return -EINVAL; 3151 3152 ucode_start_addr = (uint8_t *)ta_hdr + 3153 le32_to_cpu(desc->offset_bytes) + 3154 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3155 3156 switch (desc->fw_type) { 3157 case TA_FW_TYPE_PSP_ASD: 3158 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3159 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3160 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3161 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3162 break; 3163 case TA_FW_TYPE_PSP_XGMI: 3164 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3165 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3166 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3167 break; 3168 case TA_FW_TYPE_PSP_RAS: 3169 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3170 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3171 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3172 break; 3173 case TA_FW_TYPE_PSP_HDCP: 3174 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3175 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3176 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3177 break; 3178 case TA_FW_TYPE_PSP_DTM: 3179 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3180 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3181 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3182 break; 3183 case TA_FW_TYPE_PSP_RAP: 3184 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3185 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3186 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3187 break; 3188 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3189 psp->securedisplay_context.context.bin_desc.fw_version = 3190 le32_to_cpu(desc->fw_version); 3191 psp->securedisplay_context.context.bin_desc.size_bytes = 3192 le32_to_cpu(desc->size_bytes); 3193 psp->securedisplay_context.context.bin_desc.start_addr = 3194 ucode_start_addr; 3195 break; 3196 default: 3197 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3198 break; 3199 } 3200 3201 return 0; 3202 } 3203 3204 int psp_init_ta_microcode(struct psp_context *psp, 3205 const char *chip_name) 3206 { 3207 struct amdgpu_device *adev = psp->adev; 3208 char fw_name[PSP_FW_NAME_LEN]; 3209 const struct ta_firmware_header_v2_0 *ta_hdr; 3210 int err = 0; 3211 int ta_index = 0; 3212 3213 if (!chip_name) { 3214 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3215 return -EINVAL; 3216 } 3217 3218 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3219 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3220 if (err) 3221 goto out; 3222 3223 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3224 if (err) 3225 goto out; 3226 3227 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3228 3229 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3230 dev_err(adev->dev, "unsupported TA header version\n"); 3231 err = -EINVAL; 3232 goto out; 3233 } 3234 3235 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3236 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3237 err = -EINVAL; 3238 goto out; 3239 } 3240 3241 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3242 err = parse_ta_bin_descriptor(psp, 3243 &ta_hdr->ta_fw_bin[ta_index], 3244 ta_hdr); 3245 if (err) 3246 goto out; 3247 } 3248 3249 return 0; 3250 out: 3251 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3252 release_firmware(adev->psp.ta_fw); 3253 adev->psp.ta_fw = NULL; 3254 return err; 3255 } 3256 3257 int psp_init_cap_microcode(struct psp_context *psp, 3258 const char *chip_name) 3259 { 3260 struct amdgpu_device *adev = psp->adev; 3261 char fw_name[PSP_FW_NAME_LEN]; 3262 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3263 struct amdgpu_firmware_info *info = NULL; 3264 int err = 0; 3265 3266 if (!chip_name) { 3267 dev_err(adev->dev, "invalid chip name for cap microcode\n"); 3268 return -EINVAL; 3269 } 3270 3271 if (!amdgpu_sriov_vf(adev)) { 3272 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3273 return -EINVAL; 3274 } 3275 3276 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3277 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev); 3278 if (err) { 3279 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3280 err = 0; 3281 goto out; 3282 } 3283 3284 err = amdgpu_ucode_validate(adev->psp.cap_fw); 3285 if (err) { 3286 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3287 goto out; 3288 } 3289 3290 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3291 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3292 info->fw = adev->psp.cap_fw; 3293 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3294 adev->psp.cap_fw->data; 3295 adev->firmware.fw_size += ALIGN( 3296 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3297 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3298 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3299 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3300 3301 return 0; 3302 3303 out: 3304 release_firmware(adev->psp.cap_fw); 3305 adev->psp.cap_fw = NULL; 3306 return err; 3307 } 3308 3309 static int psp_set_clockgating_state(void *handle, 3310 enum amd_clockgating_state state) 3311 { 3312 return 0; 3313 } 3314 3315 static int psp_set_powergating_state(void *handle, 3316 enum amd_powergating_state state) 3317 { 3318 return 0; 3319 } 3320 3321 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3322 struct device_attribute *attr, 3323 char *buf) 3324 { 3325 struct drm_device *ddev = dev_get_drvdata(dev); 3326 struct amdgpu_device *adev = drm_to_adev(ddev); 3327 uint32_t fw_ver; 3328 int ret; 3329 3330 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3331 DRM_INFO("PSP block is not ready yet."); 3332 return -EBUSY; 3333 } 3334 3335 mutex_lock(&adev->psp.mutex); 3336 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3337 mutex_unlock(&adev->psp.mutex); 3338 3339 if (ret) { 3340 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3341 return ret; 3342 } 3343 3344 return sysfs_emit(buf, "%x\n", fw_ver); 3345 } 3346 3347 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3348 struct device_attribute *attr, 3349 const char *buf, 3350 size_t count) 3351 { 3352 struct drm_device *ddev = dev_get_drvdata(dev); 3353 struct amdgpu_device *adev = drm_to_adev(ddev); 3354 int ret, idx; 3355 char fw_name[100]; 3356 const struct firmware *usbc_pd_fw; 3357 struct amdgpu_bo *fw_buf_bo = NULL; 3358 uint64_t fw_pri_mc_addr; 3359 void *fw_pri_cpu_addr; 3360 3361 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3362 DRM_INFO("PSP block is not ready yet."); 3363 return -EBUSY; 3364 } 3365 3366 if (!drm_dev_enter(ddev, &idx)) 3367 return -ENODEV; 3368 3369 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3370 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3371 if (ret) 3372 goto fail; 3373 3374 /* LFB address which is aligned to 1MB boundary per PSP request */ 3375 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3376 AMDGPU_GEM_DOMAIN_VRAM, 3377 &fw_buf_bo, 3378 &fw_pri_mc_addr, 3379 &fw_pri_cpu_addr); 3380 if (ret) 3381 goto rel_buf; 3382 3383 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3384 3385 mutex_lock(&adev->psp.mutex); 3386 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3387 mutex_unlock(&adev->psp.mutex); 3388 3389 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3390 3391 rel_buf: 3392 release_firmware(usbc_pd_fw); 3393 fail: 3394 if (ret) { 3395 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3396 count = ret; 3397 } 3398 3399 drm_dev_exit(idx); 3400 return count; 3401 } 3402 3403 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3404 { 3405 int idx; 3406 3407 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3408 return; 3409 3410 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3411 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3412 3413 drm_dev_exit(idx); 3414 } 3415 3416 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3417 psp_usbc_pd_fw_sysfs_read, 3418 psp_usbc_pd_fw_sysfs_write); 3419 3420 int is_psp_fw_valid(struct psp_bin_desc bin) 3421 { 3422 return bin.size_bytes; 3423 } 3424 3425 const struct amd_ip_funcs psp_ip_funcs = { 3426 .name = "psp", 3427 .early_init = psp_early_init, 3428 .late_init = NULL, 3429 .sw_init = psp_sw_init, 3430 .sw_fini = psp_sw_fini, 3431 .hw_init = psp_hw_init, 3432 .hw_fini = psp_hw_fini, 3433 .suspend = psp_suspend, 3434 .resume = psp_resume, 3435 .is_idle = NULL, 3436 .check_soft_reset = NULL, 3437 .wait_for_idle = NULL, 3438 .soft_reset = NULL, 3439 .set_clockgating_state = psp_set_clockgating_state, 3440 .set_powergating_state = psp_set_powergating_state, 3441 }; 3442 3443 static int psp_sysfs_init(struct amdgpu_device *adev) 3444 { 3445 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3446 3447 if (ret) 3448 DRM_ERROR("Failed to create USBC PD FW control file!"); 3449 3450 return ret; 3451 } 3452 3453 static void psp_sysfs_fini(struct amdgpu_device *adev) 3454 { 3455 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3456 } 3457 3458 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3459 { 3460 .type = AMD_IP_BLOCK_TYPE_PSP, 3461 .major = 3, 3462 .minor = 1, 3463 .rev = 0, 3464 .funcs = &psp_ip_funcs, 3465 }; 3466 3467 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3468 { 3469 .type = AMD_IP_BLOCK_TYPE_PSP, 3470 .major = 10, 3471 .minor = 0, 3472 .rev = 0, 3473 .funcs = &psp_ip_funcs, 3474 }; 3475 3476 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3477 { 3478 .type = AMD_IP_BLOCK_TYPE_PSP, 3479 .major = 11, 3480 .minor = 0, 3481 .rev = 0, 3482 .funcs = &psp_ip_funcs, 3483 }; 3484 3485 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3486 .type = AMD_IP_BLOCK_TYPE_PSP, 3487 .major = 11, 3488 .minor = 0, 3489 .rev = 8, 3490 .funcs = &psp_ip_funcs, 3491 }; 3492 3493 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3494 { 3495 .type = AMD_IP_BLOCK_TYPE_PSP, 3496 .major = 12, 3497 .minor = 0, 3498 .rev = 0, 3499 .funcs = &psp_ip_funcs, 3500 }; 3501 3502 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3503 .type = AMD_IP_BLOCK_TYPE_PSP, 3504 .major = 13, 3505 .minor = 0, 3506 .rev = 0, 3507 .funcs = &psp_ip_funcs, 3508 }; 3509