1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 #include "psp_v10_0.h" 34 #include "psp_v11_0.h" 35 #include "psp_v12_0.h" 36 37 static void psp_set_funcs(struct amdgpu_device *adev); 38 39 static int psp_early_init(void *handle) 40 { 41 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 42 struct psp_context *psp = &adev->psp; 43 44 psp_set_funcs(adev); 45 46 switch (adev->asic_type) { 47 case CHIP_VEGA10: 48 case CHIP_VEGA12: 49 psp_v3_1_set_psp_funcs(psp); 50 psp->autoload_supported = false; 51 break; 52 case CHIP_RAVEN: 53 psp_v10_0_set_psp_funcs(psp); 54 psp->autoload_supported = false; 55 break; 56 case CHIP_VEGA20: 57 case CHIP_ARCTURUS: 58 psp_v11_0_set_psp_funcs(psp); 59 psp->autoload_supported = false; 60 break; 61 case CHIP_NAVI10: 62 case CHIP_NAVI14: 63 case CHIP_NAVI12: 64 psp_v11_0_set_psp_funcs(psp); 65 psp->autoload_supported = true; 66 break; 67 case CHIP_RENOIR: 68 psp_v12_0_set_psp_funcs(psp); 69 break; 70 default: 71 return -EINVAL; 72 } 73 74 psp->adev = adev; 75 76 return 0; 77 } 78 79 static int psp_sw_init(void *handle) 80 { 81 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 82 struct psp_context *psp = &adev->psp; 83 int ret; 84 85 ret = psp_init_microcode(psp); 86 if (ret) { 87 DRM_ERROR("Failed to load psp firmware!\n"); 88 return ret; 89 } 90 91 ret = psp_mem_training_init(psp); 92 if (ret) { 93 DRM_ERROR("Failed to initialize memory training!\n"); 94 return ret; 95 } 96 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 97 if (ret) { 98 DRM_ERROR("Failed to process memory training!\n"); 99 return ret; 100 } 101 102 return 0; 103 } 104 105 static int psp_sw_fini(void *handle) 106 { 107 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 108 109 psp_mem_training_fini(&adev->psp); 110 release_firmware(adev->psp.sos_fw); 111 adev->psp.sos_fw = NULL; 112 release_firmware(adev->psp.asd_fw); 113 adev->psp.asd_fw = NULL; 114 if (adev->psp.ta_fw) { 115 release_firmware(adev->psp.ta_fw); 116 adev->psp.ta_fw = NULL; 117 } 118 return 0; 119 } 120 121 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 122 uint32_t reg_val, uint32_t mask, bool check_changed) 123 { 124 uint32_t val; 125 int i; 126 struct amdgpu_device *adev = psp->adev; 127 128 for (i = 0; i < adev->usec_timeout; i++) { 129 val = RREG32(reg_index); 130 if (check_changed) { 131 if (val != reg_val) 132 return 0; 133 } else { 134 if ((val & mask) == reg_val) 135 return 0; 136 } 137 udelay(1); 138 } 139 140 return -ETIME; 141 } 142 143 static int 144 psp_cmd_submit_buf(struct psp_context *psp, 145 struct amdgpu_firmware_info *ucode, 146 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 147 { 148 int ret; 149 int index; 150 int timeout = 2000; 151 152 mutex_lock(&psp->mutex); 153 154 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 155 156 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 157 158 index = atomic_inc_return(&psp->fence_value); 159 ret = psp_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 160 if (ret) { 161 atomic_dec(&psp->fence_value); 162 mutex_unlock(&psp->mutex); 163 return ret; 164 } 165 166 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 167 while (*((unsigned int *)psp->fence_buf) != index) { 168 if (--timeout == 0) 169 break; 170 msleep(1); 171 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 172 } 173 174 /* In some cases, psp response status is not 0 even there is no 175 * problem while the command is submitted. Some version of PSP FW 176 * doesn't write 0 to that field. 177 * So here we would like to only print a warning instead of an error 178 * during psp initialization to avoid breaking hw_init and it doesn't 179 * return -EINVAL. 180 */ 181 if (psp->cmd_buf_mem->resp.status || !timeout) { 182 if (ucode) 183 DRM_WARN("failed to load ucode id (%d) ", 184 ucode->ucode_id); 185 DRM_DEBUG_DRIVER("psp command (0x%X) failed and response status is (0x%X)\n", 186 psp->cmd_buf_mem->cmd_id, 187 psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK); 188 if (!timeout) { 189 mutex_unlock(&psp->mutex); 190 return -EINVAL; 191 } 192 } 193 194 /* get xGMI session id from response buffer */ 195 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id; 196 197 if (ucode) { 198 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 199 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 200 } 201 mutex_unlock(&psp->mutex); 202 203 return ret; 204 } 205 206 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 207 struct psp_gfx_cmd_resp *cmd, 208 uint64_t tmr_mc, uint32_t size) 209 { 210 if (psp_support_vmr_ring(psp)) 211 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 212 else 213 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 214 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 215 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 216 cmd->cmd.cmd_setup_tmr.buf_size = size; 217 } 218 219 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 220 uint64_t pri_buf_mc, uint32_t size) 221 { 222 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 223 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 224 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 225 cmd->cmd.cmd_load_toc.toc_size = size; 226 } 227 228 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 229 static int psp_load_toc(struct psp_context *psp, 230 uint32_t *tmr_size) 231 { 232 int ret; 233 struct psp_gfx_cmd_resp *cmd; 234 235 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 236 if (!cmd) 237 return -ENOMEM; 238 /* Copy toc to psp firmware private buffer */ 239 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 240 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size); 241 242 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 243 244 ret = psp_cmd_submit_buf(psp, NULL, cmd, 245 psp->fence_buf_mc_addr); 246 if (!ret) 247 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 248 kfree(cmd); 249 return ret; 250 } 251 252 /* Set up Trusted Memory Region */ 253 static int psp_tmr_init(struct psp_context *psp) 254 { 255 int ret; 256 int tmr_size; 257 void *tmr_buf; 258 void **pptr; 259 260 /* 261 * According to HW engineer, they prefer the TMR address be "naturally 262 * aligned" , e.g. the start address be an integer divide of TMR size. 263 * 264 * Note: this memory need be reserved till the driver 265 * uninitializes. 266 */ 267 tmr_size = PSP_TMR_SIZE; 268 269 /* For ASICs support RLC autoload, psp will parse the toc 270 * and calculate the total size of TMR needed */ 271 if (!amdgpu_sriov_vf(psp->adev) && 272 psp->toc_start_addr && 273 psp->toc_bin_size && 274 psp->fw_pri_buf) { 275 ret = psp_load_toc(psp, &tmr_size); 276 if (ret) { 277 DRM_ERROR("Failed to load toc\n"); 278 return ret; 279 } 280 } 281 282 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 283 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE, 284 AMDGPU_GEM_DOMAIN_VRAM, 285 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 286 287 return ret; 288 } 289 290 static int psp_tmr_load(struct psp_context *psp) 291 { 292 int ret; 293 struct psp_gfx_cmd_resp *cmd; 294 295 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 296 if (!cmd) 297 return -ENOMEM; 298 299 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, 300 amdgpu_bo_size(psp->tmr_bo)); 301 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 302 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 303 304 ret = psp_cmd_submit_buf(psp, NULL, cmd, 305 psp->fence_buf_mc_addr); 306 307 kfree(cmd); 308 309 return ret; 310 } 311 312 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd, 313 uint64_t asd_mc, uint64_t asd_mc_shared, 314 uint32_t size, uint32_t shared_size) 315 { 316 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 317 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 318 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 319 cmd->cmd.cmd_load_ta.app_len = size; 320 321 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared); 322 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared); 323 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 324 } 325 326 static int psp_asd_init(struct psp_context *psp) 327 { 328 int ret; 329 330 /* 331 * Allocate 16k memory aligned to 4k from Frame Buffer (local 332 * physical) for shared ASD <-> Driver 333 */ 334 ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE, 335 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 336 &psp->asd_shared_bo, 337 &psp->asd_shared_mc_addr, 338 &psp->asd_shared_buf); 339 340 return ret; 341 } 342 343 static int psp_asd_load(struct psp_context *psp) 344 { 345 int ret; 346 struct psp_gfx_cmd_resp *cmd; 347 348 /* If PSP version doesn't match ASD version, asd loading will be failed. 349 * add workaround to bypass it for sriov now. 350 * TODO: add version check to make it common 351 */ 352 if (amdgpu_sriov_vf(psp->adev)) 353 return 0; 354 355 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 356 if (!cmd) 357 return -ENOMEM; 358 359 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 360 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 361 362 psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr, 363 psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE); 364 365 ret = psp_cmd_submit_buf(psp, NULL, cmd, 366 psp->fence_buf_mc_addr); 367 368 kfree(cmd); 369 370 return ret; 371 } 372 373 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 374 uint32_t id, uint32_t value) 375 { 376 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 377 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 378 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 379 } 380 381 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 382 uint32_t value) 383 { 384 struct psp_gfx_cmd_resp *cmd = NULL; 385 int ret = 0; 386 387 if (reg >= PSP_REG_LAST) 388 return -EINVAL; 389 390 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 391 if (!cmd) 392 return -ENOMEM; 393 394 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 395 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 396 397 kfree(cmd); 398 return ret; 399 } 400 401 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 402 uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared, 403 uint32_t xgmi_ta_size, uint32_t shared_size) 404 { 405 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 406 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc); 407 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc); 408 cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size; 409 410 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared); 411 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared); 412 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 413 } 414 415 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 416 { 417 int ret; 418 419 /* 420 * Allocate 16k memory aligned to 4k from Frame Buffer (local 421 * physical) for xgmi ta <-> Driver 422 */ 423 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 424 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 425 &psp->xgmi_context.xgmi_shared_bo, 426 &psp->xgmi_context.xgmi_shared_mc_addr, 427 &psp->xgmi_context.xgmi_shared_buf); 428 429 return ret; 430 } 431 432 static int psp_xgmi_load(struct psp_context *psp) 433 { 434 int ret; 435 struct psp_gfx_cmd_resp *cmd; 436 437 /* 438 * TODO: bypass the loading in sriov for now 439 */ 440 if (amdgpu_sriov_vf(psp->adev)) 441 return 0; 442 443 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 444 if (!cmd) 445 return -ENOMEM; 446 447 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 448 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 449 450 psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 451 psp->xgmi_context.xgmi_shared_mc_addr, 452 psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE); 453 454 ret = psp_cmd_submit_buf(psp, NULL, cmd, 455 psp->fence_buf_mc_addr); 456 457 if (!ret) { 458 psp->xgmi_context.initialized = 1; 459 psp->xgmi_context.session_id = cmd->resp.session_id; 460 } 461 462 kfree(cmd); 463 464 return ret; 465 } 466 467 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 468 uint32_t xgmi_session_id) 469 { 470 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 471 cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id; 472 } 473 474 static int psp_xgmi_unload(struct psp_context *psp) 475 { 476 int ret; 477 struct psp_gfx_cmd_resp *cmd; 478 479 /* 480 * TODO: bypass the unloading in sriov for now 481 */ 482 if (amdgpu_sriov_vf(psp->adev)) 483 return 0; 484 485 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 486 if (!cmd) 487 return -ENOMEM; 488 489 psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 490 491 ret = psp_cmd_submit_buf(psp, NULL, cmd, 492 psp->fence_buf_mc_addr); 493 494 kfree(cmd); 495 496 return ret; 497 } 498 499 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 500 uint32_t ta_cmd_id, 501 uint32_t xgmi_session_id) 502 { 503 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 504 cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id; 505 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 506 /* Note: cmd_invoke_cmd.buf is not used for now */ 507 } 508 509 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 510 { 511 int ret; 512 struct psp_gfx_cmd_resp *cmd; 513 514 /* 515 * TODO: bypass the loading in sriov for now 516 */ 517 if (amdgpu_sriov_vf(psp->adev)) 518 return 0; 519 520 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 521 if (!cmd) 522 return -ENOMEM; 523 524 psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id, 525 psp->xgmi_context.session_id); 526 527 ret = psp_cmd_submit_buf(psp, NULL, cmd, 528 psp->fence_buf_mc_addr); 529 530 kfree(cmd); 531 532 return ret; 533 } 534 535 static int psp_xgmi_terminate(struct psp_context *psp) 536 { 537 int ret; 538 539 if (!psp->xgmi_context.initialized) 540 return 0; 541 542 ret = psp_xgmi_unload(psp); 543 if (ret) 544 return ret; 545 546 psp->xgmi_context.initialized = 0; 547 548 /* free xgmi shared memory */ 549 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 550 &psp->xgmi_context.xgmi_shared_mc_addr, 551 &psp->xgmi_context.xgmi_shared_buf); 552 553 return 0; 554 } 555 556 static int psp_xgmi_initialize(struct psp_context *psp) 557 { 558 struct ta_xgmi_shared_memory *xgmi_cmd; 559 int ret; 560 561 if (!psp->adev->psp.ta_fw) 562 return -ENOENT; 563 564 if (!psp->xgmi_context.initialized) { 565 ret = psp_xgmi_init_shared_buf(psp); 566 if (ret) 567 return ret; 568 } 569 570 /* Load XGMI TA */ 571 ret = psp_xgmi_load(psp); 572 if (ret) 573 return ret; 574 575 /* Initialize XGMI session */ 576 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 577 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 578 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 579 580 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 581 582 return ret; 583 } 584 585 // ras begin 586 static void psp_prep_ras_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 587 uint64_t ras_ta_mc, uint64_t ras_mc_shared, 588 uint32_t ras_ta_size, uint32_t shared_size) 589 { 590 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 591 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ras_ta_mc); 592 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ras_ta_mc); 593 cmd->cmd.cmd_load_ta.app_len = ras_ta_size; 594 595 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ras_mc_shared); 596 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ras_mc_shared); 597 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 598 } 599 600 static int psp_ras_init_shared_buf(struct psp_context *psp) 601 { 602 int ret; 603 604 /* 605 * Allocate 16k memory aligned to 4k from Frame Buffer (local 606 * physical) for ras ta <-> Driver 607 */ 608 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 609 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 610 &psp->ras.ras_shared_bo, 611 &psp->ras.ras_shared_mc_addr, 612 &psp->ras.ras_shared_buf); 613 614 return ret; 615 } 616 617 static int psp_ras_load(struct psp_context *psp) 618 { 619 int ret; 620 struct psp_gfx_cmd_resp *cmd; 621 622 /* 623 * TODO: bypass the loading in sriov for now 624 */ 625 if (amdgpu_sriov_vf(psp->adev)) 626 return 0; 627 628 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 629 if (!cmd) 630 return -ENOMEM; 631 632 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 633 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 634 635 psp_prep_ras_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 636 psp->ras.ras_shared_mc_addr, 637 psp->ta_ras_ucode_size, PSP_RAS_SHARED_MEM_SIZE); 638 639 ret = psp_cmd_submit_buf(psp, NULL, cmd, 640 psp->fence_buf_mc_addr); 641 642 if (!ret) { 643 psp->ras.ras_initialized = 1; 644 psp->ras.session_id = cmd->resp.session_id; 645 } 646 647 kfree(cmd); 648 649 return ret; 650 } 651 652 static void psp_prep_ras_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 653 uint32_t ras_session_id) 654 { 655 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 656 cmd->cmd.cmd_unload_ta.session_id = ras_session_id; 657 } 658 659 static int psp_ras_unload(struct psp_context *psp) 660 { 661 int ret; 662 struct psp_gfx_cmd_resp *cmd; 663 664 /* 665 * TODO: bypass the unloading in sriov for now 666 */ 667 if (amdgpu_sriov_vf(psp->adev)) 668 return 0; 669 670 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 671 if (!cmd) 672 return -ENOMEM; 673 674 psp_prep_ras_ta_unload_cmd_buf(cmd, psp->ras.session_id); 675 676 ret = psp_cmd_submit_buf(psp, NULL, cmd, 677 psp->fence_buf_mc_addr); 678 679 kfree(cmd); 680 681 return ret; 682 } 683 684 static void psp_prep_ras_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 685 uint32_t ta_cmd_id, 686 uint32_t ras_session_id) 687 { 688 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 689 cmd->cmd.cmd_invoke_cmd.session_id = ras_session_id; 690 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 691 /* Note: cmd_invoke_cmd.buf is not used for now */ 692 } 693 694 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 695 { 696 int ret; 697 struct psp_gfx_cmd_resp *cmd; 698 699 /* 700 * TODO: bypass the loading in sriov for now 701 */ 702 if (amdgpu_sriov_vf(psp->adev)) 703 return 0; 704 705 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 706 if (!cmd) 707 return -ENOMEM; 708 709 psp_prep_ras_ta_invoke_cmd_buf(cmd, ta_cmd_id, 710 psp->ras.session_id); 711 712 ret = psp_cmd_submit_buf(psp, NULL, cmd, 713 psp->fence_buf_mc_addr); 714 715 kfree(cmd); 716 717 return ret; 718 } 719 720 int psp_ras_enable_features(struct psp_context *psp, 721 union ta_ras_cmd_input *info, bool enable) 722 { 723 struct ta_ras_shared_memory *ras_cmd; 724 int ret; 725 726 if (!psp->ras.ras_initialized) 727 return -EINVAL; 728 729 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 730 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 731 732 if (enable) 733 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 734 else 735 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 736 737 ras_cmd->ras_in_message = *info; 738 739 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 740 if (ret) 741 return -EINVAL; 742 743 return ras_cmd->ras_status; 744 } 745 746 static int psp_ras_terminate(struct psp_context *psp) 747 { 748 int ret; 749 750 if (!psp->ras.ras_initialized) 751 return 0; 752 753 ret = psp_ras_unload(psp); 754 if (ret) 755 return ret; 756 757 psp->ras.ras_initialized = 0; 758 759 /* free ras shared memory */ 760 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 761 &psp->ras.ras_shared_mc_addr, 762 &psp->ras.ras_shared_buf); 763 764 return 0; 765 } 766 767 static int psp_ras_initialize(struct psp_context *psp) 768 { 769 int ret; 770 771 if (!psp->ras.ras_initialized) { 772 ret = psp_ras_init_shared_buf(psp); 773 if (ret) 774 return ret; 775 } 776 777 ret = psp_ras_load(psp); 778 if (ret) 779 return ret; 780 781 return 0; 782 } 783 // ras end 784 785 // HDCP start 786 static void psp_prep_hdcp_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 787 uint64_t hdcp_ta_mc, 788 uint64_t hdcp_mc_shared, 789 uint32_t hdcp_ta_size, 790 uint32_t shared_size) 791 { 792 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 793 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(hdcp_ta_mc); 794 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(hdcp_ta_mc); 795 cmd->cmd.cmd_load_ta.app_len = hdcp_ta_size; 796 797 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 798 lower_32_bits(hdcp_mc_shared); 799 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 800 upper_32_bits(hdcp_mc_shared); 801 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 802 } 803 804 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 805 { 806 int ret; 807 808 /* 809 * Allocate 16k memory aligned to 4k from Frame Buffer (local 810 * physical) for hdcp ta <-> Driver 811 */ 812 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 813 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 814 &psp->hdcp_context.hdcp_shared_bo, 815 &psp->hdcp_context.hdcp_shared_mc_addr, 816 &psp->hdcp_context.hdcp_shared_buf); 817 818 return ret; 819 } 820 821 static int psp_hdcp_load(struct psp_context *psp) 822 { 823 int ret; 824 struct psp_gfx_cmd_resp *cmd; 825 826 /* 827 * TODO: bypass the loading in sriov for now 828 */ 829 if (amdgpu_sriov_vf(psp->adev)) 830 return 0; 831 832 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 833 if (!cmd) 834 return -ENOMEM; 835 836 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 837 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr, 838 psp->ta_hdcp_ucode_size); 839 840 psp_prep_hdcp_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 841 psp->hdcp_context.hdcp_shared_mc_addr, 842 psp->ta_hdcp_ucode_size, 843 PSP_HDCP_SHARED_MEM_SIZE); 844 845 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 846 847 if (!ret) { 848 psp->hdcp_context.hdcp_initialized = 1; 849 psp->hdcp_context.session_id = cmd->resp.session_id; 850 } 851 852 kfree(cmd); 853 854 return ret; 855 } 856 static int psp_hdcp_initialize(struct psp_context *psp) 857 { 858 int ret; 859 860 if (!psp->hdcp_context.hdcp_initialized) { 861 ret = psp_hdcp_init_shared_buf(psp); 862 if (ret) 863 return ret; 864 } 865 866 ret = psp_hdcp_load(psp); 867 if (ret) 868 return ret; 869 870 return 0; 871 } 872 static void psp_prep_hdcp_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 873 uint32_t hdcp_session_id) 874 { 875 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 876 cmd->cmd.cmd_unload_ta.session_id = hdcp_session_id; 877 } 878 879 static int psp_hdcp_unload(struct psp_context *psp) 880 { 881 int ret; 882 struct psp_gfx_cmd_resp *cmd; 883 884 /* 885 * TODO: bypass the unloading in sriov for now 886 */ 887 if (amdgpu_sriov_vf(psp->adev)) 888 return 0; 889 890 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 891 if (!cmd) 892 return -ENOMEM; 893 894 psp_prep_hdcp_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 895 896 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 897 898 kfree(cmd); 899 900 return ret; 901 } 902 903 static void psp_prep_hdcp_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 904 uint32_t ta_cmd_id, 905 uint32_t hdcp_session_id) 906 { 907 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 908 cmd->cmd.cmd_invoke_cmd.session_id = hdcp_session_id; 909 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 910 /* Note: cmd_invoke_cmd.buf is not used for now */ 911 } 912 913 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 914 { 915 int ret; 916 struct psp_gfx_cmd_resp *cmd; 917 918 /* 919 * TODO: bypass the loading in sriov for now 920 */ 921 if (amdgpu_sriov_vf(psp->adev)) 922 return 0; 923 924 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 925 if (!cmd) 926 return -ENOMEM; 927 928 psp_prep_hdcp_ta_invoke_cmd_buf(cmd, ta_cmd_id, 929 psp->hdcp_context.session_id); 930 931 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 932 933 kfree(cmd); 934 935 return ret; 936 } 937 938 static int psp_hdcp_terminate(struct psp_context *psp) 939 { 940 int ret; 941 942 if (!psp->hdcp_context.hdcp_initialized) 943 return 0; 944 945 ret = psp_hdcp_unload(psp); 946 if (ret) 947 return ret; 948 949 psp->hdcp_context.hdcp_initialized = 0; 950 951 /* free hdcp shared memory */ 952 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 953 &psp->hdcp_context.hdcp_shared_mc_addr, 954 &psp->hdcp_context.hdcp_shared_buf); 955 956 return 0; 957 } 958 // HDCP end 959 960 // DTM start 961 static void psp_prep_dtm_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 962 uint64_t dtm_ta_mc, 963 uint64_t dtm_mc_shared, 964 uint32_t dtm_ta_size, 965 uint32_t shared_size) 966 { 967 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 968 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(dtm_ta_mc); 969 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(dtm_ta_mc); 970 cmd->cmd.cmd_load_ta.app_len = dtm_ta_size; 971 972 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(dtm_mc_shared); 973 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(dtm_mc_shared); 974 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 975 } 976 977 static int psp_dtm_init_shared_buf(struct psp_context *psp) 978 { 979 int ret; 980 981 /* 982 * Allocate 16k memory aligned to 4k from Frame Buffer (local 983 * physical) for dtm ta <-> Driver 984 */ 985 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 986 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 987 &psp->dtm_context.dtm_shared_bo, 988 &psp->dtm_context.dtm_shared_mc_addr, 989 &psp->dtm_context.dtm_shared_buf); 990 991 return ret; 992 } 993 994 static int psp_dtm_load(struct psp_context *psp) 995 { 996 int ret; 997 struct psp_gfx_cmd_resp *cmd; 998 999 /* 1000 * TODO: bypass the loading in sriov for now 1001 */ 1002 if (amdgpu_sriov_vf(psp->adev)) 1003 return 0; 1004 1005 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1006 if (!cmd) 1007 return -ENOMEM; 1008 1009 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1010 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1011 1012 psp_prep_dtm_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 1013 psp->dtm_context.dtm_shared_mc_addr, 1014 psp->ta_dtm_ucode_size, 1015 PSP_DTM_SHARED_MEM_SIZE); 1016 1017 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1018 1019 if (!ret) { 1020 psp->dtm_context.dtm_initialized = 1; 1021 psp->dtm_context.session_id = cmd->resp.session_id; 1022 } 1023 1024 kfree(cmd); 1025 1026 return ret; 1027 } 1028 1029 static int psp_dtm_initialize(struct psp_context *psp) 1030 { 1031 int ret; 1032 1033 if (!psp->dtm_context.dtm_initialized) { 1034 ret = psp_dtm_init_shared_buf(psp); 1035 if (ret) 1036 return ret; 1037 } 1038 1039 ret = psp_dtm_load(psp); 1040 if (ret) 1041 return ret; 1042 1043 return 0; 1044 } 1045 1046 static void psp_prep_dtm_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1047 uint32_t ta_cmd_id, 1048 uint32_t dtm_session_id) 1049 { 1050 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1051 cmd->cmd.cmd_invoke_cmd.session_id = dtm_session_id; 1052 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1053 /* Note: cmd_invoke_cmd.buf is not used for now */ 1054 } 1055 1056 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1057 { 1058 int ret; 1059 struct psp_gfx_cmd_resp *cmd; 1060 1061 /* 1062 * TODO: bypass the loading in sriov for now 1063 */ 1064 if (amdgpu_sriov_vf(psp->adev)) 1065 return 0; 1066 1067 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1068 if (!cmd) 1069 return -ENOMEM; 1070 1071 psp_prep_dtm_ta_invoke_cmd_buf(cmd, ta_cmd_id, 1072 psp->dtm_context.session_id); 1073 1074 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1075 1076 kfree(cmd); 1077 1078 return ret; 1079 } 1080 1081 static int psp_dtm_terminate(struct psp_context *psp) 1082 { 1083 int ret; 1084 1085 if (!psp->dtm_context.dtm_initialized) 1086 return 0; 1087 1088 ret = psp_hdcp_unload(psp); 1089 if (ret) 1090 return ret; 1091 1092 psp->dtm_context.dtm_initialized = 0; 1093 1094 /* free hdcp shared memory */ 1095 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1096 &psp->dtm_context.dtm_shared_mc_addr, 1097 &psp->dtm_context.dtm_shared_buf); 1098 1099 return 0; 1100 } 1101 // DTM end 1102 1103 static int psp_hw_start(struct psp_context *psp) 1104 { 1105 struct amdgpu_device *adev = psp->adev; 1106 int ret; 1107 1108 if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) { 1109 if (psp->kdb_bin_size && 1110 (psp->funcs->bootloader_load_kdb != NULL)) { 1111 ret = psp_bootloader_load_kdb(psp); 1112 if (ret) { 1113 DRM_ERROR("PSP load kdb failed!\n"); 1114 return ret; 1115 } 1116 } 1117 1118 ret = psp_bootloader_load_sysdrv(psp); 1119 if (ret) { 1120 DRM_ERROR("PSP load sysdrv failed!\n"); 1121 return ret; 1122 } 1123 1124 ret = psp_bootloader_load_sos(psp); 1125 if (ret) { 1126 DRM_ERROR("PSP load sos failed!\n"); 1127 return ret; 1128 } 1129 } 1130 1131 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1132 if (ret) { 1133 DRM_ERROR("PSP create ring failed!\n"); 1134 return ret; 1135 } 1136 1137 ret = psp_tmr_init(psp); 1138 if (ret) { 1139 DRM_ERROR("PSP tmr init failed!\n"); 1140 return ret; 1141 } 1142 1143 ret = psp_tmr_load(psp); 1144 if (ret) { 1145 DRM_ERROR("PSP load tmr failed!\n"); 1146 return ret; 1147 } 1148 1149 ret = psp_asd_init(psp); 1150 if (ret) { 1151 DRM_ERROR("PSP asd init failed!\n"); 1152 return ret; 1153 } 1154 1155 ret = psp_asd_load(psp); 1156 if (ret) { 1157 DRM_ERROR("PSP load asd failed!\n"); 1158 return ret; 1159 } 1160 1161 if (adev->gmc.xgmi.num_physical_nodes > 1) { 1162 ret = psp_xgmi_initialize(psp); 1163 /* Warning the XGMI seesion initialize failure 1164 * Instead of stop driver initialization 1165 */ 1166 if (ret) 1167 dev_err(psp->adev->dev, 1168 "XGMI: Failed to initialize XGMI session\n"); 1169 } 1170 1171 if (psp->adev->psp.ta_fw) { 1172 ret = psp_ras_initialize(psp); 1173 if (ret) 1174 dev_err(psp->adev->dev, 1175 "RAS: Failed to initialize RAS\n"); 1176 1177 ret = psp_hdcp_initialize(psp); 1178 if (ret) 1179 dev_err(psp->adev->dev, 1180 "HDCP: Failed to initialize HDCP\n"); 1181 1182 ret = psp_dtm_initialize(psp); 1183 if (ret) 1184 dev_err(psp->adev->dev, 1185 "DTM: Failed to initialize DTM\n"); 1186 } 1187 1188 return 0; 1189 } 1190 1191 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 1192 enum psp_gfx_fw_type *type) 1193 { 1194 switch (ucode->ucode_id) { 1195 case AMDGPU_UCODE_ID_SDMA0: 1196 *type = GFX_FW_TYPE_SDMA0; 1197 break; 1198 case AMDGPU_UCODE_ID_SDMA1: 1199 *type = GFX_FW_TYPE_SDMA1; 1200 break; 1201 case AMDGPU_UCODE_ID_SDMA2: 1202 *type = GFX_FW_TYPE_SDMA2; 1203 break; 1204 case AMDGPU_UCODE_ID_SDMA3: 1205 *type = GFX_FW_TYPE_SDMA3; 1206 break; 1207 case AMDGPU_UCODE_ID_SDMA4: 1208 *type = GFX_FW_TYPE_SDMA4; 1209 break; 1210 case AMDGPU_UCODE_ID_SDMA5: 1211 *type = GFX_FW_TYPE_SDMA5; 1212 break; 1213 case AMDGPU_UCODE_ID_SDMA6: 1214 *type = GFX_FW_TYPE_SDMA6; 1215 break; 1216 case AMDGPU_UCODE_ID_SDMA7: 1217 *type = GFX_FW_TYPE_SDMA7; 1218 break; 1219 case AMDGPU_UCODE_ID_CP_CE: 1220 *type = GFX_FW_TYPE_CP_CE; 1221 break; 1222 case AMDGPU_UCODE_ID_CP_PFP: 1223 *type = GFX_FW_TYPE_CP_PFP; 1224 break; 1225 case AMDGPU_UCODE_ID_CP_ME: 1226 *type = GFX_FW_TYPE_CP_ME; 1227 break; 1228 case AMDGPU_UCODE_ID_CP_MEC1: 1229 *type = GFX_FW_TYPE_CP_MEC; 1230 break; 1231 case AMDGPU_UCODE_ID_CP_MEC1_JT: 1232 *type = GFX_FW_TYPE_CP_MEC_ME1; 1233 break; 1234 case AMDGPU_UCODE_ID_CP_MEC2: 1235 *type = GFX_FW_TYPE_CP_MEC; 1236 break; 1237 case AMDGPU_UCODE_ID_CP_MEC2_JT: 1238 *type = GFX_FW_TYPE_CP_MEC_ME2; 1239 break; 1240 case AMDGPU_UCODE_ID_RLC_G: 1241 *type = GFX_FW_TYPE_RLC_G; 1242 break; 1243 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 1244 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 1245 break; 1246 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 1247 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 1248 break; 1249 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 1250 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 1251 break; 1252 case AMDGPU_UCODE_ID_SMC: 1253 *type = GFX_FW_TYPE_SMU; 1254 break; 1255 case AMDGPU_UCODE_ID_UVD: 1256 *type = GFX_FW_TYPE_UVD; 1257 break; 1258 case AMDGPU_UCODE_ID_UVD1: 1259 *type = GFX_FW_TYPE_UVD1; 1260 break; 1261 case AMDGPU_UCODE_ID_VCE: 1262 *type = GFX_FW_TYPE_VCE; 1263 break; 1264 case AMDGPU_UCODE_ID_VCN: 1265 *type = GFX_FW_TYPE_VCN; 1266 break; 1267 case AMDGPU_UCODE_ID_DMCU_ERAM: 1268 *type = GFX_FW_TYPE_DMCU_ERAM; 1269 break; 1270 case AMDGPU_UCODE_ID_DMCU_INTV: 1271 *type = GFX_FW_TYPE_DMCU_ISR; 1272 break; 1273 case AMDGPU_UCODE_ID_VCN0_RAM: 1274 *type = GFX_FW_TYPE_VCN0_RAM; 1275 break; 1276 case AMDGPU_UCODE_ID_VCN1_RAM: 1277 *type = GFX_FW_TYPE_VCN1_RAM; 1278 break; 1279 case AMDGPU_UCODE_ID_MAXIMUM: 1280 default: 1281 return -EINVAL; 1282 } 1283 1284 return 0; 1285 } 1286 1287 static void psp_print_fw_hdr(struct psp_context *psp, 1288 struct amdgpu_firmware_info *ucode) 1289 { 1290 struct amdgpu_device *adev = psp->adev; 1291 struct common_firmware_header *hdr; 1292 1293 switch (ucode->ucode_id) { 1294 case AMDGPU_UCODE_ID_SDMA0: 1295 case AMDGPU_UCODE_ID_SDMA1: 1296 case AMDGPU_UCODE_ID_SDMA2: 1297 case AMDGPU_UCODE_ID_SDMA3: 1298 case AMDGPU_UCODE_ID_SDMA4: 1299 case AMDGPU_UCODE_ID_SDMA5: 1300 case AMDGPU_UCODE_ID_SDMA6: 1301 case AMDGPU_UCODE_ID_SDMA7: 1302 hdr = (struct common_firmware_header *) 1303 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 1304 amdgpu_ucode_print_sdma_hdr(hdr); 1305 break; 1306 case AMDGPU_UCODE_ID_CP_CE: 1307 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 1308 amdgpu_ucode_print_gfx_hdr(hdr); 1309 break; 1310 case AMDGPU_UCODE_ID_CP_PFP: 1311 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 1312 amdgpu_ucode_print_gfx_hdr(hdr); 1313 break; 1314 case AMDGPU_UCODE_ID_CP_ME: 1315 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 1316 amdgpu_ucode_print_gfx_hdr(hdr); 1317 break; 1318 case AMDGPU_UCODE_ID_CP_MEC1: 1319 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 1320 amdgpu_ucode_print_gfx_hdr(hdr); 1321 break; 1322 case AMDGPU_UCODE_ID_RLC_G: 1323 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 1324 amdgpu_ucode_print_rlc_hdr(hdr); 1325 break; 1326 case AMDGPU_UCODE_ID_SMC: 1327 hdr = (struct common_firmware_header *)adev->pm.fw->data; 1328 amdgpu_ucode_print_smc_hdr(hdr); 1329 break; 1330 default: 1331 break; 1332 } 1333 } 1334 1335 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 1336 struct psp_gfx_cmd_resp *cmd) 1337 { 1338 int ret; 1339 uint64_t fw_mem_mc_addr = ucode->mc_addr; 1340 1341 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 1342 1343 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1344 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 1345 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 1346 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 1347 1348 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 1349 if (ret) 1350 DRM_ERROR("Unknown firmware type\n"); 1351 1352 return ret; 1353 } 1354 1355 static int psp_execute_np_fw_load(struct psp_context *psp, 1356 struct amdgpu_firmware_info *ucode) 1357 { 1358 int ret = 0; 1359 1360 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 1361 if (ret) 1362 return ret; 1363 1364 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 1365 psp->fence_buf_mc_addr); 1366 1367 return ret; 1368 } 1369 1370 static int psp_np_fw_load(struct psp_context *psp) 1371 { 1372 int i, ret; 1373 struct amdgpu_firmware_info *ucode; 1374 struct amdgpu_device* adev = psp->adev; 1375 1376 if (psp->autoload_supported) { 1377 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 1378 if (!ucode->fw) 1379 goto out; 1380 1381 ret = psp_execute_np_fw_load(psp, ucode); 1382 if (ret) 1383 return ret; 1384 } 1385 1386 out: 1387 for (i = 0; i < adev->firmware.max_ucodes; i++) { 1388 ucode = &adev->firmware.ucode[i]; 1389 if (!ucode->fw) 1390 continue; 1391 1392 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 1393 (psp_smu_reload_quirk(psp) || psp->autoload_supported)) 1394 continue; 1395 1396 if (amdgpu_sriov_vf(adev) && 1397 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 1398 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 1399 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 1400 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 1401 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 1402 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 1403 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 1404 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 1405 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) 1406 /*skip ucode loading in SRIOV VF */ 1407 continue; 1408 1409 if (psp->autoload_supported && 1410 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 1411 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 1412 /* skip mec JT when autoload is enabled */ 1413 continue; 1414 1415 psp_print_fw_hdr(psp, ucode); 1416 1417 ret = psp_execute_np_fw_load(psp, ucode); 1418 if (ret) 1419 return ret; 1420 1421 /* Start rlc autoload after psp recieved all the gfx firmware */ 1422 if (psp->autoload_supported && ucode->ucode_id == 1423 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) { 1424 ret = psp_rlc_autoload(psp); 1425 if (ret) { 1426 DRM_ERROR("Failed to start rlc autoload\n"); 1427 return ret; 1428 } 1429 } 1430 #if 0 1431 /* check if firmware loaded sucessfully */ 1432 if (!amdgpu_psp_check_fw_loading_status(adev, i)) 1433 return -EINVAL; 1434 #endif 1435 } 1436 1437 return 0; 1438 } 1439 1440 static int psp_load_fw(struct amdgpu_device *adev) 1441 { 1442 int ret; 1443 struct psp_context *psp = &adev->psp; 1444 1445 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) { 1446 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 1447 goto skip_memalloc; 1448 } 1449 1450 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1451 if (!psp->cmd) 1452 return -ENOMEM; 1453 1454 /* this fw pri bo is not used under SRIOV */ 1455 if (!amdgpu_sriov_vf(psp->adev)) { 1456 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 1457 AMDGPU_GEM_DOMAIN_GTT, 1458 &psp->fw_pri_bo, 1459 &psp->fw_pri_mc_addr, 1460 &psp->fw_pri_buf); 1461 if (ret) 1462 goto failed; 1463 } 1464 1465 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 1466 AMDGPU_GEM_DOMAIN_VRAM, 1467 &psp->fence_buf_bo, 1468 &psp->fence_buf_mc_addr, 1469 &psp->fence_buf); 1470 if (ret) 1471 goto failed; 1472 1473 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 1474 AMDGPU_GEM_DOMAIN_VRAM, 1475 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 1476 (void **)&psp->cmd_buf_mem); 1477 if (ret) 1478 goto failed; 1479 1480 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 1481 1482 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 1483 if (ret) { 1484 DRM_ERROR("PSP ring init failed!\n"); 1485 goto failed; 1486 } 1487 1488 skip_memalloc: 1489 ret = psp_hw_start(psp); 1490 if (ret) 1491 goto failed; 1492 1493 ret = psp_np_fw_load(psp); 1494 if (ret) 1495 goto failed; 1496 1497 return 0; 1498 1499 failed: 1500 /* 1501 * all cleanup jobs (xgmi terminate, ras terminate, 1502 * ring destroy, cmd/fence/fw buffers destory, 1503 * psp->cmd destory) are delayed to psp_hw_fini 1504 */ 1505 return ret; 1506 } 1507 1508 static int psp_hw_init(void *handle) 1509 { 1510 int ret; 1511 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1512 1513 mutex_lock(&adev->firmware.mutex); 1514 /* 1515 * This sequence is just used on hw_init only once, no need on 1516 * resume. 1517 */ 1518 ret = amdgpu_ucode_init_bo(adev); 1519 if (ret) 1520 goto failed; 1521 1522 ret = psp_load_fw(adev); 1523 if (ret) { 1524 DRM_ERROR("PSP firmware loading failed\n"); 1525 goto failed; 1526 } 1527 1528 mutex_unlock(&adev->firmware.mutex); 1529 return 0; 1530 1531 failed: 1532 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 1533 mutex_unlock(&adev->firmware.mutex); 1534 return -EINVAL; 1535 } 1536 1537 static int psp_hw_fini(void *handle) 1538 { 1539 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1540 struct psp_context *psp = &adev->psp; 1541 void *tmr_buf; 1542 void **pptr; 1543 1544 if (adev->gmc.xgmi.num_physical_nodes > 1 && 1545 psp->xgmi_context.initialized == 1) 1546 psp_xgmi_terminate(psp); 1547 1548 if (psp->adev->psp.ta_fw) { 1549 psp_ras_terminate(psp); 1550 psp_dtm_terminate(psp); 1551 psp_hdcp_terminate(psp); 1552 } 1553 1554 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 1555 1556 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 1557 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 1558 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 1559 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 1560 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 1561 &psp->fence_buf_mc_addr, &psp->fence_buf); 1562 amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr, 1563 &psp->asd_shared_buf); 1564 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 1565 (void **)&psp->cmd_buf_mem); 1566 1567 kfree(psp->cmd); 1568 psp->cmd = NULL; 1569 1570 return 0; 1571 } 1572 1573 static int psp_suspend(void *handle) 1574 { 1575 int ret; 1576 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1577 struct psp_context *psp = &adev->psp; 1578 1579 if (adev->gmc.xgmi.num_physical_nodes > 1 && 1580 psp->xgmi_context.initialized == 1) { 1581 ret = psp_xgmi_terminate(psp); 1582 if (ret) { 1583 DRM_ERROR("Failed to terminate xgmi ta\n"); 1584 return ret; 1585 } 1586 } 1587 1588 if (psp->adev->psp.ta_fw) { 1589 ret = psp_ras_terminate(psp); 1590 if (ret) { 1591 DRM_ERROR("Failed to terminate ras ta\n"); 1592 return ret; 1593 } 1594 ret = psp_hdcp_terminate(psp); 1595 if (ret) { 1596 DRM_ERROR("Failed to terminate hdcp ta\n"); 1597 return ret; 1598 } 1599 ret = psp_dtm_terminate(psp); 1600 if (ret) { 1601 DRM_ERROR("Failed to terminate dtm ta\n"); 1602 return ret; 1603 } 1604 } 1605 1606 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 1607 if (ret) { 1608 DRM_ERROR("PSP ring stop failed\n"); 1609 return ret; 1610 } 1611 1612 return 0; 1613 } 1614 1615 static int psp_resume(void *handle) 1616 { 1617 int ret; 1618 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1619 struct psp_context *psp = &adev->psp; 1620 1621 DRM_INFO("PSP is resuming...\n"); 1622 1623 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 1624 if (ret) { 1625 DRM_ERROR("Failed to process memory training!\n"); 1626 return ret; 1627 } 1628 1629 mutex_lock(&adev->firmware.mutex); 1630 1631 ret = psp_hw_start(psp); 1632 if (ret) 1633 goto failed; 1634 1635 ret = psp_np_fw_load(psp); 1636 if (ret) 1637 goto failed; 1638 1639 mutex_unlock(&adev->firmware.mutex); 1640 1641 return 0; 1642 1643 failed: 1644 DRM_ERROR("PSP resume failed\n"); 1645 mutex_unlock(&adev->firmware.mutex); 1646 return ret; 1647 } 1648 1649 int psp_gpu_reset(struct amdgpu_device *adev) 1650 { 1651 int ret; 1652 1653 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 1654 return 0; 1655 1656 mutex_lock(&adev->psp.mutex); 1657 ret = psp_mode1_reset(&adev->psp); 1658 mutex_unlock(&adev->psp.mutex); 1659 1660 return ret; 1661 } 1662 1663 int psp_rlc_autoload_start(struct psp_context *psp) 1664 { 1665 int ret; 1666 struct psp_gfx_cmd_resp *cmd; 1667 1668 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1669 if (!cmd) 1670 return -ENOMEM; 1671 1672 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 1673 1674 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1675 psp->fence_buf_mc_addr); 1676 kfree(cmd); 1677 return ret; 1678 } 1679 1680 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 1681 uint64_t cmd_gpu_addr, int cmd_size) 1682 { 1683 struct amdgpu_firmware_info ucode = {0}; 1684 1685 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 1686 AMDGPU_UCODE_ID_VCN0_RAM; 1687 ucode.mc_addr = cmd_gpu_addr; 1688 ucode.ucode_size = cmd_size; 1689 1690 return psp_execute_np_fw_load(&adev->psp, &ucode); 1691 } 1692 1693 static bool psp_check_fw_loading_status(struct amdgpu_device *adev, 1694 enum AMDGPU_UCODE_ID ucode_type) 1695 { 1696 struct amdgpu_firmware_info *ucode = NULL; 1697 1698 if (!adev->firmware.fw_size) 1699 return false; 1700 1701 ucode = &adev->firmware.ucode[ucode_type]; 1702 if (!ucode->fw || !ucode->ucode_size) 1703 return false; 1704 1705 return psp_compare_sram_data(&adev->psp, ucode, ucode_type); 1706 } 1707 1708 static int psp_set_clockgating_state(void *handle, 1709 enum amd_clockgating_state state) 1710 { 1711 return 0; 1712 } 1713 1714 static int psp_set_powergating_state(void *handle, 1715 enum amd_powergating_state state) 1716 { 1717 return 0; 1718 } 1719 1720 const struct amd_ip_funcs psp_ip_funcs = { 1721 .name = "psp", 1722 .early_init = psp_early_init, 1723 .late_init = NULL, 1724 .sw_init = psp_sw_init, 1725 .sw_fini = psp_sw_fini, 1726 .hw_init = psp_hw_init, 1727 .hw_fini = psp_hw_fini, 1728 .suspend = psp_suspend, 1729 .resume = psp_resume, 1730 .is_idle = NULL, 1731 .check_soft_reset = NULL, 1732 .wait_for_idle = NULL, 1733 .soft_reset = NULL, 1734 .set_clockgating_state = psp_set_clockgating_state, 1735 .set_powergating_state = psp_set_powergating_state, 1736 }; 1737 1738 static const struct amdgpu_psp_funcs psp_funcs = { 1739 .check_fw_loading_status = psp_check_fw_loading_status, 1740 }; 1741 1742 static void psp_set_funcs(struct amdgpu_device *adev) 1743 { 1744 if (NULL == adev->firmware.funcs) 1745 adev->firmware.funcs = &psp_funcs; 1746 } 1747 1748 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 1749 { 1750 .type = AMD_IP_BLOCK_TYPE_PSP, 1751 .major = 3, 1752 .minor = 1, 1753 .rev = 0, 1754 .funcs = &psp_ip_funcs, 1755 }; 1756 1757 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 1758 { 1759 .type = AMD_IP_BLOCK_TYPE_PSP, 1760 .major = 10, 1761 .minor = 0, 1762 .rev = 0, 1763 .funcs = &psp_ip_funcs, 1764 }; 1765 1766 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 1767 { 1768 .type = AMD_IP_BLOCK_TYPE_PSP, 1769 .major = 11, 1770 .minor = 0, 1771 .rev = 0, 1772 .funcs = &psp_ip_funcs, 1773 }; 1774 1775 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 1776 { 1777 .type = AMD_IP_BLOCK_TYPE_PSP, 1778 .major = 12, 1779 .minor = 0, 1780 .rev = 0, 1781 .funcs = &psp_ip_funcs, 1782 }; 1783