1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 41 #include "amdgpu_ras.h" 42 #include "amdgpu_securedisplay.h" 43 #include "amdgpu_atomfirmware.h" 44 45 static int psp_sysfs_init(struct amdgpu_device *adev); 46 static void psp_sysfs_fini(struct amdgpu_device *adev); 47 48 static int psp_load_smu_fw(struct psp_context *psp); 49 static int psp_ta_unload(struct psp_context *psp, struct ta_context *context); 50 static int psp_ta_load(struct psp_context *psp, struct ta_context *context); 51 static int psp_rap_terminate(struct psp_context *psp); 52 static int psp_securedisplay_terminate(struct psp_context *psp); 53 54 /* 55 * Due to DF Cstate management centralized to PMFW, the firmware 56 * loading sequence will be updated as below: 57 * - Load KDB 58 * - Load SYS_DRV 59 * - Load tOS 60 * - Load PMFW 61 * - Setup TMR 62 * - Load other non-psp fw 63 * - Load ASD 64 * - Load XGMI/RAS/HDCP/DTM TA if any 65 * 66 * This new sequence is required for 67 * - Arcturus and onwards 68 */ 69 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 70 { 71 struct amdgpu_device *adev = psp->adev; 72 73 if (amdgpu_sriov_vf(adev)) { 74 psp->pmfw_centralized_cstate_management = false; 75 return; 76 } 77 78 switch (adev->ip_versions[MP0_HWIP][0]) { 79 case IP_VERSION(11, 0, 0): 80 case IP_VERSION(11, 0, 4): 81 case IP_VERSION(11, 0, 5): 82 case IP_VERSION(11, 0, 7): 83 case IP_VERSION(11, 0, 9): 84 case IP_VERSION(11, 0, 11): 85 case IP_VERSION(11, 0, 12): 86 case IP_VERSION(11, 0, 13): 87 case IP_VERSION(13, 0, 2): 88 psp->pmfw_centralized_cstate_management = true; 89 break; 90 default: 91 psp->pmfw_centralized_cstate_management = false; 92 break; 93 } 94 } 95 96 static int psp_early_init(void *handle) 97 { 98 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 99 struct psp_context *psp = &adev->psp; 100 101 switch (adev->ip_versions[MP0_HWIP][0]) { 102 case IP_VERSION(9, 0, 0): 103 psp_v3_1_set_psp_funcs(psp); 104 psp->autoload_supported = false; 105 break; 106 case IP_VERSION(10, 0, 0): 107 case IP_VERSION(10, 0, 1): 108 psp_v10_0_set_psp_funcs(psp); 109 psp->autoload_supported = false; 110 break; 111 case IP_VERSION(11, 0, 2): 112 case IP_VERSION(11, 0, 4): 113 psp_v11_0_set_psp_funcs(psp); 114 psp->autoload_supported = false; 115 break; 116 case IP_VERSION(11, 0, 0): 117 case IP_VERSION(11, 0, 5): 118 case IP_VERSION(11, 0, 9): 119 case IP_VERSION(11, 0, 7): 120 case IP_VERSION(11, 0, 11): 121 case IP_VERSION(11, 5, 0): 122 case IP_VERSION(11, 0, 12): 123 case IP_VERSION(11, 0, 13): 124 psp_v11_0_set_psp_funcs(psp); 125 psp->autoload_supported = true; 126 break; 127 case IP_VERSION(11, 0, 3): 128 case IP_VERSION(12, 0, 1): 129 psp_v12_0_set_psp_funcs(psp); 130 break; 131 case IP_VERSION(13, 0, 2): 132 psp_v13_0_set_psp_funcs(psp); 133 break; 134 case IP_VERSION(13, 0, 1): 135 case IP_VERSION(13, 0, 3): 136 case IP_VERSION(13, 0, 5): 137 case IP_VERSION(13, 0, 8): 138 psp_v13_0_set_psp_funcs(psp); 139 psp->autoload_supported = true; 140 break; 141 case IP_VERSION(11, 0, 8): 142 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 143 psp_v11_0_8_set_psp_funcs(psp); 144 psp->autoload_supported = false; 145 } 146 break; 147 default: 148 return -EINVAL; 149 } 150 151 psp->adev = adev; 152 153 psp_check_pmfw_centralized_cstate_management(psp); 154 155 return 0; 156 } 157 158 static void psp_memory_training_fini(struct psp_context *psp) 159 { 160 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 161 162 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 163 kfree(ctx->sys_cache); 164 ctx->sys_cache = NULL; 165 } 166 167 static int psp_memory_training_init(struct psp_context *psp) 168 { 169 int ret; 170 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 171 172 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 173 DRM_DEBUG("memory training is not supported!\n"); 174 return 0; 175 } 176 177 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 178 if (ctx->sys_cache == NULL) { 179 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 180 ret = -ENOMEM; 181 goto Err_out; 182 } 183 184 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 185 ctx->train_data_size, 186 ctx->p2c_train_data_offset, 187 ctx->c2p_train_data_offset); 188 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 189 return 0; 190 191 Err_out: 192 psp_memory_training_fini(psp); 193 return ret; 194 } 195 196 /* 197 * Helper funciton to query psp runtime database entry 198 * 199 * @adev: amdgpu_device pointer 200 * @entry_type: the type of psp runtime database entry 201 * @db_entry: runtime database entry pointer 202 * 203 * Return false if runtime database doesn't exit or entry is invalid 204 * or true if the specific database entry is found, and copy to @db_entry 205 */ 206 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 207 enum psp_runtime_entry_type entry_type, 208 void *db_entry) 209 { 210 uint64_t db_header_pos, db_dir_pos; 211 struct psp_runtime_data_header db_header = {0}; 212 struct psp_runtime_data_directory db_dir = {0}; 213 bool ret = false; 214 int i; 215 216 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 217 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 218 219 /* read runtime db header from vram */ 220 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 221 sizeof(struct psp_runtime_data_header), false); 222 223 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 224 /* runtime db doesn't exist, exit */ 225 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 226 return false; 227 } 228 229 /* read runtime database entry from vram */ 230 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 231 sizeof(struct psp_runtime_data_directory), false); 232 233 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 234 /* invalid db entry count, exit */ 235 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 236 return false; 237 } 238 239 /* look up for requested entry type */ 240 for (i = 0; i < db_dir.entry_count && !ret; i++) { 241 if (db_dir.entry_list[i].entry_type == entry_type) { 242 switch (entry_type) { 243 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 244 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 245 /* invalid db entry size */ 246 dev_warn(adev->dev, "Invalid PSP runtime database entry size\n"); 247 return false; 248 } 249 /* read runtime database entry */ 250 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 251 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 252 ret = true; 253 break; 254 default: 255 ret = false; 256 break; 257 } 258 } 259 } 260 261 return ret; 262 } 263 264 static int psp_init_sriov_microcode(struct psp_context *psp) 265 { 266 struct amdgpu_device *adev = psp->adev; 267 int ret = 0; 268 269 switch (adev->ip_versions[MP0_HWIP][0]) { 270 case IP_VERSION(9, 0, 0): 271 ret = psp_init_cap_microcode(psp, "vega10"); 272 break; 273 case IP_VERSION(11, 0, 9): 274 ret = psp_init_cap_microcode(psp, "navi12"); 275 break; 276 case IP_VERSION(11, 0, 7): 277 ret = psp_init_cap_microcode(psp, "sienna_cichlid"); 278 break; 279 case IP_VERSION(13, 0, 2): 280 ret = psp_init_ta_microcode(psp, "aldebaran"); 281 break; 282 default: 283 BUG(); 284 break; 285 } 286 287 return ret; 288 } 289 290 static int psp_sw_init(void *handle) 291 { 292 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 293 struct psp_context *psp = &adev->psp; 294 int ret; 295 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 296 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 297 298 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 299 if (!psp->cmd) { 300 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 301 ret = -ENOMEM; 302 } 303 304 if (amdgpu_sriov_vf(adev)) 305 ret = psp_init_sriov_microcode(psp); 306 else 307 ret = psp_init_microcode(psp); 308 if (ret) { 309 DRM_ERROR("Failed to load psp firmware!\n"); 310 return ret; 311 } 312 313 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 314 if (psp_get_runtime_db_entry(adev, 315 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 316 &boot_cfg_entry)) { 317 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 318 if ((psp->boot_cfg_bitmask) & 319 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 320 /* If psp runtime database exists, then 321 * only enable two stage memory training 322 * when TWO_STAGE_DRAM_TRAINING bit is set 323 * in runtime database */ 324 mem_training_ctx->enable_mem_training = true; 325 } 326 327 } else { 328 /* If psp runtime database doesn't exist or 329 * is invalid, force enable two stage memory 330 * training */ 331 mem_training_ctx->enable_mem_training = true; 332 } 333 334 if (mem_training_ctx->enable_mem_training) { 335 ret = psp_memory_training_init(psp); 336 if (ret) { 337 DRM_ERROR("Failed to initialize memory training!\n"); 338 return ret; 339 } 340 341 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 342 if (ret) { 343 DRM_ERROR("Failed to process memory training!\n"); 344 return ret; 345 } 346 } 347 348 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 349 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 350 ret= psp_sysfs_init(adev); 351 if (ret) { 352 return ret; 353 } 354 } 355 356 return 0; 357 } 358 359 static int psp_sw_fini(void *handle) 360 { 361 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 362 struct psp_context *psp = &adev->psp; 363 struct psp_gfx_cmd_resp *cmd = psp->cmd; 364 365 psp_memory_training_fini(psp); 366 if (psp->sos_fw) { 367 release_firmware(psp->sos_fw); 368 psp->sos_fw = NULL; 369 } 370 if (psp->asd_fw) { 371 release_firmware(psp->asd_fw); 372 psp->asd_fw = NULL; 373 } 374 if (psp->ta_fw) { 375 release_firmware(psp->ta_fw); 376 psp->ta_fw = NULL; 377 } 378 if (adev->psp.cap_fw) { 379 release_firmware(psp->cap_fw); 380 psp->cap_fw = NULL; 381 } 382 383 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 384 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 385 psp_sysfs_fini(adev); 386 387 kfree(cmd); 388 cmd = NULL; 389 390 return 0; 391 } 392 393 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 394 uint32_t reg_val, uint32_t mask, bool check_changed) 395 { 396 uint32_t val; 397 int i; 398 struct amdgpu_device *adev = psp->adev; 399 400 if (psp->adev->no_hw_access) 401 return 0; 402 403 for (i = 0; i < adev->usec_timeout; i++) { 404 val = RREG32(reg_index); 405 if (check_changed) { 406 if (val != reg_val) 407 return 0; 408 } else { 409 if ((val & mask) == reg_val) 410 return 0; 411 } 412 udelay(1); 413 } 414 415 return -ETIME; 416 } 417 418 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 419 { 420 switch (cmd_id) { 421 case GFX_CMD_ID_LOAD_TA: 422 return "LOAD_TA"; 423 case GFX_CMD_ID_UNLOAD_TA: 424 return "UNLOAD_TA"; 425 case GFX_CMD_ID_INVOKE_CMD: 426 return "INVOKE_CMD"; 427 case GFX_CMD_ID_LOAD_ASD: 428 return "LOAD_ASD"; 429 case GFX_CMD_ID_SETUP_TMR: 430 return "SETUP_TMR"; 431 case GFX_CMD_ID_LOAD_IP_FW: 432 return "LOAD_IP_FW"; 433 case GFX_CMD_ID_DESTROY_TMR: 434 return "DESTROY_TMR"; 435 case GFX_CMD_ID_SAVE_RESTORE: 436 return "SAVE_RESTORE_IP_FW"; 437 case GFX_CMD_ID_SETUP_VMR: 438 return "SETUP_VMR"; 439 case GFX_CMD_ID_DESTROY_VMR: 440 return "DESTROY_VMR"; 441 case GFX_CMD_ID_PROG_REG: 442 return "PROG_REG"; 443 case GFX_CMD_ID_GET_FW_ATTESTATION: 444 return "GET_FW_ATTESTATION"; 445 case GFX_CMD_ID_LOAD_TOC: 446 return "ID_LOAD_TOC"; 447 case GFX_CMD_ID_AUTOLOAD_RLC: 448 return "AUTOLOAD_RLC"; 449 case GFX_CMD_ID_BOOT_CFG: 450 return "BOOT_CFG"; 451 default: 452 return "UNKNOWN CMD"; 453 } 454 } 455 456 static int 457 psp_cmd_submit_buf(struct psp_context *psp, 458 struct amdgpu_firmware_info *ucode, 459 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 460 { 461 int ret; 462 int index, idx; 463 int timeout = 20000; 464 bool ras_intr = false; 465 bool skip_unsupport = false; 466 467 if (psp->adev->no_hw_access) 468 return 0; 469 470 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 471 return 0; 472 473 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 474 475 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 476 477 index = atomic_inc_return(&psp->fence_value); 478 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 479 if (ret) { 480 atomic_dec(&psp->fence_value); 481 goto exit; 482 } 483 484 amdgpu_device_invalidate_hdp(psp->adev, NULL); 485 while (*((unsigned int *)psp->fence_buf) != index) { 486 if (--timeout == 0) 487 break; 488 /* 489 * Shouldn't wait for timeout when err_event_athub occurs, 490 * because gpu reset thread triggered and lock resource should 491 * be released for psp resume sequence. 492 */ 493 ras_intr = amdgpu_ras_intr_triggered(); 494 if (ras_intr) 495 break; 496 usleep_range(10, 100); 497 amdgpu_device_invalidate_hdp(psp->adev, NULL); 498 } 499 500 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 501 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 502 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 503 504 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 505 506 /* In some cases, psp response status is not 0 even there is no 507 * problem while the command is submitted. Some version of PSP FW 508 * doesn't write 0 to that field. 509 * So here we would like to only print a warning instead of an error 510 * during psp initialization to avoid breaking hw_init and it doesn't 511 * return -EINVAL. 512 */ 513 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 514 if (ucode) 515 DRM_WARN("failed to load ucode %s(0x%X) ", 516 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 517 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 518 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 519 psp->cmd_buf_mem->resp.status); 520 /* If we load CAP FW, PSP must return 0 under SRIOV 521 * also return failure in case of timeout 522 */ 523 if ((ucode && (ucode->ucode_id == AMDGPU_UCODE_ID_CAP)) || !timeout) { 524 ret = -EINVAL; 525 goto exit; 526 } 527 } 528 529 if (ucode) { 530 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 531 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 532 } 533 534 exit: 535 drm_dev_exit(idx); 536 return ret; 537 } 538 539 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 540 { 541 struct psp_gfx_cmd_resp *cmd = psp->cmd; 542 543 mutex_lock(&psp->mutex); 544 545 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 546 547 return cmd; 548 } 549 550 static void release_psp_cmd_buf(struct psp_context *psp) 551 { 552 mutex_unlock(&psp->mutex); 553 } 554 555 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 556 struct psp_gfx_cmd_resp *cmd, 557 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 558 { 559 struct amdgpu_device *adev = psp->adev; 560 uint32_t size = amdgpu_bo_size(tmr_bo); 561 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 562 563 if (amdgpu_sriov_vf(psp->adev)) 564 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 565 else 566 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 567 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 568 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 569 cmd->cmd.cmd_setup_tmr.buf_size = size; 570 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 571 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 572 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 573 } 574 575 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 576 uint64_t pri_buf_mc, uint32_t size) 577 { 578 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 579 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 580 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 581 cmd->cmd.cmd_load_toc.toc_size = size; 582 } 583 584 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 585 static int psp_load_toc(struct psp_context *psp, 586 uint32_t *tmr_size) 587 { 588 int ret; 589 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 590 591 /* Copy toc to psp firmware private buffer */ 592 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 593 594 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 595 596 ret = psp_cmd_submit_buf(psp, NULL, cmd, 597 psp->fence_buf_mc_addr); 598 if (!ret) 599 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 600 601 release_psp_cmd_buf(psp); 602 603 return ret; 604 } 605 606 /* Set up Trusted Memory Region */ 607 static int psp_tmr_init(struct psp_context *psp) 608 { 609 int ret; 610 int tmr_size; 611 void *tmr_buf; 612 void **pptr; 613 614 /* 615 * According to HW engineer, they prefer the TMR address be "naturally 616 * aligned" , e.g. the start address be an integer divide of TMR size. 617 * 618 * Note: this memory need be reserved till the driver 619 * uninitializes. 620 */ 621 tmr_size = PSP_TMR_SIZE(psp->adev); 622 623 /* For ASICs support RLC autoload, psp will parse the toc 624 * and calculate the total size of TMR needed */ 625 if (!amdgpu_sriov_vf(psp->adev) && 626 psp->toc.start_addr && 627 psp->toc.size_bytes && 628 psp->fw_pri_buf) { 629 ret = psp_load_toc(psp, &tmr_size); 630 if (ret) { 631 DRM_ERROR("Failed to load toc\n"); 632 return ret; 633 } 634 } 635 636 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 637 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 638 AMDGPU_GEM_DOMAIN_VRAM, 639 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 640 641 return ret; 642 } 643 644 static bool psp_skip_tmr(struct psp_context *psp) 645 { 646 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 647 case IP_VERSION(11, 0, 9): 648 case IP_VERSION(11, 0, 7): 649 case IP_VERSION(13, 0, 2): 650 return true; 651 default: 652 return false; 653 } 654 } 655 656 static int psp_tmr_load(struct psp_context *psp) 657 { 658 int ret; 659 struct psp_gfx_cmd_resp *cmd; 660 661 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 662 * Already set up by host driver. 663 */ 664 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 665 return 0; 666 667 cmd = acquire_psp_cmd_buf(psp); 668 669 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 670 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 671 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 672 673 ret = psp_cmd_submit_buf(psp, NULL, cmd, 674 psp->fence_buf_mc_addr); 675 676 release_psp_cmd_buf(psp); 677 678 return ret; 679 } 680 681 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 682 struct psp_gfx_cmd_resp *cmd) 683 { 684 if (amdgpu_sriov_vf(psp->adev)) 685 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 686 else 687 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 688 } 689 690 static int psp_tmr_unload(struct psp_context *psp) 691 { 692 int ret; 693 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 694 695 psp_prep_tmr_unload_cmd_buf(psp, cmd); 696 DRM_INFO("free PSP TMR buffer\n"); 697 698 ret = psp_cmd_submit_buf(psp, NULL, cmd, 699 psp->fence_buf_mc_addr); 700 701 release_psp_cmd_buf(psp); 702 703 return ret; 704 } 705 706 static int psp_tmr_terminate(struct psp_context *psp) 707 { 708 int ret; 709 void *tmr_buf; 710 void **pptr; 711 712 ret = psp_tmr_unload(psp); 713 if (ret) 714 return ret; 715 716 /* free TMR memory buffer */ 717 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 718 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 719 720 return 0; 721 } 722 723 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 724 uint64_t *output_ptr) 725 { 726 int ret; 727 struct psp_gfx_cmd_resp *cmd; 728 729 if (!output_ptr) 730 return -EINVAL; 731 732 if (amdgpu_sriov_vf(psp->adev)) 733 return 0; 734 735 cmd = acquire_psp_cmd_buf(psp); 736 737 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 738 739 ret = psp_cmd_submit_buf(psp, NULL, cmd, 740 psp->fence_buf_mc_addr); 741 742 if (!ret) { 743 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 744 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 745 } 746 747 release_psp_cmd_buf(psp); 748 749 return ret; 750 } 751 752 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 753 { 754 struct psp_context *psp = &adev->psp; 755 struct psp_gfx_cmd_resp *cmd; 756 int ret; 757 758 if (amdgpu_sriov_vf(adev)) 759 return 0; 760 761 cmd = acquire_psp_cmd_buf(psp); 762 763 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 764 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 765 766 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 767 if (!ret) { 768 *boot_cfg = 769 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 770 } 771 772 release_psp_cmd_buf(psp); 773 774 return ret; 775 } 776 777 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 778 { 779 int ret; 780 struct psp_context *psp = &adev->psp; 781 struct psp_gfx_cmd_resp *cmd; 782 783 if (amdgpu_sriov_vf(adev)) 784 return 0; 785 786 cmd = acquire_psp_cmd_buf(psp); 787 788 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 789 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 790 cmd->cmd.boot_cfg.boot_config = boot_cfg; 791 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 792 793 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 794 795 release_psp_cmd_buf(psp); 796 797 return ret; 798 } 799 800 static int psp_rl_load(struct amdgpu_device *adev) 801 { 802 int ret; 803 struct psp_context *psp = &adev->psp; 804 struct psp_gfx_cmd_resp *cmd; 805 806 if (!is_psp_fw_valid(psp->rl)) 807 return 0; 808 809 cmd = acquire_psp_cmd_buf(psp); 810 811 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 812 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 813 814 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 815 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 816 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 817 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 818 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 819 820 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 821 822 release_psp_cmd_buf(psp); 823 824 return ret; 825 } 826 827 static int psp_asd_load(struct psp_context *psp) 828 { 829 return psp_ta_load(psp, &psp->asd_context); 830 } 831 832 static int psp_asd_initialize(struct psp_context *psp) 833 { 834 int ret; 835 836 /* If PSP version doesn't match ASD version, asd loading will be failed. 837 * add workaround to bypass it for sriov now. 838 * TODO: add version check to make it common 839 */ 840 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 841 return 0; 842 843 psp->asd_context.mem_context.shared_mc_addr = 0; 844 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 845 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 846 847 ret = psp_asd_load(psp); 848 if (!ret) 849 psp->asd_context.initialized = true; 850 851 return ret; 852 } 853 854 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 855 uint32_t session_id) 856 { 857 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 858 cmd->cmd.cmd_unload_ta.session_id = session_id; 859 } 860 861 static int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 862 { 863 int ret; 864 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 865 866 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 867 868 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 869 870 release_psp_cmd_buf(psp); 871 872 return ret; 873 } 874 875 static int psp_asd_unload(struct psp_context *psp) 876 { 877 return psp_ta_unload(psp, &psp->asd_context); 878 } 879 880 static int psp_asd_terminate(struct psp_context *psp) 881 { 882 int ret; 883 884 if (amdgpu_sriov_vf(psp->adev)) 885 return 0; 886 887 if (!psp->asd_context.initialized) 888 return 0; 889 890 ret = psp_asd_unload(psp); 891 892 if (!ret) 893 psp->asd_context.initialized = false; 894 895 return ret; 896 } 897 898 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 899 uint32_t id, uint32_t value) 900 { 901 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 902 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 903 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 904 } 905 906 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 907 uint32_t value) 908 { 909 struct psp_gfx_cmd_resp *cmd; 910 int ret = 0; 911 912 if (reg >= PSP_REG_LAST) 913 return -EINVAL; 914 915 cmd = acquire_psp_cmd_buf(psp); 916 917 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 918 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 919 if (ret) 920 DRM_ERROR("PSP failed to program reg id %d", reg); 921 922 release_psp_cmd_buf(psp); 923 924 return ret; 925 } 926 927 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 928 uint64_t ta_bin_mc, 929 struct ta_context *context) 930 { 931 cmd->cmd_id = context->ta_load_type; 932 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 933 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 934 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 935 936 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 937 lower_32_bits(context->mem_context.shared_mc_addr); 938 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 939 upper_32_bits(context->mem_context.shared_mc_addr); 940 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 941 } 942 943 static int psp_ta_init_shared_buf(struct psp_context *psp, 944 struct ta_mem_context *mem_ctx) 945 { 946 /* 947 * Allocate 16k memory aligned to 4k from Frame Buffer (local 948 * physical) for ta to host memory 949 */ 950 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 951 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 952 &mem_ctx->shared_bo, 953 &mem_ctx->shared_mc_addr, 954 &mem_ctx->shared_buf); 955 } 956 957 static void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 958 { 959 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 960 &mem_ctx->shared_buf); 961 } 962 963 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 964 { 965 return psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 966 } 967 968 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 969 uint32_t ta_cmd_id, 970 uint32_t session_id) 971 { 972 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 973 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 974 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 975 } 976 977 static int psp_ta_invoke(struct psp_context *psp, 978 uint32_t ta_cmd_id, 979 struct ta_context *context) 980 { 981 int ret; 982 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 983 984 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 985 986 ret = psp_cmd_submit_buf(psp, NULL, cmd, 987 psp->fence_buf_mc_addr); 988 989 release_psp_cmd_buf(psp); 990 991 return ret; 992 } 993 994 static int psp_ta_load(struct psp_context *psp, struct ta_context *context) 995 { 996 int ret; 997 struct psp_gfx_cmd_resp *cmd; 998 999 cmd = acquire_psp_cmd_buf(psp); 1000 1001 psp_copy_fw(psp, context->bin_desc.start_addr, 1002 context->bin_desc.size_bytes); 1003 1004 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1005 1006 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1007 psp->fence_buf_mc_addr); 1008 1009 if (!ret) { 1010 context->session_id = cmd->resp.session_id; 1011 } 1012 1013 release_psp_cmd_buf(psp); 1014 1015 return ret; 1016 } 1017 1018 static int psp_xgmi_load(struct psp_context *psp) 1019 { 1020 return psp_ta_load(psp, &psp->xgmi_context.context); 1021 } 1022 1023 static int psp_xgmi_unload(struct psp_context *psp) 1024 { 1025 return psp_ta_unload(psp, &psp->xgmi_context.context); 1026 } 1027 1028 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1029 { 1030 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1031 } 1032 1033 int psp_xgmi_terminate(struct psp_context *psp) 1034 { 1035 int ret; 1036 struct amdgpu_device *adev = psp->adev; 1037 1038 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1039 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1040 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1041 adev->gmc.xgmi.connected_to_cpu)) 1042 return 0; 1043 1044 if (!psp->xgmi_context.context.initialized) 1045 return 0; 1046 1047 ret = psp_xgmi_unload(psp); 1048 if (ret) 1049 return ret; 1050 1051 psp->xgmi_context.context.initialized = false; 1052 1053 /* free xgmi shared memory */ 1054 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 1055 1056 return 0; 1057 } 1058 1059 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1060 { 1061 struct ta_xgmi_shared_memory *xgmi_cmd; 1062 int ret; 1063 1064 if (!psp->ta_fw || 1065 !psp->xgmi_context.context.bin_desc.size_bytes || 1066 !psp->xgmi_context.context.bin_desc.start_addr) 1067 return -ENOENT; 1068 1069 if (!load_ta) 1070 goto invoke; 1071 1072 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1073 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1074 1075 if (!psp->xgmi_context.context.initialized) { 1076 ret = psp_xgmi_init_shared_buf(psp); 1077 if (ret) 1078 return ret; 1079 } 1080 1081 /* Load XGMI TA */ 1082 ret = psp_xgmi_load(psp); 1083 if (!ret) 1084 psp->xgmi_context.context.initialized = true; 1085 else 1086 return ret; 1087 1088 invoke: 1089 /* Initialize XGMI session */ 1090 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1091 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1092 xgmi_cmd->flag_extend_link_record = set_extended_data; 1093 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1094 1095 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1096 1097 return ret; 1098 } 1099 1100 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1101 { 1102 struct ta_xgmi_shared_memory *xgmi_cmd; 1103 int ret; 1104 1105 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1106 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1107 1108 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1109 1110 /* Invoke xgmi ta to get hive id */ 1111 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1112 if (ret) 1113 return ret; 1114 1115 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1116 1117 return 0; 1118 } 1119 1120 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1121 { 1122 struct ta_xgmi_shared_memory *xgmi_cmd; 1123 int ret; 1124 1125 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1126 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1127 1128 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1129 1130 /* Invoke xgmi ta to get the node id */ 1131 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1132 if (ret) 1133 return ret; 1134 1135 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1136 1137 return 0; 1138 } 1139 1140 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1141 { 1142 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1143 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1144 } 1145 1146 /* 1147 * Chips that support extended topology information require the driver to 1148 * reflect topology information in the opposite direction. This is 1149 * because the TA has already exceeded its link record limit and if the 1150 * TA holds bi-directional information, the driver would have to do 1151 * multiple fetches instead of just two. 1152 */ 1153 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1154 struct psp_xgmi_node_info node_info) 1155 { 1156 struct amdgpu_device *mirror_adev; 1157 struct amdgpu_hive_info *hive; 1158 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1159 uint64_t dst_node_id = node_info.node_id; 1160 uint8_t dst_num_hops = node_info.num_hops; 1161 uint8_t dst_num_links = node_info.num_links; 1162 1163 hive = amdgpu_get_xgmi_hive(psp->adev); 1164 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1165 struct psp_xgmi_topology_info *mirror_top_info; 1166 int j; 1167 1168 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1169 continue; 1170 1171 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1172 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1173 if (mirror_top_info->nodes[j].node_id != src_node_id) 1174 continue; 1175 1176 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1177 /* 1178 * prevent 0 num_links value re-reflection since reflection 1179 * criteria is based on num_hops (direct or indirect). 1180 * 1181 */ 1182 if (dst_num_links) 1183 mirror_top_info->nodes[j].num_links = dst_num_links; 1184 1185 break; 1186 } 1187 1188 break; 1189 } 1190 } 1191 1192 int psp_xgmi_get_topology_info(struct psp_context *psp, 1193 int number_devices, 1194 struct psp_xgmi_topology_info *topology, 1195 bool get_extended_data) 1196 { 1197 struct ta_xgmi_shared_memory *xgmi_cmd; 1198 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1199 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1200 int i; 1201 int ret; 1202 1203 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1204 return -EINVAL; 1205 1206 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1207 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1208 xgmi_cmd->flag_extend_link_record = get_extended_data; 1209 1210 /* Fill in the shared memory with topology information as input */ 1211 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1212 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1213 topology_info_input->num_nodes = number_devices; 1214 1215 for (i = 0; i < topology_info_input->num_nodes; i++) { 1216 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1217 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1218 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1219 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1220 } 1221 1222 /* Invoke xgmi ta to get the topology information */ 1223 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1224 if (ret) 1225 return ret; 1226 1227 /* Read the output topology information from the shared memory */ 1228 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1229 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1230 for (i = 0; i < topology->num_nodes; i++) { 1231 /* extended data will either be 0 or equal to non-extended data */ 1232 if (topology_info_output->nodes[i].num_hops) 1233 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1234 1235 /* non-extended data gets everything here so no need to update */ 1236 if (!get_extended_data) { 1237 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1238 topology->nodes[i].is_sharing_enabled = 1239 topology_info_output->nodes[i].is_sharing_enabled; 1240 topology->nodes[i].sdma_engine = 1241 topology_info_output->nodes[i].sdma_engine; 1242 } 1243 1244 } 1245 1246 /* Invoke xgmi ta again to get the link information */ 1247 if (psp_xgmi_peer_link_info_supported(psp)) { 1248 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1249 1250 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1251 1252 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1253 1254 if (ret) 1255 return ret; 1256 1257 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1258 for (i = 0; i < topology->num_nodes; i++) { 1259 /* accumulate num_links on extended data */ 1260 topology->nodes[i].num_links = get_extended_data ? 1261 topology->nodes[i].num_links + 1262 link_info_output->nodes[i].num_links : 1263 link_info_output->nodes[i].num_links; 1264 1265 /* reflect the topology information for bi-directionality */ 1266 if (psp->xgmi_context.supports_extended_data && 1267 get_extended_data && topology->nodes[i].num_hops) 1268 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1269 } 1270 } 1271 1272 return 0; 1273 } 1274 1275 int psp_xgmi_set_topology_info(struct psp_context *psp, 1276 int number_devices, 1277 struct psp_xgmi_topology_info *topology) 1278 { 1279 struct ta_xgmi_shared_memory *xgmi_cmd; 1280 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1281 int i; 1282 1283 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1284 return -EINVAL; 1285 1286 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1287 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1288 1289 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1290 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1291 topology_info_input->num_nodes = number_devices; 1292 1293 for (i = 0; i < topology_info_input->num_nodes; i++) { 1294 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1295 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1296 topology_info_input->nodes[i].is_sharing_enabled = 1; 1297 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1298 } 1299 1300 /* Invoke xgmi ta to set topology information */ 1301 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1302 } 1303 1304 // ras begin 1305 static int psp_ras_init_shared_buf(struct psp_context *psp) 1306 { 1307 return psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1308 } 1309 1310 static int psp_ras_load(struct psp_context *psp) 1311 { 1312 return psp_ta_load(psp, &psp->ras_context.context); 1313 } 1314 1315 static int psp_ras_unload(struct psp_context *psp) 1316 { 1317 return psp_ta_unload(psp, &psp->ras_context.context); 1318 } 1319 1320 static void psp_ras_ta_check_status(struct psp_context *psp) 1321 { 1322 struct ta_ras_shared_memory *ras_cmd = 1323 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1324 1325 switch (ras_cmd->ras_status) { 1326 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1327 dev_warn(psp->adev->dev, 1328 "RAS WARNING: cmd failed due to unsupported ip\n"); 1329 break; 1330 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1331 dev_warn(psp->adev->dev, 1332 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1333 break; 1334 case TA_RAS_STATUS__SUCCESS: 1335 break; 1336 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1337 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1338 dev_warn(psp->adev->dev, 1339 "RAS WARNING: Inject error to critical region is not allowed\n"); 1340 break; 1341 default: 1342 dev_warn(psp->adev->dev, 1343 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1344 break; 1345 } 1346 } 1347 1348 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1349 { 1350 struct ta_ras_shared_memory *ras_cmd; 1351 int ret; 1352 1353 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1354 1355 /* 1356 * TODO: bypass the loading in sriov for now 1357 */ 1358 if (amdgpu_sriov_vf(psp->adev)) 1359 return 0; 1360 1361 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1362 1363 if (amdgpu_ras_intr_triggered()) 1364 return ret; 1365 1366 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1367 { 1368 DRM_WARN("RAS: Unsupported Interface"); 1369 return -EINVAL; 1370 } 1371 1372 if (!ret) { 1373 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1374 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1375 1376 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1377 } 1378 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1379 dev_warn(psp->adev->dev, 1380 "RAS internal register access blocked\n"); 1381 1382 psp_ras_ta_check_status(psp); 1383 } 1384 1385 return ret; 1386 } 1387 1388 int psp_ras_enable_features(struct psp_context *psp, 1389 union ta_ras_cmd_input *info, bool enable) 1390 { 1391 struct ta_ras_shared_memory *ras_cmd; 1392 int ret; 1393 1394 if (!psp->ras_context.context.initialized) 1395 return -EINVAL; 1396 1397 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1398 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1399 1400 if (enable) 1401 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1402 else 1403 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1404 1405 ras_cmd->ras_in_message = *info; 1406 1407 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1408 if (ret) 1409 return -EINVAL; 1410 1411 return 0; 1412 } 1413 1414 static int psp_ras_terminate(struct psp_context *psp) 1415 { 1416 int ret; 1417 1418 /* 1419 * TODO: bypass the terminate in sriov for now 1420 */ 1421 if (amdgpu_sriov_vf(psp->adev)) 1422 return 0; 1423 1424 if (!psp->ras_context.context.initialized) 1425 return 0; 1426 1427 ret = psp_ras_unload(psp); 1428 if (ret) 1429 return ret; 1430 1431 psp->ras_context.context.initialized = false; 1432 1433 /* free ras shared memory */ 1434 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 1435 1436 return 0; 1437 } 1438 1439 static int psp_ras_initialize(struct psp_context *psp) 1440 { 1441 int ret; 1442 uint32_t boot_cfg = 0xFF; 1443 struct amdgpu_device *adev = psp->adev; 1444 struct ta_ras_shared_memory *ras_cmd; 1445 1446 /* 1447 * TODO: bypass the initialize in sriov for now 1448 */ 1449 if (amdgpu_sriov_vf(adev)) 1450 return 0; 1451 1452 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1453 !adev->psp.ras_context.context.bin_desc.start_addr) { 1454 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1455 return 0; 1456 } 1457 1458 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1459 /* query GECC enablement status from boot config 1460 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1461 */ 1462 ret = psp_boot_config_get(adev, &boot_cfg); 1463 if (ret) 1464 dev_warn(adev->dev, "PSP get boot config failed\n"); 1465 1466 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1467 if (!boot_cfg) { 1468 dev_info(adev->dev, "GECC is disabled\n"); 1469 } else { 1470 /* disable GECC in next boot cycle if ras is 1471 * disabled by module parameter amdgpu_ras_enable 1472 * and/or amdgpu_ras_mask, or boot_config_get call 1473 * is failed 1474 */ 1475 ret = psp_boot_config_set(adev, 0); 1476 if (ret) 1477 dev_warn(adev->dev, "PSP set boot config failed\n"); 1478 else 1479 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1480 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1481 } 1482 } else { 1483 if (1 == boot_cfg) { 1484 dev_info(adev->dev, "GECC is enabled\n"); 1485 } else { 1486 /* enable GECC in next boot cycle if it is disabled 1487 * in boot config, or force enable GECC if failed to 1488 * get boot configuration 1489 */ 1490 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1491 if (ret) 1492 dev_warn(adev->dev, "PSP set boot config failed\n"); 1493 else 1494 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1495 } 1496 } 1497 } 1498 1499 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1500 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1501 1502 if (!psp->ras_context.context.initialized) { 1503 ret = psp_ras_init_shared_buf(psp); 1504 if (ret) 1505 return ret; 1506 } 1507 1508 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1509 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1510 1511 if (amdgpu_ras_is_poison_mode_supported(adev)) 1512 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1513 if (!adev->gmc.xgmi.connected_to_cpu) 1514 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1515 1516 ret = psp_ras_load(psp); 1517 1518 if (!ret && !ras_cmd->ras_status) 1519 psp->ras_context.context.initialized = true; 1520 else { 1521 if (ras_cmd->ras_status) 1522 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1523 amdgpu_ras_fini(psp->adev); 1524 } 1525 1526 return ret; 1527 } 1528 1529 int psp_ras_trigger_error(struct psp_context *psp, 1530 struct ta_ras_trigger_error_input *info) 1531 { 1532 struct ta_ras_shared_memory *ras_cmd; 1533 int ret; 1534 1535 if (!psp->ras_context.context.initialized) 1536 return -EINVAL; 1537 1538 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1539 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1540 1541 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1542 ras_cmd->ras_in_message.trigger_error = *info; 1543 1544 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1545 if (ret) 1546 return -EINVAL; 1547 1548 /* If err_event_athub occurs error inject was successful, however 1549 return status from TA is no long reliable */ 1550 if (amdgpu_ras_intr_triggered()) 1551 return 0; 1552 1553 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1554 return -EACCES; 1555 else if (ras_cmd->ras_status) 1556 return -EINVAL; 1557 1558 return 0; 1559 } 1560 // ras end 1561 1562 // HDCP start 1563 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1564 { 1565 return psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1566 } 1567 1568 static int psp_hdcp_load(struct psp_context *psp) 1569 { 1570 return psp_ta_load(psp, &psp->hdcp_context.context); 1571 } 1572 1573 static int psp_hdcp_initialize(struct psp_context *psp) 1574 { 1575 int ret; 1576 1577 /* 1578 * TODO: bypass the initialize in sriov for now 1579 */ 1580 if (amdgpu_sriov_vf(psp->adev)) 1581 return 0; 1582 1583 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1584 !psp->hdcp_context.context.bin_desc.start_addr) { 1585 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1586 return 0; 1587 } 1588 1589 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1590 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1591 1592 if (!psp->hdcp_context.context.initialized) { 1593 ret = psp_hdcp_init_shared_buf(psp); 1594 if (ret) 1595 return ret; 1596 } 1597 1598 ret = psp_hdcp_load(psp); 1599 if (!ret) { 1600 psp->hdcp_context.context.initialized = true; 1601 mutex_init(&psp->hdcp_context.mutex); 1602 } 1603 1604 return ret; 1605 } 1606 1607 static int psp_hdcp_unload(struct psp_context *psp) 1608 { 1609 return psp_ta_unload(psp, &psp->hdcp_context.context); 1610 } 1611 1612 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1613 { 1614 /* 1615 * TODO: bypass the loading in sriov for now 1616 */ 1617 if (amdgpu_sriov_vf(psp->adev)) 1618 return 0; 1619 1620 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1621 } 1622 1623 static int psp_hdcp_terminate(struct psp_context *psp) 1624 { 1625 int ret; 1626 1627 /* 1628 * TODO: bypass the terminate in sriov for now 1629 */ 1630 if (amdgpu_sriov_vf(psp->adev)) 1631 return 0; 1632 1633 if (!psp->hdcp_context.context.initialized) { 1634 if (psp->hdcp_context.context.mem_context.shared_buf) 1635 goto out; 1636 else 1637 return 0; 1638 } 1639 1640 ret = psp_hdcp_unload(psp); 1641 if (ret) 1642 return ret; 1643 1644 psp->hdcp_context.context.initialized = false; 1645 1646 out: 1647 /* free hdcp shared memory */ 1648 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 1649 1650 return 0; 1651 } 1652 // HDCP end 1653 1654 // DTM start 1655 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1656 { 1657 return psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1658 } 1659 1660 static int psp_dtm_load(struct psp_context *psp) 1661 { 1662 return psp_ta_load(psp, &psp->dtm_context.context); 1663 } 1664 1665 static int psp_dtm_initialize(struct psp_context *psp) 1666 { 1667 int ret; 1668 1669 /* 1670 * TODO: bypass the initialize in sriov for now 1671 */ 1672 if (amdgpu_sriov_vf(psp->adev)) 1673 return 0; 1674 1675 if (!psp->dtm_context.context.bin_desc.size_bytes || 1676 !psp->dtm_context.context.bin_desc.start_addr) { 1677 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1678 return 0; 1679 } 1680 1681 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1682 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1683 1684 if (!psp->dtm_context.context.initialized) { 1685 ret = psp_dtm_init_shared_buf(psp); 1686 if (ret) 1687 return ret; 1688 } 1689 1690 ret = psp_dtm_load(psp); 1691 if (!ret) { 1692 psp->dtm_context.context.initialized = true; 1693 mutex_init(&psp->dtm_context.mutex); 1694 } 1695 1696 return ret; 1697 } 1698 1699 static int psp_dtm_unload(struct psp_context *psp) 1700 { 1701 return psp_ta_unload(psp, &psp->dtm_context.context); 1702 } 1703 1704 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1705 { 1706 /* 1707 * TODO: bypass the loading in sriov for now 1708 */ 1709 if (amdgpu_sriov_vf(psp->adev)) 1710 return 0; 1711 1712 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1713 } 1714 1715 static int psp_dtm_terminate(struct psp_context *psp) 1716 { 1717 int ret; 1718 1719 /* 1720 * TODO: bypass the terminate in sriov for now 1721 */ 1722 if (amdgpu_sriov_vf(psp->adev)) 1723 return 0; 1724 1725 if (!psp->dtm_context.context.initialized) { 1726 if (psp->dtm_context.context.mem_context.shared_buf) 1727 goto out; 1728 else 1729 return 0; 1730 } 1731 1732 ret = psp_dtm_unload(psp); 1733 if (ret) 1734 return ret; 1735 1736 psp->dtm_context.context.initialized = false; 1737 1738 out: 1739 /* free dtm shared memory */ 1740 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 1741 1742 return 0; 1743 } 1744 // DTM end 1745 1746 // RAP start 1747 static int psp_rap_init_shared_buf(struct psp_context *psp) 1748 { 1749 return psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1750 } 1751 1752 static int psp_rap_load(struct psp_context *psp) 1753 { 1754 return psp_ta_load(psp, &psp->rap_context.context); 1755 } 1756 1757 static int psp_rap_unload(struct psp_context *psp) 1758 { 1759 return psp_ta_unload(psp, &psp->rap_context.context); 1760 } 1761 1762 static int psp_rap_initialize(struct psp_context *psp) 1763 { 1764 int ret; 1765 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1766 1767 /* 1768 * TODO: bypass the initialize in sriov for now 1769 */ 1770 if (amdgpu_sriov_vf(psp->adev)) 1771 return 0; 1772 1773 if (!psp->rap_context.context.bin_desc.size_bytes || 1774 !psp->rap_context.context.bin_desc.start_addr) { 1775 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1776 return 0; 1777 } 1778 1779 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1780 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1781 1782 if (!psp->rap_context.context.initialized) { 1783 ret = psp_rap_init_shared_buf(psp); 1784 if (ret) 1785 return ret; 1786 } 1787 1788 ret = psp_rap_load(psp); 1789 if (!ret) { 1790 psp->rap_context.context.initialized = true; 1791 mutex_init(&psp->rap_context.mutex); 1792 } else 1793 return ret; 1794 1795 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1796 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1797 psp_rap_terminate(psp); 1798 1799 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1800 ret, status); 1801 1802 return ret; 1803 } 1804 1805 return 0; 1806 } 1807 1808 static int psp_rap_terminate(struct psp_context *psp) 1809 { 1810 int ret; 1811 1812 if (!psp->rap_context.context.initialized) 1813 return 0; 1814 1815 ret = psp_rap_unload(psp); 1816 1817 psp->rap_context.context.initialized = false; 1818 1819 /* free rap shared memory */ 1820 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1821 1822 return ret; 1823 } 1824 1825 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1826 { 1827 struct ta_rap_shared_memory *rap_cmd; 1828 int ret = 0; 1829 1830 if (!psp->rap_context.context.initialized) 1831 return 0; 1832 1833 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1834 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1835 return -EINVAL; 1836 1837 mutex_lock(&psp->rap_context.mutex); 1838 1839 rap_cmd = (struct ta_rap_shared_memory *) 1840 psp->rap_context.context.mem_context.shared_buf; 1841 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1842 1843 rap_cmd->cmd_id = ta_cmd_id; 1844 rap_cmd->validation_method_id = METHOD_A; 1845 1846 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1847 if (ret) 1848 goto out_unlock; 1849 1850 if (status) 1851 *status = rap_cmd->rap_status; 1852 1853 out_unlock: 1854 mutex_unlock(&psp->rap_context.mutex); 1855 1856 return ret; 1857 } 1858 // RAP end 1859 1860 /* securedisplay start */ 1861 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1862 { 1863 return psp_ta_init_shared_buf( 1864 psp, &psp->securedisplay_context.context.mem_context); 1865 } 1866 1867 static int psp_securedisplay_load(struct psp_context *psp) 1868 { 1869 return psp_ta_load(psp, &psp->securedisplay_context.context); 1870 } 1871 1872 static int psp_securedisplay_unload(struct psp_context *psp) 1873 { 1874 return psp_ta_unload(psp, &psp->securedisplay_context.context); 1875 } 1876 1877 static int psp_securedisplay_initialize(struct psp_context *psp) 1878 { 1879 int ret; 1880 struct securedisplay_cmd *securedisplay_cmd; 1881 1882 /* 1883 * TODO: bypass the initialize in sriov for now 1884 */ 1885 if (amdgpu_sriov_vf(psp->adev)) 1886 return 0; 1887 1888 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1889 !psp->securedisplay_context.context.bin_desc.start_addr) { 1890 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1891 return 0; 1892 } 1893 1894 psp->securedisplay_context.context.mem_context.shared_mem_size = 1895 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1896 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1897 1898 if (!psp->securedisplay_context.context.initialized) { 1899 ret = psp_securedisplay_init_shared_buf(psp); 1900 if (ret) 1901 return ret; 1902 } 1903 1904 ret = psp_securedisplay_load(psp); 1905 if (!ret) { 1906 psp->securedisplay_context.context.initialized = true; 1907 mutex_init(&psp->securedisplay_context.mutex); 1908 } else 1909 return ret; 1910 1911 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1912 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1913 1914 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1915 if (ret) { 1916 psp_securedisplay_terminate(psp); 1917 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1918 return -EINVAL; 1919 } 1920 1921 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1922 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1923 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1924 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1925 } 1926 1927 return 0; 1928 } 1929 1930 static int psp_securedisplay_terminate(struct psp_context *psp) 1931 { 1932 int ret; 1933 1934 /* 1935 * TODO:bypass the terminate in sriov for now 1936 */ 1937 if (amdgpu_sriov_vf(psp->adev)) 1938 return 0; 1939 1940 if (!psp->securedisplay_context.context.initialized) 1941 return 0; 1942 1943 ret = psp_securedisplay_unload(psp); 1944 if (ret) 1945 return ret; 1946 1947 psp->securedisplay_context.context.initialized = false; 1948 1949 /* free securedisplay shared memory */ 1950 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1951 1952 return ret; 1953 } 1954 1955 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1956 { 1957 int ret; 1958 1959 if (!psp->securedisplay_context.context.initialized) 1960 return -EINVAL; 1961 1962 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1963 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1964 return -EINVAL; 1965 1966 mutex_lock(&psp->securedisplay_context.mutex); 1967 1968 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1969 1970 mutex_unlock(&psp->securedisplay_context.mutex); 1971 1972 return ret; 1973 } 1974 /* SECUREDISPLAY end */ 1975 1976 static int psp_hw_start(struct psp_context *psp) 1977 { 1978 struct amdgpu_device *adev = psp->adev; 1979 int ret; 1980 1981 if (!amdgpu_sriov_vf(adev)) { 1982 if ((is_psp_fw_valid(psp->kdb)) && 1983 (psp->funcs->bootloader_load_kdb != NULL)) { 1984 ret = psp_bootloader_load_kdb(psp); 1985 if (ret) { 1986 DRM_ERROR("PSP load kdb failed!\n"); 1987 return ret; 1988 } 1989 } 1990 1991 if ((is_psp_fw_valid(psp->spl)) && 1992 (psp->funcs->bootloader_load_spl != NULL)) { 1993 ret = psp_bootloader_load_spl(psp); 1994 if (ret) { 1995 DRM_ERROR("PSP load spl failed!\n"); 1996 return ret; 1997 } 1998 } 1999 2000 if ((is_psp_fw_valid(psp->sys)) && 2001 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2002 ret = psp_bootloader_load_sysdrv(psp); 2003 if (ret) { 2004 DRM_ERROR("PSP load sys drv failed!\n"); 2005 return ret; 2006 } 2007 } 2008 2009 if ((is_psp_fw_valid(psp->soc_drv)) && 2010 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2011 ret = psp_bootloader_load_soc_drv(psp); 2012 if (ret) { 2013 DRM_ERROR("PSP load soc drv failed!\n"); 2014 return ret; 2015 } 2016 } 2017 2018 if ((is_psp_fw_valid(psp->intf_drv)) && 2019 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2020 ret = psp_bootloader_load_intf_drv(psp); 2021 if (ret) { 2022 DRM_ERROR("PSP load intf drv failed!\n"); 2023 return ret; 2024 } 2025 } 2026 2027 if ((is_psp_fw_valid(psp->dbg_drv)) && 2028 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2029 ret = psp_bootloader_load_dbg_drv(psp); 2030 if (ret) { 2031 DRM_ERROR("PSP load dbg drv failed!\n"); 2032 return ret; 2033 } 2034 } 2035 2036 if ((is_psp_fw_valid(psp->sos)) && 2037 (psp->funcs->bootloader_load_sos != NULL)) { 2038 ret = psp_bootloader_load_sos(psp); 2039 if (ret) { 2040 DRM_ERROR("PSP load sos failed!\n"); 2041 return ret; 2042 } 2043 } 2044 } 2045 2046 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2047 if (ret) { 2048 DRM_ERROR("PSP create ring failed!\n"); 2049 return ret; 2050 } 2051 2052 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2053 goto skip_pin_bo; 2054 2055 ret = psp_tmr_init(psp); 2056 if (ret) { 2057 DRM_ERROR("PSP tmr init failed!\n"); 2058 return ret; 2059 } 2060 2061 skip_pin_bo: 2062 /* 2063 * For ASICs with DF Cstate management centralized 2064 * to PMFW, TMR setup should be performed after PMFW 2065 * loaded and before other non-psp firmware loaded. 2066 */ 2067 if (psp->pmfw_centralized_cstate_management) { 2068 ret = psp_load_smu_fw(psp); 2069 if (ret) 2070 return ret; 2071 } 2072 2073 ret = psp_tmr_load(psp); 2074 if (ret) { 2075 DRM_ERROR("PSP load tmr failed!\n"); 2076 return ret; 2077 } 2078 2079 return 0; 2080 } 2081 2082 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2083 enum psp_gfx_fw_type *type) 2084 { 2085 switch (ucode->ucode_id) { 2086 case AMDGPU_UCODE_ID_CAP: 2087 *type = GFX_FW_TYPE_CAP; 2088 break; 2089 case AMDGPU_UCODE_ID_SDMA0: 2090 *type = GFX_FW_TYPE_SDMA0; 2091 break; 2092 case AMDGPU_UCODE_ID_SDMA1: 2093 *type = GFX_FW_TYPE_SDMA1; 2094 break; 2095 case AMDGPU_UCODE_ID_SDMA2: 2096 *type = GFX_FW_TYPE_SDMA2; 2097 break; 2098 case AMDGPU_UCODE_ID_SDMA3: 2099 *type = GFX_FW_TYPE_SDMA3; 2100 break; 2101 case AMDGPU_UCODE_ID_SDMA4: 2102 *type = GFX_FW_TYPE_SDMA4; 2103 break; 2104 case AMDGPU_UCODE_ID_SDMA5: 2105 *type = GFX_FW_TYPE_SDMA5; 2106 break; 2107 case AMDGPU_UCODE_ID_SDMA6: 2108 *type = GFX_FW_TYPE_SDMA6; 2109 break; 2110 case AMDGPU_UCODE_ID_SDMA7: 2111 *type = GFX_FW_TYPE_SDMA7; 2112 break; 2113 case AMDGPU_UCODE_ID_CP_MES: 2114 *type = GFX_FW_TYPE_CP_MES; 2115 break; 2116 case AMDGPU_UCODE_ID_CP_MES_DATA: 2117 *type = GFX_FW_TYPE_MES_STACK; 2118 break; 2119 case AMDGPU_UCODE_ID_CP_CE: 2120 *type = GFX_FW_TYPE_CP_CE; 2121 break; 2122 case AMDGPU_UCODE_ID_CP_PFP: 2123 *type = GFX_FW_TYPE_CP_PFP; 2124 break; 2125 case AMDGPU_UCODE_ID_CP_ME: 2126 *type = GFX_FW_TYPE_CP_ME; 2127 break; 2128 case AMDGPU_UCODE_ID_CP_MEC1: 2129 *type = GFX_FW_TYPE_CP_MEC; 2130 break; 2131 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2132 *type = GFX_FW_TYPE_CP_MEC_ME1; 2133 break; 2134 case AMDGPU_UCODE_ID_CP_MEC2: 2135 *type = GFX_FW_TYPE_CP_MEC; 2136 break; 2137 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2138 *type = GFX_FW_TYPE_CP_MEC_ME2; 2139 break; 2140 case AMDGPU_UCODE_ID_RLC_G: 2141 *type = GFX_FW_TYPE_RLC_G; 2142 break; 2143 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2144 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2145 break; 2146 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2147 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2148 break; 2149 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2150 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2151 break; 2152 case AMDGPU_UCODE_ID_RLC_IRAM: 2153 *type = GFX_FW_TYPE_RLC_IRAM; 2154 break; 2155 case AMDGPU_UCODE_ID_RLC_DRAM: 2156 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2157 break; 2158 case AMDGPU_UCODE_ID_SMC: 2159 *type = GFX_FW_TYPE_SMU; 2160 break; 2161 case AMDGPU_UCODE_ID_UVD: 2162 *type = GFX_FW_TYPE_UVD; 2163 break; 2164 case AMDGPU_UCODE_ID_UVD1: 2165 *type = GFX_FW_TYPE_UVD1; 2166 break; 2167 case AMDGPU_UCODE_ID_VCE: 2168 *type = GFX_FW_TYPE_VCE; 2169 break; 2170 case AMDGPU_UCODE_ID_VCN: 2171 *type = GFX_FW_TYPE_VCN; 2172 break; 2173 case AMDGPU_UCODE_ID_VCN1: 2174 *type = GFX_FW_TYPE_VCN1; 2175 break; 2176 case AMDGPU_UCODE_ID_DMCU_ERAM: 2177 *type = GFX_FW_TYPE_DMCU_ERAM; 2178 break; 2179 case AMDGPU_UCODE_ID_DMCU_INTV: 2180 *type = GFX_FW_TYPE_DMCU_ISR; 2181 break; 2182 case AMDGPU_UCODE_ID_VCN0_RAM: 2183 *type = GFX_FW_TYPE_VCN0_RAM; 2184 break; 2185 case AMDGPU_UCODE_ID_VCN1_RAM: 2186 *type = GFX_FW_TYPE_VCN1_RAM; 2187 break; 2188 case AMDGPU_UCODE_ID_DMCUB: 2189 *type = GFX_FW_TYPE_DMUB; 2190 break; 2191 case AMDGPU_UCODE_ID_MAXIMUM: 2192 default: 2193 return -EINVAL; 2194 } 2195 2196 return 0; 2197 } 2198 2199 static void psp_print_fw_hdr(struct psp_context *psp, 2200 struct amdgpu_firmware_info *ucode) 2201 { 2202 struct amdgpu_device *adev = psp->adev; 2203 struct common_firmware_header *hdr; 2204 2205 switch (ucode->ucode_id) { 2206 case AMDGPU_UCODE_ID_SDMA0: 2207 case AMDGPU_UCODE_ID_SDMA1: 2208 case AMDGPU_UCODE_ID_SDMA2: 2209 case AMDGPU_UCODE_ID_SDMA3: 2210 case AMDGPU_UCODE_ID_SDMA4: 2211 case AMDGPU_UCODE_ID_SDMA5: 2212 case AMDGPU_UCODE_ID_SDMA6: 2213 case AMDGPU_UCODE_ID_SDMA7: 2214 hdr = (struct common_firmware_header *) 2215 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2216 amdgpu_ucode_print_sdma_hdr(hdr); 2217 break; 2218 case AMDGPU_UCODE_ID_CP_CE: 2219 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2220 amdgpu_ucode_print_gfx_hdr(hdr); 2221 break; 2222 case AMDGPU_UCODE_ID_CP_PFP: 2223 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2224 amdgpu_ucode_print_gfx_hdr(hdr); 2225 break; 2226 case AMDGPU_UCODE_ID_CP_ME: 2227 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2228 amdgpu_ucode_print_gfx_hdr(hdr); 2229 break; 2230 case AMDGPU_UCODE_ID_CP_MEC1: 2231 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2232 amdgpu_ucode_print_gfx_hdr(hdr); 2233 break; 2234 case AMDGPU_UCODE_ID_RLC_G: 2235 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2236 amdgpu_ucode_print_rlc_hdr(hdr); 2237 break; 2238 case AMDGPU_UCODE_ID_SMC: 2239 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2240 amdgpu_ucode_print_smc_hdr(hdr); 2241 break; 2242 default: 2243 break; 2244 } 2245 } 2246 2247 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2248 struct psp_gfx_cmd_resp *cmd) 2249 { 2250 int ret; 2251 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2252 2253 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2254 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2255 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2256 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2257 2258 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2259 if (ret) 2260 DRM_ERROR("Unknown firmware type\n"); 2261 2262 return ret; 2263 } 2264 2265 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2266 struct amdgpu_firmware_info *ucode) 2267 { 2268 int ret = 0; 2269 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2270 2271 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2272 if (!ret) { 2273 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2274 psp->fence_buf_mc_addr); 2275 } 2276 2277 release_psp_cmd_buf(psp); 2278 2279 return ret; 2280 } 2281 2282 static int psp_load_smu_fw(struct psp_context *psp) 2283 { 2284 int ret; 2285 struct amdgpu_device *adev = psp->adev; 2286 struct amdgpu_firmware_info *ucode = 2287 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2288 struct amdgpu_ras *ras = psp->ras_context.ras; 2289 2290 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2291 return 0; 2292 2293 if ((amdgpu_in_reset(adev) && 2294 ras && adev->ras_enabled && 2295 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2296 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2297 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2298 if (ret) { 2299 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2300 } 2301 } 2302 2303 ret = psp_execute_non_psp_fw_load(psp, ucode); 2304 2305 if (ret) 2306 DRM_ERROR("PSP load smu failed!\n"); 2307 2308 return ret; 2309 } 2310 2311 static bool fw_load_skip_check(struct psp_context *psp, 2312 struct amdgpu_firmware_info *ucode) 2313 { 2314 if (!ucode->fw) 2315 return true; 2316 2317 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2318 (psp_smu_reload_quirk(psp) || 2319 psp->autoload_supported || 2320 psp->pmfw_centralized_cstate_management)) 2321 return true; 2322 2323 if (amdgpu_sriov_vf(psp->adev) && 2324 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2325 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2326 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2327 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2328 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2329 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2330 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2331 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2332 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2333 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2334 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2335 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2336 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2337 /*skip ucode loading in SRIOV VF */ 2338 return true; 2339 2340 if (psp->autoload_supported && 2341 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2342 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2343 /* skip mec JT when autoload is enabled */ 2344 return true; 2345 2346 return false; 2347 } 2348 2349 int psp_load_fw_list(struct psp_context *psp, 2350 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2351 { 2352 int ret = 0, i; 2353 struct amdgpu_firmware_info *ucode; 2354 2355 for (i = 0; i < ucode_count; ++i) { 2356 ucode = ucode_list[i]; 2357 psp_print_fw_hdr(psp, ucode); 2358 ret = psp_execute_non_psp_fw_load(psp, ucode); 2359 if (ret) 2360 return ret; 2361 } 2362 return ret; 2363 } 2364 2365 static int psp_load_non_psp_fw(struct psp_context *psp) 2366 { 2367 int i, ret; 2368 struct amdgpu_firmware_info *ucode; 2369 struct amdgpu_device *adev = psp->adev; 2370 2371 if (psp->autoload_supported && 2372 !psp->pmfw_centralized_cstate_management) { 2373 ret = psp_load_smu_fw(psp); 2374 if (ret) 2375 return ret; 2376 } 2377 2378 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2379 ucode = &adev->firmware.ucode[i]; 2380 2381 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2382 !fw_load_skip_check(psp, ucode)) { 2383 ret = psp_load_smu_fw(psp); 2384 if (ret) 2385 return ret; 2386 continue; 2387 } 2388 2389 if (fw_load_skip_check(psp, ucode)) 2390 continue; 2391 2392 if (psp->autoload_supported && 2393 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2394 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2395 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2396 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2397 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2398 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2399 /* PSP only receive one SDMA fw for sienna_cichlid, 2400 * as all four sdma fw are same */ 2401 continue; 2402 2403 psp_print_fw_hdr(psp, ucode); 2404 2405 ret = psp_execute_non_psp_fw_load(psp, ucode); 2406 if (ret) 2407 return ret; 2408 2409 /* Start rlc autoload after psp recieved all the gfx firmware */ 2410 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2411 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2412 ret = psp_rlc_autoload_start(psp); 2413 if (ret) { 2414 DRM_ERROR("Failed to start rlc autoload\n"); 2415 return ret; 2416 } 2417 } 2418 } 2419 2420 return 0; 2421 } 2422 2423 static int psp_load_fw(struct amdgpu_device *adev) 2424 { 2425 int ret; 2426 struct psp_context *psp = &adev->psp; 2427 2428 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2429 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2430 goto skip_memalloc; 2431 } 2432 2433 if (amdgpu_sriov_vf(adev)) { 2434 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2435 AMDGPU_GEM_DOMAIN_VRAM, 2436 &psp->fw_pri_bo, 2437 &psp->fw_pri_mc_addr, 2438 &psp->fw_pri_buf); 2439 } else { 2440 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2441 AMDGPU_GEM_DOMAIN_GTT, 2442 &psp->fw_pri_bo, 2443 &psp->fw_pri_mc_addr, 2444 &psp->fw_pri_buf); 2445 } 2446 2447 if (ret) 2448 goto failed; 2449 2450 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2451 AMDGPU_GEM_DOMAIN_VRAM, 2452 &psp->fence_buf_bo, 2453 &psp->fence_buf_mc_addr, 2454 &psp->fence_buf); 2455 if (ret) 2456 goto failed; 2457 2458 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2459 AMDGPU_GEM_DOMAIN_VRAM, 2460 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2461 (void **)&psp->cmd_buf_mem); 2462 if (ret) 2463 goto failed; 2464 2465 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2466 2467 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2468 if (ret) { 2469 DRM_ERROR("PSP ring init failed!\n"); 2470 goto failed; 2471 } 2472 2473 skip_memalloc: 2474 ret = psp_hw_start(psp); 2475 if (ret) 2476 goto failed; 2477 2478 ret = psp_load_non_psp_fw(psp); 2479 if (ret) 2480 goto failed; 2481 2482 ret = psp_asd_initialize(psp); 2483 if (ret) { 2484 DRM_ERROR("PSP load asd failed!\n"); 2485 return ret; 2486 } 2487 2488 ret = psp_rl_load(adev); 2489 if (ret) { 2490 DRM_ERROR("PSP load RL failed!\n"); 2491 return ret; 2492 } 2493 2494 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2495 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2496 ret = psp_xgmi_initialize(psp, false, true); 2497 /* Warning the XGMI seesion initialize failure 2498 * Instead of stop driver initialization 2499 */ 2500 if (ret) 2501 dev_err(psp->adev->dev, 2502 "XGMI: Failed to initialize XGMI session\n"); 2503 } 2504 } 2505 2506 if (psp->ta_fw) { 2507 ret = psp_ras_initialize(psp); 2508 if (ret) 2509 dev_err(psp->adev->dev, 2510 "RAS: Failed to initialize RAS\n"); 2511 2512 ret = psp_hdcp_initialize(psp); 2513 if (ret) 2514 dev_err(psp->adev->dev, 2515 "HDCP: Failed to initialize HDCP\n"); 2516 2517 ret = psp_dtm_initialize(psp); 2518 if (ret) 2519 dev_err(psp->adev->dev, 2520 "DTM: Failed to initialize DTM\n"); 2521 2522 ret = psp_rap_initialize(psp); 2523 if (ret) 2524 dev_err(psp->adev->dev, 2525 "RAP: Failed to initialize RAP\n"); 2526 2527 ret = psp_securedisplay_initialize(psp); 2528 if (ret) 2529 dev_err(psp->adev->dev, 2530 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2531 } 2532 2533 return 0; 2534 2535 failed: 2536 /* 2537 * all cleanup jobs (xgmi terminate, ras terminate, 2538 * ring destroy, cmd/fence/fw buffers destory, 2539 * psp->cmd destory) are delayed to psp_hw_fini 2540 */ 2541 return ret; 2542 } 2543 2544 static int psp_hw_init(void *handle) 2545 { 2546 int ret; 2547 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2548 2549 mutex_lock(&adev->firmware.mutex); 2550 /* 2551 * This sequence is just used on hw_init only once, no need on 2552 * resume. 2553 */ 2554 ret = amdgpu_ucode_init_bo(adev); 2555 if (ret) 2556 goto failed; 2557 2558 ret = psp_load_fw(adev); 2559 if (ret) { 2560 DRM_ERROR("PSP firmware loading failed\n"); 2561 goto failed; 2562 } 2563 2564 mutex_unlock(&adev->firmware.mutex); 2565 return 0; 2566 2567 failed: 2568 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2569 mutex_unlock(&adev->firmware.mutex); 2570 return -EINVAL; 2571 } 2572 2573 static int psp_hw_fini(void *handle) 2574 { 2575 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2576 struct psp_context *psp = &adev->psp; 2577 2578 if (psp->ta_fw) { 2579 psp_ras_terminate(psp); 2580 psp_securedisplay_terminate(psp); 2581 psp_rap_terminate(psp); 2582 psp_dtm_terminate(psp); 2583 psp_hdcp_terminate(psp); 2584 } 2585 2586 psp_asd_terminate(psp); 2587 2588 psp_tmr_terminate(psp); 2589 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2590 2591 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2592 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2593 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2594 &psp->fence_buf_mc_addr, &psp->fence_buf); 2595 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2596 (void **)&psp->cmd_buf_mem); 2597 2598 return 0; 2599 } 2600 2601 static int psp_suspend(void *handle) 2602 { 2603 int ret; 2604 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2605 struct psp_context *psp = &adev->psp; 2606 2607 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2608 psp->xgmi_context.context.initialized) { 2609 ret = psp_xgmi_terminate(psp); 2610 if (ret) { 2611 DRM_ERROR("Failed to terminate xgmi ta\n"); 2612 return ret; 2613 } 2614 } 2615 2616 if (psp->ta_fw) { 2617 ret = psp_ras_terminate(psp); 2618 if (ret) { 2619 DRM_ERROR("Failed to terminate ras ta\n"); 2620 return ret; 2621 } 2622 ret = psp_hdcp_terminate(psp); 2623 if (ret) { 2624 DRM_ERROR("Failed to terminate hdcp ta\n"); 2625 return ret; 2626 } 2627 ret = psp_dtm_terminate(psp); 2628 if (ret) { 2629 DRM_ERROR("Failed to terminate dtm ta\n"); 2630 return ret; 2631 } 2632 ret = psp_rap_terminate(psp); 2633 if (ret) { 2634 DRM_ERROR("Failed to terminate rap ta\n"); 2635 return ret; 2636 } 2637 ret = psp_securedisplay_terminate(psp); 2638 if (ret) { 2639 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2640 return ret; 2641 } 2642 } 2643 2644 ret = psp_asd_terminate(psp); 2645 if (ret) { 2646 DRM_ERROR("Failed to terminate asd\n"); 2647 return ret; 2648 } 2649 2650 ret = psp_tmr_terminate(psp); 2651 if (ret) { 2652 DRM_ERROR("Failed to terminate tmr\n"); 2653 return ret; 2654 } 2655 2656 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2657 if (ret) { 2658 DRM_ERROR("PSP ring stop failed\n"); 2659 return ret; 2660 } 2661 2662 return 0; 2663 } 2664 2665 static int psp_resume(void *handle) 2666 { 2667 int ret; 2668 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2669 struct psp_context *psp = &adev->psp; 2670 2671 DRM_INFO("PSP is resuming...\n"); 2672 2673 if (psp->mem_train_ctx.enable_mem_training) { 2674 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2675 if (ret) { 2676 DRM_ERROR("Failed to process memory training!\n"); 2677 return ret; 2678 } 2679 } 2680 2681 mutex_lock(&adev->firmware.mutex); 2682 2683 ret = psp_hw_start(psp); 2684 if (ret) 2685 goto failed; 2686 2687 ret = psp_load_non_psp_fw(psp); 2688 if (ret) 2689 goto failed; 2690 2691 ret = psp_asd_initialize(psp); 2692 if (ret) { 2693 DRM_ERROR("PSP load asd failed!\n"); 2694 goto failed; 2695 } 2696 2697 ret = psp_rl_load(adev); 2698 if (ret) { 2699 dev_err(adev->dev, "PSP load RL failed!\n"); 2700 goto failed; 2701 } 2702 2703 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2704 ret = psp_xgmi_initialize(psp, false, true); 2705 /* Warning the XGMI seesion initialize failure 2706 * Instead of stop driver initialization 2707 */ 2708 if (ret) 2709 dev_err(psp->adev->dev, 2710 "XGMI: Failed to initialize XGMI session\n"); 2711 } 2712 2713 if (psp->ta_fw) { 2714 ret = psp_ras_initialize(psp); 2715 if (ret) 2716 dev_err(psp->adev->dev, 2717 "RAS: Failed to initialize RAS\n"); 2718 2719 ret = psp_hdcp_initialize(psp); 2720 if (ret) 2721 dev_err(psp->adev->dev, 2722 "HDCP: Failed to initialize HDCP\n"); 2723 2724 ret = psp_dtm_initialize(psp); 2725 if (ret) 2726 dev_err(psp->adev->dev, 2727 "DTM: Failed to initialize DTM\n"); 2728 2729 ret = psp_rap_initialize(psp); 2730 if (ret) 2731 dev_err(psp->adev->dev, 2732 "RAP: Failed to initialize RAP\n"); 2733 2734 ret = psp_securedisplay_initialize(psp); 2735 if (ret) 2736 dev_err(psp->adev->dev, 2737 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2738 } 2739 2740 mutex_unlock(&adev->firmware.mutex); 2741 2742 return 0; 2743 2744 failed: 2745 DRM_ERROR("PSP resume failed\n"); 2746 mutex_unlock(&adev->firmware.mutex); 2747 return ret; 2748 } 2749 2750 int psp_gpu_reset(struct amdgpu_device *adev) 2751 { 2752 int ret; 2753 2754 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2755 return 0; 2756 2757 mutex_lock(&adev->psp.mutex); 2758 ret = psp_mode1_reset(&adev->psp); 2759 mutex_unlock(&adev->psp.mutex); 2760 2761 return ret; 2762 } 2763 2764 int psp_rlc_autoload_start(struct psp_context *psp) 2765 { 2766 int ret; 2767 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2768 2769 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2770 2771 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2772 psp->fence_buf_mc_addr); 2773 2774 release_psp_cmd_buf(psp); 2775 2776 return ret; 2777 } 2778 2779 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2780 uint64_t cmd_gpu_addr, int cmd_size) 2781 { 2782 struct amdgpu_firmware_info ucode = {0}; 2783 2784 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2785 AMDGPU_UCODE_ID_VCN0_RAM; 2786 ucode.mc_addr = cmd_gpu_addr; 2787 ucode.ucode_size = cmd_size; 2788 2789 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2790 } 2791 2792 int psp_ring_cmd_submit(struct psp_context *psp, 2793 uint64_t cmd_buf_mc_addr, 2794 uint64_t fence_mc_addr, 2795 int index) 2796 { 2797 unsigned int psp_write_ptr_reg = 0; 2798 struct psp_gfx_rb_frame *write_frame; 2799 struct psp_ring *ring = &psp->km_ring; 2800 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2801 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2802 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2803 struct amdgpu_device *adev = psp->adev; 2804 uint32_t ring_size_dw = ring->ring_size / 4; 2805 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2806 2807 /* KM (GPCOM) prepare write pointer */ 2808 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2809 2810 /* Update KM RB frame pointer to new frame */ 2811 /* write_frame ptr increments by size of rb_frame in bytes */ 2812 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2813 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2814 write_frame = ring_buffer_start; 2815 else 2816 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2817 /* Check invalid write_frame ptr address */ 2818 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2819 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2820 ring_buffer_start, ring_buffer_end, write_frame); 2821 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2822 return -EINVAL; 2823 } 2824 2825 /* Initialize KM RB frame */ 2826 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2827 2828 /* Update KM RB frame */ 2829 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2830 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2831 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2832 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2833 write_frame->fence_value = index; 2834 amdgpu_device_flush_hdp(adev, NULL); 2835 2836 /* Update the write Pointer in DWORDs */ 2837 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2838 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2839 return 0; 2840 } 2841 2842 int psp_init_asd_microcode(struct psp_context *psp, 2843 const char *chip_name) 2844 { 2845 struct amdgpu_device *adev = psp->adev; 2846 char fw_name[PSP_FW_NAME_LEN]; 2847 const struct psp_firmware_header_v1_0 *asd_hdr; 2848 int err = 0; 2849 2850 if (!chip_name) { 2851 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2852 return -EINVAL; 2853 } 2854 2855 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2856 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2857 if (err) 2858 goto out; 2859 2860 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2861 if (err) 2862 goto out; 2863 2864 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2865 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2866 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2867 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2868 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2869 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2870 return 0; 2871 out: 2872 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2873 release_firmware(adev->psp.asd_fw); 2874 adev->psp.asd_fw = NULL; 2875 return err; 2876 } 2877 2878 int psp_init_toc_microcode(struct psp_context *psp, 2879 const char *chip_name) 2880 { 2881 struct amdgpu_device *adev = psp->adev; 2882 char fw_name[PSP_FW_NAME_LEN]; 2883 const struct psp_firmware_header_v1_0 *toc_hdr; 2884 int err = 0; 2885 2886 if (!chip_name) { 2887 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2888 return -EINVAL; 2889 } 2890 2891 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2892 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2893 if (err) 2894 goto out; 2895 2896 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2897 if (err) 2898 goto out; 2899 2900 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2901 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2902 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2903 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2904 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2905 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2906 return 0; 2907 out: 2908 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2909 release_firmware(adev->psp.toc_fw); 2910 adev->psp.toc_fw = NULL; 2911 return err; 2912 } 2913 2914 static int parse_sos_bin_descriptor(struct psp_context *psp, 2915 const struct psp_fw_bin_desc *desc, 2916 const struct psp_firmware_header_v2_0 *sos_hdr) 2917 { 2918 uint8_t *ucode_start_addr = NULL; 2919 2920 if (!psp || !desc || !sos_hdr) 2921 return -EINVAL; 2922 2923 ucode_start_addr = (uint8_t *)sos_hdr + 2924 le32_to_cpu(desc->offset_bytes) + 2925 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2926 2927 switch (desc->fw_type) { 2928 case PSP_FW_TYPE_PSP_SOS: 2929 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2930 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2931 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2932 psp->sos.start_addr = ucode_start_addr; 2933 break; 2934 case PSP_FW_TYPE_PSP_SYS_DRV: 2935 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2936 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2937 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2938 psp->sys.start_addr = ucode_start_addr; 2939 break; 2940 case PSP_FW_TYPE_PSP_KDB: 2941 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2942 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2943 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2944 psp->kdb.start_addr = ucode_start_addr; 2945 break; 2946 case PSP_FW_TYPE_PSP_TOC: 2947 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2948 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2949 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 2950 psp->toc.start_addr = ucode_start_addr; 2951 break; 2952 case PSP_FW_TYPE_PSP_SPL: 2953 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 2954 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 2955 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 2956 psp->spl.start_addr = ucode_start_addr; 2957 break; 2958 case PSP_FW_TYPE_PSP_RL: 2959 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 2960 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 2961 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 2962 psp->rl.start_addr = ucode_start_addr; 2963 break; 2964 case PSP_FW_TYPE_PSP_SOC_DRV: 2965 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 2966 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 2967 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2968 psp->soc_drv.start_addr = ucode_start_addr; 2969 break; 2970 case PSP_FW_TYPE_PSP_INTF_DRV: 2971 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 2972 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 2973 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2974 psp->intf_drv.start_addr = ucode_start_addr; 2975 break; 2976 case PSP_FW_TYPE_PSP_DBG_DRV: 2977 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 2978 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 2979 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2980 psp->dbg_drv.start_addr = ucode_start_addr; 2981 break; 2982 default: 2983 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 2984 break; 2985 } 2986 2987 return 0; 2988 } 2989 2990 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 2991 { 2992 const struct psp_firmware_header_v1_0 *sos_hdr; 2993 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2994 uint8_t *ucode_array_start_addr; 2995 2996 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2997 ucode_array_start_addr = (uint8_t *)sos_hdr + 2998 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2999 3000 if (adev->gmc.xgmi.connected_to_cpu || 3001 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3002 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3003 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3004 3005 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3006 adev->psp.sys.start_addr = ucode_array_start_addr; 3007 3008 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3009 adev->psp.sos.start_addr = ucode_array_start_addr + 3010 le32_to_cpu(sos_hdr->sos.offset_bytes); 3011 adev->psp.xgmi_context.supports_extended_data = false; 3012 } else { 3013 /* Load alternate PSP SOS FW */ 3014 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3015 3016 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3017 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3018 3019 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3020 adev->psp.sys.start_addr = ucode_array_start_addr + 3021 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3022 3023 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3024 adev->psp.sos.start_addr = ucode_array_start_addr + 3025 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3026 adev->psp.xgmi_context.supports_extended_data = true; 3027 } 3028 3029 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3030 dev_warn(adev->dev, "PSP SOS FW not available"); 3031 return -EINVAL; 3032 } 3033 3034 return 0; 3035 } 3036 3037 int psp_init_sos_microcode(struct psp_context *psp, 3038 const char *chip_name) 3039 { 3040 struct amdgpu_device *adev = psp->adev; 3041 char fw_name[PSP_FW_NAME_LEN]; 3042 const struct psp_firmware_header_v1_0 *sos_hdr; 3043 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3044 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3045 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3046 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3047 int err = 0; 3048 uint8_t *ucode_array_start_addr; 3049 int fw_index = 0; 3050 3051 if (!chip_name) { 3052 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3053 return -EINVAL; 3054 } 3055 3056 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3057 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3058 if (err) 3059 goto out; 3060 3061 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3062 if (err) 3063 goto out; 3064 3065 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3066 ucode_array_start_addr = (uint8_t *)sos_hdr + 3067 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3068 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3069 3070 switch (sos_hdr->header.header_version_major) { 3071 case 1: 3072 err = psp_init_sos_base_fw(adev); 3073 if (err) 3074 goto out; 3075 3076 if (sos_hdr->header.header_version_minor == 1) { 3077 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3078 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3079 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3080 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3081 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3082 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3083 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3084 } 3085 if (sos_hdr->header.header_version_minor == 2) { 3086 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3087 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3088 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3089 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3090 } 3091 if (sos_hdr->header.header_version_minor == 3) { 3092 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3093 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3094 adev->psp.toc.start_addr = ucode_array_start_addr + 3095 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3096 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3097 adev->psp.kdb.start_addr = ucode_array_start_addr + 3098 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3099 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3100 adev->psp.spl.start_addr = ucode_array_start_addr + 3101 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3102 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3103 adev->psp.rl.start_addr = ucode_array_start_addr + 3104 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3105 } 3106 break; 3107 case 2: 3108 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3109 3110 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3111 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3112 err = -EINVAL; 3113 goto out; 3114 } 3115 3116 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3117 err = parse_sos_bin_descriptor(psp, 3118 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3119 sos_hdr_v2_0); 3120 if (err) 3121 goto out; 3122 } 3123 break; 3124 default: 3125 dev_err(adev->dev, 3126 "unsupported psp sos firmware\n"); 3127 err = -EINVAL; 3128 goto out; 3129 } 3130 3131 return 0; 3132 out: 3133 dev_err(adev->dev, 3134 "failed to init sos firmware\n"); 3135 release_firmware(adev->psp.sos_fw); 3136 adev->psp.sos_fw = NULL; 3137 3138 return err; 3139 } 3140 3141 static int parse_ta_bin_descriptor(struct psp_context *psp, 3142 const struct psp_fw_bin_desc *desc, 3143 const struct ta_firmware_header_v2_0 *ta_hdr) 3144 { 3145 uint8_t *ucode_start_addr = NULL; 3146 3147 if (!psp || !desc || !ta_hdr) 3148 return -EINVAL; 3149 3150 ucode_start_addr = (uint8_t *)ta_hdr + 3151 le32_to_cpu(desc->offset_bytes) + 3152 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3153 3154 switch (desc->fw_type) { 3155 case TA_FW_TYPE_PSP_ASD: 3156 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3157 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3158 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3159 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3160 break; 3161 case TA_FW_TYPE_PSP_XGMI: 3162 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3163 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3164 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3165 break; 3166 case TA_FW_TYPE_PSP_RAS: 3167 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3168 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3169 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3170 break; 3171 case TA_FW_TYPE_PSP_HDCP: 3172 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3173 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3174 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3175 break; 3176 case TA_FW_TYPE_PSP_DTM: 3177 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3178 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3179 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3180 break; 3181 case TA_FW_TYPE_PSP_RAP: 3182 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3183 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3184 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3185 break; 3186 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3187 psp->securedisplay_context.context.bin_desc.fw_version = 3188 le32_to_cpu(desc->fw_version); 3189 psp->securedisplay_context.context.bin_desc.size_bytes = 3190 le32_to_cpu(desc->size_bytes); 3191 psp->securedisplay_context.context.bin_desc.start_addr = 3192 ucode_start_addr; 3193 break; 3194 default: 3195 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3196 break; 3197 } 3198 3199 return 0; 3200 } 3201 3202 int psp_init_ta_microcode(struct psp_context *psp, 3203 const char *chip_name) 3204 { 3205 struct amdgpu_device *adev = psp->adev; 3206 char fw_name[PSP_FW_NAME_LEN]; 3207 const struct ta_firmware_header_v2_0 *ta_hdr; 3208 int err = 0; 3209 int ta_index = 0; 3210 3211 if (!chip_name) { 3212 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3213 return -EINVAL; 3214 } 3215 3216 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3217 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3218 if (err) 3219 goto out; 3220 3221 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3222 if (err) 3223 goto out; 3224 3225 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3226 3227 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3228 dev_err(adev->dev, "unsupported TA header version\n"); 3229 err = -EINVAL; 3230 goto out; 3231 } 3232 3233 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3234 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3235 err = -EINVAL; 3236 goto out; 3237 } 3238 3239 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3240 err = parse_ta_bin_descriptor(psp, 3241 &ta_hdr->ta_fw_bin[ta_index], 3242 ta_hdr); 3243 if (err) 3244 goto out; 3245 } 3246 3247 return 0; 3248 out: 3249 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3250 release_firmware(adev->psp.ta_fw); 3251 adev->psp.ta_fw = NULL; 3252 return err; 3253 } 3254 3255 int psp_init_cap_microcode(struct psp_context *psp, 3256 const char *chip_name) 3257 { 3258 struct amdgpu_device *adev = psp->adev; 3259 char fw_name[PSP_FW_NAME_LEN]; 3260 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3261 struct amdgpu_firmware_info *info = NULL; 3262 int err = 0; 3263 3264 if (!chip_name) { 3265 dev_err(adev->dev, "invalid chip name for cap microcode\n"); 3266 return -EINVAL; 3267 } 3268 3269 if (!amdgpu_sriov_vf(adev)) { 3270 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3271 return -EINVAL; 3272 } 3273 3274 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3275 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev); 3276 if (err) { 3277 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3278 err = 0; 3279 goto out; 3280 } 3281 3282 err = amdgpu_ucode_validate(adev->psp.cap_fw); 3283 if (err) { 3284 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3285 goto out; 3286 } 3287 3288 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3289 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3290 info->fw = adev->psp.cap_fw; 3291 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3292 adev->psp.cap_fw->data; 3293 adev->firmware.fw_size += ALIGN( 3294 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3295 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3296 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3297 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3298 3299 return 0; 3300 3301 out: 3302 release_firmware(adev->psp.cap_fw); 3303 adev->psp.cap_fw = NULL; 3304 return err; 3305 } 3306 3307 static int psp_set_clockgating_state(void *handle, 3308 enum amd_clockgating_state state) 3309 { 3310 return 0; 3311 } 3312 3313 static int psp_set_powergating_state(void *handle, 3314 enum amd_powergating_state state) 3315 { 3316 return 0; 3317 } 3318 3319 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3320 struct device_attribute *attr, 3321 char *buf) 3322 { 3323 struct drm_device *ddev = dev_get_drvdata(dev); 3324 struct amdgpu_device *adev = drm_to_adev(ddev); 3325 uint32_t fw_ver; 3326 int ret; 3327 3328 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3329 DRM_INFO("PSP block is not ready yet."); 3330 return -EBUSY; 3331 } 3332 3333 mutex_lock(&adev->psp.mutex); 3334 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3335 mutex_unlock(&adev->psp.mutex); 3336 3337 if (ret) { 3338 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3339 return ret; 3340 } 3341 3342 return sysfs_emit(buf, "%x\n", fw_ver); 3343 } 3344 3345 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3346 struct device_attribute *attr, 3347 const char *buf, 3348 size_t count) 3349 { 3350 struct drm_device *ddev = dev_get_drvdata(dev); 3351 struct amdgpu_device *adev = drm_to_adev(ddev); 3352 int ret, idx; 3353 char fw_name[100]; 3354 const struct firmware *usbc_pd_fw; 3355 struct amdgpu_bo *fw_buf_bo = NULL; 3356 uint64_t fw_pri_mc_addr; 3357 void *fw_pri_cpu_addr; 3358 3359 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3360 DRM_INFO("PSP block is not ready yet."); 3361 return -EBUSY; 3362 } 3363 3364 if (!drm_dev_enter(ddev, &idx)) 3365 return -ENODEV; 3366 3367 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3368 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3369 if (ret) 3370 goto fail; 3371 3372 /* LFB address which is aligned to 1MB boundary per PSP request */ 3373 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3374 AMDGPU_GEM_DOMAIN_VRAM, 3375 &fw_buf_bo, 3376 &fw_pri_mc_addr, 3377 &fw_pri_cpu_addr); 3378 if (ret) 3379 goto rel_buf; 3380 3381 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3382 3383 mutex_lock(&adev->psp.mutex); 3384 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3385 mutex_unlock(&adev->psp.mutex); 3386 3387 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3388 3389 rel_buf: 3390 release_firmware(usbc_pd_fw); 3391 fail: 3392 if (ret) { 3393 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3394 count = ret; 3395 } 3396 3397 drm_dev_exit(idx); 3398 return count; 3399 } 3400 3401 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3402 { 3403 int idx; 3404 3405 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3406 return; 3407 3408 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3409 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3410 3411 drm_dev_exit(idx); 3412 } 3413 3414 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3415 psp_usbc_pd_fw_sysfs_read, 3416 psp_usbc_pd_fw_sysfs_write); 3417 3418 int is_psp_fw_valid(struct psp_bin_desc bin) 3419 { 3420 return bin.size_bytes; 3421 } 3422 3423 const struct amd_ip_funcs psp_ip_funcs = { 3424 .name = "psp", 3425 .early_init = psp_early_init, 3426 .late_init = NULL, 3427 .sw_init = psp_sw_init, 3428 .sw_fini = psp_sw_fini, 3429 .hw_init = psp_hw_init, 3430 .hw_fini = psp_hw_fini, 3431 .suspend = psp_suspend, 3432 .resume = psp_resume, 3433 .is_idle = NULL, 3434 .check_soft_reset = NULL, 3435 .wait_for_idle = NULL, 3436 .soft_reset = NULL, 3437 .set_clockgating_state = psp_set_clockgating_state, 3438 .set_powergating_state = psp_set_powergating_state, 3439 }; 3440 3441 static int psp_sysfs_init(struct amdgpu_device *adev) 3442 { 3443 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3444 3445 if (ret) 3446 DRM_ERROR("Failed to create USBC PD FW control file!"); 3447 3448 return ret; 3449 } 3450 3451 static void psp_sysfs_fini(struct amdgpu_device *adev) 3452 { 3453 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3454 } 3455 3456 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3457 { 3458 .type = AMD_IP_BLOCK_TYPE_PSP, 3459 .major = 3, 3460 .minor = 1, 3461 .rev = 0, 3462 .funcs = &psp_ip_funcs, 3463 }; 3464 3465 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3466 { 3467 .type = AMD_IP_BLOCK_TYPE_PSP, 3468 .major = 10, 3469 .minor = 0, 3470 .rev = 0, 3471 .funcs = &psp_ip_funcs, 3472 }; 3473 3474 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3475 { 3476 .type = AMD_IP_BLOCK_TYPE_PSP, 3477 .major = 11, 3478 .minor = 0, 3479 .rev = 0, 3480 .funcs = &psp_ip_funcs, 3481 }; 3482 3483 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3484 .type = AMD_IP_BLOCK_TYPE_PSP, 3485 .major = 11, 3486 .minor = 0, 3487 .rev = 8, 3488 .funcs = &psp_ip_funcs, 3489 }; 3490 3491 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3492 { 3493 .type = AMD_IP_BLOCK_TYPE_PSP, 3494 .major = 12, 3495 .minor = 0, 3496 .rev = 0, 3497 .funcs = &psp_ip_funcs, 3498 }; 3499 3500 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3501 .type = AMD_IP_BLOCK_TYPE_PSP, 3502 .major = 13, 3503 .minor = 0, 3504 .rev = 0, 3505 .funcs = &psp_ip_funcs, 3506 }; 3507