1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 #include "psp_v10_0.h" 34 #include "psp_v11_0.h" 35 #include "psp_v12_0.h" 36 37 #include "amdgpu_ras.h" 38 39 static void psp_set_funcs(struct amdgpu_device *adev); 40 41 static int psp_early_init(void *handle) 42 { 43 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 44 struct psp_context *psp = &adev->psp; 45 46 psp_set_funcs(adev); 47 48 switch (adev->asic_type) { 49 case CHIP_VEGA10: 50 case CHIP_VEGA12: 51 psp_v3_1_set_psp_funcs(psp); 52 psp->autoload_supported = false; 53 break; 54 case CHIP_RAVEN: 55 psp_v10_0_set_psp_funcs(psp); 56 psp->autoload_supported = false; 57 break; 58 case CHIP_VEGA20: 59 case CHIP_ARCTURUS: 60 psp_v11_0_set_psp_funcs(psp); 61 psp->autoload_supported = false; 62 break; 63 case CHIP_NAVI10: 64 case CHIP_NAVI14: 65 case CHIP_NAVI12: 66 psp_v11_0_set_psp_funcs(psp); 67 psp->autoload_supported = true; 68 break; 69 case CHIP_RENOIR: 70 psp_v12_0_set_psp_funcs(psp); 71 break; 72 default: 73 return -EINVAL; 74 } 75 76 psp->adev = adev; 77 78 return 0; 79 } 80 81 static int psp_sw_init(void *handle) 82 { 83 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 84 struct psp_context *psp = &adev->psp; 85 int ret; 86 87 ret = psp_init_microcode(psp); 88 if (ret) { 89 DRM_ERROR("Failed to load psp firmware!\n"); 90 return ret; 91 } 92 93 ret = psp_mem_training_init(psp); 94 if (ret) { 95 DRM_ERROR("Failed to initialize memory training!\n"); 96 return ret; 97 } 98 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 99 if (ret) { 100 DRM_ERROR("Failed to process memory training!\n"); 101 return ret; 102 } 103 104 return 0; 105 } 106 107 static int psp_sw_fini(void *handle) 108 { 109 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 110 111 psp_mem_training_fini(&adev->psp); 112 release_firmware(adev->psp.sos_fw); 113 adev->psp.sos_fw = NULL; 114 release_firmware(adev->psp.asd_fw); 115 adev->psp.asd_fw = NULL; 116 if (adev->psp.ta_fw) { 117 release_firmware(adev->psp.ta_fw); 118 adev->psp.ta_fw = NULL; 119 } 120 return 0; 121 } 122 123 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 124 uint32_t reg_val, uint32_t mask, bool check_changed) 125 { 126 uint32_t val; 127 int i; 128 struct amdgpu_device *adev = psp->adev; 129 130 for (i = 0; i < adev->usec_timeout; i++) { 131 val = RREG32(reg_index); 132 if (check_changed) { 133 if (val != reg_val) 134 return 0; 135 } else { 136 if ((val & mask) == reg_val) 137 return 0; 138 } 139 udelay(1); 140 } 141 142 return -ETIME; 143 } 144 145 static int 146 psp_cmd_submit_buf(struct psp_context *psp, 147 struct amdgpu_firmware_info *ucode, 148 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 149 { 150 int ret; 151 int index; 152 int timeout = 2000; 153 154 mutex_lock(&psp->mutex); 155 156 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 157 158 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 159 160 index = atomic_inc_return(&psp->fence_value); 161 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 162 if (ret) { 163 atomic_dec(&psp->fence_value); 164 mutex_unlock(&psp->mutex); 165 return ret; 166 } 167 168 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 169 while (*((unsigned int *)psp->fence_buf) != index) { 170 if (--timeout == 0) 171 break; 172 /* 173 * Shouldn't wait for timeout when err_event_athub occurs, 174 * because gpu reset thread triggered and lock resource should 175 * be released for psp resume sequence. 176 */ 177 if (amdgpu_ras_intr_triggered()) 178 break; 179 msleep(1); 180 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 181 } 182 183 /* In some cases, psp response status is not 0 even there is no 184 * problem while the command is submitted. Some version of PSP FW 185 * doesn't write 0 to that field. 186 * So here we would like to only print a warning instead of an error 187 * during psp initialization to avoid breaking hw_init and it doesn't 188 * return -EINVAL. 189 */ 190 if (psp->cmd_buf_mem->resp.status || !timeout) { 191 if (ucode) 192 DRM_WARN("failed to load ucode id (%d) ", 193 ucode->ucode_id); 194 DRM_DEBUG_DRIVER("psp command (0x%X) failed and response status is (0x%X)\n", 195 psp->cmd_buf_mem->cmd_id, 196 psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK); 197 if (!timeout) { 198 mutex_unlock(&psp->mutex); 199 return -EINVAL; 200 } 201 } 202 203 /* get xGMI session id from response buffer */ 204 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id; 205 206 if (ucode) { 207 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 208 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 209 } 210 mutex_unlock(&psp->mutex); 211 212 return ret; 213 } 214 215 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 216 struct psp_gfx_cmd_resp *cmd, 217 uint64_t tmr_mc, uint32_t size) 218 { 219 if (psp_support_vmr_ring(psp)) 220 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 221 else 222 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 223 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 224 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 225 cmd->cmd.cmd_setup_tmr.buf_size = size; 226 } 227 228 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 229 uint64_t pri_buf_mc, uint32_t size) 230 { 231 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 232 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 233 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 234 cmd->cmd.cmd_load_toc.toc_size = size; 235 } 236 237 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 238 static int psp_load_toc(struct psp_context *psp, 239 uint32_t *tmr_size) 240 { 241 int ret; 242 struct psp_gfx_cmd_resp *cmd; 243 244 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 245 if (!cmd) 246 return -ENOMEM; 247 /* Copy toc to psp firmware private buffer */ 248 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 249 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size); 250 251 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 252 253 ret = psp_cmd_submit_buf(psp, NULL, cmd, 254 psp->fence_buf_mc_addr); 255 if (!ret) 256 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 257 kfree(cmd); 258 return ret; 259 } 260 261 /* Set up Trusted Memory Region */ 262 static int psp_tmr_init(struct psp_context *psp) 263 { 264 int ret; 265 int tmr_size; 266 void *tmr_buf; 267 void **pptr; 268 269 /* 270 * According to HW engineer, they prefer the TMR address be "naturally 271 * aligned" , e.g. the start address be an integer divide of TMR size. 272 * 273 * Note: this memory need be reserved till the driver 274 * uninitializes. 275 */ 276 tmr_size = PSP_TMR_SIZE; 277 278 /* For ASICs support RLC autoload, psp will parse the toc 279 * and calculate the total size of TMR needed */ 280 if (!amdgpu_sriov_vf(psp->adev) && 281 psp->toc_start_addr && 282 psp->toc_bin_size && 283 psp->fw_pri_buf) { 284 ret = psp_load_toc(psp, &tmr_size); 285 if (ret) { 286 DRM_ERROR("Failed to load toc\n"); 287 return ret; 288 } 289 } 290 291 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 292 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE, 293 AMDGPU_GEM_DOMAIN_VRAM, 294 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 295 296 return ret; 297 } 298 299 static int psp_tmr_load(struct psp_context *psp) 300 { 301 int ret; 302 struct psp_gfx_cmd_resp *cmd; 303 304 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 305 if (!cmd) 306 return -ENOMEM; 307 308 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, 309 amdgpu_bo_size(psp->tmr_bo)); 310 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 311 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 312 313 ret = psp_cmd_submit_buf(psp, NULL, cmd, 314 psp->fence_buf_mc_addr); 315 316 kfree(cmd); 317 318 return ret; 319 } 320 321 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 322 uint64_t asd_mc, uint32_t size) 323 { 324 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 325 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 326 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 327 cmd->cmd.cmd_load_ta.app_len = size; 328 329 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 330 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 331 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 332 } 333 334 static int psp_asd_load(struct psp_context *psp) 335 { 336 int ret; 337 struct psp_gfx_cmd_resp *cmd; 338 339 /* If PSP version doesn't match ASD version, asd loading will be failed. 340 * add workaround to bypass it for sriov now. 341 * TODO: add version check to make it common 342 */ 343 if (amdgpu_sriov_vf(psp->adev)) 344 return 0; 345 346 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 347 if (!cmd) 348 return -ENOMEM; 349 350 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 351 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 352 353 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 354 psp->asd_ucode_size); 355 356 ret = psp_cmd_submit_buf(psp, NULL, cmd, 357 psp->fence_buf_mc_addr); 358 if (!ret) { 359 psp->asd_context.asd_initialized = true; 360 psp->asd_context.session_id = cmd->resp.session_id; 361 } 362 363 kfree(cmd); 364 365 return ret; 366 } 367 368 static void psp_prep_asd_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 369 uint32_t asd_session_id) 370 { 371 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 372 cmd->cmd.cmd_unload_ta.session_id = asd_session_id; 373 } 374 375 static int psp_asd_unload(struct psp_context *psp) 376 { 377 int ret; 378 struct psp_gfx_cmd_resp *cmd; 379 380 if (amdgpu_sriov_vf(psp->adev)) 381 return 0; 382 383 if (!psp->asd_context.asd_initialized) 384 return 0; 385 386 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 387 if (!cmd) 388 return -ENOMEM; 389 390 psp_prep_asd_unload_cmd_buf(cmd, psp->asd_context.session_id); 391 392 ret = psp_cmd_submit_buf(psp, NULL, cmd, 393 psp->fence_buf_mc_addr); 394 if (!ret) 395 psp->asd_context.asd_initialized = false; 396 397 kfree(cmd); 398 399 return ret; 400 } 401 402 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 403 uint32_t id, uint32_t value) 404 { 405 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 406 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 407 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 408 } 409 410 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 411 uint32_t value) 412 { 413 struct psp_gfx_cmd_resp *cmd = NULL; 414 int ret = 0; 415 416 if (reg >= PSP_REG_LAST) 417 return -EINVAL; 418 419 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 420 if (!cmd) 421 return -ENOMEM; 422 423 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 424 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 425 426 kfree(cmd); 427 return ret; 428 } 429 430 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 431 uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared, 432 uint32_t xgmi_ta_size, uint32_t shared_size) 433 { 434 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 435 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc); 436 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc); 437 cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size; 438 439 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared); 440 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared); 441 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 442 } 443 444 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 445 { 446 int ret; 447 448 /* 449 * Allocate 16k memory aligned to 4k from Frame Buffer (local 450 * physical) for xgmi ta <-> Driver 451 */ 452 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 453 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 454 &psp->xgmi_context.xgmi_shared_bo, 455 &psp->xgmi_context.xgmi_shared_mc_addr, 456 &psp->xgmi_context.xgmi_shared_buf); 457 458 return ret; 459 } 460 461 static int psp_xgmi_load(struct psp_context *psp) 462 { 463 int ret; 464 struct psp_gfx_cmd_resp *cmd; 465 466 /* 467 * TODO: bypass the loading in sriov for now 468 */ 469 if (amdgpu_sriov_vf(psp->adev)) 470 return 0; 471 472 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 473 if (!cmd) 474 return -ENOMEM; 475 476 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 477 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 478 479 psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 480 psp->xgmi_context.xgmi_shared_mc_addr, 481 psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE); 482 483 ret = psp_cmd_submit_buf(psp, NULL, cmd, 484 psp->fence_buf_mc_addr); 485 486 if (!ret) { 487 psp->xgmi_context.initialized = 1; 488 psp->xgmi_context.session_id = cmd->resp.session_id; 489 } 490 491 kfree(cmd); 492 493 return ret; 494 } 495 496 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 497 uint32_t xgmi_session_id) 498 { 499 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 500 cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id; 501 } 502 503 static int psp_xgmi_unload(struct psp_context *psp) 504 { 505 int ret; 506 struct psp_gfx_cmd_resp *cmd; 507 508 /* 509 * TODO: bypass the unloading in sriov for now 510 */ 511 if (amdgpu_sriov_vf(psp->adev)) 512 return 0; 513 514 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 515 if (!cmd) 516 return -ENOMEM; 517 518 psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 519 520 ret = psp_cmd_submit_buf(psp, NULL, cmd, 521 psp->fence_buf_mc_addr); 522 523 kfree(cmd); 524 525 return ret; 526 } 527 528 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 529 uint32_t ta_cmd_id, 530 uint32_t xgmi_session_id) 531 { 532 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 533 cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id; 534 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 535 /* Note: cmd_invoke_cmd.buf is not used for now */ 536 } 537 538 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 539 { 540 int ret; 541 struct psp_gfx_cmd_resp *cmd; 542 543 /* 544 * TODO: bypass the loading in sriov for now 545 */ 546 if (amdgpu_sriov_vf(psp->adev)) 547 return 0; 548 549 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 550 if (!cmd) 551 return -ENOMEM; 552 553 psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id, 554 psp->xgmi_context.session_id); 555 556 ret = psp_cmd_submit_buf(psp, NULL, cmd, 557 psp->fence_buf_mc_addr); 558 559 kfree(cmd); 560 561 return ret; 562 } 563 564 static int psp_xgmi_terminate(struct psp_context *psp) 565 { 566 int ret; 567 568 if (!psp->xgmi_context.initialized) 569 return 0; 570 571 ret = psp_xgmi_unload(psp); 572 if (ret) 573 return ret; 574 575 psp->xgmi_context.initialized = 0; 576 577 /* free xgmi shared memory */ 578 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 579 &psp->xgmi_context.xgmi_shared_mc_addr, 580 &psp->xgmi_context.xgmi_shared_buf); 581 582 return 0; 583 } 584 585 static int psp_xgmi_initialize(struct psp_context *psp) 586 { 587 struct ta_xgmi_shared_memory *xgmi_cmd; 588 int ret; 589 590 if (!psp->adev->psp.ta_fw || 591 !psp->adev->psp.ta_xgmi_ucode_size || 592 !psp->adev->psp.ta_xgmi_start_addr) 593 return -ENOENT; 594 595 if (!psp->xgmi_context.initialized) { 596 ret = psp_xgmi_init_shared_buf(psp); 597 if (ret) 598 return ret; 599 } 600 601 /* Load XGMI TA */ 602 ret = psp_xgmi_load(psp); 603 if (ret) 604 return ret; 605 606 /* Initialize XGMI session */ 607 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 608 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 609 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 610 611 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 612 613 return ret; 614 } 615 616 // ras begin 617 static void psp_prep_ras_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 618 uint64_t ras_ta_mc, uint64_t ras_mc_shared, 619 uint32_t ras_ta_size, uint32_t shared_size) 620 { 621 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 622 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ras_ta_mc); 623 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ras_ta_mc); 624 cmd->cmd.cmd_load_ta.app_len = ras_ta_size; 625 626 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ras_mc_shared); 627 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ras_mc_shared); 628 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 629 } 630 631 static int psp_ras_init_shared_buf(struct psp_context *psp) 632 { 633 int ret; 634 635 /* 636 * Allocate 16k memory aligned to 4k from Frame Buffer (local 637 * physical) for ras ta <-> Driver 638 */ 639 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 640 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 641 &psp->ras.ras_shared_bo, 642 &psp->ras.ras_shared_mc_addr, 643 &psp->ras.ras_shared_buf); 644 645 return ret; 646 } 647 648 static int psp_ras_load(struct psp_context *psp) 649 { 650 int ret; 651 struct psp_gfx_cmd_resp *cmd; 652 653 /* 654 * TODO: bypass the loading in sriov for now 655 */ 656 if (amdgpu_sriov_vf(psp->adev)) 657 return 0; 658 659 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 660 if (!cmd) 661 return -ENOMEM; 662 663 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 664 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 665 666 psp_prep_ras_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 667 psp->ras.ras_shared_mc_addr, 668 psp->ta_ras_ucode_size, PSP_RAS_SHARED_MEM_SIZE); 669 670 ret = psp_cmd_submit_buf(psp, NULL, cmd, 671 psp->fence_buf_mc_addr); 672 673 if (!ret) { 674 psp->ras.ras_initialized = 1; 675 psp->ras.session_id = cmd->resp.session_id; 676 } 677 678 kfree(cmd); 679 680 return ret; 681 } 682 683 static void psp_prep_ras_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 684 uint32_t ras_session_id) 685 { 686 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 687 cmd->cmd.cmd_unload_ta.session_id = ras_session_id; 688 } 689 690 static int psp_ras_unload(struct psp_context *psp) 691 { 692 int ret; 693 struct psp_gfx_cmd_resp *cmd; 694 695 /* 696 * TODO: bypass the unloading in sriov for now 697 */ 698 if (amdgpu_sriov_vf(psp->adev)) 699 return 0; 700 701 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 702 if (!cmd) 703 return -ENOMEM; 704 705 psp_prep_ras_ta_unload_cmd_buf(cmd, psp->ras.session_id); 706 707 ret = psp_cmd_submit_buf(psp, NULL, cmd, 708 psp->fence_buf_mc_addr); 709 710 kfree(cmd); 711 712 return ret; 713 } 714 715 static void psp_prep_ras_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 716 uint32_t ta_cmd_id, 717 uint32_t ras_session_id) 718 { 719 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 720 cmd->cmd.cmd_invoke_cmd.session_id = ras_session_id; 721 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 722 /* Note: cmd_invoke_cmd.buf is not used for now */ 723 } 724 725 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 726 { 727 int ret; 728 struct psp_gfx_cmd_resp *cmd; 729 730 /* 731 * TODO: bypass the loading in sriov for now 732 */ 733 if (amdgpu_sriov_vf(psp->adev)) 734 return 0; 735 736 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 737 if (!cmd) 738 return -ENOMEM; 739 740 psp_prep_ras_ta_invoke_cmd_buf(cmd, ta_cmd_id, 741 psp->ras.session_id); 742 743 ret = psp_cmd_submit_buf(psp, NULL, cmd, 744 psp->fence_buf_mc_addr); 745 746 kfree(cmd); 747 748 return ret; 749 } 750 751 int psp_ras_enable_features(struct psp_context *psp, 752 union ta_ras_cmd_input *info, bool enable) 753 { 754 struct ta_ras_shared_memory *ras_cmd; 755 int ret; 756 757 if (!psp->ras.ras_initialized) 758 return -EINVAL; 759 760 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 761 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 762 763 if (enable) 764 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 765 else 766 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 767 768 ras_cmd->ras_in_message = *info; 769 770 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 771 if (ret) 772 return -EINVAL; 773 774 return ras_cmd->ras_status; 775 } 776 777 static int psp_ras_terminate(struct psp_context *psp) 778 { 779 int ret; 780 781 /* 782 * TODO: bypass the terminate in sriov for now 783 */ 784 if (amdgpu_sriov_vf(psp->adev)) 785 return 0; 786 787 if (!psp->ras.ras_initialized) 788 return 0; 789 790 ret = psp_ras_unload(psp); 791 if (ret) 792 return ret; 793 794 psp->ras.ras_initialized = 0; 795 796 /* free ras shared memory */ 797 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 798 &psp->ras.ras_shared_mc_addr, 799 &psp->ras.ras_shared_buf); 800 801 return 0; 802 } 803 804 static int psp_ras_initialize(struct psp_context *psp) 805 { 806 int ret; 807 808 /* 809 * TODO: bypass the initialize in sriov for now 810 */ 811 if (amdgpu_sriov_vf(psp->adev)) 812 return 0; 813 814 if (!psp->adev->psp.ta_ras_ucode_size || 815 !psp->adev->psp.ta_ras_start_addr) { 816 dev_warn(psp->adev->dev, "RAS: ras ta ucode is not available\n"); 817 return 0; 818 } 819 820 if (!psp->ras.ras_initialized) { 821 ret = psp_ras_init_shared_buf(psp); 822 if (ret) 823 return ret; 824 } 825 826 ret = psp_ras_load(psp); 827 if (ret) 828 return ret; 829 830 return 0; 831 } 832 // ras end 833 834 // HDCP start 835 static void psp_prep_hdcp_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 836 uint64_t hdcp_ta_mc, 837 uint64_t hdcp_mc_shared, 838 uint32_t hdcp_ta_size, 839 uint32_t shared_size) 840 { 841 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 842 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(hdcp_ta_mc); 843 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(hdcp_ta_mc); 844 cmd->cmd.cmd_load_ta.app_len = hdcp_ta_size; 845 846 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 847 lower_32_bits(hdcp_mc_shared); 848 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 849 upper_32_bits(hdcp_mc_shared); 850 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 851 } 852 853 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 854 { 855 int ret; 856 857 /* 858 * Allocate 16k memory aligned to 4k from Frame Buffer (local 859 * physical) for hdcp ta <-> Driver 860 */ 861 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 862 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 863 &psp->hdcp_context.hdcp_shared_bo, 864 &psp->hdcp_context.hdcp_shared_mc_addr, 865 &psp->hdcp_context.hdcp_shared_buf); 866 867 return ret; 868 } 869 870 static int psp_hdcp_load(struct psp_context *psp) 871 { 872 int ret; 873 struct psp_gfx_cmd_resp *cmd; 874 875 /* 876 * TODO: bypass the loading in sriov for now 877 */ 878 if (amdgpu_sriov_vf(psp->adev)) 879 return 0; 880 881 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 882 if (!cmd) 883 return -ENOMEM; 884 885 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 886 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr, 887 psp->ta_hdcp_ucode_size); 888 889 psp_prep_hdcp_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 890 psp->hdcp_context.hdcp_shared_mc_addr, 891 psp->ta_hdcp_ucode_size, 892 PSP_HDCP_SHARED_MEM_SIZE); 893 894 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 895 896 if (!ret) { 897 psp->hdcp_context.hdcp_initialized = 1; 898 psp->hdcp_context.session_id = cmd->resp.session_id; 899 } 900 901 kfree(cmd); 902 903 return ret; 904 } 905 static int psp_hdcp_initialize(struct psp_context *psp) 906 { 907 int ret; 908 909 /* 910 * TODO: bypass the initialize in sriov for now 911 */ 912 if (amdgpu_sriov_vf(psp->adev)) 913 return 0; 914 915 if (!psp->adev->psp.ta_hdcp_ucode_size || 916 !psp->adev->psp.ta_hdcp_start_addr) { 917 dev_warn(psp->adev->dev, "HDCP: hdcp ta ucode is not available\n"); 918 return 0; 919 } 920 921 if (!psp->hdcp_context.hdcp_initialized) { 922 ret = psp_hdcp_init_shared_buf(psp); 923 if (ret) 924 return ret; 925 } 926 927 ret = psp_hdcp_load(psp); 928 if (ret) 929 return ret; 930 931 return 0; 932 } 933 static void psp_prep_hdcp_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 934 uint32_t hdcp_session_id) 935 { 936 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 937 cmd->cmd.cmd_unload_ta.session_id = hdcp_session_id; 938 } 939 940 static int psp_hdcp_unload(struct psp_context *psp) 941 { 942 int ret; 943 struct psp_gfx_cmd_resp *cmd; 944 945 /* 946 * TODO: bypass the unloading in sriov for now 947 */ 948 if (amdgpu_sriov_vf(psp->adev)) 949 return 0; 950 951 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 952 if (!cmd) 953 return -ENOMEM; 954 955 psp_prep_hdcp_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 956 957 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 958 959 kfree(cmd); 960 961 return ret; 962 } 963 964 static void psp_prep_hdcp_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 965 uint32_t ta_cmd_id, 966 uint32_t hdcp_session_id) 967 { 968 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 969 cmd->cmd.cmd_invoke_cmd.session_id = hdcp_session_id; 970 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 971 /* Note: cmd_invoke_cmd.buf is not used for now */ 972 } 973 974 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 975 { 976 int ret; 977 struct psp_gfx_cmd_resp *cmd; 978 979 /* 980 * TODO: bypass the loading in sriov for now 981 */ 982 if (amdgpu_sriov_vf(psp->adev)) 983 return 0; 984 985 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 986 if (!cmd) 987 return -ENOMEM; 988 989 psp_prep_hdcp_ta_invoke_cmd_buf(cmd, ta_cmd_id, 990 psp->hdcp_context.session_id); 991 992 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 993 994 kfree(cmd); 995 996 return ret; 997 } 998 999 static int psp_hdcp_terminate(struct psp_context *psp) 1000 { 1001 int ret; 1002 1003 /* 1004 * TODO: bypass the terminate in sriov for now 1005 */ 1006 if (amdgpu_sriov_vf(psp->adev)) 1007 return 0; 1008 1009 if (!psp->hdcp_context.hdcp_initialized) 1010 return 0; 1011 1012 ret = psp_hdcp_unload(psp); 1013 if (ret) 1014 return ret; 1015 1016 psp->hdcp_context.hdcp_initialized = 0; 1017 1018 /* free hdcp shared memory */ 1019 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1020 &psp->hdcp_context.hdcp_shared_mc_addr, 1021 &psp->hdcp_context.hdcp_shared_buf); 1022 1023 return 0; 1024 } 1025 // HDCP end 1026 1027 // DTM start 1028 static void psp_prep_dtm_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1029 uint64_t dtm_ta_mc, 1030 uint64_t dtm_mc_shared, 1031 uint32_t dtm_ta_size, 1032 uint32_t shared_size) 1033 { 1034 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 1035 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(dtm_ta_mc); 1036 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(dtm_ta_mc); 1037 cmd->cmd.cmd_load_ta.app_len = dtm_ta_size; 1038 1039 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(dtm_mc_shared); 1040 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(dtm_mc_shared); 1041 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 1042 } 1043 1044 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1045 { 1046 int ret; 1047 1048 /* 1049 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1050 * physical) for dtm ta <-> Driver 1051 */ 1052 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1053 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1054 &psp->dtm_context.dtm_shared_bo, 1055 &psp->dtm_context.dtm_shared_mc_addr, 1056 &psp->dtm_context.dtm_shared_buf); 1057 1058 return ret; 1059 } 1060 1061 static int psp_dtm_load(struct psp_context *psp) 1062 { 1063 int ret; 1064 struct psp_gfx_cmd_resp *cmd; 1065 1066 /* 1067 * TODO: bypass the loading in sriov for now 1068 */ 1069 if (amdgpu_sriov_vf(psp->adev)) 1070 return 0; 1071 1072 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1073 if (!cmd) 1074 return -ENOMEM; 1075 1076 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1077 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1078 1079 psp_prep_dtm_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 1080 psp->dtm_context.dtm_shared_mc_addr, 1081 psp->ta_dtm_ucode_size, 1082 PSP_DTM_SHARED_MEM_SIZE); 1083 1084 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1085 1086 if (!ret) { 1087 psp->dtm_context.dtm_initialized = 1; 1088 psp->dtm_context.session_id = cmd->resp.session_id; 1089 } 1090 1091 kfree(cmd); 1092 1093 return ret; 1094 } 1095 1096 static int psp_dtm_initialize(struct psp_context *psp) 1097 { 1098 int ret; 1099 1100 /* 1101 * TODO: bypass the initialize in sriov for now 1102 */ 1103 if (amdgpu_sriov_vf(psp->adev)) 1104 return 0; 1105 1106 if (!psp->adev->psp.ta_dtm_ucode_size || 1107 !psp->adev->psp.ta_dtm_start_addr) { 1108 dev_warn(psp->adev->dev, "DTM: dtm ta ucode is not available\n"); 1109 return 0; 1110 } 1111 1112 if (!psp->dtm_context.dtm_initialized) { 1113 ret = psp_dtm_init_shared_buf(psp); 1114 if (ret) 1115 return ret; 1116 } 1117 1118 ret = psp_dtm_load(psp); 1119 if (ret) 1120 return ret; 1121 1122 return 0; 1123 } 1124 1125 static void psp_prep_dtm_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1126 uint32_t ta_cmd_id, 1127 uint32_t dtm_session_id) 1128 { 1129 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1130 cmd->cmd.cmd_invoke_cmd.session_id = dtm_session_id; 1131 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1132 /* Note: cmd_invoke_cmd.buf is not used for now */ 1133 } 1134 1135 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1136 { 1137 int ret; 1138 struct psp_gfx_cmd_resp *cmd; 1139 1140 /* 1141 * TODO: bypass the loading in sriov for now 1142 */ 1143 if (amdgpu_sriov_vf(psp->adev)) 1144 return 0; 1145 1146 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1147 if (!cmd) 1148 return -ENOMEM; 1149 1150 psp_prep_dtm_ta_invoke_cmd_buf(cmd, ta_cmd_id, 1151 psp->dtm_context.session_id); 1152 1153 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1154 1155 kfree(cmd); 1156 1157 return ret; 1158 } 1159 1160 static int psp_dtm_terminate(struct psp_context *psp) 1161 { 1162 int ret; 1163 1164 /* 1165 * TODO: bypass the terminate in sriov for now 1166 */ 1167 if (amdgpu_sriov_vf(psp->adev)) 1168 return 0; 1169 1170 if (!psp->dtm_context.dtm_initialized) 1171 return 0; 1172 1173 ret = psp_hdcp_unload(psp); 1174 if (ret) 1175 return ret; 1176 1177 psp->dtm_context.dtm_initialized = 0; 1178 1179 /* free hdcp shared memory */ 1180 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1181 &psp->dtm_context.dtm_shared_mc_addr, 1182 &psp->dtm_context.dtm_shared_buf); 1183 1184 return 0; 1185 } 1186 // DTM end 1187 1188 static int psp_hw_start(struct psp_context *psp) 1189 { 1190 struct amdgpu_device *adev = psp->adev; 1191 int ret; 1192 1193 if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) { 1194 if (psp->kdb_bin_size && 1195 (psp->funcs->bootloader_load_kdb != NULL)) { 1196 ret = psp_bootloader_load_kdb(psp); 1197 if (ret) { 1198 DRM_ERROR("PSP load kdb failed!\n"); 1199 return ret; 1200 } 1201 } 1202 1203 ret = psp_bootloader_load_sysdrv(psp); 1204 if (ret) { 1205 DRM_ERROR("PSP load sysdrv failed!\n"); 1206 return ret; 1207 } 1208 1209 ret = psp_bootloader_load_sos(psp); 1210 if (ret) { 1211 DRM_ERROR("PSP load sos failed!\n"); 1212 return ret; 1213 } 1214 } 1215 1216 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1217 if (ret) { 1218 DRM_ERROR("PSP create ring failed!\n"); 1219 return ret; 1220 } 1221 1222 ret = psp_tmr_init(psp); 1223 if (ret) { 1224 DRM_ERROR("PSP tmr init failed!\n"); 1225 return ret; 1226 } 1227 1228 ret = psp_tmr_load(psp); 1229 if (ret) { 1230 DRM_ERROR("PSP load tmr failed!\n"); 1231 return ret; 1232 } 1233 1234 return 0; 1235 } 1236 1237 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 1238 enum psp_gfx_fw_type *type) 1239 { 1240 switch (ucode->ucode_id) { 1241 case AMDGPU_UCODE_ID_SDMA0: 1242 *type = GFX_FW_TYPE_SDMA0; 1243 break; 1244 case AMDGPU_UCODE_ID_SDMA1: 1245 *type = GFX_FW_TYPE_SDMA1; 1246 break; 1247 case AMDGPU_UCODE_ID_SDMA2: 1248 *type = GFX_FW_TYPE_SDMA2; 1249 break; 1250 case AMDGPU_UCODE_ID_SDMA3: 1251 *type = GFX_FW_TYPE_SDMA3; 1252 break; 1253 case AMDGPU_UCODE_ID_SDMA4: 1254 *type = GFX_FW_TYPE_SDMA4; 1255 break; 1256 case AMDGPU_UCODE_ID_SDMA5: 1257 *type = GFX_FW_TYPE_SDMA5; 1258 break; 1259 case AMDGPU_UCODE_ID_SDMA6: 1260 *type = GFX_FW_TYPE_SDMA6; 1261 break; 1262 case AMDGPU_UCODE_ID_SDMA7: 1263 *type = GFX_FW_TYPE_SDMA7; 1264 break; 1265 case AMDGPU_UCODE_ID_CP_CE: 1266 *type = GFX_FW_TYPE_CP_CE; 1267 break; 1268 case AMDGPU_UCODE_ID_CP_PFP: 1269 *type = GFX_FW_TYPE_CP_PFP; 1270 break; 1271 case AMDGPU_UCODE_ID_CP_ME: 1272 *type = GFX_FW_TYPE_CP_ME; 1273 break; 1274 case AMDGPU_UCODE_ID_CP_MEC1: 1275 *type = GFX_FW_TYPE_CP_MEC; 1276 break; 1277 case AMDGPU_UCODE_ID_CP_MEC1_JT: 1278 *type = GFX_FW_TYPE_CP_MEC_ME1; 1279 break; 1280 case AMDGPU_UCODE_ID_CP_MEC2: 1281 *type = GFX_FW_TYPE_CP_MEC; 1282 break; 1283 case AMDGPU_UCODE_ID_CP_MEC2_JT: 1284 *type = GFX_FW_TYPE_CP_MEC_ME2; 1285 break; 1286 case AMDGPU_UCODE_ID_RLC_G: 1287 *type = GFX_FW_TYPE_RLC_G; 1288 break; 1289 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 1290 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 1291 break; 1292 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 1293 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 1294 break; 1295 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 1296 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 1297 break; 1298 case AMDGPU_UCODE_ID_SMC: 1299 *type = GFX_FW_TYPE_SMU; 1300 break; 1301 case AMDGPU_UCODE_ID_UVD: 1302 *type = GFX_FW_TYPE_UVD; 1303 break; 1304 case AMDGPU_UCODE_ID_UVD1: 1305 *type = GFX_FW_TYPE_UVD1; 1306 break; 1307 case AMDGPU_UCODE_ID_VCE: 1308 *type = GFX_FW_TYPE_VCE; 1309 break; 1310 case AMDGPU_UCODE_ID_VCN: 1311 *type = GFX_FW_TYPE_VCN; 1312 break; 1313 case AMDGPU_UCODE_ID_DMCU_ERAM: 1314 *type = GFX_FW_TYPE_DMCU_ERAM; 1315 break; 1316 case AMDGPU_UCODE_ID_DMCU_INTV: 1317 *type = GFX_FW_TYPE_DMCU_ISR; 1318 break; 1319 case AMDGPU_UCODE_ID_VCN0_RAM: 1320 *type = GFX_FW_TYPE_VCN0_RAM; 1321 break; 1322 case AMDGPU_UCODE_ID_VCN1_RAM: 1323 *type = GFX_FW_TYPE_VCN1_RAM; 1324 break; 1325 case AMDGPU_UCODE_ID_DMCUB: 1326 *type = GFX_FW_TYPE_DMUB; 1327 break; 1328 case AMDGPU_UCODE_ID_MAXIMUM: 1329 default: 1330 return -EINVAL; 1331 } 1332 1333 return 0; 1334 } 1335 1336 static void psp_print_fw_hdr(struct psp_context *psp, 1337 struct amdgpu_firmware_info *ucode) 1338 { 1339 struct amdgpu_device *adev = psp->adev; 1340 struct common_firmware_header *hdr; 1341 1342 switch (ucode->ucode_id) { 1343 case AMDGPU_UCODE_ID_SDMA0: 1344 case AMDGPU_UCODE_ID_SDMA1: 1345 case AMDGPU_UCODE_ID_SDMA2: 1346 case AMDGPU_UCODE_ID_SDMA3: 1347 case AMDGPU_UCODE_ID_SDMA4: 1348 case AMDGPU_UCODE_ID_SDMA5: 1349 case AMDGPU_UCODE_ID_SDMA6: 1350 case AMDGPU_UCODE_ID_SDMA7: 1351 hdr = (struct common_firmware_header *) 1352 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 1353 amdgpu_ucode_print_sdma_hdr(hdr); 1354 break; 1355 case AMDGPU_UCODE_ID_CP_CE: 1356 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 1357 amdgpu_ucode_print_gfx_hdr(hdr); 1358 break; 1359 case AMDGPU_UCODE_ID_CP_PFP: 1360 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 1361 amdgpu_ucode_print_gfx_hdr(hdr); 1362 break; 1363 case AMDGPU_UCODE_ID_CP_ME: 1364 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 1365 amdgpu_ucode_print_gfx_hdr(hdr); 1366 break; 1367 case AMDGPU_UCODE_ID_CP_MEC1: 1368 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 1369 amdgpu_ucode_print_gfx_hdr(hdr); 1370 break; 1371 case AMDGPU_UCODE_ID_RLC_G: 1372 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 1373 amdgpu_ucode_print_rlc_hdr(hdr); 1374 break; 1375 case AMDGPU_UCODE_ID_SMC: 1376 hdr = (struct common_firmware_header *)adev->pm.fw->data; 1377 amdgpu_ucode_print_smc_hdr(hdr); 1378 break; 1379 default: 1380 break; 1381 } 1382 } 1383 1384 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 1385 struct psp_gfx_cmd_resp *cmd) 1386 { 1387 int ret; 1388 uint64_t fw_mem_mc_addr = ucode->mc_addr; 1389 1390 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 1391 1392 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1393 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 1394 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 1395 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 1396 1397 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 1398 if (ret) 1399 DRM_ERROR("Unknown firmware type\n"); 1400 1401 return ret; 1402 } 1403 1404 static int psp_execute_np_fw_load(struct psp_context *psp, 1405 struct amdgpu_firmware_info *ucode) 1406 { 1407 int ret = 0; 1408 1409 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 1410 if (ret) 1411 return ret; 1412 1413 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 1414 psp->fence_buf_mc_addr); 1415 1416 return ret; 1417 } 1418 1419 static int psp_np_fw_load(struct psp_context *psp) 1420 { 1421 int i, ret; 1422 struct amdgpu_firmware_info *ucode; 1423 struct amdgpu_device* adev = psp->adev; 1424 1425 if (psp->autoload_supported) { 1426 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 1427 if (!ucode->fw) 1428 goto out; 1429 1430 ret = psp_execute_np_fw_load(psp, ucode); 1431 if (ret) 1432 return ret; 1433 } 1434 1435 out: 1436 for (i = 0; i < adev->firmware.max_ucodes; i++) { 1437 ucode = &adev->firmware.ucode[i]; 1438 if (!ucode->fw) 1439 continue; 1440 1441 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 1442 (psp_smu_reload_quirk(psp) || psp->autoload_supported)) 1443 continue; 1444 1445 if (amdgpu_sriov_vf(adev) && 1446 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 1447 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 1448 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 1449 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 1450 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 1451 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 1452 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 1453 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 1454 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 1455 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 1456 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 1457 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) 1458 /*skip ucode loading in SRIOV VF */ 1459 continue; 1460 1461 if (psp->autoload_supported && 1462 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 1463 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 1464 /* skip mec JT when autoload is enabled */ 1465 continue; 1466 1467 psp_print_fw_hdr(psp, ucode); 1468 1469 ret = psp_execute_np_fw_load(psp, ucode); 1470 if (ret) 1471 return ret; 1472 1473 /* Start rlc autoload after psp recieved all the gfx firmware */ 1474 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 1475 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) { 1476 ret = psp_rlc_autoload(psp); 1477 if (ret) { 1478 DRM_ERROR("Failed to start rlc autoload\n"); 1479 return ret; 1480 } 1481 } 1482 #if 0 1483 /* check if firmware loaded sucessfully */ 1484 if (!amdgpu_psp_check_fw_loading_status(adev, i)) 1485 return -EINVAL; 1486 #endif 1487 } 1488 1489 return 0; 1490 } 1491 1492 static int psp_load_fw(struct amdgpu_device *adev) 1493 { 1494 int ret; 1495 struct psp_context *psp = &adev->psp; 1496 1497 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) { 1498 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 1499 goto skip_memalloc; 1500 } 1501 1502 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1503 if (!psp->cmd) 1504 return -ENOMEM; 1505 1506 /* this fw pri bo is not used under SRIOV */ 1507 if (!amdgpu_sriov_vf(psp->adev)) { 1508 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 1509 AMDGPU_GEM_DOMAIN_GTT, 1510 &psp->fw_pri_bo, 1511 &psp->fw_pri_mc_addr, 1512 &psp->fw_pri_buf); 1513 if (ret) 1514 goto failed; 1515 } 1516 1517 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 1518 AMDGPU_GEM_DOMAIN_VRAM, 1519 &psp->fence_buf_bo, 1520 &psp->fence_buf_mc_addr, 1521 &psp->fence_buf); 1522 if (ret) 1523 goto failed; 1524 1525 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 1526 AMDGPU_GEM_DOMAIN_VRAM, 1527 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 1528 (void **)&psp->cmd_buf_mem); 1529 if (ret) 1530 goto failed; 1531 1532 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 1533 1534 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 1535 if (ret) { 1536 DRM_ERROR("PSP ring init failed!\n"); 1537 goto failed; 1538 } 1539 1540 skip_memalloc: 1541 ret = psp_hw_start(psp); 1542 if (ret) 1543 goto failed; 1544 1545 ret = psp_np_fw_load(psp); 1546 if (ret) 1547 goto failed; 1548 1549 ret = psp_asd_load(psp); 1550 if (ret) { 1551 DRM_ERROR("PSP load asd failed!\n"); 1552 return ret; 1553 } 1554 1555 if (adev->gmc.xgmi.num_physical_nodes > 1) { 1556 ret = psp_xgmi_initialize(psp); 1557 /* Warning the XGMI seesion initialize failure 1558 * Instead of stop driver initialization 1559 */ 1560 if (ret) 1561 dev_err(psp->adev->dev, 1562 "XGMI: Failed to initialize XGMI session\n"); 1563 } 1564 1565 if (psp->adev->psp.ta_fw) { 1566 ret = psp_ras_initialize(psp); 1567 if (ret) 1568 dev_err(psp->adev->dev, 1569 "RAS: Failed to initialize RAS\n"); 1570 1571 ret = psp_hdcp_initialize(psp); 1572 if (ret) 1573 dev_err(psp->adev->dev, 1574 "HDCP: Failed to initialize HDCP\n"); 1575 1576 ret = psp_dtm_initialize(psp); 1577 if (ret) 1578 dev_err(psp->adev->dev, 1579 "DTM: Failed to initialize DTM\n"); 1580 } 1581 1582 return 0; 1583 1584 failed: 1585 /* 1586 * all cleanup jobs (xgmi terminate, ras terminate, 1587 * ring destroy, cmd/fence/fw buffers destory, 1588 * psp->cmd destory) are delayed to psp_hw_fini 1589 */ 1590 return ret; 1591 } 1592 1593 static int psp_hw_init(void *handle) 1594 { 1595 int ret; 1596 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1597 1598 mutex_lock(&adev->firmware.mutex); 1599 /* 1600 * This sequence is just used on hw_init only once, no need on 1601 * resume. 1602 */ 1603 ret = amdgpu_ucode_init_bo(adev); 1604 if (ret) 1605 goto failed; 1606 1607 ret = psp_load_fw(adev); 1608 if (ret) { 1609 DRM_ERROR("PSP firmware loading failed\n"); 1610 goto failed; 1611 } 1612 1613 mutex_unlock(&adev->firmware.mutex); 1614 return 0; 1615 1616 failed: 1617 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 1618 mutex_unlock(&adev->firmware.mutex); 1619 return -EINVAL; 1620 } 1621 1622 static int psp_hw_fini(void *handle) 1623 { 1624 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1625 struct psp_context *psp = &adev->psp; 1626 void *tmr_buf; 1627 void **pptr; 1628 1629 if (adev->gmc.xgmi.num_physical_nodes > 1 && 1630 psp->xgmi_context.initialized == 1) 1631 psp_xgmi_terminate(psp); 1632 1633 if (psp->adev->psp.ta_fw) { 1634 psp_ras_terminate(psp); 1635 psp_dtm_terminate(psp); 1636 psp_hdcp_terminate(psp); 1637 } 1638 1639 psp_asd_unload(psp); 1640 1641 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 1642 1643 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 1644 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 1645 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 1646 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 1647 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 1648 &psp->fence_buf_mc_addr, &psp->fence_buf); 1649 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 1650 (void **)&psp->cmd_buf_mem); 1651 1652 kfree(psp->cmd); 1653 psp->cmd = NULL; 1654 1655 return 0; 1656 } 1657 1658 static int psp_suspend(void *handle) 1659 { 1660 int ret; 1661 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1662 struct psp_context *psp = &adev->psp; 1663 1664 if (adev->gmc.xgmi.num_physical_nodes > 1 && 1665 psp->xgmi_context.initialized == 1) { 1666 ret = psp_xgmi_terminate(psp); 1667 if (ret) { 1668 DRM_ERROR("Failed to terminate xgmi ta\n"); 1669 return ret; 1670 } 1671 } 1672 1673 if (psp->adev->psp.ta_fw) { 1674 ret = psp_ras_terminate(psp); 1675 if (ret) { 1676 DRM_ERROR("Failed to terminate ras ta\n"); 1677 return ret; 1678 } 1679 ret = psp_hdcp_terminate(psp); 1680 if (ret) { 1681 DRM_ERROR("Failed to terminate hdcp ta\n"); 1682 return ret; 1683 } 1684 ret = psp_dtm_terminate(psp); 1685 if (ret) { 1686 DRM_ERROR("Failed to terminate dtm ta\n"); 1687 return ret; 1688 } 1689 } 1690 1691 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 1692 if (ret) { 1693 DRM_ERROR("PSP ring stop failed\n"); 1694 return ret; 1695 } 1696 1697 return 0; 1698 } 1699 1700 static int psp_resume(void *handle) 1701 { 1702 int ret; 1703 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1704 struct psp_context *psp = &adev->psp; 1705 1706 DRM_INFO("PSP is resuming...\n"); 1707 1708 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 1709 if (ret) { 1710 DRM_ERROR("Failed to process memory training!\n"); 1711 return ret; 1712 } 1713 1714 mutex_lock(&adev->firmware.mutex); 1715 1716 ret = psp_hw_start(psp); 1717 if (ret) 1718 goto failed; 1719 1720 ret = psp_np_fw_load(psp); 1721 if (ret) 1722 goto failed; 1723 1724 mutex_unlock(&adev->firmware.mutex); 1725 1726 return 0; 1727 1728 failed: 1729 DRM_ERROR("PSP resume failed\n"); 1730 mutex_unlock(&adev->firmware.mutex); 1731 return ret; 1732 } 1733 1734 int psp_gpu_reset(struct amdgpu_device *adev) 1735 { 1736 int ret; 1737 1738 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 1739 return 0; 1740 1741 mutex_lock(&adev->psp.mutex); 1742 ret = psp_mode1_reset(&adev->psp); 1743 mutex_unlock(&adev->psp.mutex); 1744 1745 return ret; 1746 } 1747 1748 int psp_rlc_autoload_start(struct psp_context *psp) 1749 { 1750 int ret; 1751 struct psp_gfx_cmd_resp *cmd; 1752 1753 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1754 if (!cmd) 1755 return -ENOMEM; 1756 1757 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 1758 1759 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1760 psp->fence_buf_mc_addr); 1761 kfree(cmd); 1762 return ret; 1763 } 1764 1765 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 1766 uint64_t cmd_gpu_addr, int cmd_size) 1767 { 1768 struct amdgpu_firmware_info ucode = {0}; 1769 1770 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 1771 AMDGPU_UCODE_ID_VCN0_RAM; 1772 ucode.mc_addr = cmd_gpu_addr; 1773 ucode.ucode_size = cmd_size; 1774 1775 return psp_execute_np_fw_load(&adev->psp, &ucode); 1776 } 1777 1778 int psp_ring_cmd_submit(struct psp_context *psp, 1779 uint64_t cmd_buf_mc_addr, 1780 uint64_t fence_mc_addr, 1781 int index) 1782 { 1783 unsigned int psp_write_ptr_reg = 0; 1784 struct psp_gfx_rb_frame *write_frame; 1785 struct psp_ring *ring = &psp->km_ring; 1786 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 1787 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 1788 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 1789 struct amdgpu_device *adev = psp->adev; 1790 uint32_t ring_size_dw = ring->ring_size / 4; 1791 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 1792 1793 /* KM (GPCOM) prepare write pointer */ 1794 psp_write_ptr_reg = psp_ring_get_wptr(psp); 1795 1796 /* Update KM RB frame pointer to new frame */ 1797 /* write_frame ptr increments by size of rb_frame in bytes */ 1798 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 1799 if ((psp_write_ptr_reg % ring_size_dw) == 0) 1800 write_frame = ring_buffer_start; 1801 else 1802 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 1803 /* Check invalid write_frame ptr address */ 1804 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 1805 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 1806 ring_buffer_start, ring_buffer_end, write_frame); 1807 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 1808 return -EINVAL; 1809 } 1810 1811 /* Initialize KM RB frame */ 1812 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 1813 1814 /* Update KM RB frame */ 1815 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 1816 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 1817 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 1818 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 1819 write_frame->fence_value = index; 1820 amdgpu_asic_flush_hdp(adev, NULL); 1821 1822 /* Update the write Pointer in DWORDs */ 1823 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 1824 psp_ring_set_wptr(psp, psp_write_ptr_reg); 1825 return 0; 1826 } 1827 1828 static bool psp_check_fw_loading_status(struct amdgpu_device *adev, 1829 enum AMDGPU_UCODE_ID ucode_type) 1830 { 1831 struct amdgpu_firmware_info *ucode = NULL; 1832 1833 if (!adev->firmware.fw_size) 1834 return false; 1835 1836 ucode = &adev->firmware.ucode[ucode_type]; 1837 if (!ucode->fw || !ucode->ucode_size) 1838 return false; 1839 1840 return psp_compare_sram_data(&adev->psp, ucode, ucode_type); 1841 } 1842 1843 static int psp_set_clockgating_state(void *handle, 1844 enum amd_clockgating_state state) 1845 { 1846 return 0; 1847 } 1848 1849 static int psp_set_powergating_state(void *handle, 1850 enum amd_powergating_state state) 1851 { 1852 return 0; 1853 } 1854 1855 const struct amd_ip_funcs psp_ip_funcs = { 1856 .name = "psp", 1857 .early_init = psp_early_init, 1858 .late_init = NULL, 1859 .sw_init = psp_sw_init, 1860 .sw_fini = psp_sw_fini, 1861 .hw_init = psp_hw_init, 1862 .hw_fini = psp_hw_fini, 1863 .suspend = psp_suspend, 1864 .resume = psp_resume, 1865 .is_idle = NULL, 1866 .check_soft_reset = NULL, 1867 .wait_for_idle = NULL, 1868 .soft_reset = NULL, 1869 .set_clockgating_state = psp_set_clockgating_state, 1870 .set_powergating_state = psp_set_powergating_state, 1871 }; 1872 1873 static const struct amdgpu_psp_funcs psp_funcs = { 1874 .check_fw_loading_status = psp_check_fw_loading_status, 1875 }; 1876 1877 static void psp_set_funcs(struct amdgpu_device *adev) 1878 { 1879 if (NULL == adev->firmware.funcs) 1880 adev->firmware.funcs = &psp_funcs; 1881 } 1882 1883 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 1884 { 1885 .type = AMD_IP_BLOCK_TYPE_PSP, 1886 .major = 3, 1887 .minor = 1, 1888 .rev = 0, 1889 .funcs = &psp_ip_funcs, 1890 }; 1891 1892 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 1893 { 1894 .type = AMD_IP_BLOCK_TYPE_PSP, 1895 .major = 10, 1896 .minor = 0, 1897 .rev = 0, 1898 .funcs = &psp_ip_funcs, 1899 }; 1900 1901 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 1902 { 1903 .type = AMD_IP_BLOCK_TYPE_PSP, 1904 .major = 11, 1905 .minor = 0, 1906 .rev = 0, 1907 .funcs = &psp_ip_funcs, 1908 }; 1909 1910 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 1911 { 1912 .type = AMD_IP_BLOCK_TYPE_PSP, 1913 .major = 12, 1914 .minor = 0, 1915 .rev = 0, 1916 .funcs = &psp_ip_funcs, 1917 }; 1918