1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 42 #include "amdgpu_ras.h" 43 #include "amdgpu_securedisplay.h" 44 #include "amdgpu_atomfirmware.h" 45 46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 47 48 static int psp_sysfs_init(struct amdgpu_device *adev); 49 static void psp_sysfs_fini(struct amdgpu_device *adev); 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 static int psp_ring_init(struct psp_context *psp, 56 enum psp_ring_type ring_type) 57 { 58 int ret = 0; 59 struct psp_ring *ring; 60 struct amdgpu_device *adev = psp->adev; 61 62 ring = &psp->km_ring; 63 64 ring->ring_type = ring_type; 65 66 /* allocate 4k Page of Local Frame Buffer memory for ring */ 67 ring->ring_size = 0x1000; 68 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 69 AMDGPU_GEM_DOMAIN_VRAM | 70 AMDGPU_GEM_DOMAIN_GTT, 71 &adev->firmware.rbuf, 72 &ring->ring_mem_mc_addr, 73 (void **)&ring->ring_mem); 74 if (ret) { 75 ring->ring_size = 0; 76 return ret; 77 } 78 79 return 0; 80 } 81 82 /* 83 * Due to DF Cstate management centralized to PMFW, the firmware 84 * loading sequence will be updated as below: 85 * - Load KDB 86 * - Load SYS_DRV 87 * - Load tOS 88 * - Load PMFW 89 * - Setup TMR 90 * - Load other non-psp fw 91 * - Load ASD 92 * - Load XGMI/RAS/HDCP/DTM TA if any 93 * 94 * This new sequence is required for 95 * - Arcturus and onwards 96 */ 97 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 98 { 99 struct amdgpu_device *adev = psp->adev; 100 101 if (amdgpu_sriov_vf(adev)) { 102 psp->pmfw_centralized_cstate_management = false; 103 return; 104 } 105 106 switch (adev->ip_versions[MP0_HWIP][0]) { 107 case IP_VERSION(11, 0, 0): 108 case IP_VERSION(11, 0, 4): 109 case IP_VERSION(11, 0, 5): 110 case IP_VERSION(11, 0, 7): 111 case IP_VERSION(11, 0, 9): 112 case IP_VERSION(11, 0, 11): 113 case IP_VERSION(11, 0, 12): 114 case IP_VERSION(11, 0, 13): 115 case IP_VERSION(13, 0, 0): 116 case IP_VERSION(13, 0, 2): 117 case IP_VERSION(13, 0, 7): 118 psp->pmfw_centralized_cstate_management = true; 119 break; 120 default: 121 psp->pmfw_centralized_cstate_management = false; 122 break; 123 } 124 } 125 126 static int psp_init_sriov_microcode(struct psp_context *psp) 127 { 128 struct amdgpu_device *adev = psp->adev; 129 char ucode_prefix[30]; 130 int ret = 0; 131 132 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 133 134 switch (adev->ip_versions[MP0_HWIP][0]) { 135 case IP_VERSION(9, 0, 0): 136 case IP_VERSION(11, 0, 7): 137 case IP_VERSION(11, 0, 9): 138 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 139 ret = psp_init_cap_microcode(psp, ucode_prefix); 140 break; 141 case IP_VERSION(13, 0, 2): 142 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 143 ret = psp_init_cap_microcode(psp, ucode_prefix); 144 ret &= psp_init_ta_microcode(psp, ucode_prefix); 145 break; 146 case IP_VERSION(13, 0, 0): 147 adev->virt.autoload_ucode_id = 0; 148 break; 149 case IP_VERSION(13, 0, 10): 150 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 151 ret = psp_init_cap_microcode(psp, ucode_prefix); 152 break; 153 default: 154 return -EINVAL; 155 } 156 return ret; 157 } 158 159 static int psp_early_init(void *handle) 160 { 161 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 162 struct psp_context *psp = &adev->psp; 163 164 switch (adev->ip_versions[MP0_HWIP][0]) { 165 case IP_VERSION(9, 0, 0): 166 psp_v3_1_set_psp_funcs(psp); 167 psp->autoload_supported = false; 168 break; 169 case IP_VERSION(10, 0, 0): 170 case IP_VERSION(10, 0, 1): 171 psp_v10_0_set_psp_funcs(psp); 172 psp->autoload_supported = false; 173 break; 174 case IP_VERSION(11, 0, 2): 175 case IP_VERSION(11, 0, 4): 176 psp_v11_0_set_psp_funcs(psp); 177 psp->autoload_supported = false; 178 break; 179 case IP_VERSION(11, 0, 0): 180 case IP_VERSION(11, 0, 5): 181 case IP_VERSION(11, 0, 9): 182 case IP_VERSION(11, 0, 7): 183 case IP_VERSION(11, 0, 11): 184 case IP_VERSION(11, 5, 0): 185 case IP_VERSION(11, 0, 12): 186 case IP_VERSION(11, 0, 13): 187 psp_v11_0_set_psp_funcs(psp); 188 psp->autoload_supported = true; 189 break; 190 case IP_VERSION(11, 0, 3): 191 case IP_VERSION(12, 0, 1): 192 psp_v12_0_set_psp_funcs(psp); 193 break; 194 case IP_VERSION(13, 0, 2): 195 case IP_VERSION(13, 0, 6): 196 psp_v13_0_set_psp_funcs(psp); 197 break; 198 case IP_VERSION(13, 0, 1): 199 case IP_VERSION(13, 0, 3): 200 case IP_VERSION(13, 0, 5): 201 case IP_VERSION(13, 0, 8): 202 case IP_VERSION(13, 0, 10): 203 case IP_VERSION(13, 0, 11): 204 psp_v13_0_set_psp_funcs(psp); 205 psp->autoload_supported = true; 206 break; 207 case IP_VERSION(11, 0, 8): 208 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 209 psp_v11_0_8_set_psp_funcs(psp); 210 psp->autoload_supported = false; 211 } 212 break; 213 case IP_VERSION(13, 0, 0): 214 case IP_VERSION(13, 0, 7): 215 psp_v13_0_set_psp_funcs(psp); 216 psp->autoload_supported = true; 217 break; 218 case IP_VERSION(13, 0, 4): 219 psp_v13_0_4_set_psp_funcs(psp); 220 psp->autoload_supported = true; 221 break; 222 default: 223 return -EINVAL; 224 } 225 226 psp->adev = adev; 227 228 psp_check_pmfw_centralized_cstate_management(psp); 229 230 if (amdgpu_sriov_vf(adev)) 231 return psp_init_sriov_microcode(psp); 232 else 233 return psp_init_microcode(psp); 234 } 235 236 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 237 { 238 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 239 &mem_ctx->shared_buf); 240 mem_ctx->shared_bo = NULL; 241 } 242 243 static void psp_free_shared_bufs(struct psp_context *psp) 244 { 245 void *tmr_buf; 246 void **pptr; 247 248 /* free TMR memory buffer */ 249 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 250 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 251 psp->tmr_bo = NULL; 252 253 /* free xgmi shared memory */ 254 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 255 256 /* free ras shared memory */ 257 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 258 259 /* free hdcp shared memory */ 260 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 261 262 /* free dtm shared memory */ 263 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 264 265 /* free rap shared memory */ 266 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 267 268 /* free securedisplay shared memory */ 269 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 270 271 272 } 273 274 static void psp_memory_training_fini(struct psp_context *psp) 275 { 276 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 277 278 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 279 kfree(ctx->sys_cache); 280 ctx->sys_cache = NULL; 281 } 282 283 static int psp_memory_training_init(struct psp_context *psp) 284 { 285 int ret; 286 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 287 288 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 289 DRM_DEBUG("memory training is not supported!\n"); 290 return 0; 291 } 292 293 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 294 if (ctx->sys_cache == NULL) { 295 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 296 ret = -ENOMEM; 297 goto Err_out; 298 } 299 300 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 301 ctx->train_data_size, 302 ctx->p2c_train_data_offset, 303 ctx->c2p_train_data_offset); 304 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 305 return 0; 306 307 Err_out: 308 psp_memory_training_fini(psp); 309 return ret; 310 } 311 312 /* 313 * Helper funciton to query psp runtime database entry 314 * 315 * @adev: amdgpu_device pointer 316 * @entry_type: the type of psp runtime database entry 317 * @db_entry: runtime database entry pointer 318 * 319 * Return false if runtime database doesn't exit or entry is invalid 320 * or true if the specific database entry is found, and copy to @db_entry 321 */ 322 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 323 enum psp_runtime_entry_type entry_type, 324 void *db_entry) 325 { 326 uint64_t db_header_pos, db_dir_pos; 327 struct psp_runtime_data_header db_header = {0}; 328 struct psp_runtime_data_directory db_dir = {0}; 329 bool ret = false; 330 int i; 331 332 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 333 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 334 335 /* read runtime db header from vram */ 336 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 337 sizeof(struct psp_runtime_data_header), false); 338 339 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 340 /* runtime db doesn't exist, exit */ 341 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 342 return false; 343 } 344 345 /* read runtime database entry from vram */ 346 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 347 sizeof(struct psp_runtime_data_directory), false); 348 349 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 350 /* invalid db entry count, exit */ 351 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 352 return false; 353 } 354 355 /* look up for requested entry type */ 356 for (i = 0; i < db_dir.entry_count && !ret; i++) { 357 if (db_dir.entry_list[i].entry_type == entry_type) { 358 switch (entry_type) { 359 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 360 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 361 /* invalid db entry size */ 362 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 363 return false; 364 } 365 /* read runtime database entry */ 366 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 367 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 368 ret = true; 369 break; 370 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 371 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 372 /* invalid db entry size */ 373 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 374 return false; 375 } 376 /* read runtime database entry */ 377 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 378 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 379 ret = true; 380 break; 381 default: 382 ret = false; 383 break; 384 } 385 } 386 } 387 388 return ret; 389 } 390 391 static int psp_sw_init(void *handle) 392 { 393 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 394 struct psp_context *psp = &adev->psp; 395 int ret; 396 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 397 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 398 struct psp_runtime_scpm_entry scpm_entry; 399 400 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 401 if (!psp->cmd) { 402 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 403 ret = -ENOMEM; 404 } 405 406 adev->psp.xgmi_context.supports_extended_data = 407 !adev->gmc.xgmi.connected_to_cpu && 408 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 409 410 memset(&scpm_entry, 0, sizeof(scpm_entry)); 411 if ((psp_get_runtime_db_entry(adev, 412 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 413 &scpm_entry)) && 414 (scpm_entry.scpm_status != SCPM_DISABLE)) { 415 adev->scpm_enabled = true; 416 adev->scpm_status = scpm_entry.scpm_status; 417 } else { 418 adev->scpm_enabled = false; 419 adev->scpm_status = SCPM_DISABLE; 420 } 421 422 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 423 424 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 425 if (psp_get_runtime_db_entry(adev, 426 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 427 &boot_cfg_entry)) { 428 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 429 if ((psp->boot_cfg_bitmask) & 430 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 431 /* If psp runtime database exists, then 432 * only enable two stage memory training 433 * when TWO_STAGE_DRAM_TRAINING bit is set 434 * in runtime database */ 435 mem_training_ctx->enable_mem_training = true; 436 } 437 438 } else { 439 /* If psp runtime database doesn't exist or 440 * is invalid, force enable two stage memory 441 * training */ 442 mem_training_ctx->enable_mem_training = true; 443 } 444 445 if (mem_training_ctx->enable_mem_training) { 446 ret = psp_memory_training_init(psp); 447 if (ret) { 448 DRM_ERROR("Failed to initialize memory training!\n"); 449 return ret; 450 } 451 452 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 453 if (ret) { 454 DRM_ERROR("Failed to process memory training!\n"); 455 return ret; 456 } 457 } 458 459 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 460 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 461 ret = psp_sysfs_init(adev); 462 if (ret) 463 return ret; 464 } 465 466 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 467 amdgpu_sriov_vf(adev) ? 468 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 469 &psp->fw_pri_bo, 470 &psp->fw_pri_mc_addr, 471 &psp->fw_pri_buf); 472 if (ret) 473 return ret; 474 475 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 476 AMDGPU_GEM_DOMAIN_VRAM, 477 &psp->fence_buf_bo, 478 &psp->fence_buf_mc_addr, 479 &psp->fence_buf); 480 if (ret) 481 goto failed1; 482 483 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 484 AMDGPU_GEM_DOMAIN_VRAM, 485 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 486 (void **)&psp->cmd_buf_mem); 487 if (ret) 488 goto failed2; 489 490 return 0; 491 492 failed2: 493 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 494 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 495 failed1: 496 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 497 &psp->fence_buf_mc_addr, &psp->fence_buf); 498 return ret; 499 } 500 501 static int psp_sw_fini(void *handle) 502 { 503 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 504 struct psp_context *psp = &adev->psp; 505 struct psp_gfx_cmd_resp *cmd = psp->cmd; 506 507 psp_memory_training_fini(psp); 508 509 amdgpu_ucode_release(&psp->sos_fw); 510 amdgpu_ucode_release(&psp->asd_fw); 511 amdgpu_ucode_release(&psp->ta_fw); 512 amdgpu_ucode_release(&psp->cap_fw); 513 amdgpu_ucode_release(&psp->toc_fw); 514 515 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 516 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 517 psp_sysfs_fini(adev); 518 519 kfree(cmd); 520 cmd = NULL; 521 522 psp_free_shared_bufs(psp); 523 524 if (psp->km_ring.ring_mem) 525 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 526 &psp->km_ring.ring_mem_mc_addr, 527 (void **)&psp->km_ring.ring_mem); 528 529 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 530 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 531 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 532 &psp->fence_buf_mc_addr, &psp->fence_buf); 533 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 534 (void **)&psp->cmd_buf_mem); 535 536 return 0; 537 } 538 539 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 540 uint32_t reg_val, uint32_t mask, bool check_changed) 541 { 542 uint32_t val; 543 int i; 544 struct amdgpu_device *adev = psp->adev; 545 546 if (psp->adev->no_hw_access) 547 return 0; 548 549 for (i = 0; i < adev->usec_timeout; i++) { 550 val = RREG32(reg_index); 551 if (check_changed) { 552 if (val != reg_val) 553 return 0; 554 } else { 555 if ((val & mask) == reg_val) 556 return 0; 557 } 558 udelay(1); 559 } 560 561 return -ETIME; 562 } 563 564 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 565 { 566 switch (cmd_id) { 567 case GFX_CMD_ID_LOAD_TA: 568 return "LOAD_TA"; 569 case GFX_CMD_ID_UNLOAD_TA: 570 return "UNLOAD_TA"; 571 case GFX_CMD_ID_INVOKE_CMD: 572 return "INVOKE_CMD"; 573 case GFX_CMD_ID_LOAD_ASD: 574 return "LOAD_ASD"; 575 case GFX_CMD_ID_SETUP_TMR: 576 return "SETUP_TMR"; 577 case GFX_CMD_ID_LOAD_IP_FW: 578 return "LOAD_IP_FW"; 579 case GFX_CMD_ID_DESTROY_TMR: 580 return "DESTROY_TMR"; 581 case GFX_CMD_ID_SAVE_RESTORE: 582 return "SAVE_RESTORE_IP_FW"; 583 case GFX_CMD_ID_SETUP_VMR: 584 return "SETUP_VMR"; 585 case GFX_CMD_ID_DESTROY_VMR: 586 return "DESTROY_VMR"; 587 case GFX_CMD_ID_PROG_REG: 588 return "PROG_REG"; 589 case GFX_CMD_ID_GET_FW_ATTESTATION: 590 return "GET_FW_ATTESTATION"; 591 case GFX_CMD_ID_LOAD_TOC: 592 return "ID_LOAD_TOC"; 593 case GFX_CMD_ID_AUTOLOAD_RLC: 594 return "AUTOLOAD_RLC"; 595 case GFX_CMD_ID_BOOT_CFG: 596 return "BOOT_CFG"; 597 default: 598 return "UNKNOWN CMD"; 599 } 600 } 601 602 static int 603 psp_cmd_submit_buf(struct psp_context *psp, 604 struct amdgpu_firmware_info *ucode, 605 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 606 { 607 int ret; 608 int index; 609 int timeout = 20000; 610 bool ras_intr = false; 611 bool skip_unsupport = false; 612 613 if (psp->adev->no_hw_access) 614 return 0; 615 616 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 617 618 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 619 620 index = atomic_inc_return(&psp->fence_value); 621 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 622 if (ret) { 623 atomic_dec(&psp->fence_value); 624 goto exit; 625 } 626 627 amdgpu_device_invalidate_hdp(psp->adev, NULL); 628 while (*((unsigned int *)psp->fence_buf) != index) { 629 if (--timeout == 0) 630 break; 631 /* 632 * Shouldn't wait for timeout when err_event_athub occurs, 633 * because gpu reset thread triggered and lock resource should 634 * be released for psp resume sequence. 635 */ 636 ras_intr = amdgpu_ras_intr_triggered(); 637 if (ras_intr) 638 break; 639 usleep_range(10, 100); 640 amdgpu_device_invalidate_hdp(psp->adev, NULL); 641 } 642 643 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 644 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 645 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 646 647 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 648 649 /* In some cases, psp response status is not 0 even there is no 650 * problem while the command is submitted. Some version of PSP FW 651 * doesn't write 0 to that field. 652 * So here we would like to only print a warning instead of an error 653 * during psp initialization to avoid breaking hw_init and it doesn't 654 * return -EINVAL. 655 */ 656 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 657 if (ucode) 658 DRM_WARN("failed to load ucode %s(0x%X) ", 659 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 660 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 661 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 662 psp->cmd_buf_mem->resp.status); 663 /* If any firmware (including CAP) load fails under SRIOV, it should 664 * return failure to stop the VF from initializing. 665 * Also return failure in case of timeout 666 */ 667 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 668 ret = -EINVAL; 669 goto exit; 670 } 671 } 672 673 if (ucode) { 674 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 675 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 676 } 677 678 exit: 679 return ret; 680 } 681 682 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 683 { 684 struct psp_gfx_cmd_resp *cmd = psp->cmd; 685 686 mutex_lock(&psp->mutex); 687 688 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 689 690 return cmd; 691 } 692 693 static void release_psp_cmd_buf(struct psp_context *psp) 694 { 695 mutex_unlock(&psp->mutex); 696 } 697 698 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 699 struct psp_gfx_cmd_resp *cmd, 700 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 701 { 702 struct amdgpu_device *adev = psp->adev; 703 uint32_t size = amdgpu_bo_size(tmr_bo); 704 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 705 706 if (amdgpu_sriov_vf(psp->adev)) 707 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 708 else 709 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 710 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 711 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 712 cmd->cmd.cmd_setup_tmr.buf_size = size; 713 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 714 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 715 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 716 } 717 718 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 719 uint64_t pri_buf_mc, uint32_t size) 720 { 721 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 722 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 723 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 724 cmd->cmd.cmd_load_toc.toc_size = size; 725 } 726 727 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 728 static int psp_load_toc(struct psp_context *psp, 729 uint32_t *tmr_size) 730 { 731 int ret; 732 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 733 734 /* Copy toc to psp firmware private buffer */ 735 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 736 737 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 738 739 ret = psp_cmd_submit_buf(psp, NULL, cmd, 740 psp->fence_buf_mc_addr); 741 if (!ret) 742 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 743 744 release_psp_cmd_buf(psp); 745 746 return ret; 747 } 748 749 /* Set up Trusted Memory Region */ 750 static int psp_tmr_init(struct psp_context *psp) 751 { 752 int ret = 0; 753 int tmr_size; 754 void *tmr_buf; 755 void **pptr; 756 757 /* 758 * According to HW engineer, they prefer the TMR address be "naturally 759 * aligned" , e.g. the start address be an integer divide of TMR size. 760 * 761 * Note: this memory need be reserved till the driver 762 * uninitializes. 763 */ 764 tmr_size = PSP_TMR_SIZE(psp->adev); 765 766 /* For ASICs support RLC autoload, psp will parse the toc 767 * and calculate the total size of TMR needed */ 768 if (!amdgpu_sriov_vf(psp->adev) && 769 psp->toc.start_addr && 770 psp->toc.size_bytes && 771 psp->fw_pri_buf) { 772 ret = psp_load_toc(psp, &tmr_size); 773 if (ret) { 774 DRM_ERROR("Failed to load toc\n"); 775 return ret; 776 } 777 } 778 779 if (!psp->tmr_bo) { 780 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 781 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 782 PSP_TMR_ALIGNMENT, 783 AMDGPU_HAS_VRAM(psp->adev) ? 784 AMDGPU_GEM_DOMAIN_VRAM : 785 AMDGPU_GEM_DOMAIN_GTT, 786 &psp->tmr_bo, &psp->tmr_mc_addr, 787 pptr); 788 } 789 790 return ret; 791 } 792 793 static bool psp_skip_tmr(struct psp_context *psp) 794 { 795 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 796 case IP_VERSION(11, 0, 9): 797 case IP_VERSION(11, 0, 7): 798 case IP_VERSION(13, 0, 2): 799 case IP_VERSION(13, 0, 10): 800 return true; 801 default: 802 return false; 803 } 804 } 805 806 static int psp_tmr_load(struct psp_context *psp) 807 { 808 int ret; 809 struct psp_gfx_cmd_resp *cmd; 810 811 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 812 * Already set up by host driver. 813 */ 814 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 815 return 0; 816 817 cmd = acquire_psp_cmd_buf(psp); 818 819 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 820 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 821 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 822 823 ret = psp_cmd_submit_buf(psp, NULL, cmd, 824 psp->fence_buf_mc_addr); 825 826 release_psp_cmd_buf(psp); 827 828 return ret; 829 } 830 831 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 832 struct psp_gfx_cmd_resp *cmd) 833 { 834 if (amdgpu_sriov_vf(psp->adev)) 835 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 836 else 837 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 838 } 839 840 static int psp_tmr_unload(struct psp_context *psp) 841 { 842 int ret; 843 struct psp_gfx_cmd_resp *cmd; 844 845 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV, 846 * as TMR is not loaded at all 847 */ 848 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 849 return 0; 850 851 cmd = acquire_psp_cmd_buf(psp); 852 853 psp_prep_tmr_unload_cmd_buf(psp, cmd); 854 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 855 856 ret = psp_cmd_submit_buf(psp, NULL, cmd, 857 psp->fence_buf_mc_addr); 858 859 release_psp_cmd_buf(psp); 860 861 return ret; 862 } 863 864 static int psp_tmr_terminate(struct psp_context *psp) 865 { 866 return psp_tmr_unload(psp); 867 } 868 869 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 870 uint64_t *output_ptr) 871 { 872 int ret; 873 struct psp_gfx_cmd_resp *cmd; 874 875 if (!output_ptr) 876 return -EINVAL; 877 878 if (amdgpu_sriov_vf(psp->adev)) 879 return 0; 880 881 cmd = acquire_psp_cmd_buf(psp); 882 883 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 884 885 ret = psp_cmd_submit_buf(psp, NULL, cmd, 886 psp->fence_buf_mc_addr); 887 888 if (!ret) { 889 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 890 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 891 } 892 893 release_psp_cmd_buf(psp); 894 895 return ret; 896 } 897 898 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 899 { 900 struct psp_context *psp = &adev->psp; 901 struct psp_gfx_cmd_resp *cmd; 902 int ret; 903 904 if (amdgpu_sriov_vf(adev)) 905 return 0; 906 907 cmd = acquire_psp_cmd_buf(psp); 908 909 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 910 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 911 912 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 913 if (!ret) { 914 *boot_cfg = 915 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 916 } 917 918 release_psp_cmd_buf(psp); 919 920 return ret; 921 } 922 923 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 924 { 925 int ret; 926 struct psp_context *psp = &adev->psp; 927 struct psp_gfx_cmd_resp *cmd; 928 929 if (amdgpu_sriov_vf(adev)) 930 return 0; 931 932 cmd = acquire_psp_cmd_buf(psp); 933 934 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 935 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 936 cmd->cmd.boot_cfg.boot_config = boot_cfg; 937 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 938 939 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 940 941 release_psp_cmd_buf(psp); 942 943 return ret; 944 } 945 946 static int psp_rl_load(struct amdgpu_device *adev) 947 { 948 int ret; 949 struct psp_context *psp = &adev->psp; 950 struct psp_gfx_cmd_resp *cmd; 951 952 if (!is_psp_fw_valid(psp->rl)) 953 return 0; 954 955 cmd = acquire_psp_cmd_buf(psp); 956 957 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 958 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 959 960 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 961 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 962 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 963 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 964 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 965 966 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 967 968 release_psp_cmd_buf(psp); 969 970 return ret; 971 } 972 973 static int psp_asd_initialize(struct psp_context *psp) 974 { 975 int ret; 976 977 /* If PSP version doesn't match ASD version, asd loading will be failed. 978 * add workaround to bypass it for sriov now. 979 * TODO: add version check to make it common 980 */ 981 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 982 return 0; 983 984 psp->asd_context.mem_context.shared_mc_addr = 0; 985 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 986 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 987 988 ret = psp_ta_load(psp, &psp->asd_context); 989 if (!ret) 990 psp->asd_context.initialized = true; 991 992 return ret; 993 } 994 995 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 996 uint32_t session_id) 997 { 998 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 999 cmd->cmd.cmd_unload_ta.session_id = session_id; 1000 } 1001 1002 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1003 { 1004 int ret; 1005 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1006 1007 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1008 1009 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1010 1011 context->resp_status = cmd->resp.status; 1012 1013 release_psp_cmd_buf(psp); 1014 1015 return ret; 1016 } 1017 1018 static int psp_asd_terminate(struct psp_context *psp) 1019 { 1020 int ret; 1021 1022 if (amdgpu_sriov_vf(psp->adev)) 1023 return 0; 1024 1025 if (!psp->asd_context.initialized) 1026 return 0; 1027 1028 ret = psp_ta_unload(psp, &psp->asd_context); 1029 if (!ret) 1030 psp->asd_context.initialized = false; 1031 1032 return ret; 1033 } 1034 1035 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1036 uint32_t id, uint32_t value) 1037 { 1038 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1039 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1040 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1041 } 1042 1043 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1044 uint32_t value) 1045 { 1046 struct psp_gfx_cmd_resp *cmd; 1047 int ret = 0; 1048 1049 if (reg >= PSP_REG_LAST) 1050 return -EINVAL; 1051 1052 cmd = acquire_psp_cmd_buf(psp); 1053 1054 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1055 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1056 if (ret) 1057 DRM_ERROR("PSP failed to program reg id %d", reg); 1058 1059 release_psp_cmd_buf(psp); 1060 1061 return ret; 1062 } 1063 1064 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1065 uint64_t ta_bin_mc, 1066 struct ta_context *context) 1067 { 1068 cmd->cmd_id = context->ta_load_type; 1069 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1070 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1071 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1072 1073 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1074 lower_32_bits(context->mem_context.shared_mc_addr); 1075 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1076 upper_32_bits(context->mem_context.shared_mc_addr); 1077 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1078 } 1079 1080 int psp_ta_init_shared_buf(struct psp_context *psp, 1081 struct ta_mem_context *mem_ctx) 1082 { 1083 /* 1084 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1085 * physical) for ta to host memory 1086 */ 1087 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1088 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1089 AMDGPU_GEM_DOMAIN_GTT, 1090 &mem_ctx->shared_bo, 1091 &mem_ctx->shared_mc_addr, 1092 &mem_ctx->shared_buf); 1093 } 1094 1095 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1096 uint32_t ta_cmd_id, 1097 uint32_t session_id) 1098 { 1099 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1100 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1101 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1102 } 1103 1104 int psp_ta_invoke(struct psp_context *psp, 1105 uint32_t ta_cmd_id, 1106 struct ta_context *context) 1107 { 1108 int ret; 1109 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1110 1111 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1112 1113 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1114 psp->fence_buf_mc_addr); 1115 1116 context->resp_status = cmd->resp.status; 1117 1118 release_psp_cmd_buf(psp); 1119 1120 return ret; 1121 } 1122 1123 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1124 { 1125 int ret; 1126 struct psp_gfx_cmd_resp *cmd; 1127 1128 cmd = acquire_psp_cmd_buf(psp); 1129 1130 psp_copy_fw(psp, context->bin_desc.start_addr, 1131 context->bin_desc.size_bytes); 1132 1133 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1134 1135 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1136 psp->fence_buf_mc_addr); 1137 1138 context->resp_status = cmd->resp.status; 1139 1140 if (!ret) 1141 context->session_id = cmd->resp.session_id; 1142 1143 release_psp_cmd_buf(psp); 1144 1145 return ret; 1146 } 1147 1148 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1149 { 1150 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1151 } 1152 1153 int psp_xgmi_terminate(struct psp_context *psp) 1154 { 1155 int ret; 1156 struct amdgpu_device *adev = psp->adev; 1157 1158 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1159 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1160 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1161 adev->gmc.xgmi.connected_to_cpu)) 1162 return 0; 1163 1164 if (!psp->xgmi_context.context.initialized) 1165 return 0; 1166 1167 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1168 1169 psp->xgmi_context.context.initialized = false; 1170 1171 return ret; 1172 } 1173 1174 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1175 { 1176 struct ta_xgmi_shared_memory *xgmi_cmd; 1177 int ret; 1178 1179 if (!psp->ta_fw || 1180 !psp->xgmi_context.context.bin_desc.size_bytes || 1181 !psp->xgmi_context.context.bin_desc.start_addr) 1182 return -ENOENT; 1183 1184 if (!load_ta) 1185 goto invoke; 1186 1187 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1188 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1189 1190 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1191 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1192 if (ret) 1193 return ret; 1194 } 1195 1196 /* Load XGMI TA */ 1197 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1198 if (!ret) 1199 psp->xgmi_context.context.initialized = true; 1200 else 1201 return ret; 1202 1203 invoke: 1204 /* Initialize XGMI session */ 1205 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1206 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1207 xgmi_cmd->flag_extend_link_record = set_extended_data; 1208 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1209 1210 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1211 1212 return ret; 1213 } 1214 1215 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1216 { 1217 struct ta_xgmi_shared_memory *xgmi_cmd; 1218 int ret; 1219 1220 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1221 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1222 1223 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1224 1225 /* Invoke xgmi ta to get hive id */ 1226 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1227 if (ret) 1228 return ret; 1229 1230 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1231 1232 return 0; 1233 } 1234 1235 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1236 { 1237 struct ta_xgmi_shared_memory *xgmi_cmd; 1238 int ret; 1239 1240 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1241 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1242 1243 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1244 1245 /* Invoke xgmi ta to get the node id */ 1246 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1247 if (ret) 1248 return ret; 1249 1250 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1251 1252 return 0; 1253 } 1254 1255 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1256 { 1257 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1258 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1259 } 1260 1261 /* 1262 * Chips that support extended topology information require the driver to 1263 * reflect topology information in the opposite direction. This is 1264 * because the TA has already exceeded its link record limit and if the 1265 * TA holds bi-directional information, the driver would have to do 1266 * multiple fetches instead of just two. 1267 */ 1268 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1269 struct psp_xgmi_node_info node_info) 1270 { 1271 struct amdgpu_device *mirror_adev; 1272 struct amdgpu_hive_info *hive; 1273 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1274 uint64_t dst_node_id = node_info.node_id; 1275 uint8_t dst_num_hops = node_info.num_hops; 1276 uint8_t dst_num_links = node_info.num_links; 1277 1278 hive = amdgpu_get_xgmi_hive(psp->adev); 1279 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1280 struct psp_xgmi_topology_info *mirror_top_info; 1281 int j; 1282 1283 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1284 continue; 1285 1286 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1287 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1288 if (mirror_top_info->nodes[j].node_id != src_node_id) 1289 continue; 1290 1291 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1292 /* 1293 * prevent 0 num_links value re-reflection since reflection 1294 * criteria is based on num_hops (direct or indirect). 1295 * 1296 */ 1297 if (dst_num_links) 1298 mirror_top_info->nodes[j].num_links = dst_num_links; 1299 1300 break; 1301 } 1302 1303 break; 1304 } 1305 1306 amdgpu_put_xgmi_hive(hive); 1307 } 1308 1309 int psp_xgmi_get_topology_info(struct psp_context *psp, 1310 int number_devices, 1311 struct psp_xgmi_topology_info *topology, 1312 bool get_extended_data) 1313 { 1314 struct ta_xgmi_shared_memory *xgmi_cmd; 1315 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1316 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1317 int i; 1318 int ret; 1319 1320 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1321 return -EINVAL; 1322 1323 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1324 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1325 xgmi_cmd->flag_extend_link_record = get_extended_data; 1326 1327 /* Fill in the shared memory with topology information as input */ 1328 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1329 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1330 topology_info_input->num_nodes = number_devices; 1331 1332 for (i = 0; i < topology_info_input->num_nodes; i++) { 1333 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1334 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1335 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1336 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1337 } 1338 1339 /* Invoke xgmi ta to get the topology information */ 1340 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1341 if (ret) 1342 return ret; 1343 1344 /* Read the output topology information from the shared memory */ 1345 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1346 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1347 for (i = 0; i < topology->num_nodes; i++) { 1348 /* extended data will either be 0 or equal to non-extended data */ 1349 if (topology_info_output->nodes[i].num_hops) 1350 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1351 1352 /* non-extended data gets everything here so no need to update */ 1353 if (!get_extended_data) { 1354 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1355 topology->nodes[i].is_sharing_enabled = 1356 topology_info_output->nodes[i].is_sharing_enabled; 1357 topology->nodes[i].sdma_engine = 1358 topology_info_output->nodes[i].sdma_engine; 1359 } 1360 1361 } 1362 1363 /* Invoke xgmi ta again to get the link information */ 1364 if (psp_xgmi_peer_link_info_supported(psp)) { 1365 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1366 1367 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1368 1369 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1370 1371 if (ret) 1372 return ret; 1373 1374 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1375 for (i = 0; i < topology->num_nodes; i++) { 1376 /* accumulate num_links on extended data */ 1377 topology->nodes[i].num_links = get_extended_data ? 1378 topology->nodes[i].num_links + 1379 link_info_output->nodes[i].num_links : 1380 link_info_output->nodes[i].num_links; 1381 1382 /* reflect the topology information for bi-directionality */ 1383 if (psp->xgmi_context.supports_extended_data && 1384 get_extended_data && topology->nodes[i].num_hops) 1385 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1386 } 1387 } 1388 1389 return 0; 1390 } 1391 1392 int psp_xgmi_set_topology_info(struct psp_context *psp, 1393 int number_devices, 1394 struct psp_xgmi_topology_info *topology) 1395 { 1396 struct ta_xgmi_shared_memory *xgmi_cmd; 1397 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1398 int i; 1399 1400 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1401 return -EINVAL; 1402 1403 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1404 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1405 1406 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1407 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1408 topology_info_input->num_nodes = number_devices; 1409 1410 for (i = 0; i < topology_info_input->num_nodes; i++) { 1411 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1412 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1413 topology_info_input->nodes[i].is_sharing_enabled = 1; 1414 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1415 } 1416 1417 /* Invoke xgmi ta to set topology information */ 1418 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1419 } 1420 1421 // ras begin 1422 static void psp_ras_ta_check_status(struct psp_context *psp) 1423 { 1424 struct ta_ras_shared_memory *ras_cmd = 1425 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1426 1427 switch (ras_cmd->ras_status) { 1428 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1429 dev_warn(psp->adev->dev, 1430 "RAS WARNING: cmd failed due to unsupported ip\n"); 1431 break; 1432 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1433 dev_warn(psp->adev->dev, 1434 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1435 break; 1436 case TA_RAS_STATUS__SUCCESS: 1437 break; 1438 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1439 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1440 dev_warn(psp->adev->dev, 1441 "RAS WARNING: Inject error to critical region is not allowed\n"); 1442 break; 1443 default: 1444 dev_warn(psp->adev->dev, 1445 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1446 break; 1447 } 1448 } 1449 1450 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1451 { 1452 struct ta_ras_shared_memory *ras_cmd; 1453 int ret; 1454 1455 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1456 1457 /* 1458 * TODO: bypass the loading in sriov for now 1459 */ 1460 if (amdgpu_sriov_vf(psp->adev)) 1461 return 0; 1462 1463 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1464 1465 if (amdgpu_ras_intr_triggered()) 1466 return ret; 1467 1468 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 1469 DRM_WARN("RAS: Unsupported Interface"); 1470 return -EINVAL; 1471 } 1472 1473 if (!ret) { 1474 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1475 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1476 1477 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1478 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1479 dev_warn(psp->adev->dev, 1480 "RAS internal register access blocked\n"); 1481 1482 psp_ras_ta_check_status(psp); 1483 } 1484 1485 return ret; 1486 } 1487 1488 int psp_ras_enable_features(struct psp_context *psp, 1489 union ta_ras_cmd_input *info, bool enable) 1490 { 1491 struct ta_ras_shared_memory *ras_cmd; 1492 int ret; 1493 1494 if (!psp->ras_context.context.initialized) 1495 return -EINVAL; 1496 1497 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1498 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1499 1500 if (enable) 1501 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1502 else 1503 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1504 1505 ras_cmd->ras_in_message = *info; 1506 1507 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1508 if (ret) 1509 return -EINVAL; 1510 1511 return 0; 1512 } 1513 1514 int psp_ras_terminate(struct psp_context *psp) 1515 { 1516 int ret; 1517 1518 /* 1519 * TODO: bypass the terminate in sriov for now 1520 */ 1521 if (amdgpu_sriov_vf(psp->adev)) 1522 return 0; 1523 1524 if (!psp->ras_context.context.initialized) 1525 return 0; 1526 1527 ret = psp_ta_unload(psp, &psp->ras_context.context); 1528 1529 psp->ras_context.context.initialized = false; 1530 1531 return ret; 1532 } 1533 1534 int psp_ras_initialize(struct psp_context *psp) 1535 { 1536 int ret; 1537 uint32_t boot_cfg = 0xFF; 1538 struct amdgpu_device *adev = psp->adev; 1539 struct ta_ras_shared_memory *ras_cmd; 1540 1541 /* 1542 * TODO: bypass the initialize in sriov for now 1543 */ 1544 if (amdgpu_sriov_vf(adev)) 1545 return 0; 1546 1547 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1548 !adev->psp.ras_context.context.bin_desc.start_addr) { 1549 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1550 return 0; 1551 } 1552 1553 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1554 /* query GECC enablement status from boot config 1555 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1556 */ 1557 ret = psp_boot_config_get(adev, &boot_cfg); 1558 if (ret) 1559 dev_warn(adev->dev, "PSP get boot config failed\n"); 1560 1561 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1562 if (!boot_cfg) { 1563 dev_info(adev->dev, "GECC is disabled\n"); 1564 } else { 1565 /* disable GECC in next boot cycle if ras is 1566 * disabled by module parameter amdgpu_ras_enable 1567 * and/or amdgpu_ras_mask, or boot_config_get call 1568 * is failed 1569 */ 1570 ret = psp_boot_config_set(adev, 0); 1571 if (ret) 1572 dev_warn(adev->dev, "PSP set boot config failed\n"); 1573 else 1574 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1575 } 1576 } else { 1577 if (boot_cfg == 1) { 1578 dev_info(adev->dev, "GECC is enabled\n"); 1579 } else { 1580 /* enable GECC in next boot cycle if it is disabled 1581 * in boot config, or force enable GECC if failed to 1582 * get boot configuration 1583 */ 1584 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1585 if (ret) 1586 dev_warn(adev->dev, "PSP set boot config failed\n"); 1587 else 1588 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1589 } 1590 } 1591 } 1592 1593 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1594 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1595 1596 if (!psp->ras_context.context.mem_context.shared_buf) { 1597 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1598 if (ret) 1599 return ret; 1600 } 1601 1602 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1603 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1604 1605 if (amdgpu_ras_is_poison_mode_supported(adev)) 1606 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1607 if (!adev->gmc.xgmi.connected_to_cpu) 1608 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1609 1610 ret = psp_ta_load(psp, &psp->ras_context.context); 1611 1612 if (!ret && !ras_cmd->ras_status) 1613 psp->ras_context.context.initialized = true; 1614 else { 1615 if (ras_cmd->ras_status) 1616 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1617 1618 /* fail to load RAS TA */ 1619 psp->ras_context.context.initialized = false; 1620 } 1621 1622 return ret; 1623 } 1624 1625 int psp_ras_trigger_error(struct psp_context *psp, 1626 struct ta_ras_trigger_error_input *info) 1627 { 1628 struct ta_ras_shared_memory *ras_cmd; 1629 int ret; 1630 1631 if (!psp->ras_context.context.initialized) 1632 return -EINVAL; 1633 1634 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1635 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1636 1637 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1638 ras_cmd->ras_in_message.trigger_error = *info; 1639 1640 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1641 if (ret) 1642 return -EINVAL; 1643 1644 /* If err_event_athub occurs error inject was successful, however 1645 return status from TA is no long reliable */ 1646 if (amdgpu_ras_intr_triggered()) 1647 return 0; 1648 1649 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1650 return -EACCES; 1651 else if (ras_cmd->ras_status) 1652 return -EINVAL; 1653 1654 return 0; 1655 } 1656 // ras end 1657 1658 // HDCP start 1659 static int psp_hdcp_initialize(struct psp_context *psp) 1660 { 1661 int ret; 1662 1663 /* 1664 * TODO: bypass the initialize in sriov for now 1665 */ 1666 if (amdgpu_sriov_vf(psp->adev)) 1667 return 0; 1668 1669 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1670 !psp->hdcp_context.context.bin_desc.start_addr) { 1671 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1672 return 0; 1673 } 1674 1675 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1676 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1677 1678 if (!psp->hdcp_context.context.mem_context.shared_buf) { 1679 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1680 if (ret) 1681 return ret; 1682 } 1683 1684 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1685 if (!ret) { 1686 psp->hdcp_context.context.initialized = true; 1687 mutex_init(&psp->hdcp_context.mutex); 1688 } 1689 1690 return ret; 1691 } 1692 1693 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1694 { 1695 /* 1696 * TODO: bypass the loading in sriov for now 1697 */ 1698 if (amdgpu_sriov_vf(psp->adev)) 1699 return 0; 1700 1701 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1702 } 1703 1704 static int psp_hdcp_terminate(struct psp_context *psp) 1705 { 1706 int ret; 1707 1708 /* 1709 * TODO: bypass the terminate in sriov for now 1710 */ 1711 if (amdgpu_sriov_vf(psp->adev)) 1712 return 0; 1713 1714 if (!psp->hdcp_context.context.initialized) 1715 return 0; 1716 1717 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1718 1719 psp->hdcp_context.context.initialized = false; 1720 1721 return ret; 1722 } 1723 // HDCP end 1724 1725 // DTM start 1726 static int psp_dtm_initialize(struct psp_context *psp) 1727 { 1728 int ret; 1729 1730 /* 1731 * TODO: bypass the initialize in sriov for now 1732 */ 1733 if (amdgpu_sriov_vf(psp->adev)) 1734 return 0; 1735 1736 if (!psp->dtm_context.context.bin_desc.size_bytes || 1737 !psp->dtm_context.context.bin_desc.start_addr) { 1738 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1739 return 0; 1740 } 1741 1742 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1743 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1744 1745 if (!psp->dtm_context.context.mem_context.shared_buf) { 1746 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1747 if (ret) 1748 return ret; 1749 } 1750 1751 ret = psp_ta_load(psp, &psp->dtm_context.context); 1752 if (!ret) { 1753 psp->dtm_context.context.initialized = true; 1754 mutex_init(&psp->dtm_context.mutex); 1755 } 1756 1757 return ret; 1758 } 1759 1760 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1761 { 1762 /* 1763 * TODO: bypass the loading in sriov for now 1764 */ 1765 if (amdgpu_sriov_vf(psp->adev)) 1766 return 0; 1767 1768 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1769 } 1770 1771 static int psp_dtm_terminate(struct psp_context *psp) 1772 { 1773 int ret; 1774 1775 /* 1776 * TODO: bypass the terminate in sriov for now 1777 */ 1778 if (amdgpu_sriov_vf(psp->adev)) 1779 return 0; 1780 1781 if (!psp->dtm_context.context.initialized) 1782 return 0; 1783 1784 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1785 1786 psp->dtm_context.context.initialized = false; 1787 1788 return ret; 1789 } 1790 // DTM end 1791 1792 // RAP start 1793 static int psp_rap_initialize(struct psp_context *psp) 1794 { 1795 int ret; 1796 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1797 1798 /* 1799 * TODO: bypass the initialize in sriov for now 1800 */ 1801 if (amdgpu_sriov_vf(psp->adev)) 1802 return 0; 1803 1804 if (!psp->rap_context.context.bin_desc.size_bytes || 1805 !psp->rap_context.context.bin_desc.start_addr) { 1806 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1807 return 0; 1808 } 1809 1810 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1811 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1812 1813 if (!psp->rap_context.context.mem_context.shared_buf) { 1814 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1815 if (ret) 1816 return ret; 1817 } 1818 1819 ret = psp_ta_load(psp, &psp->rap_context.context); 1820 if (!ret) { 1821 psp->rap_context.context.initialized = true; 1822 mutex_init(&psp->rap_context.mutex); 1823 } else 1824 return ret; 1825 1826 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1827 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1828 psp_rap_terminate(psp); 1829 /* free rap shared memory */ 1830 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1831 1832 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1833 ret, status); 1834 1835 return ret; 1836 } 1837 1838 return 0; 1839 } 1840 1841 static int psp_rap_terminate(struct psp_context *psp) 1842 { 1843 int ret; 1844 1845 if (!psp->rap_context.context.initialized) 1846 return 0; 1847 1848 ret = psp_ta_unload(psp, &psp->rap_context.context); 1849 1850 psp->rap_context.context.initialized = false; 1851 1852 return ret; 1853 } 1854 1855 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1856 { 1857 struct ta_rap_shared_memory *rap_cmd; 1858 int ret = 0; 1859 1860 if (!psp->rap_context.context.initialized) 1861 return 0; 1862 1863 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1864 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1865 return -EINVAL; 1866 1867 mutex_lock(&psp->rap_context.mutex); 1868 1869 rap_cmd = (struct ta_rap_shared_memory *) 1870 psp->rap_context.context.mem_context.shared_buf; 1871 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1872 1873 rap_cmd->cmd_id = ta_cmd_id; 1874 rap_cmd->validation_method_id = METHOD_A; 1875 1876 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1877 if (ret) 1878 goto out_unlock; 1879 1880 if (status) 1881 *status = rap_cmd->rap_status; 1882 1883 out_unlock: 1884 mutex_unlock(&psp->rap_context.mutex); 1885 1886 return ret; 1887 } 1888 // RAP end 1889 1890 /* securedisplay start */ 1891 static int psp_securedisplay_initialize(struct psp_context *psp) 1892 { 1893 int ret; 1894 struct ta_securedisplay_cmd *securedisplay_cmd; 1895 1896 /* 1897 * TODO: bypass the initialize in sriov for now 1898 */ 1899 if (amdgpu_sriov_vf(psp->adev)) 1900 return 0; 1901 1902 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1903 !psp->securedisplay_context.context.bin_desc.start_addr) { 1904 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1905 return 0; 1906 } 1907 1908 psp->securedisplay_context.context.mem_context.shared_mem_size = 1909 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1910 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1911 1912 if (!psp->securedisplay_context.context.initialized) { 1913 ret = psp_ta_init_shared_buf(psp, 1914 &psp->securedisplay_context.context.mem_context); 1915 if (ret) 1916 return ret; 1917 } 1918 1919 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 1920 if (!ret) { 1921 psp->securedisplay_context.context.initialized = true; 1922 mutex_init(&psp->securedisplay_context.mutex); 1923 } else 1924 return ret; 1925 1926 mutex_lock(&psp->securedisplay_context.mutex); 1927 1928 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1929 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1930 1931 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1932 1933 mutex_unlock(&psp->securedisplay_context.mutex); 1934 1935 if (ret) { 1936 psp_securedisplay_terminate(psp); 1937 /* free securedisplay shared memory */ 1938 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1939 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1940 return -EINVAL; 1941 } 1942 1943 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1944 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1945 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1946 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1947 } 1948 1949 return 0; 1950 } 1951 1952 static int psp_securedisplay_terminate(struct psp_context *psp) 1953 { 1954 int ret; 1955 1956 /* 1957 * TODO:bypass the terminate in sriov for now 1958 */ 1959 if (amdgpu_sriov_vf(psp->adev)) 1960 return 0; 1961 1962 if (!psp->securedisplay_context.context.initialized) 1963 return 0; 1964 1965 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 1966 1967 psp->securedisplay_context.context.initialized = false; 1968 1969 return ret; 1970 } 1971 1972 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1973 { 1974 int ret; 1975 1976 if (!psp->securedisplay_context.context.initialized) 1977 return -EINVAL; 1978 1979 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1980 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1981 return -EINVAL; 1982 1983 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1984 1985 return ret; 1986 } 1987 /* SECUREDISPLAY end */ 1988 1989 static int psp_hw_start(struct psp_context *psp) 1990 { 1991 struct amdgpu_device *adev = psp->adev; 1992 int ret; 1993 1994 if (!amdgpu_sriov_vf(adev)) { 1995 if ((is_psp_fw_valid(psp->kdb)) && 1996 (psp->funcs->bootloader_load_kdb != NULL)) { 1997 ret = psp_bootloader_load_kdb(psp); 1998 if (ret) { 1999 DRM_ERROR("PSP load kdb failed!\n"); 2000 return ret; 2001 } 2002 } 2003 2004 if ((is_psp_fw_valid(psp->spl)) && 2005 (psp->funcs->bootloader_load_spl != NULL)) { 2006 ret = psp_bootloader_load_spl(psp); 2007 if (ret) { 2008 DRM_ERROR("PSP load spl failed!\n"); 2009 return ret; 2010 } 2011 } 2012 2013 if ((is_psp_fw_valid(psp->sys)) && 2014 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2015 ret = psp_bootloader_load_sysdrv(psp); 2016 if (ret) { 2017 DRM_ERROR("PSP load sys drv failed!\n"); 2018 return ret; 2019 } 2020 } 2021 2022 if ((is_psp_fw_valid(psp->soc_drv)) && 2023 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2024 ret = psp_bootloader_load_soc_drv(psp); 2025 if (ret) { 2026 DRM_ERROR("PSP load soc drv failed!\n"); 2027 return ret; 2028 } 2029 } 2030 2031 if ((is_psp_fw_valid(psp->intf_drv)) && 2032 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2033 ret = psp_bootloader_load_intf_drv(psp); 2034 if (ret) { 2035 DRM_ERROR("PSP load intf drv failed!\n"); 2036 return ret; 2037 } 2038 } 2039 2040 if ((is_psp_fw_valid(psp->dbg_drv)) && 2041 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2042 ret = psp_bootloader_load_dbg_drv(psp); 2043 if (ret) { 2044 DRM_ERROR("PSP load dbg drv failed!\n"); 2045 return ret; 2046 } 2047 } 2048 2049 if ((is_psp_fw_valid(psp->ras_drv)) && 2050 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2051 ret = psp_bootloader_load_ras_drv(psp); 2052 if (ret) { 2053 DRM_ERROR("PSP load ras_drv failed!\n"); 2054 return ret; 2055 } 2056 } 2057 2058 if ((is_psp_fw_valid(psp->sos)) && 2059 (psp->funcs->bootloader_load_sos != NULL)) { 2060 ret = psp_bootloader_load_sos(psp); 2061 if (ret) { 2062 DRM_ERROR("PSP load sos failed!\n"); 2063 return ret; 2064 } 2065 } 2066 } 2067 2068 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2069 if (ret) { 2070 DRM_ERROR("PSP create ring failed!\n"); 2071 return ret; 2072 } 2073 2074 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2075 goto skip_pin_bo; 2076 2077 ret = psp_tmr_init(psp); 2078 if (ret) { 2079 DRM_ERROR("PSP tmr init failed!\n"); 2080 return ret; 2081 } 2082 2083 skip_pin_bo: 2084 /* 2085 * For ASICs with DF Cstate management centralized 2086 * to PMFW, TMR setup should be performed after PMFW 2087 * loaded and before other non-psp firmware loaded. 2088 */ 2089 if (psp->pmfw_centralized_cstate_management) { 2090 ret = psp_load_smu_fw(psp); 2091 if (ret) 2092 return ret; 2093 } 2094 2095 ret = psp_tmr_load(psp); 2096 if (ret) { 2097 DRM_ERROR("PSP load tmr failed!\n"); 2098 return ret; 2099 } 2100 2101 return 0; 2102 } 2103 2104 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2105 enum psp_gfx_fw_type *type) 2106 { 2107 switch (ucode->ucode_id) { 2108 case AMDGPU_UCODE_ID_CAP: 2109 *type = GFX_FW_TYPE_CAP; 2110 break; 2111 case AMDGPU_UCODE_ID_SDMA0: 2112 *type = GFX_FW_TYPE_SDMA0; 2113 break; 2114 case AMDGPU_UCODE_ID_SDMA1: 2115 *type = GFX_FW_TYPE_SDMA1; 2116 break; 2117 case AMDGPU_UCODE_ID_SDMA2: 2118 *type = GFX_FW_TYPE_SDMA2; 2119 break; 2120 case AMDGPU_UCODE_ID_SDMA3: 2121 *type = GFX_FW_TYPE_SDMA3; 2122 break; 2123 case AMDGPU_UCODE_ID_SDMA4: 2124 *type = GFX_FW_TYPE_SDMA4; 2125 break; 2126 case AMDGPU_UCODE_ID_SDMA5: 2127 *type = GFX_FW_TYPE_SDMA5; 2128 break; 2129 case AMDGPU_UCODE_ID_SDMA6: 2130 *type = GFX_FW_TYPE_SDMA6; 2131 break; 2132 case AMDGPU_UCODE_ID_SDMA7: 2133 *type = GFX_FW_TYPE_SDMA7; 2134 break; 2135 case AMDGPU_UCODE_ID_CP_MES: 2136 *type = GFX_FW_TYPE_CP_MES; 2137 break; 2138 case AMDGPU_UCODE_ID_CP_MES_DATA: 2139 *type = GFX_FW_TYPE_MES_STACK; 2140 break; 2141 case AMDGPU_UCODE_ID_CP_MES1: 2142 *type = GFX_FW_TYPE_CP_MES_KIQ; 2143 break; 2144 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2145 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2146 break; 2147 case AMDGPU_UCODE_ID_CP_CE: 2148 *type = GFX_FW_TYPE_CP_CE; 2149 break; 2150 case AMDGPU_UCODE_ID_CP_PFP: 2151 *type = GFX_FW_TYPE_CP_PFP; 2152 break; 2153 case AMDGPU_UCODE_ID_CP_ME: 2154 *type = GFX_FW_TYPE_CP_ME; 2155 break; 2156 case AMDGPU_UCODE_ID_CP_MEC1: 2157 *type = GFX_FW_TYPE_CP_MEC; 2158 break; 2159 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2160 *type = GFX_FW_TYPE_CP_MEC_ME1; 2161 break; 2162 case AMDGPU_UCODE_ID_CP_MEC2: 2163 *type = GFX_FW_TYPE_CP_MEC; 2164 break; 2165 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2166 *type = GFX_FW_TYPE_CP_MEC_ME2; 2167 break; 2168 case AMDGPU_UCODE_ID_RLC_P: 2169 *type = GFX_FW_TYPE_RLC_P; 2170 break; 2171 case AMDGPU_UCODE_ID_RLC_V: 2172 *type = GFX_FW_TYPE_RLC_V; 2173 break; 2174 case AMDGPU_UCODE_ID_RLC_G: 2175 *type = GFX_FW_TYPE_RLC_G; 2176 break; 2177 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2178 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2179 break; 2180 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2181 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2182 break; 2183 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2184 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2185 break; 2186 case AMDGPU_UCODE_ID_RLC_IRAM: 2187 *type = GFX_FW_TYPE_RLC_IRAM; 2188 break; 2189 case AMDGPU_UCODE_ID_RLC_DRAM: 2190 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2191 break; 2192 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2193 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2194 break; 2195 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2196 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2197 break; 2198 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2199 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2200 break; 2201 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2202 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2203 break; 2204 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2205 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2206 break; 2207 case AMDGPU_UCODE_ID_SMC: 2208 *type = GFX_FW_TYPE_SMU; 2209 break; 2210 case AMDGPU_UCODE_ID_PPTABLE: 2211 *type = GFX_FW_TYPE_PPTABLE; 2212 break; 2213 case AMDGPU_UCODE_ID_UVD: 2214 *type = GFX_FW_TYPE_UVD; 2215 break; 2216 case AMDGPU_UCODE_ID_UVD1: 2217 *type = GFX_FW_TYPE_UVD1; 2218 break; 2219 case AMDGPU_UCODE_ID_VCE: 2220 *type = GFX_FW_TYPE_VCE; 2221 break; 2222 case AMDGPU_UCODE_ID_VCN: 2223 *type = GFX_FW_TYPE_VCN; 2224 break; 2225 case AMDGPU_UCODE_ID_VCN1: 2226 *type = GFX_FW_TYPE_VCN1; 2227 break; 2228 case AMDGPU_UCODE_ID_DMCU_ERAM: 2229 *type = GFX_FW_TYPE_DMCU_ERAM; 2230 break; 2231 case AMDGPU_UCODE_ID_DMCU_INTV: 2232 *type = GFX_FW_TYPE_DMCU_ISR; 2233 break; 2234 case AMDGPU_UCODE_ID_VCN0_RAM: 2235 *type = GFX_FW_TYPE_VCN0_RAM; 2236 break; 2237 case AMDGPU_UCODE_ID_VCN1_RAM: 2238 *type = GFX_FW_TYPE_VCN1_RAM; 2239 break; 2240 case AMDGPU_UCODE_ID_DMCUB: 2241 *type = GFX_FW_TYPE_DMUB; 2242 break; 2243 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2244 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2245 break; 2246 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2247 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2248 break; 2249 case AMDGPU_UCODE_ID_IMU_I: 2250 *type = GFX_FW_TYPE_IMU_I; 2251 break; 2252 case AMDGPU_UCODE_ID_IMU_D: 2253 *type = GFX_FW_TYPE_IMU_D; 2254 break; 2255 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2256 *type = GFX_FW_TYPE_RS64_PFP; 2257 break; 2258 case AMDGPU_UCODE_ID_CP_RS64_ME: 2259 *type = GFX_FW_TYPE_RS64_ME; 2260 break; 2261 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2262 *type = GFX_FW_TYPE_RS64_MEC; 2263 break; 2264 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2265 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2266 break; 2267 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2268 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2269 break; 2270 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2271 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2272 break; 2273 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2274 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2275 break; 2276 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2277 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2278 break; 2279 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2280 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2281 break; 2282 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2283 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2284 break; 2285 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2286 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2287 break; 2288 case AMDGPU_UCODE_ID_MAXIMUM: 2289 default: 2290 return -EINVAL; 2291 } 2292 2293 return 0; 2294 } 2295 2296 static void psp_print_fw_hdr(struct psp_context *psp, 2297 struct amdgpu_firmware_info *ucode) 2298 { 2299 struct amdgpu_device *adev = psp->adev; 2300 struct common_firmware_header *hdr; 2301 2302 switch (ucode->ucode_id) { 2303 case AMDGPU_UCODE_ID_SDMA0: 2304 case AMDGPU_UCODE_ID_SDMA1: 2305 case AMDGPU_UCODE_ID_SDMA2: 2306 case AMDGPU_UCODE_ID_SDMA3: 2307 case AMDGPU_UCODE_ID_SDMA4: 2308 case AMDGPU_UCODE_ID_SDMA5: 2309 case AMDGPU_UCODE_ID_SDMA6: 2310 case AMDGPU_UCODE_ID_SDMA7: 2311 hdr = (struct common_firmware_header *) 2312 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2313 amdgpu_ucode_print_sdma_hdr(hdr); 2314 break; 2315 case AMDGPU_UCODE_ID_CP_CE: 2316 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2317 amdgpu_ucode_print_gfx_hdr(hdr); 2318 break; 2319 case AMDGPU_UCODE_ID_CP_PFP: 2320 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2321 amdgpu_ucode_print_gfx_hdr(hdr); 2322 break; 2323 case AMDGPU_UCODE_ID_CP_ME: 2324 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2325 amdgpu_ucode_print_gfx_hdr(hdr); 2326 break; 2327 case AMDGPU_UCODE_ID_CP_MEC1: 2328 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2329 amdgpu_ucode_print_gfx_hdr(hdr); 2330 break; 2331 case AMDGPU_UCODE_ID_RLC_G: 2332 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2333 amdgpu_ucode_print_rlc_hdr(hdr); 2334 break; 2335 case AMDGPU_UCODE_ID_SMC: 2336 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2337 amdgpu_ucode_print_smc_hdr(hdr); 2338 break; 2339 default: 2340 break; 2341 } 2342 } 2343 2344 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2345 struct psp_gfx_cmd_resp *cmd) 2346 { 2347 int ret; 2348 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2349 2350 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2351 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2352 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2353 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2354 2355 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2356 if (ret) 2357 DRM_ERROR("Unknown firmware type\n"); 2358 2359 return ret; 2360 } 2361 2362 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2363 struct amdgpu_firmware_info *ucode) 2364 { 2365 int ret = 0; 2366 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2367 2368 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2369 if (!ret) { 2370 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2371 psp->fence_buf_mc_addr); 2372 } 2373 2374 release_psp_cmd_buf(psp); 2375 2376 return ret; 2377 } 2378 2379 static int psp_load_smu_fw(struct psp_context *psp) 2380 { 2381 int ret; 2382 struct amdgpu_device *adev = psp->adev; 2383 struct amdgpu_firmware_info *ucode = 2384 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2385 struct amdgpu_ras *ras = psp->ras_context.ras; 2386 2387 /* 2388 * Skip SMU FW reloading in case of using BACO for runpm only, 2389 * as SMU is always alive. 2390 */ 2391 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2392 return 0; 2393 2394 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2395 return 0; 2396 2397 if ((amdgpu_in_reset(adev) && 2398 ras && adev->ras_enabled && 2399 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2400 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2401 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2402 if (ret) 2403 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2404 } 2405 2406 ret = psp_execute_non_psp_fw_load(psp, ucode); 2407 2408 if (ret) 2409 DRM_ERROR("PSP load smu failed!\n"); 2410 2411 return ret; 2412 } 2413 2414 static bool fw_load_skip_check(struct psp_context *psp, 2415 struct amdgpu_firmware_info *ucode) 2416 { 2417 if (!ucode->fw || !ucode->ucode_size) 2418 return true; 2419 2420 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2421 (psp_smu_reload_quirk(psp) || 2422 psp->autoload_supported || 2423 psp->pmfw_centralized_cstate_management)) 2424 return true; 2425 2426 if (amdgpu_sriov_vf(psp->adev) && 2427 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2428 return true; 2429 2430 if (psp->autoload_supported && 2431 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2432 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2433 /* skip mec JT when autoload is enabled */ 2434 return true; 2435 2436 return false; 2437 } 2438 2439 int psp_load_fw_list(struct psp_context *psp, 2440 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2441 { 2442 int ret = 0, i; 2443 struct amdgpu_firmware_info *ucode; 2444 2445 for (i = 0; i < ucode_count; ++i) { 2446 ucode = ucode_list[i]; 2447 psp_print_fw_hdr(psp, ucode); 2448 ret = psp_execute_non_psp_fw_load(psp, ucode); 2449 if (ret) 2450 return ret; 2451 } 2452 return ret; 2453 } 2454 2455 static int psp_load_non_psp_fw(struct psp_context *psp) 2456 { 2457 int i, ret; 2458 struct amdgpu_firmware_info *ucode; 2459 struct amdgpu_device *adev = psp->adev; 2460 2461 if (psp->autoload_supported && 2462 !psp->pmfw_centralized_cstate_management) { 2463 ret = psp_load_smu_fw(psp); 2464 if (ret) 2465 return ret; 2466 } 2467 2468 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2469 ucode = &adev->firmware.ucode[i]; 2470 2471 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2472 !fw_load_skip_check(psp, ucode)) { 2473 ret = psp_load_smu_fw(psp); 2474 if (ret) 2475 return ret; 2476 continue; 2477 } 2478 2479 if (fw_load_skip_check(psp, ucode)) 2480 continue; 2481 2482 if (psp->autoload_supported && 2483 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2484 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2485 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2486 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2487 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2488 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2489 /* PSP only receive one SDMA fw for sienna_cichlid, 2490 * as all four sdma fw are same */ 2491 continue; 2492 2493 psp_print_fw_hdr(psp, ucode); 2494 2495 ret = psp_execute_non_psp_fw_load(psp, ucode); 2496 if (ret) 2497 return ret; 2498 2499 /* Start rlc autoload after psp recieved all the gfx firmware */ 2500 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2501 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2502 ret = psp_rlc_autoload_start(psp); 2503 if (ret) { 2504 DRM_ERROR("Failed to start rlc autoload\n"); 2505 return ret; 2506 } 2507 } 2508 } 2509 2510 return 0; 2511 } 2512 2513 static int psp_load_fw(struct amdgpu_device *adev) 2514 { 2515 int ret; 2516 struct psp_context *psp = &adev->psp; 2517 2518 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2519 /* should not destroy ring, only stop */ 2520 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2521 } else { 2522 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2523 2524 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2525 if (ret) { 2526 DRM_ERROR("PSP ring init failed!\n"); 2527 goto failed; 2528 } 2529 } 2530 2531 ret = psp_hw_start(psp); 2532 if (ret) 2533 goto failed; 2534 2535 ret = psp_load_non_psp_fw(psp); 2536 if (ret) 2537 goto failed1; 2538 2539 ret = psp_asd_initialize(psp); 2540 if (ret) { 2541 DRM_ERROR("PSP load asd failed!\n"); 2542 goto failed1; 2543 } 2544 2545 ret = psp_rl_load(adev); 2546 if (ret) { 2547 DRM_ERROR("PSP load RL failed!\n"); 2548 goto failed1; 2549 } 2550 2551 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2552 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2553 ret = psp_xgmi_initialize(psp, false, true); 2554 /* Warning the XGMI seesion initialize failure 2555 * Instead of stop driver initialization 2556 */ 2557 if (ret) 2558 dev_err(psp->adev->dev, 2559 "XGMI: Failed to initialize XGMI session\n"); 2560 } 2561 } 2562 2563 if (psp->ta_fw) { 2564 ret = psp_ras_initialize(psp); 2565 if (ret) 2566 dev_err(psp->adev->dev, 2567 "RAS: Failed to initialize RAS\n"); 2568 2569 ret = psp_hdcp_initialize(psp); 2570 if (ret) 2571 dev_err(psp->adev->dev, 2572 "HDCP: Failed to initialize HDCP\n"); 2573 2574 ret = psp_dtm_initialize(psp); 2575 if (ret) 2576 dev_err(psp->adev->dev, 2577 "DTM: Failed to initialize DTM\n"); 2578 2579 ret = psp_rap_initialize(psp); 2580 if (ret) 2581 dev_err(psp->adev->dev, 2582 "RAP: Failed to initialize RAP\n"); 2583 2584 ret = psp_securedisplay_initialize(psp); 2585 if (ret) 2586 dev_err(psp->adev->dev, 2587 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2588 } 2589 2590 return 0; 2591 2592 failed1: 2593 psp_free_shared_bufs(psp); 2594 failed: 2595 /* 2596 * all cleanup jobs (xgmi terminate, ras terminate, 2597 * ring destroy, cmd/fence/fw buffers destory, 2598 * psp->cmd destory) are delayed to psp_hw_fini 2599 */ 2600 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2601 return ret; 2602 } 2603 2604 static int psp_hw_init(void *handle) 2605 { 2606 int ret; 2607 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2608 2609 mutex_lock(&adev->firmware.mutex); 2610 /* 2611 * This sequence is just used on hw_init only once, no need on 2612 * resume. 2613 */ 2614 ret = amdgpu_ucode_init_bo(adev); 2615 if (ret) 2616 goto failed; 2617 2618 ret = psp_load_fw(adev); 2619 if (ret) { 2620 DRM_ERROR("PSP firmware loading failed\n"); 2621 goto failed; 2622 } 2623 2624 mutex_unlock(&adev->firmware.mutex); 2625 return 0; 2626 2627 failed: 2628 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2629 mutex_unlock(&adev->firmware.mutex); 2630 return -EINVAL; 2631 } 2632 2633 static int psp_hw_fini(void *handle) 2634 { 2635 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2636 struct psp_context *psp = &adev->psp; 2637 2638 if (psp->ta_fw) { 2639 psp_ras_terminate(psp); 2640 psp_securedisplay_terminate(psp); 2641 psp_rap_terminate(psp); 2642 psp_dtm_terminate(psp); 2643 psp_hdcp_terminate(psp); 2644 2645 if (adev->gmc.xgmi.num_physical_nodes > 1) 2646 psp_xgmi_terminate(psp); 2647 } 2648 2649 psp_asd_terminate(psp); 2650 psp_tmr_terminate(psp); 2651 2652 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2653 2654 return 0; 2655 } 2656 2657 static int psp_suspend(void *handle) 2658 { 2659 int ret = 0; 2660 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2661 struct psp_context *psp = &adev->psp; 2662 2663 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2664 psp->xgmi_context.context.initialized) { 2665 ret = psp_xgmi_terminate(psp); 2666 if (ret) { 2667 DRM_ERROR("Failed to terminate xgmi ta\n"); 2668 goto out; 2669 } 2670 } 2671 2672 if (psp->ta_fw) { 2673 ret = psp_ras_terminate(psp); 2674 if (ret) { 2675 DRM_ERROR("Failed to terminate ras ta\n"); 2676 goto out; 2677 } 2678 ret = psp_hdcp_terminate(psp); 2679 if (ret) { 2680 DRM_ERROR("Failed to terminate hdcp ta\n"); 2681 goto out; 2682 } 2683 ret = psp_dtm_terminate(psp); 2684 if (ret) { 2685 DRM_ERROR("Failed to terminate dtm ta\n"); 2686 goto out; 2687 } 2688 ret = psp_rap_terminate(psp); 2689 if (ret) { 2690 DRM_ERROR("Failed to terminate rap ta\n"); 2691 goto out; 2692 } 2693 ret = psp_securedisplay_terminate(psp); 2694 if (ret) { 2695 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2696 goto out; 2697 } 2698 } 2699 2700 ret = psp_asd_terminate(psp); 2701 if (ret) { 2702 DRM_ERROR("Failed to terminate asd\n"); 2703 goto out; 2704 } 2705 2706 ret = psp_tmr_terminate(psp); 2707 if (ret) { 2708 DRM_ERROR("Failed to terminate tmr\n"); 2709 goto out; 2710 } 2711 2712 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2713 if (ret) 2714 DRM_ERROR("PSP ring stop failed\n"); 2715 2716 out: 2717 return ret; 2718 } 2719 2720 static int psp_resume(void *handle) 2721 { 2722 int ret; 2723 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2724 struct psp_context *psp = &adev->psp; 2725 2726 DRM_INFO("PSP is resuming...\n"); 2727 2728 if (psp->mem_train_ctx.enable_mem_training) { 2729 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2730 if (ret) { 2731 DRM_ERROR("Failed to process memory training!\n"); 2732 return ret; 2733 } 2734 } 2735 2736 mutex_lock(&adev->firmware.mutex); 2737 2738 ret = psp_hw_start(psp); 2739 if (ret) 2740 goto failed; 2741 2742 ret = psp_load_non_psp_fw(psp); 2743 if (ret) 2744 goto failed; 2745 2746 ret = psp_asd_initialize(psp); 2747 if (ret) { 2748 DRM_ERROR("PSP load asd failed!\n"); 2749 goto failed; 2750 } 2751 2752 ret = psp_rl_load(adev); 2753 if (ret) { 2754 dev_err(adev->dev, "PSP load RL failed!\n"); 2755 goto failed; 2756 } 2757 2758 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2759 ret = psp_xgmi_initialize(psp, false, true); 2760 /* Warning the XGMI seesion initialize failure 2761 * Instead of stop driver initialization 2762 */ 2763 if (ret) 2764 dev_err(psp->adev->dev, 2765 "XGMI: Failed to initialize XGMI session\n"); 2766 } 2767 2768 if (psp->ta_fw) { 2769 ret = psp_ras_initialize(psp); 2770 if (ret) 2771 dev_err(psp->adev->dev, 2772 "RAS: Failed to initialize RAS\n"); 2773 2774 ret = psp_hdcp_initialize(psp); 2775 if (ret) 2776 dev_err(psp->adev->dev, 2777 "HDCP: Failed to initialize HDCP\n"); 2778 2779 ret = psp_dtm_initialize(psp); 2780 if (ret) 2781 dev_err(psp->adev->dev, 2782 "DTM: Failed to initialize DTM\n"); 2783 2784 ret = psp_rap_initialize(psp); 2785 if (ret) 2786 dev_err(psp->adev->dev, 2787 "RAP: Failed to initialize RAP\n"); 2788 2789 ret = psp_securedisplay_initialize(psp); 2790 if (ret) 2791 dev_err(psp->adev->dev, 2792 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2793 } 2794 2795 mutex_unlock(&adev->firmware.mutex); 2796 2797 return 0; 2798 2799 failed: 2800 DRM_ERROR("PSP resume failed\n"); 2801 mutex_unlock(&adev->firmware.mutex); 2802 return ret; 2803 } 2804 2805 int psp_gpu_reset(struct amdgpu_device *adev) 2806 { 2807 int ret; 2808 2809 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2810 return 0; 2811 2812 mutex_lock(&adev->psp.mutex); 2813 ret = psp_mode1_reset(&adev->psp); 2814 mutex_unlock(&adev->psp.mutex); 2815 2816 return ret; 2817 } 2818 2819 int psp_rlc_autoload_start(struct psp_context *psp) 2820 { 2821 int ret; 2822 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2823 2824 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2825 2826 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2827 psp->fence_buf_mc_addr); 2828 2829 release_psp_cmd_buf(psp); 2830 2831 return ret; 2832 } 2833 2834 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2835 uint64_t cmd_gpu_addr, int cmd_size) 2836 { 2837 struct amdgpu_firmware_info ucode = {0}; 2838 2839 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2840 AMDGPU_UCODE_ID_VCN0_RAM; 2841 ucode.mc_addr = cmd_gpu_addr; 2842 ucode.ucode_size = cmd_size; 2843 2844 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2845 } 2846 2847 int psp_ring_cmd_submit(struct psp_context *psp, 2848 uint64_t cmd_buf_mc_addr, 2849 uint64_t fence_mc_addr, 2850 int index) 2851 { 2852 unsigned int psp_write_ptr_reg = 0; 2853 struct psp_gfx_rb_frame *write_frame; 2854 struct psp_ring *ring = &psp->km_ring; 2855 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2856 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2857 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2858 struct amdgpu_device *adev = psp->adev; 2859 uint32_t ring_size_dw = ring->ring_size / 4; 2860 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2861 2862 /* KM (GPCOM) prepare write pointer */ 2863 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2864 2865 /* Update KM RB frame pointer to new frame */ 2866 /* write_frame ptr increments by size of rb_frame in bytes */ 2867 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2868 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2869 write_frame = ring_buffer_start; 2870 else 2871 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2872 /* Check invalid write_frame ptr address */ 2873 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2874 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2875 ring_buffer_start, ring_buffer_end, write_frame); 2876 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2877 return -EINVAL; 2878 } 2879 2880 /* Initialize KM RB frame */ 2881 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2882 2883 /* Update KM RB frame */ 2884 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2885 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2886 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2887 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2888 write_frame->fence_value = index; 2889 amdgpu_device_flush_hdp(adev, NULL); 2890 2891 /* Update the write Pointer in DWORDs */ 2892 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2893 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2894 return 0; 2895 } 2896 2897 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 2898 { 2899 struct amdgpu_device *adev = psp->adev; 2900 char fw_name[PSP_FW_NAME_LEN]; 2901 const struct psp_firmware_header_v1_0 *asd_hdr; 2902 int err = 0; 2903 2904 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2905 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name); 2906 if (err) 2907 goto out; 2908 2909 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2910 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2911 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2912 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2913 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2914 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2915 return 0; 2916 out: 2917 amdgpu_ucode_release(&adev->psp.asd_fw); 2918 return err; 2919 } 2920 2921 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 2922 { 2923 struct amdgpu_device *adev = psp->adev; 2924 char fw_name[PSP_FW_NAME_LEN]; 2925 const struct psp_firmware_header_v1_0 *toc_hdr; 2926 int err = 0; 2927 2928 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2929 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 2930 if (err) 2931 goto out; 2932 2933 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2934 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2935 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2936 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2937 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2938 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2939 return 0; 2940 out: 2941 amdgpu_ucode_release(&adev->psp.toc_fw); 2942 return err; 2943 } 2944 2945 static int parse_sos_bin_descriptor(struct psp_context *psp, 2946 const struct psp_fw_bin_desc *desc, 2947 const struct psp_firmware_header_v2_0 *sos_hdr) 2948 { 2949 uint8_t *ucode_start_addr = NULL; 2950 2951 if (!psp || !desc || !sos_hdr) 2952 return -EINVAL; 2953 2954 ucode_start_addr = (uint8_t *)sos_hdr + 2955 le32_to_cpu(desc->offset_bytes) + 2956 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2957 2958 switch (desc->fw_type) { 2959 case PSP_FW_TYPE_PSP_SOS: 2960 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2961 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2962 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2963 psp->sos.start_addr = ucode_start_addr; 2964 break; 2965 case PSP_FW_TYPE_PSP_SYS_DRV: 2966 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2967 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2968 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2969 psp->sys.start_addr = ucode_start_addr; 2970 break; 2971 case PSP_FW_TYPE_PSP_KDB: 2972 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2973 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2974 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2975 psp->kdb.start_addr = ucode_start_addr; 2976 break; 2977 case PSP_FW_TYPE_PSP_TOC: 2978 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2979 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2980 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 2981 psp->toc.start_addr = ucode_start_addr; 2982 break; 2983 case PSP_FW_TYPE_PSP_SPL: 2984 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 2985 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 2986 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 2987 psp->spl.start_addr = ucode_start_addr; 2988 break; 2989 case PSP_FW_TYPE_PSP_RL: 2990 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 2991 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 2992 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 2993 psp->rl.start_addr = ucode_start_addr; 2994 break; 2995 case PSP_FW_TYPE_PSP_SOC_DRV: 2996 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 2997 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 2998 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2999 psp->soc_drv.start_addr = ucode_start_addr; 3000 break; 3001 case PSP_FW_TYPE_PSP_INTF_DRV: 3002 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3003 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3004 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3005 psp->intf_drv.start_addr = ucode_start_addr; 3006 break; 3007 case PSP_FW_TYPE_PSP_DBG_DRV: 3008 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3009 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3010 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3011 psp->dbg_drv.start_addr = ucode_start_addr; 3012 break; 3013 case PSP_FW_TYPE_PSP_RAS_DRV: 3014 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3015 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3016 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3017 psp->ras_drv.start_addr = ucode_start_addr; 3018 break; 3019 default: 3020 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3021 break; 3022 } 3023 3024 return 0; 3025 } 3026 3027 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3028 { 3029 const struct psp_firmware_header_v1_0 *sos_hdr; 3030 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3031 uint8_t *ucode_array_start_addr; 3032 3033 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3034 ucode_array_start_addr = (uint8_t *)sos_hdr + 3035 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3036 3037 if (adev->gmc.xgmi.connected_to_cpu || 3038 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3039 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3040 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3041 3042 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3043 adev->psp.sys.start_addr = ucode_array_start_addr; 3044 3045 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3046 adev->psp.sos.start_addr = ucode_array_start_addr + 3047 le32_to_cpu(sos_hdr->sos.offset_bytes); 3048 } else { 3049 /* Load alternate PSP SOS FW */ 3050 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3051 3052 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3053 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3054 3055 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3056 adev->psp.sys.start_addr = ucode_array_start_addr + 3057 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3058 3059 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3060 adev->psp.sos.start_addr = ucode_array_start_addr + 3061 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3062 } 3063 3064 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3065 dev_warn(adev->dev, "PSP SOS FW not available"); 3066 return -EINVAL; 3067 } 3068 3069 return 0; 3070 } 3071 3072 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3073 { 3074 struct amdgpu_device *adev = psp->adev; 3075 char fw_name[PSP_FW_NAME_LEN]; 3076 const struct psp_firmware_header_v1_0 *sos_hdr; 3077 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3078 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3079 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3080 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3081 int err = 0; 3082 uint8_t *ucode_array_start_addr; 3083 int fw_index = 0; 3084 3085 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3086 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name); 3087 if (err) 3088 goto out; 3089 3090 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3091 ucode_array_start_addr = (uint8_t *)sos_hdr + 3092 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3093 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3094 3095 switch (sos_hdr->header.header_version_major) { 3096 case 1: 3097 err = psp_init_sos_base_fw(adev); 3098 if (err) 3099 goto out; 3100 3101 if (sos_hdr->header.header_version_minor == 1) { 3102 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3103 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3104 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3105 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3106 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3107 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3108 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3109 } 3110 if (sos_hdr->header.header_version_minor == 2) { 3111 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3112 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3113 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3114 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3115 } 3116 if (sos_hdr->header.header_version_minor == 3) { 3117 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3118 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3119 adev->psp.toc.start_addr = ucode_array_start_addr + 3120 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3121 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3122 adev->psp.kdb.start_addr = ucode_array_start_addr + 3123 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3124 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3125 adev->psp.spl.start_addr = ucode_array_start_addr + 3126 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3127 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3128 adev->psp.rl.start_addr = ucode_array_start_addr + 3129 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3130 } 3131 break; 3132 case 2: 3133 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3134 3135 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3136 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3137 err = -EINVAL; 3138 goto out; 3139 } 3140 3141 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3142 err = parse_sos_bin_descriptor(psp, 3143 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3144 sos_hdr_v2_0); 3145 if (err) 3146 goto out; 3147 } 3148 break; 3149 default: 3150 dev_err(adev->dev, 3151 "unsupported psp sos firmware\n"); 3152 err = -EINVAL; 3153 goto out; 3154 } 3155 3156 return 0; 3157 out: 3158 amdgpu_ucode_release(&adev->psp.sos_fw); 3159 3160 return err; 3161 } 3162 3163 static int parse_ta_bin_descriptor(struct psp_context *psp, 3164 const struct psp_fw_bin_desc *desc, 3165 const struct ta_firmware_header_v2_0 *ta_hdr) 3166 { 3167 uint8_t *ucode_start_addr = NULL; 3168 3169 if (!psp || !desc || !ta_hdr) 3170 return -EINVAL; 3171 3172 ucode_start_addr = (uint8_t *)ta_hdr + 3173 le32_to_cpu(desc->offset_bytes) + 3174 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3175 3176 switch (desc->fw_type) { 3177 case TA_FW_TYPE_PSP_ASD: 3178 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3179 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3180 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3181 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3182 break; 3183 case TA_FW_TYPE_PSP_XGMI: 3184 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3185 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3186 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3187 break; 3188 case TA_FW_TYPE_PSP_RAS: 3189 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3190 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3191 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3192 break; 3193 case TA_FW_TYPE_PSP_HDCP: 3194 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3195 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3196 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3197 break; 3198 case TA_FW_TYPE_PSP_DTM: 3199 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3200 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3201 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3202 break; 3203 case TA_FW_TYPE_PSP_RAP: 3204 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3205 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3206 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3207 break; 3208 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3209 psp->securedisplay_context.context.bin_desc.fw_version = 3210 le32_to_cpu(desc->fw_version); 3211 psp->securedisplay_context.context.bin_desc.size_bytes = 3212 le32_to_cpu(desc->size_bytes); 3213 psp->securedisplay_context.context.bin_desc.start_addr = 3214 ucode_start_addr; 3215 break; 3216 default: 3217 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3218 break; 3219 } 3220 3221 return 0; 3222 } 3223 3224 static int parse_ta_v1_microcode(struct psp_context *psp) 3225 { 3226 const struct ta_firmware_header_v1_0 *ta_hdr; 3227 struct amdgpu_device *adev = psp->adev; 3228 3229 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3230 3231 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3232 return -EINVAL; 3233 3234 adev->psp.xgmi_context.context.bin_desc.fw_version = 3235 le32_to_cpu(ta_hdr->xgmi.fw_version); 3236 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3237 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3238 adev->psp.xgmi_context.context.bin_desc.start_addr = 3239 (uint8_t *)ta_hdr + 3240 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3241 3242 adev->psp.ras_context.context.bin_desc.fw_version = 3243 le32_to_cpu(ta_hdr->ras.fw_version); 3244 adev->psp.ras_context.context.bin_desc.size_bytes = 3245 le32_to_cpu(ta_hdr->ras.size_bytes); 3246 adev->psp.ras_context.context.bin_desc.start_addr = 3247 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3248 le32_to_cpu(ta_hdr->ras.offset_bytes); 3249 3250 adev->psp.hdcp_context.context.bin_desc.fw_version = 3251 le32_to_cpu(ta_hdr->hdcp.fw_version); 3252 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3253 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3254 adev->psp.hdcp_context.context.bin_desc.start_addr = 3255 (uint8_t *)ta_hdr + 3256 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3257 3258 adev->psp.dtm_context.context.bin_desc.fw_version = 3259 le32_to_cpu(ta_hdr->dtm.fw_version); 3260 adev->psp.dtm_context.context.bin_desc.size_bytes = 3261 le32_to_cpu(ta_hdr->dtm.size_bytes); 3262 adev->psp.dtm_context.context.bin_desc.start_addr = 3263 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3264 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3265 3266 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3267 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3268 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3269 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3270 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3271 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3272 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3273 3274 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3275 3276 return 0; 3277 } 3278 3279 static int parse_ta_v2_microcode(struct psp_context *psp) 3280 { 3281 const struct ta_firmware_header_v2_0 *ta_hdr; 3282 struct amdgpu_device *adev = psp->adev; 3283 int err = 0; 3284 int ta_index = 0; 3285 3286 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3287 3288 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3289 return -EINVAL; 3290 3291 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3292 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3293 return -EINVAL; 3294 } 3295 3296 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3297 err = parse_ta_bin_descriptor(psp, 3298 &ta_hdr->ta_fw_bin[ta_index], 3299 ta_hdr); 3300 if (err) 3301 return err; 3302 } 3303 3304 return 0; 3305 } 3306 3307 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3308 { 3309 const struct common_firmware_header *hdr; 3310 struct amdgpu_device *adev = psp->adev; 3311 char fw_name[PSP_FW_NAME_LEN]; 3312 int err; 3313 3314 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3315 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name); 3316 if (err) 3317 return err; 3318 3319 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3320 switch (le16_to_cpu(hdr->header_version_major)) { 3321 case 1: 3322 err = parse_ta_v1_microcode(psp); 3323 break; 3324 case 2: 3325 err = parse_ta_v2_microcode(psp); 3326 break; 3327 default: 3328 dev_err(adev->dev, "unsupported TA header version\n"); 3329 err = -EINVAL; 3330 } 3331 3332 if (err) 3333 amdgpu_ucode_release(&adev->psp.ta_fw); 3334 3335 return err; 3336 } 3337 3338 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 3339 { 3340 struct amdgpu_device *adev = psp->adev; 3341 char fw_name[PSP_FW_NAME_LEN]; 3342 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3343 struct amdgpu_firmware_info *info = NULL; 3344 int err = 0; 3345 3346 if (!amdgpu_sriov_vf(adev)) { 3347 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3348 return -EINVAL; 3349 } 3350 3351 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3352 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name); 3353 if (err) { 3354 if (err == -ENODEV) { 3355 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3356 err = 0; 3357 goto out; 3358 } 3359 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3360 } 3361 3362 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3363 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3364 info->fw = adev->psp.cap_fw; 3365 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3366 adev->psp.cap_fw->data; 3367 adev->firmware.fw_size += ALIGN( 3368 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3369 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3370 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3371 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3372 3373 return 0; 3374 3375 out: 3376 amdgpu_ucode_release(&adev->psp.cap_fw); 3377 return err; 3378 } 3379 3380 static int psp_set_clockgating_state(void *handle, 3381 enum amd_clockgating_state state) 3382 { 3383 return 0; 3384 } 3385 3386 static int psp_set_powergating_state(void *handle, 3387 enum amd_powergating_state state) 3388 { 3389 return 0; 3390 } 3391 3392 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3393 struct device_attribute *attr, 3394 char *buf) 3395 { 3396 struct drm_device *ddev = dev_get_drvdata(dev); 3397 struct amdgpu_device *adev = drm_to_adev(ddev); 3398 uint32_t fw_ver; 3399 int ret; 3400 3401 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3402 DRM_INFO("PSP block is not ready yet."); 3403 return -EBUSY; 3404 } 3405 3406 mutex_lock(&adev->psp.mutex); 3407 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3408 mutex_unlock(&adev->psp.mutex); 3409 3410 if (ret) { 3411 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3412 return ret; 3413 } 3414 3415 return sysfs_emit(buf, "%x\n", fw_ver); 3416 } 3417 3418 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3419 struct device_attribute *attr, 3420 const char *buf, 3421 size_t count) 3422 { 3423 struct drm_device *ddev = dev_get_drvdata(dev); 3424 struct amdgpu_device *adev = drm_to_adev(ddev); 3425 int ret, idx; 3426 char fw_name[100]; 3427 const struct firmware *usbc_pd_fw; 3428 struct amdgpu_bo *fw_buf_bo = NULL; 3429 uint64_t fw_pri_mc_addr; 3430 void *fw_pri_cpu_addr; 3431 3432 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3433 DRM_INFO("PSP block is not ready yet."); 3434 return -EBUSY; 3435 } 3436 3437 if (!drm_dev_enter(ddev, &idx)) 3438 return -ENODEV; 3439 3440 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3441 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3442 if (ret) 3443 goto fail; 3444 3445 /* LFB address which is aligned to 1MB boundary per PSP request */ 3446 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3447 AMDGPU_GEM_DOMAIN_VRAM | 3448 AMDGPU_GEM_DOMAIN_GTT, 3449 &fw_buf_bo, &fw_pri_mc_addr, 3450 &fw_pri_cpu_addr); 3451 if (ret) 3452 goto rel_buf; 3453 3454 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3455 3456 mutex_lock(&adev->psp.mutex); 3457 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3458 mutex_unlock(&adev->psp.mutex); 3459 3460 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3461 3462 rel_buf: 3463 release_firmware(usbc_pd_fw); 3464 fail: 3465 if (ret) { 3466 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3467 count = ret; 3468 } 3469 3470 drm_dev_exit(idx); 3471 return count; 3472 } 3473 3474 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3475 { 3476 int idx; 3477 3478 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3479 return; 3480 3481 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3482 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3483 3484 drm_dev_exit(idx); 3485 } 3486 3487 static DEVICE_ATTR(usbc_pd_fw, 0644, 3488 psp_usbc_pd_fw_sysfs_read, 3489 psp_usbc_pd_fw_sysfs_write); 3490 3491 int is_psp_fw_valid(struct psp_bin_desc bin) 3492 { 3493 return bin.size_bytes; 3494 } 3495 3496 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3497 struct bin_attribute *bin_attr, 3498 char *buffer, loff_t pos, size_t count) 3499 { 3500 struct device *dev = kobj_to_dev(kobj); 3501 struct drm_device *ddev = dev_get_drvdata(dev); 3502 struct amdgpu_device *adev = drm_to_adev(ddev); 3503 3504 adev->psp.vbflash_done = false; 3505 3506 /* Safeguard against memory drain */ 3507 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3508 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3509 kvfree(adev->psp.vbflash_tmp_buf); 3510 adev->psp.vbflash_tmp_buf = NULL; 3511 adev->psp.vbflash_image_size = 0; 3512 return -ENOMEM; 3513 } 3514 3515 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3516 if (!adev->psp.vbflash_tmp_buf) { 3517 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3518 if (!adev->psp.vbflash_tmp_buf) 3519 return -ENOMEM; 3520 } 3521 3522 mutex_lock(&adev->psp.mutex); 3523 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3524 adev->psp.vbflash_image_size += count; 3525 mutex_unlock(&adev->psp.mutex); 3526 3527 dev_info(adev->dev, "VBIOS flash write PSP done"); 3528 3529 return count; 3530 } 3531 3532 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3533 struct bin_attribute *bin_attr, char *buffer, 3534 loff_t pos, size_t count) 3535 { 3536 struct device *dev = kobj_to_dev(kobj); 3537 struct drm_device *ddev = dev_get_drvdata(dev); 3538 struct amdgpu_device *adev = drm_to_adev(ddev); 3539 struct amdgpu_bo *fw_buf_bo = NULL; 3540 uint64_t fw_pri_mc_addr; 3541 void *fw_pri_cpu_addr; 3542 int ret; 3543 3544 dev_info(adev->dev, "VBIOS flash to PSP started"); 3545 3546 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3547 AMDGPU_GPU_PAGE_SIZE, 3548 AMDGPU_GEM_DOMAIN_VRAM, 3549 &fw_buf_bo, 3550 &fw_pri_mc_addr, 3551 &fw_pri_cpu_addr); 3552 if (ret) 3553 goto rel_buf; 3554 3555 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3556 3557 mutex_lock(&adev->psp.mutex); 3558 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3559 mutex_unlock(&adev->psp.mutex); 3560 3561 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3562 3563 rel_buf: 3564 kvfree(adev->psp.vbflash_tmp_buf); 3565 adev->psp.vbflash_tmp_buf = NULL; 3566 adev->psp.vbflash_image_size = 0; 3567 3568 if (ret) { 3569 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret); 3570 return ret; 3571 } 3572 3573 dev_info(adev->dev, "VBIOS flash to PSP done"); 3574 return 0; 3575 } 3576 3577 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3578 struct device_attribute *attr, 3579 char *buf) 3580 { 3581 struct drm_device *ddev = dev_get_drvdata(dev); 3582 struct amdgpu_device *adev = drm_to_adev(ddev); 3583 uint32_t vbflash_status; 3584 3585 vbflash_status = psp_vbflash_status(&adev->psp); 3586 if (!adev->psp.vbflash_done) 3587 vbflash_status = 0; 3588 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3589 vbflash_status = 1; 3590 3591 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3592 } 3593 3594 static const struct bin_attribute psp_vbflash_bin_attr = { 3595 .attr = {.name = "psp_vbflash", .mode = 0664}, 3596 .size = 0, 3597 .write = amdgpu_psp_vbflash_write, 3598 .read = amdgpu_psp_vbflash_read, 3599 }; 3600 3601 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL); 3602 3603 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev) 3604 { 3605 int ret = 0; 3606 struct psp_context *psp = &adev->psp; 3607 3608 if (amdgpu_sriov_vf(adev)) 3609 return -EINVAL; 3610 3611 switch (adev->ip_versions[MP0_HWIP][0]) { 3612 case IP_VERSION(13, 0, 0): 3613 case IP_VERSION(13, 0, 7): 3614 case IP_VERSION(13, 0, 10): 3615 if (!psp->adev) { 3616 psp->adev = adev; 3617 psp_v13_0_set_psp_funcs(psp); 3618 } 3619 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3620 if (ret) 3621 dev_err(adev->dev, "Failed to create device file psp_vbflash"); 3622 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status); 3623 if (ret) 3624 dev_err(adev->dev, "Failed to create device file psp_vbflash_status"); 3625 return ret; 3626 default: 3627 return 0; 3628 } 3629 } 3630 3631 const struct amd_ip_funcs psp_ip_funcs = { 3632 .name = "psp", 3633 .early_init = psp_early_init, 3634 .late_init = NULL, 3635 .sw_init = psp_sw_init, 3636 .sw_fini = psp_sw_fini, 3637 .hw_init = psp_hw_init, 3638 .hw_fini = psp_hw_fini, 3639 .suspend = psp_suspend, 3640 .resume = psp_resume, 3641 .is_idle = NULL, 3642 .check_soft_reset = NULL, 3643 .wait_for_idle = NULL, 3644 .soft_reset = NULL, 3645 .set_clockgating_state = psp_set_clockgating_state, 3646 .set_powergating_state = psp_set_powergating_state, 3647 }; 3648 3649 static int psp_sysfs_init(struct amdgpu_device *adev) 3650 { 3651 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3652 3653 if (ret) 3654 DRM_ERROR("Failed to create USBC PD FW control file!"); 3655 3656 return ret; 3657 } 3658 3659 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev) 3660 { 3661 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3662 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status); 3663 } 3664 3665 static void psp_sysfs_fini(struct amdgpu_device *adev) 3666 { 3667 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3668 } 3669 3670 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 3671 .type = AMD_IP_BLOCK_TYPE_PSP, 3672 .major = 3, 3673 .minor = 1, 3674 .rev = 0, 3675 .funcs = &psp_ip_funcs, 3676 }; 3677 3678 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 3679 .type = AMD_IP_BLOCK_TYPE_PSP, 3680 .major = 10, 3681 .minor = 0, 3682 .rev = 0, 3683 .funcs = &psp_ip_funcs, 3684 }; 3685 3686 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 3687 .type = AMD_IP_BLOCK_TYPE_PSP, 3688 .major = 11, 3689 .minor = 0, 3690 .rev = 0, 3691 .funcs = &psp_ip_funcs, 3692 }; 3693 3694 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3695 .type = AMD_IP_BLOCK_TYPE_PSP, 3696 .major = 11, 3697 .minor = 0, 3698 .rev = 8, 3699 .funcs = &psp_ip_funcs, 3700 }; 3701 3702 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 3703 .type = AMD_IP_BLOCK_TYPE_PSP, 3704 .major = 12, 3705 .minor = 0, 3706 .rev = 0, 3707 .funcs = &psp_ip_funcs, 3708 }; 3709 3710 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3711 .type = AMD_IP_BLOCK_TYPE_PSP, 3712 .major = 13, 3713 .minor = 0, 3714 .rev = 0, 3715 .funcs = &psp_ip_funcs, 3716 }; 3717 3718 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3719 .type = AMD_IP_BLOCK_TYPE_PSP, 3720 .major = 13, 3721 .minor = 0, 3722 .rev = 4, 3723 .funcs = &psp_ip_funcs, 3724 }; 3725