1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 41 #include "amdgpu_ras.h" 42 #include "amdgpu_securedisplay.h" 43 #include "amdgpu_atomfirmware.h" 44 45 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 46 47 static int psp_sysfs_init(struct amdgpu_device *adev); 48 static void psp_sysfs_fini(struct amdgpu_device *adev); 49 50 static int psp_load_smu_fw(struct psp_context *psp); 51 static int psp_rap_terminate(struct psp_context *psp); 52 static int psp_securedisplay_terminate(struct psp_context *psp); 53 54 /* 55 * Due to DF Cstate management centralized to PMFW, the firmware 56 * loading sequence will be updated as below: 57 * - Load KDB 58 * - Load SYS_DRV 59 * - Load tOS 60 * - Load PMFW 61 * - Setup TMR 62 * - Load other non-psp fw 63 * - Load ASD 64 * - Load XGMI/RAS/HDCP/DTM TA if any 65 * 66 * This new sequence is required for 67 * - Arcturus and onwards 68 */ 69 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 70 { 71 struct amdgpu_device *adev = psp->adev; 72 73 if (amdgpu_sriov_vf(adev)) { 74 psp->pmfw_centralized_cstate_management = false; 75 return; 76 } 77 78 switch (adev->ip_versions[MP0_HWIP][0]) { 79 case IP_VERSION(11, 0, 0): 80 case IP_VERSION(11, 0, 4): 81 case IP_VERSION(11, 0, 5): 82 case IP_VERSION(11, 0, 7): 83 case IP_VERSION(11, 0, 9): 84 case IP_VERSION(11, 0, 11): 85 case IP_VERSION(11, 0, 12): 86 case IP_VERSION(11, 0, 13): 87 case IP_VERSION(13, 0, 0): 88 case IP_VERSION(13, 0, 2): 89 case IP_VERSION(13, 0, 7): 90 psp->pmfw_centralized_cstate_management = true; 91 break; 92 default: 93 psp->pmfw_centralized_cstate_management = false; 94 break; 95 } 96 } 97 98 static int psp_early_init(void *handle) 99 { 100 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 101 struct psp_context *psp = &adev->psp; 102 103 switch (adev->ip_versions[MP0_HWIP][0]) { 104 case IP_VERSION(9, 0, 0): 105 psp_v3_1_set_psp_funcs(psp); 106 psp->autoload_supported = false; 107 break; 108 case IP_VERSION(10, 0, 0): 109 case IP_VERSION(10, 0, 1): 110 psp_v10_0_set_psp_funcs(psp); 111 psp->autoload_supported = false; 112 break; 113 case IP_VERSION(11, 0, 2): 114 case IP_VERSION(11, 0, 4): 115 psp_v11_0_set_psp_funcs(psp); 116 psp->autoload_supported = false; 117 break; 118 case IP_VERSION(11, 0, 0): 119 case IP_VERSION(11, 0, 5): 120 case IP_VERSION(11, 0, 9): 121 case IP_VERSION(11, 0, 7): 122 case IP_VERSION(11, 0, 11): 123 case IP_VERSION(11, 5, 0): 124 case IP_VERSION(11, 0, 12): 125 case IP_VERSION(11, 0, 13): 126 psp_v11_0_set_psp_funcs(psp); 127 psp->autoload_supported = true; 128 break; 129 case IP_VERSION(11, 0, 3): 130 case IP_VERSION(12, 0, 1): 131 psp_v12_0_set_psp_funcs(psp); 132 break; 133 case IP_VERSION(13, 0, 2): 134 psp_v13_0_set_psp_funcs(psp); 135 break; 136 case IP_VERSION(13, 0, 1): 137 case IP_VERSION(13, 0, 3): 138 case IP_VERSION(13, 0, 5): 139 case IP_VERSION(13, 0, 8): 140 psp_v13_0_set_psp_funcs(psp); 141 psp->autoload_supported = true; 142 break; 143 case IP_VERSION(11, 0, 8): 144 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 145 psp_v11_0_8_set_psp_funcs(psp); 146 psp->autoload_supported = false; 147 } 148 break; 149 case IP_VERSION(13, 0, 0): 150 case IP_VERSION(13, 0, 7): 151 psp_v13_0_set_psp_funcs(psp); 152 psp->autoload_supported = true; 153 break; 154 default: 155 return -EINVAL; 156 } 157 158 psp->adev = adev; 159 160 psp_check_pmfw_centralized_cstate_management(psp); 161 162 return 0; 163 } 164 165 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 166 { 167 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 168 &mem_ctx->shared_buf); 169 } 170 171 static void psp_free_shared_bufs(struct psp_context *psp) 172 { 173 void *tmr_buf; 174 void **pptr; 175 176 /* free TMR memory buffer */ 177 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 178 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 179 180 /* free xgmi shared memory */ 181 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 182 183 /* free ras shared memory */ 184 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 185 186 /* free hdcp shared memory */ 187 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 188 189 /* free dtm shared memory */ 190 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 191 192 /* free rap shared memory */ 193 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 194 195 /* free securedisplay shared memory */ 196 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 197 198 199 } 200 201 static void psp_memory_training_fini(struct psp_context *psp) 202 { 203 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 204 205 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 206 kfree(ctx->sys_cache); 207 ctx->sys_cache = NULL; 208 } 209 210 static int psp_memory_training_init(struct psp_context *psp) 211 { 212 int ret; 213 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 214 215 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 216 DRM_DEBUG("memory training is not supported!\n"); 217 return 0; 218 } 219 220 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 221 if (ctx->sys_cache == NULL) { 222 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 223 ret = -ENOMEM; 224 goto Err_out; 225 } 226 227 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 228 ctx->train_data_size, 229 ctx->p2c_train_data_offset, 230 ctx->c2p_train_data_offset); 231 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 232 return 0; 233 234 Err_out: 235 psp_memory_training_fini(psp); 236 return ret; 237 } 238 239 /* 240 * Helper funciton to query psp runtime database entry 241 * 242 * @adev: amdgpu_device pointer 243 * @entry_type: the type of psp runtime database entry 244 * @db_entry: runtime database entry pointer 245 * 246 * Return false if runtime database doesn't exit or entry is invalid 247 * or true if the specific database entry is found, and copy to @db_entry 248 */ 249 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 250 enum psp_runtime_entry_type entry_type, 251 void *db_entry) 252 { 253 uint64_t db_header_pos, db_dir_pos; 254 struct psp_runtime_data_header db_header = {0}; 255 struct psp_runtime_data_directory db_dir = {0}; 256 bool ret = false; 257 int i; 258 259 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 260 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 261 262 /* read runtime db header from vram */ 263 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 264 sizeof(struct psp_runtime_data_header), false); 265 266 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 267 /* runtime db doesn't exist, exit */ 268 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 269 return false; 270 } 271 272 /* read runtime database entry from vram */ 273 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 274 sizeof(struct psp_runtime_data_directory), false); 275 276 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 277 /* invalid db entry count, exit */ 278 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 279 return false; 280 } 281 282 /* look up for requested entry type */ 283 for (i = 0; i < db_dir.entry_count && !ret; i++) { 284 if (db_dir.entry_list[i].entry_type == entry_type) { 285 switch (entry_type) { 286 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 287 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 288 /* invalid db entry size */ 289 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 290 return false; 291 } 292 /* read runtime database entry */ 293 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 294 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 295 ret = true; 296 break; 297 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 298 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 299 /* invalid db entry size */ 300 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 301 return false; 302 } 303 /* read runtime database entry */ 304 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 305 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 306 ret = true; 307 break; 308 default: 309 ret = false; 310 break; 311 } 312 } 313 } 314 315 return ret; 316 } 317 318 static int psp_init_sriov_microcode(struct psp_context *psp) 319 { 320 struct amdgpu_device *adev = psp->adev; 321 int ret = 0; 322 323 switch (adev->ip_versions[MP0_HWIP][0]) { 324 case IP_VERSION(9, 0, 0): 325 ret = psp_init_cap_microcode(psp, "vega10"); 326 break; 327 case IP_VERSION(11, 0, 9): 328 ret = psp_init_cap_microcode(psp, "navi12"); 329 break; 330 case IP_VERSION(11, 0, 7): 331 ret = psp_init_cap_microcode(psp, "sienna_cichlid"); 332 break; 333 case IP_VERSION(13, 0, 2): 334 ret = psp_init_cap_microcode(psp, "aldebaran"); 335 ret &= psp_init_ta_microcode(psp, "aldebaran"); 336 break; 337 default: 338 BUG(); 339 break; 340 } 341 342 return ret; 343 } 344 345 static int psp_sw_init(void *handle) 346 { 347 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 348 struct psp_context *psp = &adev->psp; 349 int ret; 350 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 351 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 352 struct psp_runtime_scpm_entry scpm_entry; 353 354 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 355 if (!psp->cmd) { 356 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 357 ret = -ENOMEM; 358 } 359 360 if (amdgpu_sriov_vf(adev)) 361 ret = psp_init_sriov_microcode(psp); 362 else 363 ret = psp_init_microcode(psp); 364 if (ret) { 365 DRM_ERROR("Failed to load psp firmware!\n"); 366 return ret; 367 } 368 369 adev->psp.xgmi_context.supports_extended_data = 370 !adev->gmc.xgmi.connected_to_cpu && 371 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 372 373 memset(&scpm_entry, 0, sizeof(scpm_entry)); 374 if ((psp_get_runtime_db_entry(adev, 375 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 376 &scpm_entry)) && 377 (SCPM_DISABLE != scpm_entry.scpm_status)) { 378 adev->scpm_enabled = true; 379 adev->scpm_status = scpm_entry.scpm_status; 380 } else { 381 adev->scpm_enabled = false; 382 adev->scpm_status = SCPM_DISABLE; 383 } 384 385 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 386 387 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 388 if (psp_get_runtime_db_entry(adev, 389 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 390 &boot_cfg_entry)) { 391 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 392 if ((psp->boot_cfg_bitmask) & 393 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 394 /* If psp runtime database exists, then 395 * only enable two stage memory training 396 * when TWO_STAGE_DRAM_TRAINING bit is set 397 * in runtime database */ 398 mem_training_ctx->enable_mem_training = true; 399 } 400 401 } else { 402 /* If psp runtime database doesn't exist or 403 * is invalid, force enable two stage memory 404 * training */ 405 mem_training_ctx->enable_mem_training = true; 406 } 407 408 if (mem_training_ctx->enable_mem_training) { 409 ret = psp_memory_training_init(psp); 410 if (ret) { 411 DRM_ERROR("Failed to initialize memory training!\n"); 412 return ret; 413 } 414 415 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 416 if (ret) { 417 DRM_ERROR("Failed to process memory training!\n"); 418 return ret; 419 } 420 } 421 422 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 423 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 424 ret= psp_sysfs_init(adev); 425 if (ret) { 426 return ret; 427 } 428 } 429 430 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 431 amdgpu_sriov_vf(adev) ? 432 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 433 &psp->fw_pri_bo, 434 &psp->fw_pri_mc_addr, 435 &psp->fw_pri_buf); 436 if (ret) 437 return ret; 438 439 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 440 AMDGPU_GEM_DOMAIN_VRAM, 441 &psp->fence_buf_bo, 442 &psp->fence_buf_mc_addr, 443 &psp->fence_buf); 444 if (ret) 445 goto failed1; 446 447 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 448 AMDGPU_GEM_DOMAIN_VRAM, 449 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 450 (void **)&psp->cmd_buf_mem); 451 if (ret) 452 goto failed2; 453 454 return 0; 455 456 failed2: 457 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 458 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 459 failed1: 460 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 461 &psp->fence_buf_mc_addr, &psp->fence_buf); 462 return ret; 463 } 464 465 static int psp_sw_fini(void *handle) 466 { 467 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 468 struct psp_context *psp = &adev->psp; 469 struct psp_gfx_cmd_resp *cmd = psp->cmd; 470 471 psp_memory_training_fini(psp); 472 if (psp->sos_fw) { 473 release_firmware(psp->sos_fw); 474 psp->sos_fw = NULL; 475 } 476 if (psp->asd_fw) { 477 release_firmware(psp->asd_fw); 478 psp->asd_fw = NULL; 479 } 480 if (psp->ta_fw) { 481 release_firmware(psp->ta_fw); 482 psp->ta_fw = NULL; 483 } 484 if (adev->psp.cap_fw) { 485 release_firmware(psp->cap_fw); 486 psp->cap_fw = NULL; 487 } 488 489 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 490 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 491 psp_sysfs_fini(adev); 492 493 kfree(cmd); 494 cmd = NULL; 495 496 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 497 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 498 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 499 &psp->fence_buf_mc_addr, &psp->fence_buf); 500 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 501 (void **)&psp->cmd_buf_mem); 502 503 return 0; 504 } 505 506 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 507 uint32_t reg_val, uint32_t mask, bool check_changed) 508 { 509 uint32_t val; 510 int i; 511 struct amdgpu_device *adev = psp->adev; 512 513 if (psp->adev->no_hw_access) 514 return 0; 515 516 for (i = 0; i < adev->usec_timeout; i++) { 517 val = RREG32(reg_index); 518 if (check_changed) { 519 if (val != reg_val) 520 return 0; 521 } else { 522 if ((val & mask) == reg_val) 523 return 0; 524 } 525 udelay(1); 526 } 527 528 return -ETIME; 529 } 530 531 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 532 { 533 switch (cmd_id) { 534 case GFX_CMD_ID_LOAD_TA: 535 return "LOAD_TA"; 536 case GFX_CMD_ID_UNLOAD_TA: 537 return "UNLOAD_TA"; 538 case GFX_CMD_ID_INVOKE_CMD: 539 return "INVOKE_CMD"; 540 case GFX_CMD_ID_LOAD_ASD: 541 return "LOAD_ASD"; 542 case GFX_CMD_ID_SETUP_TMR: 543 return "SETUP_TMR"; 544 case GFX_CMD_ID_LOAD_IP_FW: 545 return "LOAD_IP_FW"; 546 case GFX_CMD_ID_DESTROY_TMR: 547 return "DESTROY_TMR"; 548 case GFX_CMD_ID_SAVE_RESTORE: 549 return "SAVE_RESTORE_IP_FW"; 550 case GFX_CMD_ID_SETUP_VMR: 551 return "SETUP_VMR"; 552 case GFX_CMD_ID_DESTROY_VMR: 553 return "DESTROY_VMR"; 554 case GFX_CMD_ID_PROG_REG: 555 return "PROG_REG"; 556 case GFX_CMD_ID_GET_FW_ATTESTATION: 557 return "GET_FW_ATTESTATION"; 558 case GFX_CMD_ID_LOAD_TOC: 559 return "ID_LOAD_TOC"; 560 case GFX_CMD_ID_AUTOLOAD_RLC: 561 return "AUTOLOAD_RLC"; 562 case GFX_CMD_ID_BOOT_CFG: 563 return "BOOT_CFG"; 564 default: 565 return "UNKNOWN CMD"; 566 } 567 } 568 569 static int 570 psp_cmd_submit_buf(struct psp_context *psp, 571 struct amdgpu_firmware_info *ucode, 572 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 573 { 574 int ret; 575 int index, idx; 576 int timeout = 20000; 577 bool ras_intr = false; 578 bool skip_unsupport = false; 579 580 if (psp->adev->no_hw_access) 581 return 0; 582 583 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 584 return 0; 585 586 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 587 588 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 589 590 index = atomic_inc_return(&psp->fence_value); 591 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 592 if (ret) { 593 atomic_dec(&psp->fence_value); 594 goto exit; 595 } 596 597 amdgpu_device_invalidate_hdp(psp->adev, NULL); 598 while (*((unsigned int *)psp->fence_buf) != index) { 599 if (--timeout == 0) 600 break; 601 /* 602 * Shouldn't wait for timeout when err_event_athub occurs, 603 * because gpu reset thread triggered and lock resource should 604 * be released for psp resume sequence. 605 */ 606 ras_intr = amdgpu_ras_intr_triggered(); 607 if (ras_intr) 608 break; 609 usleep_range(10, 100); 610 amdgpu_device_invalidate_hdp(psp->adev, NULL); 611 } 612 613 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 614 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 615 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 616 617 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 618 619 /* In some cases, psp response status is not 0 even there is no 620 * problem while the command is submitted. Some version of PSP FW 621 * doesn't write 0 to that field. 622 * So here we would like to only print a warning instead of an error 623 * during psp initialization to avoid breaking hw_init and it doesn't 624 * return -EINVAL. 625 */ 626 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 627 if (ucode) 628 DRM_WARN("failed to load ucode %s(0x%X) ", 629 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 630 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 631 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 632 psp->cmd_buf_mem->resp.status); 633 /* If any firmware (including CAP) load fails under SRIOV, it should 634 * return failure to stop the VF from initializing. 635 * Also return failure in case of timeout 636 */ 637 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 638 ret = -EINVAL; 639 goto exit; 640 } 641 } 642 643 if (ucode) { 644 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 645 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 646 } 647 648 exit: 649 drm_dev_exit(idx); 650 return ret; 651 } 652 653 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 654 { 655 struct psp_gfx_cmd_resp *cmd = psp->cmd; 656 657 mutex_lock(&psp->mutex); 658 659 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 660 661 return cmd; 662 } 663 664 static void release_psp_cmd_buf(struct psp_context *psp) 665 { 666 mutex_unlock(&psp->mutex); 667 } 668 669 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 670 struct psp_gfx_cmd_resp *cmd, 671 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 672 { 673 struct amdgpu_device *adev = psp->adev; 674 uint32_t size = amdgpu_bo_size(tmr_bo); 675 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 676 677 if (amdgpu_sriov_vf(psp->adev)) 678 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 679 else 680 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 681 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 682 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 683 cmd->cmd.cmd_setup_tmr.buf_size = size; 684 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 685 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 686 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 687 } 688 689 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 690 uint64_t pri_buf_mc, uint32_t size) 691 { 692 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 693 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 694 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 695 cmd->cmd.cmd_load_toc.toc_size = size; 696 } 697 698 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 699 static int psp_load_toc(struct psp_context *psp, 700 uint32_t *tmr_size) 701 { 702 int ret; 703 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 704 705 /* Copy toc to psp firmware private buffer */ 706 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 707 708 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 709 710 ret = psp_cmd_submit_buf(psp, NULL, cmd, 711 psp->fence_buf_mc_addr); 712 if (!ret) 713 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 714 715 release_psp_cmd_buf(psp); 716 717 return ret; 718 } 719 720 /* Set up Trusted Memory Region */ 721 static int psp_tmr_init(struct psp_context *psp) 722 { 723 int ret; 724 int tmr_size; 725 void *tmr_buf; 726 void **pptr; 727 728 /* 729 * According to HW engineer, they prefer the TMR address be "naturally 730 * aligned" , e.g. the start address be an integer divide of TMR size. 731 * 732 * Note: this memory need be reserved till the driver 733 * uninitializes. 734 */ 735 tmr_size = PSP_TMR_SIZE(psp->adev); 736 737 /* For ASICs support RLC autoload, psp will parse the toc 738 * and calculate the total size of TMR needed */ 739 if (!amdgpu_sriov_vf(psp->adev) && 740 psp->toc.start_addr && 741 psp->toc.size_bytes && 742 psp->fw_pri_buf) { 743 ret = psp_load_toc(psp, &tmr_size); 744 if (ret) { 745 DRM_ERROR("Failed to load toc\n"); 746 return ret; 747 } 748 } 749 750 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 751 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 752 AMDGPU_GEM_DOMAIN_VRAM, 753 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 754 755 return ret; 756 } 757 758 static bool psp_skip_tmr(struct psp_context *psp) 759 { 760 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 761 case IP_VERSION(11, 0, 9): 762 case IP_VERSION(11, 0, 7): 763 case IP_VERSION(13, 0, 2): 764 return true; 765 default: 766 return false; 767 } 768 } 769 770 static int psp_tmr_load(struct psp_context *psp) 771 { 772 int ret; 773 struct psp_gfx_cmd_resp *cmd; 774 775 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 776 * Already set up by host driver. 777 */ 778 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 779 return 0; 780 781 cmd = acquire_psp_cmd_buf(psp); 782 783 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 784 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 785 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 786 787 ret = psp_cmd_submit_buf(psp, NULL, cmd, 788 psp->fence_buf_mc_addr); 789 790 release_psp_cmd_buf(psp); 791 792 return ret; 793 } 794 795 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 796 struct psp_gfx_cmd_resp *cmd) 797 { 798 if (amdgpu_sriov_vf(psp->adev)) 799 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 800 else 801 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 802 } 803 804 static int psp_tmr_unload(struct psp_context *psp) 805 { 806 int ret; 807 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 808 809 psp_prep_tmr_unload_cmd_buf(psp, cmd); 810 DRM_INFO("free PSP TMR buffer\n"); 811 812 ret = psp_cmd_submit_buf(psp, NULL, cmd, 813 psp->fence_buf_mc_addr); 814 815 release_psp_cmd_buf(psp); 816 817 return ret; 818 } 819 820 static int psp_tmr_terminate(struct psp_context *psp) 821 { 822 return psp_tmr_unload(psp); 823 } 824 825 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 826 uint64_t *output_ptr) 827 { 828 int ret; 829 struct psp_gfx_cmd_resp *cmd; 830 831 if (!output_ptr) 832 return -EINVAL; 833 834 if (amdgpu_sriov_vf(psp->adev)) 835 return 0; 836 837 cmd = acquire_psp_cmd_buf(psp); 838 839 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 840 841 ret = psp_cmd_submit_buf(psp, NULL, cmd, 842 psp->fence_buf_mc_addr); 843 844 if (!ret) { 845 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 846 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 847 } 848 849 release_psp_cmd_buf(psp); 850 851 return ret; 852 } 853 854 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 855 { 856 struct psp_context *psp = &adev->psp; 857 struct psp_gfx_cmd_resp *cmd; 858 int ret; 859 860 if (amdgpu_sriov_vf(adev)) 861 return 0; 862 863 cmd = acquire_psp_cmd_buf(psp); 864 865 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 866 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 867 868 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 869 if (!ret) { 870 *boot_cfg = 871 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 872 } 873 874 release_psp_cmd_buf(psp); 875 876 return ret; 877 } 878 879 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 880 { 881 int ret; 882 struct psp_context *psp = &adev->psp; 883 struct psp_gfx_cmd_resp *cmd; 884 885 if (amdgpu_sriov_vf(adev)) 886 return 0; 887 888 cmd = acquire_psp_cmd_buf(psp); 889 890 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 891 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 892 cmd->cmd.boot_cfg.boot_config = boot_cfg; 893 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 894 895 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 896 897 release_psp_cmd_buf(psp); 898 899 return ret; 900 } 901 902 static int psp_rl_load(struct amdgpu_device *adev) 903 { 904 int ret; 905 struct psp_context *psp = &adev->psp; 906 struct psp_gfx_cmd_resp *cmd; 907 908 if (!is_psp_fw_valid(psp->rl)) 909 return 0; 910 911 cmd = acquire_psp_cmd_buf(psp); 912 913 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 914 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 915 916 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 917 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 918 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 919 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 920 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 921 922 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 923 924 release_psp_cmd_buf(psp); 925 926 return ret; 927 } 928 929 static int psp_asd_initialize(struct psp_context *psp) 930 { 931 int ret; 932 933 /* If PSP version doesn't match ASD version, asd loading will be failed. 934 * add workaround to bypass it for sriov now. 935 * TODO: add version check to make it common 936 */ 937 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 938 return 0; 939 940 psp->asd_context.mem_context.shared_mc_addr = 0; 941 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 942 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 943 944 ret = psp_ta_load(psp, &psp->asd_context); 945 if (!ret) 946 psp->asd_context.initialized = true; 947 948 return ret; 949 } 950 951 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 952 uint32_t session_id) 953 { 954 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 955 cmd->cmd.cmd_unload_ta.session_id = session_id; 956 } 957 958 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 959 { 960 int ret; 961 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 962 963 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 964 965 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 966 967 release_psp_cmd_buf(psp); 968 969 return ret; 970 } 971 972 static int psp_asd_terminate(struct psp_context *psp) 973 { 974 int ret; 975 976 if (amdgpu_sriov_vf(psp->adev)) 977 return 0; 978 979 if (!psp->asd_context.initialized) 980 return 0; 981 982 ret = psp_ta_unload(psp, &psp->asd_context); 983 if (!ret) 984 psp->asd_context.initialized = false; 985 986 return ret; 987 } 988 989 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 990 uint32_t id, uint32_t value) 991 { 992 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 993 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 994 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 995 } 996 997 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 998 uint32_t value) 999 { 1000 struct psp_gfx_cmd_resp *cmd; 1001 int ret = 0; 1002 1003 if (reg >= PSP_REG_LAST) 1004 return -EINVAL; 1005 1006 cmd = acquire_psp_cmd_buf(psp); 1007 1008 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1009 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1010 if (ret) 1011 DRM_ERROR("PSP failed to program reg id %d", reg); 1012 1013 release_psp_cmd_buf(psp); 1014 1015 return ret; 1016 } 1017 1018 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1019 uint64_t ta_bin_mc, 1020 struct ta_context *context) 1021 { 1022 cmd->cmd_id = context->ta_load_type; 1023 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1024 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1025 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1026 1027 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1028 lower_32_bits(context->mem_context.shared_mc_addr); 1029 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1030 upper_32_bits(context->mem_context.shared_mc_addr); 1031 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1032 } 1033 1034 int psp_ta_init_shared_buf(struct psp_context *psp, 1035 struct ta_mem_context *mem_ctx) 1036 { 1037 /* 1038 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1039 * physical) for ta to host memory 1040 */ 1041 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1042 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1043 &mem_ctx->shared_bo, 1044 &mem_ctx->shared_mc_addr, 1045 &mem_ctx->shared_buf); 1046 } 1047 1048 static void psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1049 uint32_t ta_cmd_id, 1050 struct ta_context *context) 1051 { 1052 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1053 cmd->cmd.cmd_invoke_cmd.session_id = context->session_id; 1054 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1055 1056 cmd->cmd.cmd_invoke_cmd.buf.num_desc = 1; 1057 cmd->cmd.cmd_invoke_cmd.buf.total_size = context->mem_context.shared_mem_size; 1058 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_size = context->mem_context.shared_mem_size; 1059 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_lo = 1060 lower_32_bits(context->mem_context.shared_mc_addr); 1061 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_hi = 1062 upper_32_bits(context->mem_context.shared_mc_addr); 1063 } 1064 1065 int psp_ta_invoke_indirect(struct psp_context *psp, 1066 uint32_t ta_cmd_id, 1067 struct ta_context *context) 1068 { 1069 int ret; 1070 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1071 1072 psp_prep_ta_invoke_indirect_cmd_buf(cmd, ta_cmd_id, context); 1073 1074 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1075 psp->fence_buf_mc_addr); 1076 1077 context->resp_status = cmd->resp.status; 1078 1079 release_psp_cmd_buf(psp); 1080 1081 return ret; 1082 } 1083 1084 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1085 uint32_t ta_cmd_id, 1086 uint32_t session_id) 1087 { 1088 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1089 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1090 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1091 } 1092 1093 int psp_ta_invoke(struct psp_context *psp, 1094 uint32_t ta_cmd_id, 1095 struct ta_context *context) 1096 { 1097 int ret; 1098 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1099 1100 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1101 1102 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1103 psp->fence_buf_mc_addr); 1104 1105 context->resp_status = cmd->resp.status; 1106 1107 release_psp_cmd_buf(psp); 1108 1109 return ret; 1110 } 1111 1112 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1113 { 1114 int ret; 1115 struct psp_gfx_cmd_resp *cmd; 1116 1117 cmd = acquire_psp_cmd_buf(psp); 1118 1119 psp_copy_fw(psp, context->bin_desc.start_addr, 1120 context->bin_desc.size_bytes); 1121 1122 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1123 1124 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1125 psp->fence_buf_mc_addr); 1126 1127 context->resp_status = cmd->resp.status; 1128 1129 if (!ret) { 1130 context->session_id = cmd->resp.session_id; 1131 } 1132 1133 release_psp_cmd_buf(psp); 1134 1135 return ret; 1136 } 1137 1138 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1139 { 1140 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1141 } 1142 1143 int psp_xgmi_terminate(struct psp_context *psp) 1144 { 1145 int ret; 1146 struct amdgpu_device *adev = psp->adev; 1147 1148 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1149 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1150 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1151 adev->gmc.xgmi.connected_to_cpu)) 1152 return 0; 1153 1154 if (!psp->xgmi_context.context.initialized) 1155 return 0; 1156 1157 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1158 1159 psp->xgmi_context.context.initialized = false; 1160 1161 return ret; 1162 } 1163 1164 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1165 { 1166 struct ta_xgmi_shared_memory *xgmi_cmd; 1167 int ret; 1168 1169 if (!psp->ta_fw || 1170 !psp->xgmi_context.context.bin_desc.size_bytes || 1171 !psp->xgmi_context.context.bin_desc.start_addr) 1172 return -ENOENT; 1173 1174 if (!load_ta) 1175 goto invoke; 1176 1177 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1178 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1179 1180 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1181 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1182 if (ret) 1183 return ret; 1184 } 1185 1186 /* Load XGMI TA */ 1187 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1188 if (!ret) 1189 psp->xgmi_context.context.initialized = true; 1190 else 1191 return ret; 1192 1193 invoke: 1194 /* Initialize XGMI session */ 1195 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1196 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1197 xgmi_cmd->flag_extend_link_record = set_extended_data; 1198 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1199 1200 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1201 1202 return ret; 1203 } 1204 1205 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1206 { 1207 struct ta_xgmi_shared_memory *xgmi_cmd; 1208 int ret; 1209 1210 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1211 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1212 1213 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1214 1215 /* Invoke xgmi ta to get hive id */ 1216 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1217 if (ret) 1218 return ret; 1219 1220 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1221 1222 return 0; 1223 } 1224 1225 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1226 { 1227 struct ta_xgmi_shared_memory *xgmi_cmd; 1228 int ret; 1229 1230 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1231 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1232 1233 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1234 1235 /* Invoke xgmi ta to get the node id */ 1236 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1237 if (ret) 1238 return ret; 1239 1240 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1241 1242 return 0; 1243 } 1244 1245 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1246 { 1247 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1248 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1249 } 1250 1251 /* 1252 * Chips that support extended topology information require the driver to 1253 * reflect topology information in the opposite direction. This is 1254 * because the TA has already exceeded its link record limit and if the 1255 * TA holds bi-directional information, the driver would have to do 1256 * multiple fetches instead of just two. 1257 */ 1258 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1259 struct psp_xgmi_node_info node_info) 1260 { 1261 struct amdgpu_device *mirror_adev; 1262 struct amdgpu_hive_info *hive; 1263 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1264 uint64_t dst_node_id = node_info.node_id; 1265 uint8_t dst_num_hops = node_info.num_hops; 1266 uint8_t dst_num_links = node_info.num_links; 1267 1268 hive = amdgpu_get_xgmi_hive(psp->adev); 1269 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1270 struct psp_xgmi_topology_info *mirror_top_info; 1271 int j; 1272 1273 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1274 continue; 1275 1276 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1277 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1278 if (mirror_top_info->nodes[j].node_id != src_node_id) 1279 continue; 1280 1281 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1282 /* 1283 * prevent 0 num_links value re-reflection since reflection 1284 * criteria is based on num_hops (direct or indirect). 1285 * 1286 */ 1287 if (dst_num_links) 1288 mirror_top_info->nodes[j].num_links = dst_num_links; 1289 1290 break; 1291 } 1292 1293 break; 1294 } 1295 } 1296 1297 int psp_xgmi_get_topology_info(struct psp_context *psp, 1298 int number_devices, 1299 struct psp_xgmi_topology_info *topology, 1300 bool get_extended_data) 1301 { 1302 struct ta_xgmi_shared_memory *xgmi_cmd; 1303 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1304 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1305 int i; 1306 int ret; 1307 1308 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1309 return -EINVAL; 1310 1311 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1312 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1313 xgmi_cmd->flag_extend_link_record = get_extended_data; 1314 1315 /* Fill in the shared memory with topology information as input */ 1316 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1317 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1318 topology_info_input->num_nodes = number_devices; 1319 1320 for (i = 0; i < topology_info_input->num_nodes; i++) { 1321 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1322 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1323 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1324 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1325 } 1326 1327 /* Invoke xgmi ta to get the topology information */ 1328 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1329 if (ret) 1330 return ret; 1331 1332 /* Read the output topology information from the shared memory */ 1333 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1334 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1335 for (i = 0; i < topology->num_nodes; i++) { 1336 /* extended data will either be 0 or equal to non-extended data */ 1337 if (topology_info_output->nodes[i].num_hops) 1338 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1339 1340 /* non-extended data gets everything here so no need to update */ 1341 if (!get_extended_data) { 1342 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1343 topology->nodes[i].is_sharing_enabled = 1344 topology_info_output->nodes[i].is_sharing_enabled; 1345 topology->nodes[i].sdma_engine = 1346 topology_info_output->nodes[i].sdma_engine; 1347 } 1348 1349 } 1350 1351 /* Invoke xgmi ta again to get the link information */ 1352 if (psp_xgmi_peer_link_info_supported(psp)) { 1353 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1354 1355 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1356 1357 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1358 1359 if (ret) 1360 return ret; 1361 1362 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1363 for (i = 0; i < topology->num_nodes; i++) { 1364 /* accumulate num_links on extended data */ 1365 topology->nodes[i].num_links = get_extended_data ? 1366 topology->nodes[i].num_links + 1367 link_info_output->nodes[i].num_links : 1368 link_info_output->nodes[i].num_links; 1369 1370 /* reflect the topology information for bi-directionality */ 1371 if (psp->xgmi_context.supports_extended_data && 1372 get_extended_data && topology->nodes[i].num_hops) 1373 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1374 } 1375 } 1376 1377 return 0; 1378 } 1379 1380 int psp_xgmi_set_topology_info(struct psp_context *psp, 1381 int number_devices, 1382 struct psp_xgmi_topology_info *topology) 1383 { 1384 struct ta_xgmi_shared_memory *xgmi_cmd; 1385 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1386 int i; 1387 1388 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1389 return -EINVAL; 1390 1391 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1392 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1393 1394 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1395 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1396 topology_info_input->num_nodes = number_devices; 1397 1398 for (i = 0; i < topology_info_input->num_nodes; i++) { 1399 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1400 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1401 topology_info_input->nodes[i].is_sharing_enabled = 1; 1402 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1403 } 1404 1405 /* Invoke xgmi ta to set topology information */ 1406 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1407 } 1408 1409 // ras begin 1410 static void psp_ras_ta_check_status(struct psp_context *psp) 1411 { 1412 struct ta_ras_shared_memory *ras_cmd = 1413 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1414 1415 switch (ras_cmd->ras_status) { 1416 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1417 dev_warn(psp->adev->dev, 1418 "RAS WARNING: cmd failed due to unsupported ip\n"); 1419 break; 1420 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1421 dev_warn(psp->adev->dev, 1422 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1423 break; 1424 case TA_RAS_STATUS__SUCCESS: 1425 break; 1426 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1427 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1428 dev_warn(psp->adev->dev, 1429 "RAS WARNING: Inject error to critical region is not allowed\n"); 1430 break; 1431 default: 1432 dev_warn(psp->adev->dev, 1433 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1434 break; 1435 } 1436 } 1437 1438 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1439 { 1440 struct ta_ras_shared_memory *ras_cmd; 1441 int ret; 1442 1443 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1444 1445 /* 1446 * TODO: bypass the loading in sriov for now 1447 */ 1448 if (amdgpu_sriov_vf(psp->adev)) 1449 return 0; 1450 1451 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1452 1453 if (amdgpu_ras_intr_triggered()) 1454 return ret; 1455 1456 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1457 { 1458 DRM_WARN("RAS: Unsupported Interface"); 1459 return -EINVAL; 1460 } 1461 1462 if (!ret) { 1463 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1464 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1465 1466 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1467 } 1468 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1469 dev_warn(psp->adev->dev, 1470 "RAS internal register access blocked\n"); 1471 1472 psp_ras_ta_check_status(psp); 1473 } 1474 1475 return ret; 1476 } 1477 1478 int psp_ras_enable_features(struct psp_context *psp, 1479 union ta_ras_cmd_input *info, bool enable) 1480 { 1481 struct ta_ras_shared_memory *ras_cmd; 1482 int ret; 1483 1484 if (!psp->ras_context.context.initialized) 1485 return -EINVAL; 1486 1487 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1488 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1489 1490 if (enable) 1491 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1492 else 1493 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1494 1495 ras_cmd->ras_in_message = *info; 1496 1497 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1498 if (ret) 1499 return -EINVAL; 1500 1501 return 0; 1502 } 1503 1504 int psp_ras_terminate(struct psp_context *psp) 1505 { 1506 int ret; 1507 1508 /* 1509 * TODO: bypass the terminate in sriov for now 1510 */ 1511 if (amdgpu_sriov_vf(psp->adev)) 1512 return 0; 1513 1514 if (!psp->ras_context.context.initialized) 1515 return 0; 1516 1517 ret = psp_ta_unload(psp, &psp->ras_context.context); 1518 1519 psp->ras_context.context.initialized = false; 1520 1521 return ret; 1522 } 1523 1524 static int psp_ras_initialize(struct psp_context *psp) 1525 { 1526 int ret; 1527 uint32_t boot_cfg = 0xFF; 1528 struct amdgpu_device *adev = psp->adev; 1529 struct ta_ras_shared_memory *ras_cmd; 1530 1531 /* 1532 * TODO: bypass the initialize in sriov for now 1533 */ 1534 if (amdgpu_sriov_vf(adev)) 1535 return 0; 1536 1537 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1538 !adev->psp.ras_context.context.bin_desc.start_addr) { 1539 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1540 return 0; 1541 } 1542 1543 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1544 /* query GECC enablement status from boot config 1545 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1546 */ 1547 ret = psp_boot_config_get(adev, &boot_cfg); 1548 if (ret) 1549 dev_warn(adev->dev, "PSP get boot config failed\n"); 1550 1551 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1552 if (!boot_cfg) { 1553 dev_info(adev->dev, "GECC is disabled\n"); 1554 } else { 1555 /* disable GECC in next boot cycle if ras is 1556 * disabled by module parameter amdgpu_ras_enable 1557 * and/or amdgpu_ras_mask, or boot_config_get call 1558 * is failed 1559 */ 1560 ret = psp_boot_config_set(adev, 0); 1561 if (ret) 1562 dev_warn(adev->dev, "PSP set boot config failed\n"); 1563 else 1564 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1565 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1566 } 1567 } else { 1568 if (1 == boot_cfg) { 1569 dev_info(adev->dev, "GECC is enabled\n"); 1570 } else { 1571 /* enable GECC in next boot cycle if it is disabled 1572 * in boot config, or force enable GECC if failed to 1573 * get boot configuration 1574 */ 1575 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1576 if (ret) 1577 dev_warn(adev->dev, "PSP set boot config failed\n"); 1578 else 1579 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1580 } 1581 } 1582 } 1583 1584 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1585 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1586 1587 if (!psp->ras_context.context.initialized) { 1588 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1589 if (ret) 1590 return ret; 1591 } 1592 1593 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1594 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1595 1596 if (amdgpu_ras_is_poison_mode_supported(adev)) 1597 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1598 if (!adev->gmc.xgmi.connected_to_cpu) 1599 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1600 1601 ret = psp_ta_load(psp, &psp->ras_context.context); 1602 1603 if (!ret && !ras_cmd->ras_status) 1604 psp->ras_context.context.initialized = true; 1605 else { 1606 if (ras_cmd->ras_status) 1607 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1608 amdgpu_ras_fini(psp->adev); 1609 } 1610 1611 return ret; 1612 } 1613 1614 int psp_ras_trigger_error(struct psp_context *psp, 1615 struct ta_ras_trigger_error_input *info) 1616 { 1617 struct ta_ras_shared_memory *ras_cmd; 1618 int ret; 1619 1620 if (!psp->ras_context.context.initialized) 1621 return -EINVAL; 1622 1623 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1624 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1625 1626 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1627 ras_cmd->ras_in_message.trigger_error = *info; 1628 1629 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1630 if (ret) 1631 return -EINVAL; 1632 1633 /* If err_event_athub occurs error inject was successful, however 1634 return status from TA is no long reliable */ 1635 if (amdgpu_ras_intr_triggered()) 1636 return 0; 1637 1638 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1639 return -EACCES; 1640 else if (ras_cmd->ras_status) 1641 return -EINVAL; 1642 1643 return 0; 1644 } 1645 // ras end 1646 1647 // HDCP start 1648 static int psp_hdcp_initialize(struct psp_context *psp) 1649 { 1650 int ret; 1651 1652 /* 1653 * TODO: bypass the initialize in sriov for now 1654 */ 1655 if (amdgpu_sriov_vf(psp->adev)) 1656 return 0; 1657 1658 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1659 !psp->hdcp_context.context.bin_desc.start_addr) { 1660 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1661 return 0; 1662 } 1663 1664 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1665 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1666 1667 if (!psp->hdcp_context.context.initialized) { 1668 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1669 if (ret) 1670 return ret; 1671 } 1672 1673 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1674 if (!ret) { 1675 psp->hdcp_context.context.initialized = true; 1676 mutex_init(&psp->hdcp_context.mutex); 1677 } 1678 1679 return ret; 1680 } 1681 1682 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1683 { 1684 /* 1685 * TODO: bypass the loading in sriov for now 1686 */ 1687 if (amdgpu_sriov_vf(psp->adev)) 1688 return 0; 1689 1690 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1691 } 1692 1693 static int psp_hdcp_terminate(struct psp_context *psp) 1694 { 1695 int ret; 1696 1697 /* 1698 * TODO: bypass the terminate in sriov for now 1699 */ 1700 if (amdgpu_sriov_vf(psp->adev)) 1701 return 0; 1702 1703 if (!psp->hdcp_context.context.initialized) 1704 return 0; 1705 1706 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1707 1708 psp->hdcp_context.context.initialized = false; 1709 1710 return ret; 1711 } 1712 // HDCP end 1713 1714 // DTM start 1715 static int psp_dtm_initialize(struct psp_context *psp) 1716 { 1717 int ret; 1718 1719 /* 1720 * TODO: bypass the initialize in sriov for now 1721 */ 1722 if (amdgpu_sriov_vf(psp->adev)) 1723 return 0; 1724 1725 if (!psp->dtm_context.context.bin_desc.size_bytes || 1726 !psp->dtm_context.context.bin_desc.start_addr) { 1727 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1728 return 0; 1729 } 1730 1731 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1732 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1733 1734 if (!psp->dtm_context.context.initialized) { 1735 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1736 if (ret) 1737 return ret; 1738 } 1739 1740 ret = psp_ta_load(psp, &psp->dtm_context.context); 1741 if (!ret) { 1742 psp->dtm_context.context.initialized = true; 1743 mutex_init(&psp->dtm_context.mutex); 1744 } 1745 1746 return ret; 1747 } 1748 1749 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1750 { 1751 /* 1752 * TODO: bypass the loading in sriov for now 1753 */ 1754 if (amdgpu_sriov_vf(psp->adev)) 1755 return 0; 1756 1757 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1758 } 1759 1760 static int psp_dtm_terminate(struct psp_context *psp) 1761 { 1762 int ret; 1763 1764 /* 1765 * TODO: bypass the terminate in sriov for now 1766 */ 1767 if (amdgpu_sriov_vf(psp->adev)) 1768 return 0; 1769 1770 if (!psp->dtm_context.context.initialized) 1771 return 0; 1772 1773 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1774 1775 psp->dtm_context.context.initialized = false; 1776 1777 return ret; 1778 } 1779 // DTM end 1780 1781 // RAP start 1782 static int psp_rap_initialize(struct psp_context *psp) 1783 { 1784 int ret; 1785 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1786 1787 /* 1788 * TODO: bypass the initialize in sriov for now 1789 */ 1790 if (amdgpu_sriov_vf(psp->adev)) 1791 return 0; 1792 1793 if (!psp->rap_context.context.bin_desc.size_bytes || 1794 !psp->rap_context.context.bin_desc.start_addr) { 1795 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1796 return 0; 1797 } 1798 1799 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1800 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1801 1802 if (!psp->rap_context.context.initialized) { 1803 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1804 if (ret) 1805 return ret; 1806 } 1807 1808 ret = psp_ta_load(psp, &psp->rap_context.context); 1809 if (!ret) { 1810 psp->rap_context.context.initialized = true; 1811 mutex_init(&psp->rap_context.mutex); 1812 } else 1813 return ret; 1814 1815 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1816 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1817 psp_rap_terminate(psp); 1818 /* free rap shared memory */ 1819 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1820 1821 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1822 ret, status); 1823 1824 return ret; 1825 } 1826 1827 return 0; 1828 } 1829 1830 static int psp_rap_terminate(struct psp_context *psp) 1831 { 1832 int ret; 1833 1834 if (!psp->rap_context.context.initialized) 1835 return 0; 1836 1837 ret = psp_ta_unload(psp, &psp->rap_context.context); 1838 1839 psp->rap_context.context.initialized = false; 1840 1841 return ret; 1842 } 1843 1844 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1845 { 1846 struct ta_rap_shared_memory *rap_cmd; 1847 int ret = 0; 1848 1849 if (!psp->rap_context.context.initialized) 1850 return 0; 1851 1852 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1853 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1854 return -EINVAL; 1855 1856 mutex_lock(&psp->rap_context.mutex); 1857 1858 rap_cmd = (struct ta_rap_shared_memory *) 1859 psp->rap_context.context.mem_context.shared_buf; 1860 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1861 1862 rap_cmd->cmd_id = ta_cmd_id; 1863 rap_cmd->validation_method_id = METHOD_A; 1864 1865 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1866 if (ret) 1867 goto out_unlock; 1868 1869 if (status) 1870 *status = rap_cmd->rap_status; 1871 1872 out_unlock: 1873 mutex_unlock(&psp->rap_context.mutex); 1874 1875 return ret; 1876 } 1877 // RAP end 1878 1879 /* securedisplay start */ 1880 static int psp_securedisplay_initialize(struct psp_context *psp) 1881 { 1882 int ret; 1883 struct securedisplay_cmd *securedisplay_cmd; 1884 1885 /* 1886 * TODO: bypass the initialize in sriov for now 1887 */ 1888 if (amdgpu_sriov_vf(psp->adev)) 1889 return 0; 1890 1891 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1892 !psp->securedisplay_context.context.bin_desc.start_addr) { 1893 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1894 return 0; 1895 } 1896 1897 psp->securedisplay_context.context.mem_context.shared_mem_size = 1898 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1899 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1900 1901 if (!psp->securedisplay_context.context.initialized) { 1902 ret = psp_ta_init_shared_buf(psp, 1903 &psp->securedisplay_context.context.mem_context); 1904 if (ret) 1905 return ret; 1906 } 1907 1908 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 1909 if (!ret) { 1910 psp->securedisplay_context.context.initialized = true; 1911 mutex_init(&psp->securedisplay_context.mutex); 1912 } else 1913 return ret; 1914 1915 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1916 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1917 1918 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1919 if (ret) { 1920 psp_securedisplay_terminate(psp); 1921 /* free securedisplay shared memory */ 1922 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1923 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1924 return -EINVAL; 1925 } 1926 1927 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1928 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1929 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1930 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1931 } 1932 1933 return 0; 1934 } 1935 1936 static int psp_securedisplay_terminate(struct psp_context *psp) 1937 { 1938 int ret; 1939 1940 /* 1941 * TODO:bypass the terminate in sriov for now 1942 */ 1943 if (amdgpu_sriov_vf(psp->adev)) 1944 return 0; 1945 1946 if (!psp->securedisplay_context.context.initialized) 1947 return 0; 1948 1949 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 1950 1951 psp->securedisplay_context.context.initialized = false; 1952 1953 return ret; 1954 } 1955 1956 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1957 { 1958 int ret; 1959 1960 if (!psp->securedisplay_context.context.initialized) 1961 return -EINVAL; 1962 1963 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1964 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1965 return -EINVAL; 1966 1967 mutex_lock(&psp->securedisplay_context.mutex); 1968 1969 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1970 1971 mutex_unlock(&psp->securedisplay_context.mutex); 1972 1973 return ret; 1974 } 1975 /* SECUREDISPLAY end */ 1976 1977 static int psp_hw_start(struct psp_context *psp) 1978 { 1979 struct amdgpu_device *adev = psp->adev; 1980 int ret; 1981 1982 if (!amdgpu_sriov_vf(adev)) { 1983 if ((is_psp_fw_valid(psp->kdb)) && 1984 (psp->funcs->bootloader_load_kdb != NULL)) { 1985 ret = psp_bootloader_load_kdb(psp); 1986 if (ret) { 1987 DRM_ERROR("PSP load kdb failed!\n"); 1988 return ret; 1989 } 1990 } 1991 1992 if ((is_psp_fw_valid(psp->spl)) && 1993 (psp->funcs->bootloader_load_spl != NULL)) { 1994 ret = psp_bootloader_load_spl(psp); 1995 if (ret) { 1996 DRM_ERROR("PSP load spl failed!\n"); 1997 return ret; 1998 } 1999 } 2000 2001 if ((is_psp_fw_valid(psp->sys)) && 2002 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2003 ret = psp_bootloader_load_sysdrv(psp); 2004 if (ret) { 2005 DRM_ERROR("PSP load sys drv failed!\n"); 2006 return ret; 2007 } 2008 } 2009 2010 if ((is_psp_fw_valid(psp->soc_drv)) && 2011 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2012 ret = psp_bootloader_load_soc_drv(psp); 2013 if (ret) { 2014 DRM_ERROR("PSP load soc drv failed!\n"); 2015 return ret; 2016 } 2017 } 2018 2019 if ((is_psp_fw_valid(psp->intf_drv)) && 2020 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2021 ret = psp_bootloader_load_intf_drv(psp); 2022 if (ret) { 2023 DRM_ERROR("PSP load intf drv failed!\n"); 2024 return ret; 2025 } 2026 } 2027 2028 if ((is_psp_fw_valid(psp->dbg_drv)) && 2029 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2030 ret = psp_bootloader_load_dbg_drv(psp); 2031 if (ret) { 2032 DRM_ERROR("PSP load dbg drv failed!\n"); 2033 return ret; 2034 } 2035 } 2036 2037 if ((is_psp_fw_valid(psp->sos)) && 2038 (psp->funcs->bootloader_load_sos != NULL)) { 2039 ret = psp_bootloader_load_sos(psp); 2040 if (ret) { 2041 DRM_ERROR("PSP load sos failed!\n"); 2042 return ret; 2043 } 2044 } 2045 } 2046 2047 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2048 if (ret) { 2049 DRM_ERROR("PSP create ring failed!\n"); 2050 return ret; 2051 } 2052 2053 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2054 goto skip_pin_bo; 2055 2056 ret = psp_tmr_init(psp); 2057 if (ret) { 2058 DRM_ERROR("PSP tmr init failed!\n"); 2059 return ret; 2060 } 2061 2062 skip_pin_bo: 2063 /* 2064 * For ASICs with DF Cstate management centralized 2065 * to PMFW, TMR setup should be performed after PMFW 2066 * loaded and before other non-psp firmware loaded. 2067 */ 2068 if (psp->pmfw_centralized_cstate_management) { 2069 ret = psp_load_smu_fw(psp); 2070 if (ret) 2071 return ret; 2072 } 2073 2074 ret = psp_tmr_load(psp); 2075 if (ret) { 2076 DRM_ERROR("PSP load tmr failed!\n"); 2077 return ret; 2078 } 2079 2080 return 0; 2081 } 2082 2083 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2084 enum psp_gfx_fw_type *type) 2085 { 2086 switch (ucode->ucode_id) { 2087 case AMDGPU_UCODE_ID_CAP: 2088 *type = GFX_FW_TYPE_CAP; 2089 break; 2090 case AMDGPU_UCODE_ID_SDMA0: 2091 *type = GFX_FW_TYPE_SDMA0; 2092 break; 2093 case AMDGPU_UCODE_ID_SDMA1: 2094 *type = GFX_FW_TYPE_SDMA1; 2095 break; 2096 case AMDGPU_UCODE_ID_SDMA2: 2097 *type = GFX_FW_TYPE_SDMA2; 2098 break; 2099 case AMDGPU_UCODE_ID_SDMA3: 2100 *type = GFX_FW_TYPE_SDMA3; 2101 break; 2102 case AMDGPU_UCODE_ID_SDMA4: 2103 *type = GFX_FW_TYPE_SDMA4; 2104 break; 2105 case AMDGPU_UCODE_ID_SDMA5: 2106 *type = GFX_FW_TYPE_SDMA5; 2107 break; 2108 case AMDGPU_UCODE_ID_SDMA6: 2109 *type = GFX_FW_TYPE_SDMA6; 2110 break; 2111 case AMDGPU_UCODE_ID_SDMA7: 2112 *type = GFX_FW_TYPE_SDMA7; 2113 break; 2114 case AMDGPU_UCODE_ID_CP_MES: 2115 *type = GFX_FW_TYPE_CP_MES; 2116 break; 2117 case AMDGPU_UCODE_ID_CP_MES_DATA: 2118 *type = GFX_FW_TYPE_MES_STACK; 2119 break; 2120 case AMDGPU_UCODE_ID_CP_MES1: 2121 *type = GFX_FW_TYPE_CP_MES_KIQ; 2122 break; 2123 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2124 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2125 break; 2126 case AMDGPU_UCODE_ID_CP_CE: 2127 *type = GFX_FW_TYPE_CP_CE; 2128 break; 2129 case AMDGPU_UCODE_ID_CP_PFP: 2130 *type = GFX_FW_TYPE_CP_PFP; 2131 break; 2132 case AMDGPU_UCODE_ID_CP_ME: 2133 *type = GFX_FW_TYPE_CP_ME; 2134 break; 2135 case AMDGPU_UCODE_ID_CP_MEC1: 2136 *type = GFX_FW_TYPE_CP_MEC; 2137 break; 2138 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2139 *type = GFX_FW_TYPE_CP_MEC_ME1; 2140 break; 2141 case AMDGPU_UCODE_ID_CP_MEC2: 2142 *type = GFX_FW_TYPE_CP_MEC; 2143 break; 2144 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2145 *type = GFX_FW_TYPE_CP_MEC_ME2; 2146 break; 2147 case AMDGPU_UCODE_ID_RLC_P: 2148 *type = GFX_FW_TYPE_RLC_P; 2149 break; 2150 case AMDGPU_UCODE_ID_RLC_V: 2151 *type = GFX_FW_TYPE_RLC_V; 2152 break; 2153 case AMDGPU_UCODE_ID_RLC_G: 2154 *type = GFX_FW_TYPE_RLC_G; 2155 break; 2156 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2157 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2158 break; 2159 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2160 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2161 break; 2162 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2163 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2164 break; 2165 case AMDGPU_UCODE_ID_RLC_IRAM: 2166 *type = GFX_FW_TYPE_RLC_IRAM; 2167 break; 2168 case AMDGPU_UCODE_ID_RLC_DRAM: 2169 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2170 break; 2171 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2172 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2173 break; 2174 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2175 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2176 break; 2177 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2178 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2179 break; 2180 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2181 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2182 break; 2183 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2184 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2185 break; 2186 case AMDGPU_UCODE_ID_SMC: 2187 *type = GFX_FW_TYPE_SMU; 2188 break; 2189 case AMDGPU_UCODE_ID_PPTABLE: 2190 *type = GFX_FW_TYPE_PPTABLE; 2191 break; 2192 case AMDGPU_UCODE_ID_UVD: 2193 *type = GFX_FW_TYPE_UVD; 2194 break; 2195 case AMDGPU_UCODE_ID_UVD1: 2196 *type = GFX_FW_TYPE_UVD1; 2197 break; 2198 case AMDGPU_UCODE_ID_VCE: 2199 *type = GFX_FW_TYPE_VCE; 2200 break; 2201 case AMDGPU_UCODE_ID_VCN: 2202 *type = GFX_FW_TYPE_VCN; 2203 break; 2204 case AMDGPU_UCODE_ID_VCN1: 2205 *type = GFX_FW_TYPE_VCN1; 2206 break; 2207 case AMDGPU_UCODE_ID_DMCU_ERAM: 2208 *type = GFX_FW_TYPE_DMCU_ERAM; 2209 break; 2210 case AMDGPU_UCODE_ID_DMCU_INTV: 2211 *type = GFX_FW_TYPE_DMCU_ISR; 2212 break; 2213 case AMDGPU_UCODE_ID_VCN0_RAM: 2214 *type = GFX_FW_TYPE_VCN0_RAM; 2215 break; 2216 case AMDGPU_UCODE_ID_VCN1_RAM: 2217 *type = GFX_FW_TYPE_VCN1_RAM; 2218 break; 2219 case AMDGPU_UCODE_ID_DMCUB: 2220 *type = GFX_FW_TYPE_DMUB; 2221 break; 2222 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2223 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2224 break; 2225 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2226 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2227 break; 2228 case AMDGPU_UCODE_ID_IMU_I: 2229 *type = GFX_FW_TYPE_IMU_I; 2230 break; 2231 case AMDGPU_UCODE_ID_IMU_D: 2232 *type = GFX_FW_TYPE_IMU_D; 2233 break; 2234 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2235 *type = GFX_FW_TYPE_RS64_PFP; 2236 break; 2237 case AMDGPU_UCODE_ID_CP_RS64_ME: 2238 *type = GFX_FW_TYPE_RS64_ME; 2239 break; 2240 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2241 *type = GFX_FW_TYPE_RS64_MEC; 2242 break; 2243 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2244 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2245 break; 2246 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2247 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2248 break; 2249 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2250 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2251 break; 2252 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2253 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2254 break; 2255 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2256 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2257 break; 2258 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2259 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2260 break; 2261 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2262 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2263 break; 2264 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2265 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2266 break; 2267 case AMDGPU_UCODE_ID_MAXIMUM: 2268 default: 2269 return -EINVAL; 2270 } 2271 2272 return 0; 2273 } 2274 2275 static void psp_print_fw_hdr(struct psp_context *psp, 2276 struct amdgpu_firmware_info *ucode) 2277 { 2278 struct amdgpu_device *adev = psp->adev; 2279 struct common_firmware_header *hdr; 2280 2281 switch (ucode->ucode_id) { 2282 case AMDGPU_UCODE_ID_SDMA0: 2283 case AMDGPU_UCODE_ID_SDMA1: 2284 case AMDGPU_UCODE_ID_SDMA2: 2285 case AMDGPU_UCODE_ID_SDMA3: 2286 case AMDGPU_UCODE_ID_SDMA4: 2287 case AMDGPU_UCODE_ID_SDMA5: 2288 case AMDGPU_UCODE_ID_SDMA6: 2289 case AMDGPU_UCODE_ID_SDMA7: 2290 hdr = (struct common_firmware_header *) 2291 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2292 amdgpu_ucode_print_sdma_hdr(hdr); 2293 break; 2294 case AMDGPU_UCODE_ID_CP_CE: 2295 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2296 amdgpu_ucode_print_gfx_hdr(hdr); 2297 break; 2298 case AMDGPU_UCODE_ID_CP_PFP: 2299 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2300 amdgpu_ucode_print_gfx_hdr(hdr); 2301 break; 2302 case AMDGPU_UCODE_ID_CP_ME: 2303 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2304 amdgpu_ucode_print_gfx_hdr(hdr); 2305 break; 2306 case AMDGPU_UCODE_ID_CP_MEC1: 2307 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2308 amdgpu_ucode_print_gfx_hdr(hdr); 2309 break; 2310 case AMDGPU_UCODE_ID_RLC_G: 2311 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2312 amdgpu_ucode_print_rlc_hdr(hdr); 2313 break; 2314 case AMDGPU_UCODE_ID_SMC: 2315 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2316 amdgpu_ucode_print_smc_hdr(hdr); 2317 break; 2318 default: 2319 break; 2320 } 2321 } 2322 2323 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2324 struct psp_gfx_cmd_resp *cmd) 2325 { 2326 int ret; 2327 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2328 2329 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2330 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2331 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2332 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2333 2334 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2335 if (ret) 2336 DRM_ERROR("Unknown firmware type\n"); 2337 2338 return ret; 2339 } 2340 2341 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2342 struct amdgpu_firmware_info *ucode) 2343 { 2344 int ret = 0; 2345 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2346 2347 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2348 if (!ret) { 2349 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2350 psp->fence_buf_mc_addr); 2351 } 2352 2353 release_psp_cmd_buf(psp); 2354 2355 return ret; 2356 } 2357 2358 static int psp_load_smu_fw(struct psp_context *psp) 2359 { 2360 int ret; 2361 struct amdgpu_device *adev = psp->adev; 2362 struct amdgpu_firmware_info *ucode = 2363 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2364 struct amdgpu_ras *ras = psp->ras_context.ras; 2365 2366 /* 2367 * Skip SMU FW reloading in case of using BACO for runpm only, 2368 * as SMU is always alive. 2369 */ 2370 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2371 return 0; 2372 2373 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2374 return 0; 2375 2376 if ((amdgpu_in_reset(adev) && 2377 ras && adev->ras_enabled && 2378 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2379 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2380 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2381 if (ret) { 2382 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2383 } 2384 } 2385 2386 ret = psp_execute_non_psp_fw_load(psp, ucode); 2387 2388 if (ret) 2389 DRM_ERROR("PSP load smu failed!\n"); 2390 2391 return ret; 2392 } 2393 2394 static bool fw_load_skip_check(struct psp_context *psp, 2395 struct amdgpu_firmware_info *ucode) 2396 { 2397 if (!ucode->fw) 2398 return true; 2399 2400 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2401 (psp_smu_reload_quirk(psp) || 2402 psp->autoload_supported || 2403 psp->pmfw_centralized_cstate_management)) 2404 return true; 2405 2406 if (amdgpu_sriov_vf(psp->adev) && 2407 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2408 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2409 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2410 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2411 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2412 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2413 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2414 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2415 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2416 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2417 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2418 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2419 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2420 /*skip ucode loading in SRIOV VF */ 2421 return true; 2422 2423 if (psp->autoload_supported && 2424 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2425 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2426 /* skip mec JT when autoload is enabled */ 2427 return true; 2428 2429 return false; 2430 } 2431 2432 int psp_load_fw_list(struct psp_context *psp, 2433 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2434 { 2435 int ret = 0, i; 2436 struct amdgpu_firmware_info *ucode; 2437 2438 for (i = 0; i < ucode_count; ++i) { 2439 ucode = ucode_list[i]; 2440 psp_print_fw_hdr(psp, ucode); 2441 ret = psp_execute_non_psp_fw_load(psp, ucode); 2442 if (ret) 2443 return ret; 2444 } 2445 return ret; 2446 } 2447 2448 static int psp_load_non_psp_fw(struct psp_context *psp) 2449 { 2450 int i, ret; 2451 struct amdgpu_firmware_info *ucode; 2452 struct amdgpu_device *adev = psp->adev; 2453 2454 if (psp->autoload_supported && 2455 !psp->pmfw_centralized_cstate_management) { 2456 ret = psp_load_smu_fw(psp); 2457 if (ret) 2458 return ret; 2459 } 2460 2461 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2462 ucode = &adev->firmware.ucode[i]; 2463 2464 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2465 !fw_load_skip_check(psp, ucode)) { 2466 ret = psp_load_smu_fw(psp); 2467 if (ret) 2468 return ret; 2469 continue; 2470 } 2471 2472 if (fw_load_skip_check(psp, ucode)) 2473 continue; 2474 2475 if (psp->autoload_supported && 2476 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2477 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2478 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2479 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2480 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2481 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2482 /* PSP only receive one SDMA fw for sienna_cichlid, 2483 * as all four sdma fw are same */ 2484 continue; 2485 2486 psp_print_fw_hdr(psp, ucode); 2487 2488 ret = psp_execute_non_psp_fw_load(psp, ucode); 2489 if (ret) 2490 return ret; 2491 2492 /* Start rlc autoload after psp recieved all the gfx firmware */ 2493 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2494 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2495 ret = psp_rlc_autoload_start(psp); 2496 if (ret) { 2497 DRM_ERROR("Failed to start rlc autoload\n"); 2498 return ret; 2499 } 2500 } 2501 } 2502 2503 return 0; 2504 } 2505 2506 static int psp_load_fw(struct amdgpu_device *adev) 2507 { 2508 int ret; 2509 struct psp_context *psp = &adev->psp; 2510 2511 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2512 /* should not destroy ring, only stop */ 2513 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2514 } else { 2515 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2516 2517 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2518 if (ret) { 2519 DRM_ERROR("PSP ring init failed!\n"); 2520 goto failed; 2521 } 2522 } 2523 2524 ret = psp_hw_start(psp); 2525 if (ret) 2526 goto failed; 2527 2528 ret = psp_load_non_psp_fw(psp); 2529 if (ret) 2530 goto failed1; 2531 2532 ret = psp_asd_initialize(psp); 2533 if (ret) { 2534 DRM_ERROR("PSP load asd failed!\n"); 2535 goto failed1; 2536 } 2537 2538 ret = psp_rl_load(adev); 2539 if (ret) { 2540 DRM_ERROR("PSP load RL failed!\n"); 2541 goto failed1; 2542 } 2543 2544 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2545 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2546 ret = psp_xgmi_initialize(psp, false, true); 2547 /* Warning the XGMI seesion initialize failure 2548 * Instead of stop driver initialization 2549 */ 2550 if (ret) 2551 dev_err(psp->adev->dev, 2552 "XGMI: Failed to initialize XGMI session\n"); 2553 } 2554 } 2555 2556 if (psp->ta_fw) { 2557 ret = psp_ras_initialize(psp); 2558 if (ret) 2559 dev_err(psp->adev->dev, 2560 "RAS: Failed to initialize RAS\n"); 2561 2562 ret = psp_hdcp_initialize(psp); 2563 if (ret) 2564 dev_err(psp->adev->dev, 2565 "HDCP: Failed to initialize HDCP\n"); 2566 2567 ret = psp_dtm_initialize(psp); 2568 if (ret) 2569 dev_err(psp->adev->dev, 2570 "DTM: Failed to initialize DTM\n"); 2571 2572 ret = psp_rap_initialize(psp); 2573 if (ret) 2574 dev_err(psp->adev->dev, 2575 "RAP: Failed to initialize RAP\n"); 2576 2577 ret = psp_securedisplay_initialize(psp); 2578 if (ret) 2579 dev_err(psp->adev->dev, 2580 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2581 } 2582 2583 return 0; 2584 2585 failed1: 2586 psp_free_shared_bufs(psp); 2587 failed: 2588 /* 2589 * all cleanup jobs (xgmi terminate, ras terminate, 2590 * ring destroy, cmd/fence/fw buffers destory, 2591 * psp->cmd destory) are delayed to psp_hw_fini 2592 */ 2593 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2594 return ret; 2595 } 2596 2597 static int psp_hw_init(void *handle) 2598 { 2599 int ret; 2600 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2601 2602 mutex_lock(&adev->firmware.mutex); 2603 /* 2604 * This sequence is just used on hw_init only once, no need on 2605 * resume. 2606 */ 2607 ret = amdgpu_ucode_init_bo(adev); 2608 if (ret) 2609 goto failed; 2610 2611 ret = psp_load_fw(adev); 2612 if (ret) { 2613 DRM_ERROR("PSP firmware loading failed\n"); 2614 goto failed; 2615 } 2616 2617 mutex_unlock(&adev->firmware.mutex); 2618 return 0; 2619 2620 failed: 2621 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2622 mutex_unlock(&adev->firmware.mutex); 2623 return -EINVAL; 2624 } 2625 2626 static int psp_hw_fini(void *handle) 2627 { 2628 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2629 struct psp_context *psp = &adev->psp; 2630 2631 if (psp->ta_fw) { 2632 psp_ras_terminate(psp); 2633 psp_securedisplay_terminate(psp); 2634 psp_rap_terminate(psp); 2635 psp_dtm_terminate(psp); 2636 psp_hdcp_terminate(psp); 2637 } 2638 2639 psp_asd_terminate(psp); 2640 psp_tmr_terminate(psp); 2641 2642 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2643 2644 psp_free_shared_bufs(psp); 2645 2646 return 0; 2647 } 2648 2649 static int psp_suspend(void *handle) 2650 { 2651 int ret = 0; 2652 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2653 struct psp_context *psp = &adev->psp; 2654 2655 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2656 psp->xgmi_context.context.initialized) { 2657 ret = psp_xgmi_terminate(psp); 2658 if (ret) { 2659 DRM_ERROR("Failed to terminate xgmi ta\n"); 2660 goto out; 2661 } 2662 } 2663 2664 if (psp->ta_fw) { 2665 ret = psp_ras_terminate(psp); 2666 if (ret) { 2667 DRM_ERROR("Failed to terminate ras ta\n"); 2668 goto out; 2669 } 2670 ret = psp_hdcp_terminate(psp); 2671 if (ret) { 2672 DRM_ERROR("Failed to terminate hdcp ta\n"); 2673 goto out; 2674 } 2675 ret = psp_dtm_terminate(psp); 2676 if (ret) { 2677 DRM_ERROR("Failed to terminate dtm ta\n"); 2678 goto out; 2679 } 2680 ret = psp_rap_terminate(psp); 2681 if (ret) { 2682 DRM_ERROR("Failed to terminate rap ta\n"); 2683 goto out; 2684 } 2685 ret = psp_securedisplay_terminate(psp); 2686 if (ret) { 2687 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2688 goto out; 2689 } 2690 } 2691 2692 ret = psp_asd_terminate(psp); 2693 if (ret) { 2694 DRM_ERROR("Failed to terminate asd\n"); 2695 goto out; 2696 } 2697 2698 ret = psp_tmr_terminate(psp); 2699 if (ret) { 2700 DRM_ERROR("Failed to terminate tmr\n"); 2701 goto out; 2702 } 2703 2704 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2705 if (ret) { 2706 DRM_ERROR("PSP ring stop failed\n"); 2707 } 2708 2709 out: 2710 psp_free_shared_bufs(psp); 2711 2712 return ret; 2713 } 2714 2715 static int psp_resume(void *handle) 2716 { 2717 int ret; 2718 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2719 struct psp_context *psp = &adev->psp; 2720 2721 DRM_INFO("PSP is resuming...\n"); 2722 2723 if (psp->mem_train_ctx.enable_mem_training) { 2724 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2725 if (ret) { 2726 DRM_ERROR("Failed to process memory training!\n"); 2727 return ret; 2728 } 2729 } 2730 2731 mutex_lock(&adev->firmware.mutex); 2732 2733 ret = psp_hw_start(psp); 2734 if (ret) 2735 goto failed; 2736 2737 ret = psp_load_non_psp_fw(psp); 2738 if (ret) 2739 goto failed; 2740 2741 ret = psp_asd_initialize(psp); 2742 if (ret) { 2743 DRM_ERROR("PSP load asd failed!\n"); 2744 goto failed; 2745 } 2746 2747 ret = psp_rl_load(adev); 2748 if (ret) { 2749 dev_err(adev->dev, "PSP load RL failed!\n"); 2750 goto failed; 2751 } 2752 2753 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2754 ret = psp_xgmi_initialize(psp, false, true); 2755 /* Warning the XGMI seesion initialize failure 2756 * Instead of stop driver initialization 2757 */ 2758 if (ret) 2759 dev_err(psp->adev->dev, 2760 "XGMI: Failed to initialize XGMI session\n"); 2761 } 2762 2763 if (psp->ta_fw) { 2764 ret = psp_ras_initialize(psp); 2765 if (ret) 2766 dev_err(psp->adev->dev, 2767 "RAS: Failed to initialize RAS\n"); 2768 2769 ret = psp_hdcp_initialize(psp); 2770 if (ret) 2771 dev_err(psp->adev->dev, 2772 "HDCP: Failed to initialize HDCP\n"); 2773 2774 ret = psp_dtm_initialize(psp); 2775 if (ret) 2776 dev_err(psp->adev->dev, 2777 "DTM: Failed to initialize DTM\n"); 2778 2779 ret = psp_rap_initialize(psp); 2780 if (ret) 2781 dev_err(psp->adev->dev, 2782 "RAP: Failed to initialize RAP\n"); 2783 2784 ret = psp_securedisplay_initialize(psp); 2785 if (ret) 2786 dev_err(psp->adev->dev, 2787 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2788 } 2789 2790 mutex_unlock(&adev->firmware.mutex); 2791 2792 return 0; 2793 2794 failed: 2795 DRM_ERROR("PSP resume failed\n"); 2796 mutex_unlock(&adev->firmware.mutex); 2797 return ret; 2798 } 2799 2800 int psp_gpu_reset(struct amdgpu_device *adev) 2801 { 2802 int ret; 2803 2804 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2805 return 0; 2806 2807 mutex_lock(&adev->psp.mutex); 2808 ret = psp_mode1_reset(&adev->psp); 2809 mutex_unlock(&adev->psp.mutex); 2810 2811 return ret; 2812 } 2813 2814 int psp_rlc_autoload_start(struct psp_context *psp) 2815 { 2816 int ret; 2817 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2818 2819 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2820 2821 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2822 psp->fence_buf_mc_addr); 2823 2824 release_psp_cmd_buf(psp); 2825 2826 return ret; 2827 } 2828 2829 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2830 uint64_t cmd_gpu_addr, int cmd_size) 2831 { 2832 struct amdgpu_firmware_info ucode = {0}; 2833 2834 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2835 AMDGPU_UCODE_ID_VCN0_RAM; 2836 ucode.mc_addr = cmd_gpu_addr; 2837 ucode.ucode_size = cmd_size; 2838 2839 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2840 } 2841 2842 int psp_ring_cmd_submit(struct psp_context *psp, 2843 uint64_t cmd_buf_mc_addr, 2844 uint64_t fence_mc_addr, 2845 int index) 2846 { 2847 unsigned int psp_write_ptr_reg = 0; 2848 struct psp_gfx_rb_frame *write_frame; 2849 struct psp_ring *ring = &psp->km_ring; 2850 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2851 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2852 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2853 struct amdgpu_device *adev = psp->adev; 2854 uint32_t ring_size_dw = ring->ring_size / 4; 2855 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2856 2857 /* KM (GPCOM) prepare write pointer */ 2858 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2859 2860 /* Update KM RB frame pointer to new frame */ 2861 /* write_frame ptr increments by size of rb_frame in bytes */ 2862 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2863 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2864 write_frame = ring_buffer_start; 2865 else 2866 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2867 /* Check invalid write_frame ptr address */ 2868 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2869 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2870 ring_buffer_start, ring_buffer_end, write_frame); 2871 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2872 return -EINVAL; 2873 } 2874 2875 /* Initialize KM RB frame */ 2876 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2877 2878 /* Update KM RB frame */ 2879 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2880 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2881 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2882 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2883 write_frame->fence_value = index; 2884 amdgpu_device_flush_hdp(adev, NULL); 2885 2886 /* Update the write Pointer in DWORDs */ 2887 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2888 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2889 return 0; 2890 } 2891 2892 int psp_init_asd_microcode(struct psp_context *psp, 2893 const char *chip_name) 2894 { 2895 struct amdgpu_device *adev = psp->adev; 2896 char fw_name[PSP_FW_NAME_LEN]; 2897 const struct psp_firmware_header_v1_0 *asd_hdr; 2898 int err = 0; 2899 2900 if (!chip_name) { 2901 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2902 return -EINVAL; 2903 } 2904 2905 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2906 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2907 if (err) 2908 goto out; 2909 2910 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2911 if (err) 2912 goto out; 2913 2914 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2915 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2916 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2917 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2918 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2919 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2920 return 0; 2921 out: 2922 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2923 release_firmware(adev->psp.asd_fw); 2924 adev->psp.asd_fw = NULL; 2925 return err; 2926 } 2927 2928 int psp_init_toc_microcode(struct psp_context *psp, 2929 const char *chip_name) 2930 { 2931 struct amdgpu_device *adev = psp->adev; 2932 char fw_name[PSP_FW_NAME_LEN]; 2933 const struct psp_firmware_header_v1_0 *toc_hdr; 2934 int err = 0; 2935 2936 if (!chip_name) { 2937 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2938 return -EINVAL; 2939 } 2940 2941 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2942 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2943 if (err) 2944 goto out; 2945 2946 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2947 if (err) 2948 goto out; 2949 2950 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2951 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2952 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2953 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2954 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2955 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2956 return 0; 2957 out: 2958 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2959 release_firmware(adev->psp.toc_fw); 2960 adev->psp.toc_fw = NULL; 2961 return err; 2962 } 2963 2964 static int parse_sos_bin_descriptor(struct psp_context *psp, 2965 const struct psp_fw_bin_desc *desc, 2966 const struct psp_firmware_header_v2_0 *sos_hdr) 2967 { 2968 uint8_t *ucode_start_addr = NULL; 2969 2970 if (!psp || !desc || !sos_hdr) 2971 return -EINVAL; 2972 2973 ucode_start_addr = (uint8_t *)sos_hdr + 2974 le32_to_cpu(desc->offset_bytes) + 2975 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2976 2977 switch (desc->fw_type) { 2978 case PSP_FW_TYPE_PSP_SOS: 2979 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2980 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2981 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2982 psp->sos.start_addr = ucode_start_addr; 2983 break; 2984 case PSP_FW_TYPE_PSP_SYS_DRV: 2985 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2986 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2987 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2988 psp->sys.start_addr = ucode_start_addr; 2989 break; 2990 case PSP_FW_TYPE_PSP_KDB: 2991 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2992 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2993 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2994 psp->kdb.start_addr = ucode_start_addr; 2995 break; 2996 case PSP_FW_TYPE_PSP_TOC: 2997 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2998 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2999 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3000 psp->toc.start_addr = ucode_start_addr; 3001 break; 3002 case PSP_FW_TYPE_PSP_SPL: 3003 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3004 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3005 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3006 psp->spl.start_addr = ucode_start_addr; 3007 break; 3008 case PSP_FW_TYPE_PSP_RL: 3009 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3010 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3011 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3012 psp->rl.start_addr = ucode_start_addr; 3013 break; 3014 case PSP_FW_TYPE_PSP_SOC_DRV: 3015 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3016 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3017 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3018 psp->soc_drv.start_addr = ucode_start_addr; 3019 break; 3020 case PSP_FW_TYPE_PSP_INTF_DRV: 3021 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3022 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3023 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3024 psp->intf_drv.start_addr = ucode_start_addr; 3025 break; 3026 case PSP_FW_TYPE_PSP_DBG_DRV: 3027 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3028 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3029 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3030 psp->dbg_drv.start_addr = ucode_start_addr; 3031 break; 3032 default: 3033 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3034 break; 3035 } 3036 3037 return 0; 3038 } 3039 3040 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3041 { 3042 const struct psp_firmware_header_v1_0 *sos_hdr; 3043 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3044 uint8_t *ucode_array_start_addr; 3045 3046 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3047 ucode_array_start_addr = (uint8_t *)sos_hdr + 3048 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3049 3050 if (adev->gmc.xgmi.connected_to_cpu || 3051 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3052 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3053 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3054 3055 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3056 adev->psp.sys.start_addr = ucode_array_start_addr; 3057 3058 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3059 adev->psp.sos.start_addr = ucode_array_start_addr + 3060 le32_to_cpu(sos_hdr->sos.offset_bytes); 3061 } else { 3062 /* Load alternate PSP SOS FW */ 3063 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3064 3065 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3066 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3067 3068 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3069 adev->psp.sys.start_addr = ucode_array_start_addr + 3070 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3071 3072 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3073 adev->psp.sos.start_addr = ucode_array_start_addr + 3074 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3075 } 3076 3077 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3078 dev_warn(adev->dev, "PSP SOS FW not available"); 3079 return -EINVAL; 3080 } 3081 3082 return 0; 3083 } 3084 3085 int psp_init_sos_microcode(struct psp_context *psp, 3086 const char *chip_name) 3087 { 3088 struct amdgpu_device *adev = psp->adev; 3089 char fw_name[PSP_FW_NAME_LEN]; 3090 const struct psp_firmware_header_v1_0 *sos_hdr; 3091 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3092 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3093 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3094 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3095 int err = 0; 3096 uint8_t *ucode_array_start_addr; 3097 int fw_index = 0; 3098 3099 if (!chip_name) { 3100 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3101 return -EINVAL; 3102 } 3103 3104 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3105 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3106 if (err) 3107 goto out; 3108 3109 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3110 if (err) 3111 goto out; 3112 3113 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3114 ucode_array_start_addr = (uint8_t *)sos_hdr + 3115 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3116 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3117 3118 switch (sos_hdr->header.header_version_major) { 3119 case 1: 3120 err = psp_init_sos_base_fw(adev); 3121 if (err) 3122 goto out; 3123 3124 if (sos_hdr->header.header_version_minor == 1) { 3125 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3126 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3127 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3128 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3129 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3130 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3131 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3132 } 3133 if (sos_hdr->header.header_version_minor == 2) { 3134 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3135 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3136 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3137 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3138 } 3139 if (sos_hdr->header.header_version_minor == 3) { 3140 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3141 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3142 adev->psp.toc.start_addr = ucode_array_start_addr + 3143 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3144 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3145 adev->psp.kdb.start_addr = ucode_array_start_addr + 3146 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3147 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3148 adev->psp.spl.start_addr = ucode_array_start_addr + 3149 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3150 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3151 adev->psp.rl.start_addr = ucode_array_start_addr + 3152 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3153 } 3154 break; 3155 case 2: 3156 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3157 3158 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3159 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3160 err = -EINVAL; 3161 goto out; 3162 } 3163 3164 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3165 err = parse_sos_bin_descriptor(psp, 3166 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3167 sos_hdr_v2_0); 3168 if (err) 3169 goto out; 3170 } 3171 break; 3172 default: 3173 dev_err(adev->dev, 3174 "unsupported psp sos firmware\n"); 3175 err = -EINVAL; 3176 goto out; 3177 } 3178 3179 return 0; 3180 out: 3181 dev_err(adev->dev, 3182 "failed to init sos firmware\n"); 3183 release_firmware(adev->psp.sos_fw); 3184 adev->psp.sos_fw = NULL; 3185 3186 return err; 3187 } 3188 3189 static int parse_ta_bin_descriptor(struct psp_context *psp, 3190 const struct psp_fw_bin_desc *desc, 3191 const struct ta_firmware_header_v2_0 *ta_hdr) 3192 { 3193 uint8_t *ucode_start_addr = NULL; 3194 3195 if (!psp || !desc || !ta_hdr) 3196 return -EINVAL; 3197 3198 ucode_start_addr = (uint8_t *)ta_hdr + 3199 le32_to_cpu(desc->offset_bytes) + 3200 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3201 3202 switch (desc->fw_type) { 3203 case TA_FW_TYPE_PSP_ASD: 3204 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3205 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3206 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3207 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3208 break; 3209 case TA_FW_TYPE_PSP_XGMI: 3210 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3211 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3212 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3213 break; 3214 case TA_FW_TYPE_PSP_RAS: 3215 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3216 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3217 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3218 break; 3219 case TA_FW_TYPE_PSP_HDCP: 3220 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3221 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3222 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3223 break; 3224 case TA_FW_TYPE_PSP_DTM: 3225 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3226 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3227 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3228 break; 3229 case TA_FW_TYPE_PSP_RAP: 3230 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3231 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3232 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3233 break; 3234 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3235 psp->securedisplay_context.context.bin_desc.fw_version = 3236 le32_to_cpu(desc->fw_version); 3237 psp->securedisplay_context.context.bin_desc.size_bytes = 3238 le32_to_cpu(desc->size_bytes); 3239 psp->securedisplay_context.context.bin_desc.start_addr = 3240 ucode_start_addr; 3241 break; 3242 default: 3243 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3244 break; 3245 } 3246 3247 return 0; 3248 } 3249 3250 int psp_init_ta_microcode(struct psp_context *psp, 3251 const char *chip_name) 3252 { 3253 struct amdgpu_device *adev = psp->adev; 3254 char fw_name[PSP_FW_NAME_LEN]; 3255 const struct ta_firmware_header_v2_0 *ta_hdr; 3256 int err = 0; 3257 int ta_index = 0; 3258 3259 if (!chip_name) { 3260 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3261 return -EINVAL; 3262 } 3263 3264 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3265 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3266 if (err) 3267 goto out; 3268 3269 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3270 if (err) 3271 goto out; 3272 3273 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3274 3275 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3276 dev_err(adev->dev, "unsupported TA header version\n"); 3277 err = -EINVAL; 3278 goto out; 3279 } 3280 3281 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3282 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3283 err = -EINVAL; 3284 goto out; 3285 } 3286 3287 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3288 err = parse_ta_bin_descriptor(psp, 3289 &ta_hdr->ta_fw_bin[ta_index], 3290 ta_hdr); 3291 if (err) 3292 goto out; 3293 } 3294 3295 return 0; 3296 out: 3297 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3298 release_firmware(adev->psp.ta_fw); 3299 adev->psp.ta_fw = NULL; 3300 return err; 3301 } 3302 3303 int psp_init_cap_microcode(struct psp_context *psp, 3304 const char *chip_name) 3305 { 3306 struct amdgpu_device *adev = psp->adev; 3307 char fw_name[PSP_FW_NAME_LEN]; 3308 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3309 struct amdgpu_firmware_info *info = NULL; 3310 int err = 0; 3311 3312 if (!chip_name) { 3313 dev_err(adev->dev, "invalid chip name for cap microcode\n"); 3314 return -EINVAL; 3315 } 3316 3317 if (!amdgpu_sriov_vf(adev)) { 3318 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3319 return -EINVAL; 3320 } 3321 3322 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3323 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev); 3324 if (err) { 3325 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3326 err = 0; 3327 goto out; 3328 } 3329 3330 err = amdgpu_ucode_validate(adev->psp.cap_fw); 3331 if (err) { 3332 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3333 goto out; 3334 } 3335 3336 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3337 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3338 info->fw = adev->psp.cap_fw; 3339 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3340 adev->psp.cap_fw->data; 3341 adev->firmware.fw_size += ALIGN( 3342 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3343 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3344 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3345 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3346 3347 return 0; 3348 3349 out: 3350 release_firmware(adev->psp.cap_fw); 3351 adev->psp.cap_fw = NULL; 3352 return err; 3353 } 3354 3355 static int psp_set_clockgating_state(void *handle, 3356 enum amd_clockgating_state state) 3357 { 3358 return 0; 3359 } 3360 3361 static int psp_set_powergating_state(void *handle, 3362 enum amd_powergating_state state) 3363 { 3364 return 0; 3365 } 3366 3367 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3368 struct device_attribute *attr, 3369 char *buf) 3370 { 3371 struct drm_device *ddev = dev_get_drvdata(dev); 3372 struct amdgpu_device *adev = drm_to_adev(ddev); 3373 uint32_t fw_ver; 3374 int ret; 3375 3376 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3377 DRM_INFO("PSP block is not ready yet."); 3378 return -EBUSY; 3379 } 3380 3381 mutex_lock(&adev->psp.mutex); 3382 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3383 mutex_unlock(&adev->psp.mutex); 3384 3385 if (ret) { 3386 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3387 return ret; 3388 } 3389 3390 return sysfs_emit(buf, "%x\n", fw_ver); 3391 } 3392 3393 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3394 struct device_attribute *attr, 3395 const char *buf, 3396 size_t count) 3397 { 3398 struct drm_device *ddev = dev_get_drvdata(dev); 3399 struct amdgpu_device *adev = drm_to_adev(ddev); 3400 int ret, idx; 3401 char fw_name[100]; 3402 const struct firmware *usbc_pd_fw; 3403 struct amdgpu_bo *fw_buf_bo = NULL; 3404 uint64_t fw_pri_mc_addr; 3405 void *fw_pri_cpu_addr; 3406 3407 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3408 DRM_INFO("PSP block is not ready yet."); 3409 return -EBUSY; 3410 } 3411 3412 if (!drm_dev_enter(ddev, &idx)) 3413 return -ENODEV; 3414 3415 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3416 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3417 if (ret) 3418 goto fail; 3419 3420 /* LFB address which is aligned to 1MB boundary per PSP request */ 3421 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3422 AMDGPU_GEM_DOMAIN_VRAM, 3423 &fw_buf_bo, 3424 &fw_pri_mc_addr, 3425 &fw_pri_cpu_addr); 3426 if (ret) 3427 goto rel_buf; 3428 3429 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3430 3431 mutex_lock(&adev->psp.mutex); 3432 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3433 mutex_unlock(&adev->psp.mutex); 3434 3435 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3436 3437 rel_buf: 3438 release_firmware(usbc_pd_fw); 3439 fail: 3440 if (ret) { 3441 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3442 count = ret; 3443 } 3444 3445 drm_dev_exit(idx); 3446 return count; 3447 } 3448 3449 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3450 { 3451 int idx; 3452 3453 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3454 return; 3455 3456 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3457 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3458 3459 drm_dev_exit(idx); 3460 } 3461 3462 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3463 psp_usbc_pd_fw_sysfs_read, 3464 psp_usbc_pd_fw_sysfs_write); 3465 3466 int is_psp_fw_valid(struct psp_bin_desc bin) 3467 { 3468 return bin.size_bytes; 3469 } 3470 3471 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3472 struct bin_attribute *bin_attr, 3473 char *buffer, loff_t pos, size_t count) 3474 { 3475 struct device *dev = kobj_to_dev(kobj); 3476 struct drm_device *ddev = dev_get_drvdata(dev); 3477 struct amdgpu_device *adev = drm_to_adev(ddev); 3478 3479 adev->psp.vbflash_done = false; 3480 3481 /* Safeguard against memory drain */ 3482 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3483 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3484 kvfree(adev->psp.vbflash_tmp_buf); 3485 adev->psp.vbflash_tmp_buf = NULL; 3486 adev->psp.vbflash_image_size = 0; 3487 return -ENOMEM; 3488 } 3489 3490 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3491 if (!adev->psp.vbflash_tmp_buf) { 3492 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3493 if (!adev->psp.vbflash_tmp_buf) 3494 return -ENOMEM; 3495 } 3496 3497 mutex_lock(&adev->psp.mutex); 3498 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3499 adev->psp.vbflash_image_size += count; 3500 mutex_unlock(&adev->psp.mutex); 3501 3502 dev_info(adev->dev, "VBIOS flash write PSP done"); 3503 3504 return count; 3505 } 3506 3507 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3508 struct bin_attribute *bin_attr, char *buffer, 3509 loff_t pos, size_t count) 3510 { 3511 struct device *dev = kobj_to_dev(kobj); 3512 struct drm_device *ddev = dev_get_drvdata(dev); 3513 struct amdgpu_device *adev = drm_to_adev(ddev); 3514 struct amdgpu_bo *fw_buf_bo = NULL; 3515 uint64_t fw_pri_mc_addr; 3516 void *fw_pri_cpu_addr; 3517 int ret; 3518 3519 dev_info(adev->dev, "VBIOS flash to PSP started"); 3520 3521 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3522 AMDGPU_GPU_PAGE_SIZE, 3523 AMDGPU_GEM_DOMAIN_VRAM, 3524 &fw_buf_bo, 3525 &fw_pri_mc_addr, 3526 &fw_pri_cpu_addr); 3527 if (ret) 3528 goto rel_buf; 3529 3530 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3531 3532 mutex_lock(&adev->psp.mutex); 3533 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3534 mutex_unlock(&adev->psp.mutex); 3535 3536 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3537 3538 rel_buf: 3539 kvfree(adev->psp.vbflash_tmp_buf); 3540 adev->psp.vbflash_tmp_buf = NULL; 3541 adev->psp.vbflash_image_size = 0; 3542 3543 if (ret) { 3544 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret); 3545 return ret; 3546 } 3547 3548 dev_info(adev->dev, "VBIOS flash to PSP done"); 3549 return 0; 3550 } 3551 3552 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3553 struct device_attribute *attr, 3554 char *buf) 3555 { 3556 struct drm_device *ddev = dev_get_drvdata(dev); 3557 struct amdgpu_device *adev = drm_to_adev(ddev); 3558 uint32_t vbflash_status; 3559 3560 vbflash_status = psp_vbflash_status(&adev->psp); 3561 if (!adev->psp.vbflash_done) 3562 vbflash_status = 0; 3563 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3564 vbflash_status = 1; 3565 3566 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3567 } 3568 3569 static const struct bin_attribute psp_vbflash_bin_attr = { 3570 .attr = {.name = "psp_vbflash", .mode = 0664}, 3571 .size = 0, 3572 .write = amdgpu_psp_vbflash_write, 3573 .read = amdgpu_psp_vbflash_read, 3574 }; 3575 3576 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL); 3577 3578 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev) 3579 { 3580 int ret = 0; 3581 struct psp_context *psp = &adev->psp; 3582 3583 if (amdgpu_sriov_vf(adev)) 3584 return -EINVAL; 3585 3586 switch (adev->ip_versions[MP0_HWIP][0]) { 3587 case IP_VERSION(13, 0, 0): 3588 case IP_VERSION(13, 0, 7): 3589 if (!psp->adev) { 3590 psp->adev = adev; 3591 psp_v13_0_set_psp_funcs(psp); 3592 } 3593 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3594 if (ret) 3595 dev_err(adev->dev, "Failed to create device file psp_vbflash"); 3596 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status); 3597 if (ret) 3598 dev_err(adev->dev, "Failed to create device file psp_vbflash_status"); 3599 return ret; 3600 default: 3601 return 0; 3602 } 3603 } 3604 3605 const struct amd_ip_funcs psp_ip_funcs = { 3606 .name = "psp", 3607 .early_init = psp_early_init, 3608 .late_init = NULL, 3609 .sw_init = psp_sw_init, 3610 .sw_fini = psp_sw_fini, 3611 .hw_init = psp_hw_init, 3612 .hw_fini = psp_hw_fini, 3613 .suspend = psp_suspend, 3614 .resume = psp_resume, 3615 .is_idle = NULL, 3616 .check_soft_reset = NULL, 3617 .wait_for_idle = NULL, 3618 .soft_reset = NULL, 3619 .set_clockgating_state = psp_set_clockgating_state, 3620 .set_powergating_state = psp_set_powergating_state, 3621 }; 3622 3623 static int psp_sysfs_init(struct amdgpu_device *adev) 3624 { 3625 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3626 3627 if (ret) 3628 DRM_ERROR("Failed to create USBC PD FW control file!"); 3629 3630 return ret; 3631 } 3632 3633 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev) 3634 { 3635 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3636 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status); 3637 } 3638 3639 static void psp_sysfs_fini(struct amdgpu_device *adev) 3640 { 3641 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3642 } 3643 3644 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3645 { 3646 .type = AMD_IP_BLOCK_TYPE_PSP, 3647 .major = 3, 3648 .minor = 1, 3649 .rev = 0, 3650 .funcs = &psp_ip_funcs, 3651 }; 3652 3653 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3654 { 3655 .type = AMD_IP_BLOCK_TYPE_PSP, 3656 .major = 10, 3657 .minor = 0, 3658 .rev = 0, 3659 .funcs = &psp_ip_funcs, 3660 }; 3661 3662 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3663 { 3664 .type = AMD_IP_BLOCK_TYPE_PSP, 3665 .major = 11, 3666 .minor = 0, 3667 .rev = 0, 3668 .funcs = &psp_ip_funcs, 3669 }; 3670 3671 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3672 .type = AMD_IP_BLOCK_TYPE_PSP, 3673 .major = 11, 3674 .minor = 0, 3675 .rev = 8, 3676 .funcs = &psp_ip_funcs, 3677 }; 3678 3679 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3680 { 3681 .type = AMD_IP_BLOCK_TYPE_PSP, 3682 .major = 12, 3683 .minor = 0, 3684 .rev = 0, 3685 .funcs = &psp_ip_funcs, 3686 }; 3687 3688 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3689 .type = AMD_IP_BLOCK_TYPE_PSP, 3690 .major = 13, 3691 .minor = 0, 3692 .rev = 0, 3693 .funcs = &psp_ip_funcs, 3694 }; 3695