1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 #include "psp_v10_0.h" 34 35 static void psp_set_funcs(struct amdgpu_device *adev); 36 37 static int psp_early_init(void *handle) 38 { 39 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 40 41 psp_set_funcs(adev); 42 43 return 0; 44 } 45 46 static int psp_sw_init(void *handle) 47 { 48 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 49 struct psp_context *psp = &adev->psp; 50 int ret; 51 52 switch (adev->asic_type) { 53 case CHIP_VEGA10: 54 psp_v3_1_set_psp_funcs(psp); 55 break; 56 case CHIP_RAVEN: 57 psp_v10_0_set_psp_funcs(psp); 58 break; 59 default: 60 return -EINVAL; 61 } 62 63 psp->adev = adev; 64 65 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 66 return 0; 67 68 ret = psp_init_microcode(psp); 69 if (ret) { 70 DRM_ERROR("Failed to load psp firmware!\n"); 71 return ret; 72 } 73 74 return 0; 75 } 76 77 static int psp_sw_fini(void *handle) 78 { 79 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 80 81 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 82 return 0; 83 84 release_firmware(adev->psp.sos_fw); 85 adev->psp.sos_fw = NULL; 86 release_firmware(adev->psp.asd_fw); 87 adev->psp.asd_fw = NULL; 88 return 0; 89 } 90 91 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 92 uint32_t reg_val, uint32_t mask, bool check_changed) 93 { 94 uint32_t val; 95 int i; 96 struct amdgpu_device *adev = psp->adev; 97 98 for (i = 0; i < adev->usec_timeout; i++) { 99 val = RREG32(reg_index); 100 if (check_changed) { 101 if (val != reg_val) 102 return 0; 103 } else { 104 if ((val & mask) == reg_val) 105 return 0; 106 } 107 udelay(1); 108 } 109 110 return -ETIME; 111 } 112 113 static int 114 psp_cmd_submit_buf(struct psp_context *psp, 115 struct amdgpu_firmware_info *ucode, 116 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr, 117 int index) 118 { 119 int ret; 120 121 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 122 123 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 124 125 ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr, 126 fence_mc_addr, index); 127 128 while (*((unsigned int *)psp->fence_buf) != index) { 129 msleep(1); 130 } 131 132 return ret; 133 } 134 135 static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd, 136 uint64_t tmr_mc, uint32_t size) 137 { 138 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 139 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 140 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 141 cmd->cmd.cmd_setup_tmr.buf_size = size; 142 } 143 144 /* Set up Trusted Memory Region */ 145 static int psp_tmr_init(struct psp_context *psp) 146 { 147 int ret; 148 149 /* 150 * Allocate 3M memory aligned to 1M from Frame Buffer (local 151 * physical). 152 * 153 * Note: this memory need be reserved till the driver 154 * uninitializes. 155 */ 156 ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000, 157 AMDGPU_GEM_DOMAIN_VRAM, 158 &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 159 160 return ret; 161 } 162 163 static int psp_tmr_load(struct psp_context *psp) 164 { 165 int ret; 166 struct psp_gfx_cmd_resp *cmd; 167 168 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 169 if (!cmd) 170 return -ENOMEM; 171 172 psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000); 173 174 ret = psp_cmd_submit_buf(psp, NULL, cmd, 175 psp->fence_buf_mc_addr, 1); 176 if (ret) 177 goto failed; 178 179 kfree(cmd); 180 181 return 0; 182 183 failed: 184 kfree(cmd); 185 return ret; 186 } 187 188 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd, 189 uint64_t asd_mc, uint64_t asd_mc_shared, 190 uint32_t size, uint32_t shared_size) 191 { 192 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 193 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 194 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 195 cmd->cmd.cmd_load_ta.app_len = size; 196 197 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared); 198 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared); 199 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 200 } 201 202 static int psp_asd_init(struct psp_context *psp) 203 { 204 int ret; 205 206 /* 207 * Allocate 16k memory aligned to 4k from Frame Buffer (local 208 * physical) for shared ASD <-> Driver 209 */ 210 ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE, 211 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 212 &psp->asd_shared_bo, 213 &psp->asd_shared_mc_addr, 214 &psp->asd_shared_buf); 215 216 return ret; 217 } 218 219 static int psp_asd_load(struct psp_context *psp) 220 { 221 int ret; 222 struct psp_gfx_cmd_resp *cmd; 223 224 /* If PSP version doesn't match ASD version, asd loading will be failed. 225 * add workaround to bypass it for sriov now. 226 * TODO: add version check to make it common 227 */ 228 if (amdgpu_sriov_vf(psp->adev)) 229 return 0; 230 231 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 232 if (!cmd) 233 return -ENOMEM; 234 235 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 236 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 237 238 psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr, 239 psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE); 240 241 ret = psp_cmd_submit_buf(psp, NULL, cmd, 242 psp->fence_buf_mc_addr, 2); 243 244 kfree(cmd); 245 246 return ret; 247 } 248 249 static int psp_hw_start(struct psp_context *psp) 250 { 251 struct amdgpu_device *adev = psp->adev; 252 int ret; 253 254 if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) { 255 ret = psp_bootloader_load_sysdrv(psp); 256 if (ret) 257 return ret; 258 259 ret = psp_bootloader_load_sos(psp); 260 if (ret) 261 return ret; 262 } 263 264 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 265 if (ret) 266 return ret; 267 268 ret = psp_tmr_load(psp); 269 if (ret) 270 return ret; 271 272 ret = psp_asd_load(psp); 273 if (ret) 274 return ret; 275 276 return 0; 277 } 278 279 static int psp_np_fw_load(struct psp_context *psp) 280 { 281 int i, ret; 282 struct amdgpu_firmware_info *ucode; 283 struct amdgpu_device* adev = psp->adev; 284 285 for (i = 0; i < adev->firmware.max_ucodes; i++) { 286 ucode = &adev->firmware.ucode[i]; 287 if (!ucode->fw) 288 continue; 289 290 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 291 psp_smu_reload_quirk(psp)) 292 continue; 293 if (amdgpu_sriov_vf(adev) && 294 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 295 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 296 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) 297 /*skip ucode loading in SRIOV VF */ 298 continue; 299 300 ret = psp_prep_cmd_buf(ucode, psp->cmd); 301 if (ret) 302 return ret; 303 304 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 305 psp->fence_buf_mc_addr, i + 3); 306 if (ret) 307 return ret; 308 309 #if 0 310 /* check if firmware loaded sucessfully */ 311 if (!amdgpu_psp_check_fw_loading_status(adev, i)) 312 return -EINVAL; 313 #endif 314 } 315 316 return 0; 317 } 318 319 static int psp_load_fw(struct amdgpu_device *adev) 320 { 321 int ret; 322 struct psp_context *psp = &adev->psp; 323 324 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset != 0) 325 goto skip_memalloc; 326 327 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 328 if (!psp->cmd) 329 return -ENOMEM; 330 331 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 332 AMDGPU_GEM_DOMAIN_GTT, 333 &psp->fw_pri_bo, 334 &psp->fw_pri_mc_addr, 335 &psp->fw_pri_buf); 336 if (ret) 337 goto failed; 338 339 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 340 AMDGPU_GEM_DOMAIN_VRAM, 341 &psp->fence_buf_bo, 342 &psp->fence_buf_mc_addr, 343 &psp->fence_buf); 344 if (ret) 345 goto failed_mem2; 346 347 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 348 AMDGPU_GEM_DOMAIN_VRAM, 349 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 350 (void **)&psp->cmd_buf_mem); 351 if (ret) 352 goto failed_mem1; 353 354 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 355 356 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 357 if (ret) 358 goto failed_mem; 359 360 ret = psp_tmr_init(psp); 361 if (ret) 362 goto failed_mem; 363 364 ret = psp_asd_init(psp); 365 if (ret) 366 goto failed_mem; 367 368 skip_memalloc: 369 ret = psp_hw_start(psp); 370 if (ret) 371 goto failed_mem; 372 373 ret = psp_np_fw_load(psp); 374 if (ret) 375 goto failed_mem; 376 377 return 0; 378 379 failed_mem: 380 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, 381 &psp->cmd_buf_mc_addr, 382 (void **)&psp->cmd_buf_mem); 383 failed_mem1: 384 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 385 &psp->fence_buf_mc_addr, &psp->fence_buf); 386 failed_mem2: 387 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 388 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 389 failed: 390 kfree(psp->cmd); 391 psp->cmd = NULL; 392 return ret; 393 } 394 395 static int psp_hw_init(void *handle) 396 { 397 int ret; 398 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 399 400 401 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 402 return 0; 403 404 mutex_lock(&adev->firmware.mutex); 405 /* 406 * This sequence is just used on hw_init only once, no need on 407 * resume. 408 */ 409 ret = amdgpu_ucode_init_bo(adev); 410 if (ret) 411 goto failed; 412 413 ret = psp_load_fw(adev); 414 if (ret) { 415 DRM_ERROR("PSP firmware loading failed\n"); 416 goto failed; 417 } 418 419 mutex_unlock(&adev->firmware.mutex); 420 return 0; 421 422 failed: 423 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 424 mutex_unlock(&adev->firmware.mutex); 425 return -EINVAL; 426 } 427 428 static int psp_hw_fini(void *handle) 429 { 430 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 431 struct psp_context *psp = &adev->psp; 432 433 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 434 return 0; 435 436 amdgpu_ucode_fini_bo(adev); 437 438 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 439 440 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 441 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 442 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 443 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 444 &psp->fence_buf_mc_addr, &psp->fence_buf); 445 amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr, 446 &psp->asd_shared_buf); 447 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 448 (void **)&psp->cmd_buf_mem); 449 450 kfree(psp->cmd); 451 psp->cmd = NULL; 452 453 return 0; 454 } 455 456 static int psp_suspend(void *handle) 457 { 458 int ret; 459 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 460 struct psp_context *psp = &adev->psp; 461 462 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 463 return 0; 464 465 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 466 if (ret) { 467 DRM_ERROR("PSP ring stop failed\n"); 468 return ret; 469 } 470 471 return 0; 472 } 473 474 static int psp_resume(void *handle) 475 { 476 int ret; 477 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 478 struct psp_context *psp = &adev->psp; 479 480 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 481 return 0; 482 483 DRM_INFO("PSP is resuming...\n"); 484 485 mutex_lock(&adev->firmware.mutex); 486 487 ret = psp_hw_start(psp); 488 if (ret) 489 goto failed; 490 491 ret = psp_np_fw_load(psp); 492 if (ret) 493 goto failed; 494 495 mutex_unlock(&adev->firmware.mutex); 496 497 return 0; 498 499 failed: 500 DRM_ERROR("PSP resume failed\n"); 501 mutex_unlock(&adev->firmware.mutex); 502 return ret; 503 } 504 505 int psp_gpu_reset(struct amdgpu_device *adev) 506 { 507 return psp_mode1_reset(&adev->psp); 508 } 509 510 static bool psp_check_fw_loading_status(struct amdgpu_device *adev, 511 enum AMDGPU_UCODE_ID ucode_type) 512 { 513 struct amdgpu_firmware_info *ucode = NULL; 514 515 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 516 DRM_INFO("firmware is not loaded by PSP\n"); 517 return true; 518 } 519 520 if (!adev->firmware.fw_size) 521 return false; 522 523 ucode = &adev->firmware.ucode[ucode_type]; 524 if (!ucode->fw || !ucode->ucode_size) 525 return false; 526 527 return psp_compare_sram_data(&adev->psp, ucode, ucode_type); 528 } 529 530 static int psp_set_clockgating_state(void *handle, 531 enum amd_clockgating_state state) 532 { 533 return 0; 534 } 535 536 static int psp_set_powergating_state(void *handle, 537 enum amd_powergating_state state) 538 { 539 return 0; 540 } 541 542 const struct amd_ip_funcs psp_ip_funcs = { 543 .name = "psp", 544 .early_init = psp_early_init, 545 .late_init = NULL, 546 .sw_init = psp_sw_init, 547 .sw_fini = psp_sw_fini, 548 .hw_init = psp_hw_init, 549 .hw_fini = psp_hw_fini, 550 .suspend = psp_suspend, 551 .resume = psp_resume, 552 .is_idle = NULL, 553 .check_soft_reset = NULL, 554 .wait_for_idle = NULL, 555 .soft_reset = NULL, 556 .set_clockgating_state = psp_set_clockgating_state, 557 .set_powergating_state = psp_set_powergating_state, 558 }; 559 560 static const struct amdgpu_psp_funcs psp_funcs = { 561 .check_fw_loading_status = psp_check_fw_loading_status, 562 }; 563 564 static void psp_set_funcs(struct amdgpu_device *adev) 565 { 566 if (NULL == adev->firmware.funcs) 567 adev->firmware.funcs = &psp_funcs; 568 } 569 570 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 571 { 572 .type = AMD_IP_BLOCK_TYPE_PSP, 573 .major = 3, 574 .minor = 1, 575 .rev = 0, 576 .funcs = &psp_ip_funcs, 577 }; 578 579 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 580 { 581 .type = AMD_IP_BLOCK_TYPE_PSP, 582 .major = 10, 583 .minor = 0, 584 .rev = 0, 585 .funcs = &psp_ip_funcs, 586 }; 587