1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/dma-mapping.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v3_1.h" 34 #include "psp_v10_0.h" 35 #include "psp_v11_0.h" 36 #include "psp_v12_0.h" 37 #include "psp_v13_0.h" 38 39 #include "amdgpu_ras.h" 40 #include "amdgpu_securedisplay.h" 41 #include "amdgpu_atomfirmware.h" 42 43 static int psp_sysfs_init(struct amdgpu_device *adev); 44 static void psp_sysfs_fini(struct amdgpu_device *adev); 45 46 static int psp_load_smu_fw(struct psp_context *psp); 47 48 /* 49 * Due to DF Cstate management centralized to PMFW, the firmware 50 * loading sequence will be updated as below: 51 * - Load KDB 52 * - Load SYS_DRV 53 * - Load tOS 54 * - Load PMFW 55 * - Setup TMR 56 * - Load other non-psp fw 57 * - Load ASD 58 * - Load XGMI/RAS/HDCP/DTM TA if any 59 * 60 * This new sequence is required for 61 * - Arcturus and onwards 62 * - Navi12 and onwards 63 */ 64 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 65 { 66 struct amdgpu_device *adev = psp->adev; 67 68 psp->pmfw_centralized_cstate_management = false; 69 70 if (amdgpu_sriov_vf(adev)) 71 return; 72 73 if (adev->flags & AMD_IS_APU) 74 return; 75 76 if ((adev->asic_type >= CHIP_ARCTURUS) || 77 (adev->asic_type >= CHIP_NAVI12)) 78 psp->pmfw_centralized_cstate_management = true; 79 } 80 81 static int psp_early_init(void *handle) 82 { 83 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 84 struct psp_context *psp = &adev->psp; 85 86 switch (adev->asic_type) { 87 case CHIP_VEGA10: 88 case CHIP_VEGA12: 89 psp_v3_1_set_psp_funcs(psp); 90 psp->autoload_supported = false; 91 break; 92 case CHIP_RAVEN: 93 psp_v10_0_set_psp_funcs(psp); 94 psp->autoload_supported = false; 95 break; 96 case CHIP_VEGA20: 97 case CHIP_ARCTURUS: 98 psp_v11_0_set_psp_funcs(psp); 99 psp->autoload_supported = false; 100 break; 101 case CHIP_NAVI10: 102 case CHIP_NAVI14: 103 case CHIP_NAVI12: 104 case CHIP_SIENNA_CICHLID: 105 case CHIP_NAVY_FLOUNDER: 106 case CHIP_VANGOGH: 107 case CHIP_DIMGREY_CAVEFISH: 108 psp_v11_0_set_psp_funcs(psp); 109 psp->autoload_supported = true; 110 break; 111 case CHIP_RENOIR: 112 psp_v12_0_set_psp_funcs(psp); 113 break; 114 case CHIP_ALDEBARAN: 115 psp_v13_0_set_psp_funcs(psp); 116 break; 117 default: 118 return -EINVAL; 119 } 120 121 psp->adev = adev; 122 123 psp_check_pmfw_centralized_cstate_management(psp); 124 125 return 0; 126 } 127 128 static void psp_memory_training_fini(struct psp_context *psp) 129 { 130 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 131 132 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 133 kfree(ctx->sys_cache); 134 ctx->sys_cache = NULL; 135 } 136 137 static int psp_memory_training_init(struct psp_context *psp) 138 { 139 int ret; 140 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 141 142 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 143 DRM_DEBUG("memory training is not supported!\n"); 144 return 0; 145 } 146 147 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 148 if (ctx->sys_cache == NULL) { 149 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 150 ret = -ENOMEM; 151 goto Err_out; 152 } 153 154 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 155 ctx->train_data_size, 156 ctx->p2c_train_data_offset, 157 ctx->c2p_train_data_offset); 158 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 159 return 0; 160 161 Err_out: 162 psp_memory_training_fini(psp); 163 return ret; 164 } 165 166 static int psp_sw_init(void *handle) 167 { 168 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 169 struct psp_context *psp = &adev->psp; 170 int ret; 171 172 if (!amdgpu_sriov_vf(adev)) { 173 ret = psp_init_microcode(psp); 174 if (ret) { 175 DRM_ERROR("Failed to load psp firmware!\n"); 176 return ret; 177 } 178 } 179 180 ret = psp_memory_training_init(psp); 181 if (ret) { 182 DRM_ERROR("Failed to initialize memory training!\n"); 183 return ret; 184 } 185 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 186 if (ret) { 187 DRM_ERROR("Failed to process memory training!\n"); 188 return ret; 189 } 190 191 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 192 ret= psp_sysfs_init(adev); 193 if (ret) { 194 return ret; 195 } 196 } 197 198 return 0; 199 } 200 201 static int psp_sw_fini(void *handle) 202 { 203 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 204 205 psp_memory_training_fini(&adev->psp); 206 if (adev->psp.sos_fw) { 207 release_firmware(adev->psp.sos_fw); 208 adev->psp.sos_fw = NULL; 209 } 210 if (adev->psp.asd_fw) { 211 release_firmware(adev->psp.asd_fw); 212 adev->psp.asd_fw = NULL; 213 } 214 if (adev->psp.ta_fw) { 215 release_firmware(adev->psp.ta_fw); 216 adev->psp.ta_fw = NULL; 217 } 218 219 if (adev->asic_type == CHIP_NAVI10 || 220 adev->asic_type == CHIP_SIENNA_CICHLID) 221 psp_sysfs_fini(adev); 222 223 return 0; 224 } 225 226 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 227 uint32_t reg_val, uint32_t mask, bool check_changed) 228 { 229 uint32_t val; 230 int i; 231 struct amdgpu_device *adev = psp->adev; 232 233 if (psp->adev->in_pci_err_recovery) 234 return 0; 235 236 for (i = 0; i < adev->usec_timeout; i++) { 237 val = RREG32(reg_index); 238 if (check_changed) { 239 if (val != reg_val) 240 return 0; 241 } else { 242 if ((val & mask) == reg_val) 243 return 0; 244 } 245 udelay(1); 246 } 247 248 return -ETIME; 249 } 250 251 static int 252 psp_cmd_submit_buf(struct psp_context *psp, 253 struct amdgpu_firmware_info *ucode, 254 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 255 { 256 int ret; 257 int index; 258 int timeout = 20000; 259 bool ras_intr = false; 260 bool skip_unsupport = false; 261 262 if (psp->adev->in_pci_err_recovery) 263 return 0; 264 265 mutex_lock(&psp->mutex); 266 267 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 268 269 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 270 271 index = atomic_inc_return(&psp->fence_value); 272 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 273 if (ret) { 274 atomic_dec(&psp->fence_value); 275 mutex_unlock(&psp->mutex); 276 return ret; 277 } 278 279 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 280 while (*((unsigned int *)psp->fence_buf) != index) { 281 if (--timeout == 0) 282 break; 283 /* 284 * Shouldn't wait for timeout when err_event_athub occurs, 285 * because gpu reset thread triggered and lock resource should 286 * be released for psp resume sequence. 287 */ 288 ras_intr = amdgpu_ras_intr_triggered(); 289 if (ras_intr) 290 break; 291 usleep_range(10, 100); 292 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 293 } 294 295 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 296 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 297 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 298 299 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 300 301 /* In some cases, psp response status is not 0 even there is no 302 * problem while the command is submitted. Some version of PSP FW 303 * doesn't write 0 to that field. 304 * So here we would like to only print a warning instead of an error 305 * during psp initialization to avoid breaking hw_init and it doesn't 306 * return -EINVAL. 307 */ 308 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 309 if (ucode) 310 DRM_WARN("failed to load ucode id (%d) ", 311 ucode->ucode_id); 312 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n", 313 psp->cmd_buf_mem->cmd_id, 314 psp->cmd_buf_mem->resp.status); 315 if (!timeout) { 316 mutex_unlock(&psp->mutex); 317 return -EINVAL; 318 } 319 } 320 321 if (ucode) { 322 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 323 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 324 } 325 mutex_unlock(&psp->mutex); 326 327 return ret; 328 } 329 330 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 331 struct psp_gfx_cmd_resp *cmd, 332 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 333 { 334 struct amdgpu_device *adev = psp->adev; 335 uint32_t size = amdgpu_bo_size(tmr_bo); 336 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 337 338 if (amdgpu_sriov_vf(psp->adev)) 339 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 340 else 341 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 342 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 343 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 344 cmd->cmd.cmd_setup_tmr.buf_size = size; 345 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 346 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 347 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 348 } 349 350 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 351 uint64_t pri_buf_mc, uint32_t size) 352 { 353 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 354 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 355 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 356 cmd->cmd.cmd_load_toc.toc_size = size; 357 } 358 359 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 360 static int psp_load_toc(struct psp_context *psp, 361 uint32_t *tmr_size) 362 { 363 int ret; 364 struct psp_gfx_cmd_resp *cmd; 365 366 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 367 if (!cmd) 368 return -ENOMEM; 369 /* Copy toc to psp firmware private buffer */ 370 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 371 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size); 372 373 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 374 375 ret = psp_cmd_submit_buf(psp, NULL, cmd, 376 psp->fence_buf_mc_addr); 377 if (!ret) 378 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 379 kfree(cmd); 380 return ret; 381 } 382 383 /* Set up Trusted Memory Region */ 384 static int psp_tmr_init(struct psp_context *psp) 385 { 386 int ret; 387 int tmr_size; 388 void *tmr_buf; 389 void **pptr; 390 391 /* 392 * According to HW engineer, they prefer the TMR address be "naturally 393 * aligned" , e.g. the start address be an integer divide of TMR size. 394 * 395 * Note: this memory need be reserved till the driver 396 * uninitializes. 397 */ 398 tmr_size = PSP_TMR_SIZE(psp->adev); 399 400 /* For ASICs support RLC autoload, psp will parse the toc 401 * and calculate the total size of TMR needed */ 402 if (!amdgpu_sriov_vf(psp->adev) && 403 psp->toc_start_addr && 404 psp->toc_bin_size && 405 psp->fw_pri_buf) { 406 ret = psp_load_toc(psp, &tmr_size); 407 if (ret) { 408 DRM_ERROR("Failed to load toc\n"); 409 return ret; 410 } 411 } 412 413 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 414 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 415 AMDGPU_GEM_DOMAIN_VRAM, 416 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 417 418 return ret; 419 } 420 421 static bool psp_skip_tmr(struct psp_context *psp) 422 { 423 switch (psp->adev->asic_type) { 424 case CHIP_NAVI12: 425 case CHIP_SIENNA_CICHLID: 426 case CHIP_ALDEBARAN: 427 return true; 428 default: 429 return false; 430 } 431 } 432 433 static int psp_tmr_load(struct psp_context *psp) 434 { 435 int ret; 436 struct psp_gfx_cmd_resp *cmd; 437 438 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 439 * Already set up by host driver. 440 */ 441 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 442 return 0; 443 444 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 445 if (!cmd) 446 return -ENOMEM; 447 448 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 449 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 450 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 451 452 ret = psp_cmd_submit_buf(psp, NULL, cmd, 453 psp->fence_buf_mc_addr); 454 455 kfree(cmd); 456 457 return ret; 458 } 459 460 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 461 struct psp_gfx_cmd_resp *cmd) 462 { 463 if (amdgpu_sriov_vf(psp->adev)) 464 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 465 else 466 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 467 } 468 469 static int psp_tmr_unload(struct psp_context *psp) 470 { 471 int ret; 472 struct psp_gfx_cmd_resp *cmd; 473 474 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 475 if (!cmd) 476 return -ENOMEM; 477 478 psp_prep_tmr_unload_cmd_buf(psp, cmd); 479 DRM_INFO("free PSP TMR buffer\n"); 480 481 ret = psp_cmd_submit_buf(psp, NULL, cmd, 482 psp->fence_buf_mc_addr); 483 484 kfree(cmd); 485 486 return ret; 487 } 488 489 static int psp_tmr_terminate(struct psp_context *psp) 490 { 491 int ret; 492 void *tmr_buf; 493 void **pptr; 494 495 ret = psp_tmr_unload(psp); 496 if (ret) 497 return ret; 498 499 /* free TMR memory buffer */ 500 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 501 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 502 503 return 0; 504 } 505 506 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 507 uint64_t *output_ptr) 508 { 509 int ret; 510 struct psp_gfx_cmd_resp *cmd; 511 512 if (!output_ptr) 513 return -EINVAL; 514 515 if (amdgpu_sriov_vf(psp->adev)) 516 return 0; 517 518 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 519 if (!cmd) 520 return -ENOMEM; 521 522 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 523 524 ret = psp_cmd_submit_buf(psp, NULL, cmd, 525 psp->fence_buf_mc_addr); 526 527 if (!ret) { 528 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 529 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 530 } 531 532 kfree(cmd); 533 534 return ret; 535 } 536 537 static int psp_boot_config_set(struct amdgpu_device *adev) 538 { 539 struct psp_context *psp = &adev->psp; 540 struct psp_gfx_cmd_resp *cmd = psp->cmd; 541 542 if (amdgpu_sriov_vf(adev)) 543 return 0; 544 545 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 546 547 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 548 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 549 cmd->cmd.boot_cfg.boot_config = BOOT_CONFIG_GECC; 550 cmd->cmd.boot_cfg.boot_config_valid = BOOT_CONFIG_GECC; 551 552 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 553 } 554 555 static int psp_rl_load(struct amdgpu_device *adev) 556 { 557 struct psp_context *psp = &adev->psp; 558 struct psp_gfx_cmd_resp *cmd = psp->cmd; 559 560 if (psp->rl_bin_size == 0) 561 return 0; 562 563 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 564 memcpy(psp->fw_pri_buf, psp->rl_start_addr, psp->rl_bin_size); 565 566 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 567 568 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 569 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 570 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 571 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl_bin_size; 572 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 573 574 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 575 } 576 577 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 578 uint64_t asd_mc, uint32_t size) 579 { 580 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 581 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 582 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 583 cmd->cmd.cmd_load_ta.app_len = size; 584 585 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 586 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 587 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 588 } 589 590 static int psp_asd_load(struct psp_context *psp) 591 { 592 int ret; 593 struct psp_gfx_cmd_resp *cmd; 594 595 /* If PSP version doesn't match ASD version, asd loading will be failed. 596 * add workaround to bypass it for sriov now. 597 * TODO: add version check to make it common 598 */ 599 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size) 600 return 0; 601 602 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 603 if (!cmd) 604 return -ENOMEM; 605 606 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 607 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 608 609 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 610 psp->asd_ucode_size); 611 612 ret = psp_cmd_submit_buf(psp, NULL, cmd, 613 psp->fence_buf_mc_addr); 614 if (!ret) { 615 psp->asd_context.asd_initialized = true; 616 psp->asd_context.session_id = cmd->resp.session_id; 617 } 618 619 kfree(cmd); 620 621 return ret; 622 } 623 624 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 625 uint32_t session_id) 626 { 627 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 628 cmd->cmd.cmd_unload_ta.session_id = session_id; 629 } 630 631 static int psp_asd_unload(struct psp_context *psp) 632 { 633 int ret; 634 struct psp_gfx_cmd_resp *cmd; 635 636 if (amdgpu_sriov_vf(psp->adev)) 637 return 0; 638 639 if (!psp->asd_context.asd_initialized) 640 return 0; 641 642 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 643 if (!cmd) 644 return -ENOMEM; 645 646 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 647 648 ret = psp_cmd_submit_buf(psp, NULL, cmd, 649 psp->fence_buf_mc_addr); 650 if (!ret) 651 psp->asd_context.asd_initialized = false; 652 653 kfree(cmd); 654 655 return ret; 656 } 657 658 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 659 uint32_t id, uint32_t value) 660 { 661 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 662 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 663 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 664 } 665 666 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 667 uint32_t value) 668 { 669 struct psp_gfx_cmd_resp *cmd = NULL; 670 int ret = 0; 671 672 if (reg >= PSP_REG_LAST) 673 return -EINVAL; 674 675 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 676 if (!cmd) 677 return -ENOMEM; 678 679 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 680 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 681 682 kfree(cmd); 683 return ret; 684 } 685 686 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 687 uint64_t ta_bin_mc, 688 uint32_t ta_bin_size, 689 uint64_t ta_shared_mc, 690 uint32_t ta_shared_size) 691 { 692 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 693 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 694 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 695 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 696 697 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 698 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 699 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 700 } 701 702 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 703 { 704 int ret; 705 706 /* 707 * Allocate 16k memory aligned to 4k from Frame Buffer (local 708 * physical) for xgmi ta <-> Driver 709 */ 710 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 711 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 712 &psp->xgmi_context.xgmi_shared_bo, 713 &psp->xgmi_context.xgmi_shared_mc_addr, 714 &psp->xgmi_context.xgmi_shared_buf); 715 716 return ret; 717 } 718 719 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 720 uint32_t ta_cmd_id, 721 uint32_t session_id) 722 { 723 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 724 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 725 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 726 } 727 728 static int psp_ta_invoke(struct psp_context *psp, 729 uint32_t ta_cmd_id, 730 uint32_t session_id) 731 { 732 int ret; 733 struct psp_gfx_cmd_resp *cmd; 734 735 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 736 if (!cmd) 737 return -ENOMEM; 738 739 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 740 741 ret = psp_cmd_submit_buf(psp, NULL, cmd, 742 psp->fence_buf_mc_addr); 743 744 kfree(cmd); 745 746 return ret; 747 } 748 749 static int psp_xgmi_load(struct psp_context *psp) 750 { 751 int ret; 752 struct psp_gfx_cmd_resp *cmd; 753 754 /* 755 * TODO: bypass the loading in sriov for now 756 */ 757 758 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 759 if (!cmd) 760 return -ENOMEM; 761 762 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 763 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 764 765 psp_prep_ta_load_cmd_buf(cmd, 766 psp->fw_pri_mc_addr, 767 psp->ta_xgmi_ucode_size, 768 psp->xgmi_context.xgmi_shared_mc_addr, 769 PSP_XGMI_SHARED_MEM_SIZE); 770 771 ret = psp_cmd_submit_buf(psp, NULL, cmd, 772 psp->fence_buf_mc_addr); 773 774 if (!ret) { 775 psp->xgmi_context.initialized = 1; 776 psp->xgmi_context.session_id = cmd->resp.session_id; 777 } 778 779 kfree(cmd); 780 781 return ret; 782 } 783 784 static int psp_xgmi_unload(struct psp_context *psp) 785 { 786 int ret; 787 struct psp_gfx_cmd_resp *cmd; 788 struct amdgpu_device *adev = psp->adev; 789 790 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 791 if (adev->asic_type == CHIP_ARCTURUS || 792 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu)) 793 return 0; 794 795 /* 796 * TODO: bypass the unloading in sriov for now 797 */ 798 799 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 800 if (!cmd) 801 return -ENOMEM; 802 803 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 804 805 ret = psp_cmd_submit_buf(psp, NULL, cmd, 806 psp->fence_buf_mc_addr); 807 808 kfree(cmd); 809 810 return ret; 811 } 812 813 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 814 { 815 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 816 } 817 818 int psp_xgmi_terminate(struct psp_context *psp) 819 { 820 int ret; 821 822 if (!psp->xgmi_context.initialized) 823 return 0; 824 825 ret = psp_xgmi_unload(psp); 826 if (ret) 827 return ret; 828 829 psp->xgmi_context.initialized = 0; 830 831 /* free xgmi shared memory */ 832 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 833 &psp->xgmi_context.xgmi_shared_mc_addr, 834 &psp->xgmi_context.xgmi_shared_buf); 835 836 return 0; 837 } 838 839 int psp_xgmi_initialize(struct psp_context *psp) 840 { 841 struct ta_xgmi_shared_memory *xgmi_cmd; 842 int ret; 843 844 if (!psp->adev->psp.ta_fw || 845 !psp->adev->psp.ta_xgmi_ucode_size || 846 !psp->adev->psp.ta_xgmi_start_addr) 847 return -ENOENT; 848 849 if (!psp->xgmi_context.initialized) { 850 ret = psp_xgmi_init_shared_buf(psp); 851 if (ret) 852 return ret; 853 } 854 855 /* Load XGMI TA */ 856 ret = psp_xgmi_load(psp); 857 if (ret) 858 return ret; 859 860 /* Initialize XGMI session */ 861 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 862 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 863 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 864 865 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 866 867 return ret; 868 } 869 870 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 871 { 872 struct ta_xgmi_shared_memory *xgmi_cmd; 873 int ret; 874 875 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 876 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 877 878 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 879 880 /* Invoke xgmi ta to get hive id */ 881 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 882 if (ret) 883 return ret; 884 885 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 886 887 return 0; 888 } 889 890 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 891 { 892 struct ta_xgmi_shared_memory *xgmi_cmd; 893 int ret; 894 895 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 896 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 897 898 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 899 900 /* Invoke xgmi ta to get the node id */ 901 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 902 if (ret) 903 return ret; 904 905 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 906 907 return 0; 908 } 909 910 int psp_xgmi_get_topology_info(struct psp_context *psp, 911 int number_devices, 912 struct psp_xgmi_topology_info *topology) 913 { 914 struct ta_xgmi_shared_memory *xgmi_cmd; 915 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 916 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 917 int i; 918 int ret; 919 920 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 921 return -EINVAL; 922 923 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 924 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 925 926 /* Fill in the shared memory with topology information as input */ 927 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 928 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 929 topology_info_input->num_nodes = number_devices; 930 931 for (i = 0; i < topology_info_input->num_nodes; i++) { 932 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 933 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 934 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 935 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 936 } 937 938 /* Invoke xgmi ta to get the topology information */ 939 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 940 if (ret) 941 return ret; 942 943 /* Read the output topology information from the shared memory */ 944 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 945 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 946 for (i = 0; i < topology->num_nodes; i++) { 947 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 948 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 949 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 950 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 951 } 952 953 return 0; 954 } 955 956 int psp_xgmi_set_topology_info(struct psp_context *psp, 957 int number_devices, 958 struct psp_xgmi_topology_info *topology) 959 { 960 struct ta_xgmi_shared_memory *xgmi_cmd; 961 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 962 int i; 963 964 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 965 return -EINVAL; 966 967 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 968 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 969 970 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 971 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 972 topology_info_input->num_nodes = number_devices; 973 974 for (i = 0; i < topology_info_input->num_nodes; i++) { 975 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 976 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 977 topology_info_input->nodes[i].is_sharing_enabled = 1; 978 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 979 } 980 981 /* Invoke xgmi ta to set topology information */ 982 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 983 } 984 985 // ras begin 986 static int psp_ras_init_shared_buf(struct psp_context *psp) 987 { 988 int ret; 989 990 /* 991 * Allocate 16k memory aligned to 4k from Frame Buffer (local 992 * physical) for ras ta <-> Driver 993 */ 994 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 995 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 996 &psp->ras.ras_shared_bo, 997 &psp->ras.ras_shared_mc_addr, 998 &psp->ras.ras_shared_buf); 999 1000 return ret; 1001 } 1002 1003 static int psp_ras_load(struct psp_context *psp) 1004 { 1005 int ret; 1006 struct psp_gfx_cmd_resp *cmd; 1007 struct ta_ras_shared_memory *ras_cmd; 1008 1009 /* 1010 * TODO: bypass the loading in sriov for now 1011 */ 1012 if (amdgpu_sriov_vf(psp->adev)) 1013 return 0; 1014 1015 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1016 if (!cmd) 1017 return -ENOMEM; 1018 1019 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1020 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 1021 1022 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1023 1024 if (psp->adev->gmc.xgmi.connected_to_cpu) 1025 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1026 else 1027 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1028 1029 psp_prep_ta_load_cmd_buf(cmd, 1030 psp->fw_pri_mc_addr, 1031 psp->ta_ras_ucode_size, 1032 psp->ras.ras_shared_mc_addr, 1033 PSP_RAS_SHARED_MEM_SIZE); 1034 1035 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1036 psp->fence_buf_mc_addr); 1037 1038 if (!ret) { 1039 psp->ras.session_id = cmd->resp.session_id; 1040 1041 if (!ras_cmd->ras_status) 1042 psp->ras.ras_initialized = true; 1043 else 1044 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1045 } 1046 1047 if (ret || ras_cmd->ras_status) 1048 amdgpu_ras_fini(psp->adev); 1049 1050 kfree(cmd); 1051 1052 return ret; 1053 } 1054 1055 static int psp_ras_unload(struct psp_context *psp) 1056 { 1057 int ret; 1058 struct psp_gfx_cmd_resp *cmd; 1059 1060 /* 1061 * TODO: bypass the unloading in sriov for now 1062 */ 1063 if (amdgpu_sriov_vf(psp->adev)) 1064 return 0; 1065 1066 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1067 if (!cmd) 1068 return -ENOMEM; 1069 1070 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 1071 1072 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1073 psp->fence_buf_mc_addr); 1074 1075 kfree(cmd); 1076 1077 return ret; 1078 } 1079 1080 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1081 { 1082 struct ta_ras_shared_memory *ras_cmd; 1083 int ret; 1084 1085 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1086 1087 /* 1088 * TODO: bypass the loading in sriov for now 1089 */ 1090 if (amdgpu_sriov_vf(psp->adev)) 1091 return 0; 1092 1093 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 1094 1095 if (amdgpu_ras_intr_triggered()) 1096 return ret; 1097 1098 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1099 { 1100 DRM_WARN("RAS: Unsupported Interface"); 1101 return -EINVAL; 1102 } 1103 1104 if (!ret) { 1105 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1106 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1107 1108 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1109 } 1110 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1111 dev_warn(psp->adev->dev, 1112 "RAS internal register access blocked\n"); 1113 } 1114 1115 return ret; 1116 } 1117 1118 static int psp_ras_status_to_errno(struct amdgpu_device *adev, 1119 enum ta_ras_status ras_status) 1120 { 1121 int ret = -EINVAL; 1122 1123 switch (ras_status) { 1124 case TA_RAS_STATUS__SUCCESS: 1125 ret = 0; 1126 break; 1127 case TA_RAS_STATUS__RESET_NEEDED: 1128 ret = -EAGAIN; 1129 break; 1130 case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: 1131 dev_warn(adev->dev, "RAS WARN: ras function unavailable\n"); 1132 break; 1133 case TA_RAS_STATUS__ERROR_ASD_READ_WRITE: 1134 dev_warn(adev->dev, "RAS WARN: asd read or write failed\n"); 1135 break; 1136 default: 1137 dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret); 1138 } 1139 1140 return ret; 1141 } 1142 1143 int psp_ras_enable_features(struct psp_context *psp, 1144 union ta_ras_cmd_input *info, bool enable) 1145 { 1146 struct ta_ras_shared_memory *ras_cmd; 1147 int ret; 1148 1149 if (!psp->ras.ras_initialized) 1150 return -EINVAL; 1151 1152 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1153 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1154 1155 if (enable) 1156 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1157 else 1158 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1159 1160 ras_cmd->ras_in_message = *info; 1161 1162 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1163 if (ret) 1164 return -EINVAL; 1165 1166 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1167 } 1168 1169 static int psp_ras_terminate(struct psp_context *psp) 1170 { 1171 int ret; 1172 1173 /* 1174 * TODO: bypass the terminate in sriov for now 1175 */ 1176 if (amdgpu_sriov_vf(psp->adev)) 1177 return 0; 1178 1179 if (!psp->ras.ras_initialized) 1180 return 0; 1181 1182 ret = psp_ras_unload(psp); 1183 if (ret) 1184 return ret; 1185 1186 psp->ras.ras_initialized = false; 1187 1188 /* free ras shared memory */ 1189 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1190 &psp->ras.ras_shared_mc_addr, 1191 &psp->ras.ras_shared_buf); 1192 1193 return 0; 1194 } 1195 1196 static int psp_ras_initialize(struct psp_context *psp) 1197 { 1198 int ret; 1199 1200 /* 1201 * TODO: bypass the initialize in sriov for now 1202 */ 1203 if (amdgpu_sriov_vf(psp->adev)) 1204 return 0; 1205 1206 if (!psp->adev->psp.ta_ras_ucode_size || 1207 !psp->adev->psp.ta_ras_start_addr) { 1208 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n"); 1209 return 0; 1210 } 1211 1212 if (!psp->ras.ras_initialized) { 1213 ret = psp_ras_init_shared_buf(psp); 1214 if (ret) 1215 return ret; 1216 } 1217 1218 ret = psp_ras_load(psp); 1219 if (ret) 1220 return ret; 1221 1222 return 0; 1223 } 1224 1225 int psp_ras_trigger_error(struct psp_context *psp, 1226 struct ta_ras_trigger_error_input *info) 1227 { 1228 struct ta_ras_shared_memory *ras_cmd; 1229 int ret; 1230 1231 if (!psp->ras.ras_initialized) 1232 return -EINVAL; 1233 1234 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1235 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1236 1237 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1238 ras_cmd->ras_in_message.trigger_error = *info; 1239 1240 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1241 if (ret) 1242 return -EINVAL; 1243 1244 /* If err_event_athub occurs error inject was successful, however 1245 return status from TA is no long reliable */ 1246 if (amdgpu_ras_intr_triggered()) 1247 return 0; 1248 1249 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1250 } 1251 // ras end 1252 1253 // HDCP start 1254 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1255 { 1256 int ret; 1257 1258 /* 1259 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1260 * physical) for hdcp ta <-> Driver 1261 */ 1262 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1263 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1264 &psp->hdcp_context.hdcp_shared_bo, 1265 &psp->hdcp_context.hdcp_shared_mc_addr, 1266 &psp->hdcp_context.hdcp_shared_buf); 1267 1268 return ret; 1269 } 1270 1271 static int psp_hdcp_load(struct psp_context *psp) 1272 { 1273 int ret; 1274 struct psp_gfx_cmd_resp *cmd; 1275 1276 /* 1277 * TODO: bypass the loading in sriov for now 1278 */ 1279 if (amdgpu_sriov_vf(psp->adev)) 1280 return 0; 1281 1282 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1283 if (!cmd) 1284 return -ENOMEM; 1285 1286 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1287 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr, 1288 psp->ta_hdcp_ucode_size); 1289 1290 psp_prep_ta_load_cmd_buf(cmd, 1291 psp->fw_pri_mc_addr, 1292 psp->ta_hdcp_ucode_size, 1293 psp->hdcp_context.hdcp_shared_mc_addr, 1294 PSP_HDCP_SHARED_MEM_SIZE); 1295 1296 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1297 1298 if (!ret) { 1299 psp->hdcp_context.hdcp_initialized = true; 1300 psp->hdcp_context.session_id = cmd->resp.session_id; 1301 mutex_init(&psp->hdcp_context.mutex); 1302 } 1303 1304 kfree(cmd); 1305 1306 return ret; 1307 } 1308 static int psp_hdcp_initialize(struct psp_context *psp) 1309 { 1310 int ret; 1311 1312 /* 1313 * TODO: bypass the initialize in sriov for now 1314 */ 1315 if (amdgpu_sriov_vf(psp->adev)) 1316 return 0; 1317 1318 if (!psp->adev->psp.ta_hdcp_ucode_size || 1319 !psp->adev->psp.ta_hdcp_start_addr) { 1320 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1321 return 0; 1322 } 1323 1324 if (!psp->hdcp_context.hdcp_initialized) { 1325 ret = psp_hdcp_init_shared_buf(psp); 1326 if (ret) 1327 return ret; 1328 } 1329 1330 ret = psp_hdcp_load(psp); 1331 if (ret) 1332 return ret; 1333 1334 return 0; 1335 } 1336 1337 static int psp_hdcp_unload(struct psp_context *psp) 1338 { 1339 int ret; 1340 struct psp_gfx_cmd_resp *cmd; 1341 1342 /* 1343 * TODO: bypass the unloading in sriov for now 1344 */ 1345 if (amdgpu_sriov_vf(psp->adev)) 1346 return 0; 1347 1348 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1349 if (!cmd) 1350 return -ENOMEM; 1351 1352 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1353 1354 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1355 1356 kfree(cmd); 1357 1358 return ret; 1359 } 1360 1361 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1362 { 1363 /* 1364 * TODO: bypass the loading in sriov for now 1365 */ 1366 if (amdgpu_sriov_vf(psp->adev)) 1367 return 0; 1368 1369 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1370 } 1371 1372 static int psp_hdcp_terminate(struct psp_context *psp) 1373 { 1374 int ret; 1375 1376 /* 1377 * TODO: bypass the terminate in sriov for now 1378 */ 1379 if (amdgpu_sriov_vf(psp->adev)) 1380 return 0; 1381 1382 if (!psp->hdcp_context.hdcp_initialized) { 1383 if (psp->hdcp_context.hdcp_shared_buf) 1384 goto out; 1385 else 1386 return 0; 1387 } 1388 1389 ret = psp_hdcp_unload(psp); 1390 if (ret) 1391 return ret; 1392 1393 psp->hdcp_context.hdcp_initialized = false; 1394 1395 out: 1396 /* free hdcp shared memory */ 1397 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1398 &psp->hdcp_context.hdcp_shared_mc_addr, 1399 &psp->hdcp_context.hdcp_shared_buf); 1400 1401 return 0; 1402 } 1403 // HDCP end 1404 1405 // DTM start 1406 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1407 { 1408 int ret; 1409 1410 /* 1411 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1412 * physical) for dtm ta <-> Driver 1413 */ 1414 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1415 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1416 &psp->dtm_context.dtm_shared_bo, 1417 &psp->dtm_context.dtm_shared_mc_addr, 1418 &psp->dtm_context.dtm_shared_buf); 1419 1420 return ret; 1421 } 1422 1423 static int psp_dtm_load(struct psp_context *psp) 1424 { 1425 int ret; 1426 struct psp_gfx_cmd_resp *cmd; 1427 1428 /* 1429 * TODO: bypass the loading in sriov for now 1430 */ 1431 if (amdgpu_sriov_vf(psp->adev)) 1432 return 0; 1433 1434 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1435 if (!cmd) 1436 return -ENOMEM; 1437 1438 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1439 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1440 1441 psp_prep_ta_load_cmd_buf(cmd, 1442 psp->fw_pri_mc_addr, 1443 psp->ta_dtm_ucode_size, 1444 psp->dtm_context.dtm_shared_mc_addr, 1445 PSP_DTM_SHARED_MEM_SIZE); 1446 1447 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1448 1449 if (!ret) { 1450 psp->dtm_context.dtm_initialized = true; 1451 psp->dtm_context.session_id = cmd->resp.session_id; 1452 mutex_init(&psp->dtm_context.mutex); 1453 } 1454 1455 kfree(cmd); 1456 1457 return ret; 1458 } 1459 1460 static int psp_dtm_initialize(struct psp_context *psp) 1461 { 1462 int ret; 1463 1464 /* 1465 * TODO: bypass the initialize in sriov for now 1466 */ 1467 if (amdgpu_sriov_vf(psp->adev)) 1468 return 0; 1469 1470 if (!psp->adev->psp.ta_dtm_ucode_size || 1471 !psp->adev->psp.ta_dtm_start_addr) { 1472 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1473 return 0; 1474 } 1475 1476 if (!psp->dtm_context.dtm_initialized) { 1477 ret = psp_dtm_init_shared_buf(psp); 1478 if (ret) 1479 return ret; 1480 } 1481 1482 ret = psp_dtm_load(psp); 1483 if (ret) 1484 return ret; 1485 1486 return 0; 1487 } 1488 1489 static int psp_dtm_unload(struct psp_context *psp) 1490 { 1491 int ret; 1492 struct psp_gfx_cmd_resp *cmd; 1493 1494 /* 1495 * TODO: bypass the unloading in sriov for now 1496 */ 1497 if (amdgpu_sriov_vf(psp->adev)) 1498 return 0; 1499 1500 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1501 if (!cmd) 1502 return -ENOMEM; 1503 1504 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1505 1506 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1507 1508 kfree(cmd); 1509 1510 return ret; 1511 } 1512 1513 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1514 { 1515 /* 1516 * TODO: bypass the loading in sriov for now 1517 */ 1518 if (amdgpu_sriov_vf(psp->adev)) 1519 return 0; 1520 1521 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1522 } 1523 1524 static int psp_dtm_terminate(struct psp_context *psp) 1525 { 1526 int ret; 1527 1528 /* 1529 * TODO: bypass the terminate in sriov for now 1530 */ 1531 if (amdgpu_sriov_vf(psp->adev)) 1532 return 0; 1533 1534 if (!psp->dtm_context.dtm_initialized) { 1535 if (psp->dtm_context.dtm_shared_buf) 1536 goto out; 1537 else 1538 return 0; 1539 } 1540 1541 ret = psp_dtm_unload(psp); 1542 if (ret) 1543 return ret; 1544 1545 psp->dtm_context.dtm_initialized = false; 1546 1547 out: 1548 /* free hdcp shared memory */ 1549 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1550 &psp->dtm_context.dtm_shared_mc_addr, 1551 &psp->dtm_context.dtm_shared_buf); 1552 1553 return 0; 1554 } 1555 // DTM end 1556 1557 // RAP start 1558 static int psp_rap_init_shared_buf(struct psp_context *psp) 1559 { 1560 int ret; 1561 1562 /* 1563 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1564 * physical) for rap ta <-> Driver 1565 */ 1566 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE, 1567 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1568 &psp->rap_context.rap_shared_bo, 1569 &psp->rap_context.rap_shared_mc_addr, 1570 &psp->rap_context.rap_shared_buf); 1571 1572 return ret; 1573 } 1574 1575 static int psp_rap_load(struct psp_context *psp) 1576 { 1577 int ret; 1578 struct psp_gfx_cmd_resp *cmd; 1579 1580 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1581 if (!cmd) 1582 return -ENOMEM; 1583 1584 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1585 memcpy(psp->fw_pri_buf, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); 1586 1587 psp_prep_ta_load_cmd_buf(cmd, 1588 psp->fw_pri_mc_addr, 1589 psp->ta_rap_ucode_size, 1590 psp->rap_context.rap_shared_mc_addr, 1591 PSP_RAP_SHARED_MEM_SIZE); 1592 1593 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1594 1595 if (!ret) { 1596 psp->rap_context.rap_initialized = true; 1597 psp->rap_context.session_id = cmd->resp.session_id; 1598 mutex_init(&psp->rap_context.mutex); 1599 } 1600 1601 kfree(cmd); 1602 1603 return ret; 1604 } 1605 1606 static int psp_rap_unload(struct psp_context *psp) 1607 { 1608 int ret; 1609 struct psp_gfx_cmd_resp *cmd; 1610 1611 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1612 if (!cmd) 1613 return -ENOMEM; 1614 1615 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id); 1616 1617 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1618 1619 kfree(cmd); 1620 1621 return ret; 1622 } 1623 1624 static int psp_rap_initialize(struct psp_context *psp) 1625 { 1626 int ret; 1627 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1628 1629 /* 1630 * TODO: bypass the initialize in sriov for now 1631 */ 1632 if (amdgpu_sriov_vf(psp->adev)) 1633 return 0; 1634 1635 if (!psp->adev->psp.ta_rap_ucode_size || 1636 !psp->adev->psp.ta_rap_start_addr) { 1637 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1638 return 0; 1639 } 1640 1641 if (!psp->rap_context.rap_initialized) { 1642 ret = psp_rap_init_shared_buf(psp); 1643 if (ret) 1644 return ret; 1645 } 1646 1647 ret = psp_rap_load(psp); 1648 if (ret) 1649 return ret; 1650 1651 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1652 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1653 psp_rap_unload(psp); 1654 1655 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1656 &psp->rap_context.rap_shared_mc_addr, 1657 &psp->rap_context.rap_shared_buf); 1658 1659 psp->rap_context.rap_initialized = false; 1660 1661 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1662 ret, status); 1663 1664 return ret; 1665 } 1666 1667 return 0; 1668 } 1669 1670 static int psp_rap_terminate(struct psp_context *psp) 1671 { 1672 int ret; 1673 1674 if (!psp->rap_context.rap_initialized) 1675 return 0; 1676 1677 ret = psp_rap_unload(psp); 1678 1679 psp->rap_context.rap_initialized = false; 1680 1681 /* free rap shared memory */ 1682 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1683 &psp->rap_context.rap_shared_mc_addr, 1684 &psp->rap_context.rap_shared_buf); 1685 1686 return ret; 1687 } 1688 1689 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1690 { 1691 struct ta_rap_shared_memory *rap_cmd; 1692 int ret = 0; 1693 1694 if (!psp->rap_context.rap_initialized) 1695 return 0; 1696 1697 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1698 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1699 return -EINVAL; 1700 1701 mutex_lock(&psp->rap_context.mutex); 1702 1703 rap_cmd = (struct ta_rap_shared_memory *) 1704 psp->rap_context.rap_shared_buf; 1705 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1706 1707 rap_cmd->cmd_id = ta_cmd_id; 1708 rap_cmd->validation_method_id = METHOD_A; 1709 1710 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id); 1711 if (ret) 1712 goto out_unlock; 1713 1714 if (status) 1715 *status = rap_cmd->rap_status; 1716 1717 out_unlock: 1718 mutex_unlock(&psp->rap_context.mutex); 1719 1720 return ret; 1721 } 1722 // RAP end 1723 1724 /* securedisplay start */ 1725 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1726 { 1727 int ret; 1728 1729 /* 1730 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1731 * physical) for sa ta <-> Driver 1732 */ 1733 ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE, 1734 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1735 &psp->securedisplay_context.securedisplay_shared_bo, 1736 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1737 &psp->securedisplay_context.securedisplay_shared_buf); 1738 1739 return ret; 1740 } 1741 1742 static int psp_securedisplay_load(struct psp_context *psp) 1743 { 1744 int ret; 1745 struct psp_gfx_cmd_resp *cmd; 1746 1747 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1748 if (!cmd) 1749 return -ENOMEM; 1750 1751 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1752 memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size); 1753 1754 psp_prep_ta_load_cmd_buf(cmd, 1755 psp->fw_pri_mc_addr, 1756 psp->ta_securedisplay_ucode_size, 1757 psp->securedisplay_context.securedisplay_shared_mc_addr, 1758 PSP_SECUREDISPLAY_SHARED_MEM_SIZE); 1759 1760 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1761 1762 if (ret) 1763 goto failed; 1764 1765 psp->securedisplay_context.securedisplay_initialized = true; 1766 psp->securedisplay_context.session_id = cmd->resp.session_id; 1767 mutex_init(&psp->securedisplay_context.mutex); 1768 1769 failed: 1770 kfree(cmd); 1771 return ret; 1772 } 1773 1774 static int psp_securedisplay_unload(struct psp_context *psp) 1775 { 1776 int ret; 1777 struct psp_gfx_cmd_resp *cmd; 1778 1779 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1780 if (!cmd) 1781 return -ENOMEM; 1782 1783 psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id); 1784 1785 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1786 1787 kfree(cmd); 1788 1789 return ret; 1790 } 1791 1792 static int psp_securedisplay_initialize(struct psp_context *psp) 1793 { 1794 int ret; 1795 struct securedisplay_cmd *securedisplay_cmd; 1796 1797 /* 1798 * TODO: bypass the initialize in sriov for now 1799 */ 1800 if (amdgpu_sriov_vf(psp->adev)) 1801 return 0; 1802 1803 if (!psp->adev->psp.ta_securedisplay_ucode_size || 1804 !psp->adev->psp.ta_securedisplay_start_addr) { 1805 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1806 return 0; 1807 } 1808 1809 if (!psp->securedisplay_context.securedisplay_initialized) { 1810 ret = psp_securedisplay_init_shared_buf(psp); 1811 if (ret) 1812 return ret; 1813 } 1814 1815 ret = psp_securedisplay_load(psp); 1816 if (ret) 1817 return ret; 1818 1819 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1820 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1821 1822 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1823 if (ret) { 1824 psp_securedisplay_unload(psp); 1825 1826 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 1827 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1828 &psp->securedisplay_context.securedisplay_shared_buf); 1829 1830 psp->securedisplay_context.securedisplay_initialized = false; 1831 1832 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1833 return -EINVAL; 1834 } 1835 1836 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1837 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1838 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1839 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1840 } 1841 1842 return 0; 1843 } 1844 1845 static int psp_securedisplay_terminate(struct psp_context *psp) 1846 { 1847 int ret; 1848 1849 /* 1850 * TODO:bypass the terminate in sriov for now 1851 */ 1852 if (amdgpu_sriov_vf(psp->adev)) 1853 return 0; 1854 1855 if (!psp->securedisplay_context.securedisplay_initialized) 1856 return 0; 1857 1858 ret = psp_securedisplay_unload(psp); 1859 if (ret) 1860 return ret; 1861 1862 psp->securedisplay_context.securedisplay_initialized = false; 1863 1864 /* free securedisplay shared memory */ 1865 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 1866 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1867 &psp->securedisplay_context.securedisplay_shared_buf); 1868 1869 return ret; 1870 } 1871 1872 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1873 { 1874 int ret; 1875 1876 if (!psp->securedisplay_context.securedisplay_initialized) 1877 return -EINVAL; 1878 1879 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1880 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1881 return -EINVAL; 1882 1883 mutex_lock(&psp->securedisplay_context.mutex); 1884 1885 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id); 1886 1887 mutex_unlock(&psp->securedisplay_context.mutex); 1888 1889 return ret; 1890 } 1891 /* SECUREDISPLAY end */ 1892 1893 static int psp_hw_start(struct psp_context *psp) 1894 { 1895 struct amdgpu_device *adev = psp->adev; 1896 int ret; 1897 1898 if (!amdgpu_sriov_vf(adev)) { 1899 if (psp->kdb_bin_size && 1900 (psp->funcs->bootloader_load_kdb != NULL)) { 1901 ret = psp_bootloader_load_kdb(psp); 1902 if (ret) { 1903 DRM_ERROR("PSP load kdb failed!\n"); 1904 return ret; 1905 } 1906 } 1907 1908 if (psp->spl_bin_size) { 1909 ret = psp_bootloader_load_spl(psp); 1910 if (ret) { 1911 DRM_ERROR("PSP load spl failed!\n"); 1912 return ret; 1913 } 1914 } 1915 1916 ret = psp_bootloader_load_sysdrv(psp); 1917 if (ret) { 1918 DRM_ERROR("PSP load sysdrv failed!\n"); 1919 return ret; 1920 } 1921 1922 ret = psp_bootloader_load_sos(psp); 1923 if (ret) { 1924 DRM_ERROR("PSP load sos failed!\n"); 1925 return ret; 1926 } 1927 } 1928 1929 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1930 if (ret) { 1931 DRM_ERROR("PSP create ring failed!\n"); 1932 return ret; 1933 } 1934 1935 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1936 ret = psp_boot_config_set(adev); 1937 if (ret) 1938 dev_warn(adev->dev, "PSP set boot config failed\n"); 1939 } 1940 1941 ret = psp_tmr_init(psp); 1942 if (ret) { 1943 DRM_ERROR("PSP tmr init failed!\n"); 1944 return ret; 1945 } 1946 1947 /* 1948 * For ASICs with DF Cstate management centralized 1949 * to PMFW, TMR setup should be performed after PMFW 1950 * loaded and before other non-psp firmware loaded. 1951 */ 1952 if (psp->pmfw_centralized_cstate_management) { 1953 ret = psp_load_smu_fw(psp); 1954 if (ret) 1955 return ret; 1956 } 1957 1958 ret = psp_tmr_load(psp); 1959 if (ret) { 1960 DRM_ERROR("PSP load tmr failed!\n"); 1961 return ret; 1962 } 1963 1964 return 0; 1965 } 1966 1967 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 1968 enum psp_gfx_fw_type *type) 1969 { 1970 switch (ucode->ucode_id) { 1971 case AMDGPU_UCODE_ID_SDMA0: 1972 *type = GFX_FW_TYPE_SDMA0; 1973 break; 1974 case AMDGPU_UCODE_ID_SDMA1: 1975 *type = GFX_FW_TYPE_SDMA1; 1976 break; 1977 case AMDGPU_UCODE_ID_SDMA2: 1978 *type = GFX_FW_TYPE_SDMA2; 1979 break; 1980 case AMDGPU_UCODE_ID_SDMA3: 1981 *type = GFX_FW_TYPE_SDMA3; 1982 break; 1983 case AMDGPU_UCODE_ID_SDMA4: 1984 *type = GFX_FW_TYPE_SDMA4; 1985 break; 1986 case AMDGPU_UCODE_ID_SDMA5: 1987 *type = GFX_FW_TYPE_SDMA5; 1988 break; 1989 case AMDGPU_UCODE_ID_SDMA6: 1990 *type = GFX_FW_TYPE_SDMA6; 1991 break; 1992 case AMDGPU_UCODE_ID_SDMA7: 1993 *type = GFX_FW_TYPE_SDMA7; 1994 break; 1995 case AMDGPU_UCODE_ID_CP_MES: 1996 *type = GFX_FW_TYPE_CP_MES; 1997 break; 1998 case AMDGPU_UCODE_ID_CP_MES_DATA: 1999 *type = GFX_FW_TYPE_MES_STACK; 2000 break; 2001 case AMDGPU_UCODE_ID_CP_CE: 2002 *type = GFX_FW_TYPE_CP_CE; 2003 break; 2004 case AMDGPU_UCODE_ID_CP_PFP: 2005 *type = GFX_FW_TYPE_CP_PFP; 2006 break; 2007 case AMDGPU_UCODE_ID_CP_ME: 2008 *type = GFX_FW_TYPE_CP_ME; 2009 break; 2010 case AMDGPU_UCODE_ID_CP_MEC1: 2011 *type = GFX_FW_TYPE_CP_MEC; 2012 break; 2013 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2014 *type = GFX_FW_TYPE_CP_MEC_ME1; 2015 break; 2016 case AMDGPU_UCODE_ID_CP_MEC2: 2017 *type = GFX_FW_TYPE_CP_MEC; 2018 break; 2019 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2020 *type = GFX_FW_TYPE_CP_MEC_ME2; 2021 break; 2022 case AMDGPU_UCODE_ID_RLC_G: 2023 *type = GFX_FW_TYPE_RLC_G; 2024 break; 2025 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2026 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2027 break; 2028 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2029 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2030 break; 2031 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2032 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2033 break; 2034 case AMDGPU_UCODE_ID_RLC_IRAM: 2035 *type = GFX_FW_TYPE_RLC_IRAM; 2036 break; 2037 case AMDGPU_UCODE_ID_RLC_DRAM: 2038 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2039 break; 2040 case AMDGPU_UCODE_ID_SMC: 2041 *type = GFX_FW_TYPE_SMU; 2042 break; 2043 case AMDGPU_UCODE_ID_UVD: 2044 *type = GFX_FW_TYPE_UVD; 2045 break; 2046 case AMDGPU_UCODE_ID_UVD1: 2047 *type = GFX_FW_TYPE_UVD1; 2048 break; 2049 case AMDGPU_UCODE_ID_VCE: 2050 *type = GFX_FW_TYPE_VCE; 2051 break; 2052 case AMDGPU_UCODE_ID_VCN: 2053 *type = GFX_FW_TYPE_VCN; 2054 break; 2055 case AMDGPU_UCODE_ID_VCN1: 2056 *type = GFX_FW_TYPE_VCN1; 2057 break; 2058 case AMDGPU_UCODE_ID_DMCU_ERAM: 2059 *type = GFX_FW_TYPE_DMCU_ERAM; 2060 break; 2061 case AMDGPU_UCODE_ID_DMCU_INTV: 2062 *type = GFX_FW_TYPE_DMCU_ISR; 2063 break; 2064 case AMDGPU_UCODE_ID_VCN0_RAM: 2065 *type = GFX_FW_TYPE_VCN0_RAM; 2066 break; 2067 case AMDGPU_UCODE_ID_VCN1_RAM: 2068 *type = GFX_FW_TYPE_VCN1_RAM; 2069 break; 2070 case AMDGPU_UCODE_ID_DMCUB: 2071 *type = GFX_FW_TYPE_DMUB; 2072 break; 2073 case AMDGPU_UCODE_ID_MAXIMUM: 2074 default: 2075 return -EINVAL; 2076 } 2077 2078 return 0; 2079 } 2080 2081 static void psp_print_fw_hdr(struct psp_context *psp, 2082 struct amdgpu_firmware_info *ucode) 2083 { 2084 struct amdgpu_device *adev = psp->adev; 2085 struct common_firmware_header *hdr; 2086 2087 switch (ucode->ucode_id) { 2088 case AMDGPU_UCODE_ID_SDMA0: 2089 case AMDGPU_UCODE_ID_SDMA1: 2090 case AMDGPU_UCODE_ID_SDMA2: 2091 case AMDGPU_UCODE_ID_SDMA3: 2092 case AMDGPU_UCODE_ID_SDMA4: 2093 case AMDGPU_UCODE_ID_SDMA5: 2094 case AMDGPU_UCODE_ID_SDMA6: 2095 case AMDGPU_UCODE_ID_SDMA7: 2096 hdr = (struct common_firmware_header *) 2097 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2098 amdgpu_ucode_print_sdma_hdr(hdr); 2099 break; 2100 case AMDGPU_UCODE_ID_CP_CE: 2101 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2102 amdgpu_ucode_print_gfx_hdr(hdr); 2103 break; 2104 case AMDGPU_UCODE_ID_CP_PFP: 2105 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2106 amdgpu_ucode_print_gfx_hdr(hdr); 2107 break; 2108 case AMDGPU_UCODE_ID_CP_ME: 2109 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2110 amdgpu_ucode_print_gfx_hdr(hdr); 2111 break; 2112 case AMDGPU_UCODE_ID_CP_MEC1: 2113 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2114 amdgpu_ucode_print_gfx_hdr(hdr); 2115 break; 2116 case AMDGPU_UCODE_ID_RLC_G: 2117 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2118 amdgpu_ucode_print_rlc_hdr(hdr); 2119 break; 2120 case AMDGPU_UCODE_ID_SMC: 2121 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2122 amdgpu_ucode_print_smc_hdr(hdr); 2123 break; 2124 default: 2125 break; 2126 } 2127 } 2128 2129 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2130 struct psp_gfx_cmd_resp *cmd) 2131 { 2132 int ret; 2133 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2134 2135 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 2136 2137 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2138 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2139 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2140 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2141 2142 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2143 if (ret) 2144 DRM_ERROR("Unknown firmware type\n"); 2145 2146 return ret; 2147 } 2148 2149 static int psp_execute_np_fw_load(struct psp_context *psp, 2150 struct amdgpu_firmware_info *ucode) 2151 { 2152 int ret = 0; 2153 2154 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 2155 if (ret) 2156 return ret; 2157 2158 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 2159 psp->fence_buf_mc_addr); 2160 2161 return ret; 2162 } 2163 2164 static int psp_load_smu_fw(struct psp_context *psp) 2165 { 2166 int ret; 2167 struct amdgpu_device *adev = psp->adev; 2168 struct amdgpu_firmware_info *ucode = 2169 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2170 struct amdgpu_ras *ras = psp->ras.ras; 2171 2172 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2173 return 0; 2174 2175 if ((amdgpu_in_reset(adev) && 2176 ras && adev->ras_enabled && 2177 (adev->asic_type == CHIP_ARCTURUS || 2178 adev->asic_type == CHIP_VEGA20)) || 2179 (adev->in_runpm && 2180 adev->asic_type >= CHIP_NAVI10 && 2181 adev->asic_type <= CHIP_NAVI12)) { 2182 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2183 if (ret) { 2184 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2185 } 2186 } 2187 2188 ret = psp_execute_np_fw_load(psp, ucode); 2189 2190 if (ret) 2191 DRM_ERROR("PSP load smu failed!\n"); 2192 2193 return ret; 2194 } 2195 2196 static bool fw_load_skip_check(struct psp_context *psp, 2197 struct amdgpu_firmware_info *ucode) 2198 { 2199 if (!ucode->fw) 2200 return true; 2201 2202 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2203 (psp_smu_reload_quirk(psp) || 2204 psp->autoload_supported || 2205 psp->pmfw_centralized_cstate_management)) 2206 return true; 2207 2208 if (amdgpu_sriov_vf(psp->adev) && 2209 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2210 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2211 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2212 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2213 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2214 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2215 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2216 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2217 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2218 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2219 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2220 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2221 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2222 /*skip ucode loading in SRIOV VF */ 2223 return true; 2224 2225 if (psp->autoload_supported && 2226 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2227 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2228 /* skip mec JT when autoload is enabled */ 2229 return true; 2230 2231 return false; 2232 } 2233 2234 int psp_load_fw_list(struct psp_context *psp, 2235 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2236 { 2237 int ret = 0, i; 2238 struct amdgpu_firmware_info *ucode; 2239 2240 for (i = 0; i < ucode_count; ++i) { 2241 ucode = ucode_list[i]; 2242 psp_print_fw_hdr(psp, ucode); 2243 ret = psp_execute_np_fw_load(psp, ucode); 2244 if (ret) 2245 return ret; 2246 } 2247 return ret; 2248 } 2249 2250 static int psp_np_fw_load(struct psp_context *psp) 2251 { 2252 int i, ret; 2253 struct amdgpu_firmware_info *ucode; 2254 struct amdgpu_device *adev = psp->adev; 2255 2256 if (psp->autoload_supported && 2257 !psp->pmfw_centralized_cstate_management) { 2258 ret = psp_load_smu_fw(psp); 2259 if (ret) 2260 return ret; 2261 } 2262 2263 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2264 ucode = &adev->firmware.ucode[i]; 2265 2266 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2267 !fw_load_skip_check(psp, ucode)) { 2268 ret = psp_load_smu_fw(psp); 2269 if (ret) 2270 return ret; 2271 continue; 2272 } 2273 2274 if (fw_load_skip_check(psp, ucode)) 2275 continue; 2276 2277 if (psp->autoload_supported && 2278 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2279 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2280 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2281 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2282 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2283 /* PSP only receive one SDMA fw for sienna_cichlid, 2284 * as all four sdma fw are same */ 2285 continue; 2286 2287 psp_print_fw_hdr(psp, ucode); 2288 2289 ret = psp_execute_np_fw_load(psp, ucode); 2290 if (ret) 2291 return ret; 2292 2293 /* Start rlc autoload after psp recieved all the gfx firmware */ 2294 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2295 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2296 ret = psp_rlc_autoload_start(psp); 2297 if (ret) { 2298 DRM_ERROR("Failed to start rlc autoload\n"); 2299 return ret; 2300 } 2301 } 2302 } 2303 2304 return 0; 2305 } 2306 2307 static int psp_load_fw(struct amdgpu_device *adev) 2308 { 2309 int ret; 2310 struct psp_context *psp = &adev->psp; 2311 2312 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2313 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2314 goto skip_memalloc; 2315 } 2316 2317 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2318 if (!psp->cmd) 2319 return -ENOMEM; 2320 2321 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2322 AMDGPU_GEM_DOMAIN_GTT, 2323 &psp->fw_pri_bo, 2324 &psp->fw_pri_mc_addr, 2325 &psp->fw_pri_buf); 2326 if (ret) 2327 goto failed; 2328 2329 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2330 AMDGPU_GEM_DOMAIN_VRAM, 2331 &psp->fence_buf_bo, 2332 &psp->fence_buf_mc_addr, 2333 &psp->fence_buf); 2334 if (ret) 2335 goto failed; 2336 2337 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2338 AMDGPU_GEM_DOMAIN_VRAM, 2339 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2340 (void **)&psp->cmd_buf_mem); 2341 if (ret) 2342 goto failed; 2343 2344 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2345 2346 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2347 if (ret) { 2348 DRM_ERROR("PSP ring init failed!\n"); 2349 goto failed; 2350 } 2351 2352 skip_memalloc: 2353 ret = psp_hw_start(psp); 2354 if (ret) 2355 goto failed; 2356 2357 ret = psp_np_fw_load(psp); 2358 if (ret) 2359 goto failed; 2360 2361 ret = psp_asd_load(psp); 2362 if (ret) { 2363 DRM_ERROR("PSP load asd failed!\n"); 2364 return ret; 2365 } 2366 2367 ret = psp_rl_load(adev); 2368 if (ret) { 2369 DRM_ERROR("PSP load RL failed!\n"); 2370 return ret; 2371 } 2372 2373 if (psp->adev->psp.ta_fw) { 2374 ret = psp_ras_initialize(psp); 2375 if (ret) 2376 dev_err(psp->adev->dev, 2377 "RAS: Failed to initialize RAS\n"); 2378 2379 ret = psp_hdcp_initialize(psp); 2380 if (ret) 2381 dev_err(psp->adev->dev, 2382 "HDCP: Failed to initialize HDCP\n"); 2383 2384 ret = psp_dtm_initialize(psp); 2385 if (ret) 2386 dev_err(psp->adev->dev, 2387 "DTM: Failed to initialize DTM\n"); 2388 2389 ret = psp_rap_initialize(psp); 2390 if (ret) 2391 dev_err(psp->adev->dev, 2392 "RAP: Failed to initialize RAP\n"); 2393 2394 ret = psp_securedisplay_initialize(psp); 2395 if (ret) 2396 dev_err(psp->adev->dev, 2397 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2398 } 2399 2400 return 0; 2401 2402 failed: 2403 /* 2404 * all cleanup jobs (xgmi terminate, ras terminate, 2405 * ring destroy, cmd/fence/fw buffers destory, 2406 * psp->cmd destory) are delayed to psp_hw_fini 2407 */ 2408 return ret; 2409 } 2410 2411 static int psp_hw_init(void *handle) 2412 { 2413 int ret; 2414 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2415 2416 mutex_lock(&adev->firmware.mutex); 2417 /* 2418 * This sequence is just used on hw_init only once, no need on 2419 * resume. 2420 */ 2421 ret = amdgpu_ucode_init_bo(adev); 2422 if (ret) 2423 goto failed; 2424 2425 ret = psp_load_fw(adev); 2426 if (ret) { 2427 DRM_ERROR("PSP firmware loading failed\n"); 2428 goto failed; 2429 } 2430 2431 mutex_unlock(&adev->firmware.mutex); 2432 return 0; 2433 2434 failed: 2435 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2436 mutex_unlock(&adev->firmware.mutex); 2437 return -EINVAL; 2438 } 2439 2440 static int psp_hw_fini(void *handle) 2441 { 2442 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2443 struct psp_context *psp = &adev->psp; 2444 2445 if (psp->adev->psp.ta_fw) { 2446 psp_ras_terminate(psp); 2447 psp_securedisplay_terminate(psp); 2448 psp_rap_terminate(psp); 2449 psp_dtm_terminate(psp); 2450 psp_hdcp_terminate(psp); 2451 } 2452 2453 psp_asd_unload(psp); 2454 2455 psp_tmr_terminate(psp); 2456 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2457 2458 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2459 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2460 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2461 &psp->fence_buf_mc_addr, &psp->fence_buf); 2462 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2463 (void **)&psp->cmd_buf_mem); 2464 2465 kfree(psp->cmd); 2466 psp->cmd = NULL; 2467 2468 return 0; 2469 } 2470 2471 static int psp_suspend(void *handle) 2472 { 2473 int ret; 2474 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2475 struct psp_context *psp = &adev->psp; 2476 2477 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2478 psp->xgmi_context.initialized == 1) { 2479 ret = psp_xgmi_terminate(psp); 2480 if (ret) { 2481 DRM_ERROR("Failed to terminate xgmi ta\n"); 2482 return ret; 2483 } 2484 } 2485 2486 if (psp->adev->psp.ta_fw) { 2487 ret = psp_ras_terminate(psp); 2488 if (ret) { 2489 DRM_ERROR("Failed to terminate ras ta\n"); 2490 return ret; 2491 } 2492 ret = psp_hdcp_terminate(psp); 2493 if (ret) { 2494 DRM_ERROR("Failed to terminate hdcp ta\n"); 2495 return ret; 2496 } 2497 ret = psp_dtm_terminate(psp); 2498 if (ret) { 2499 DRM_ERROR("Failed to terminate dtm ta\n"); 2500 return ret; 2501 } 2502 ret = psp_rap_terminate(psp); 2503 if (ret) { 2504 DRM_ERROR("Failed to terminate rap ta\n"); 2505 return ret; 2506 } 2507 ret = psp_securedisplay_terminate(psp); 2508 if (ret) { 2509 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2510 return ret; 2511 } 2512 } 2513 2514 ret = psp_asd_unload(psp); 2515 if (ret) { 2516 DRM_ERROR("Failed to unload asd\n"); 2517 return ret; 2518 } 2519 2520 ret = psp_tmr_terminate(psp); 2521 if (ret) { 2522 DRM_ERROR("Failed to terminate tmr\n"); 2523 return ret; 2524 } 2525 2526 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2527 if (ret) { 2528 DRM_ERROR("PSP ring stop failed\n"); 2529 return ret; 2530 } 2531 2532 return 0; 2533 } 2534 2535 static int psp_resume(void *handle) 2536 { 2537 int ret; 2538 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2539 struct psp_context *psp = &adev->psp; 2540 2541 DRM_INFO("PSP is resuming...\n"); 2542 2543 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2544 if (ret) { 2545 DRM_ERROR("Failed to process memory training!\n"); 2546 return ret; 2547 } 2548 2549 mutex_lock(&adev->firmware.mutex); 2550 2551 ret = psp_hw_start(psp); 2552 if (ret) 2553 goto failed; 2554 2555 ret = psp_np_fw_load(psp); 2556 if (ret) 2557 goto failed; 2558 2559 ret = psp_asd_load(psp); 2560 if (ret) { 2561 DRM_ERROR("PSP load asd failed!\n"); 2562 goto failed; 2563 } 2564 2565 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2566 ret = psp_xgmi_initialize(psp); 2567 /* Warning the XGMI seesion initialize failure 2568 * Instead of stop driver initialization 2569 */ 2570 if (ret) 2571 dev_err(psp->adev->dev, 2572 "XGMI: Failed to initialize XGMI session\n"); 2573 } 2574 2575 if (psp->adev->psp.ta_fw) { 2576 ret = psp_ras_initialize(psp); 2577 if (ret) 2578 dev_err(psp->adev->dev, 2579 "RAS: Failed to initialize RAS\n"); 2580 2581 ret = psp_hdcp_initialize(psp); 2582 if (ret) 2583 dev_err(psp->adev->dev, 2584 "HDCP: Failed to initialize HDCP\n"); 2585 2586 ret = psp_dtm_initialize(psp); 2587 if (ret) 2588 dev_err(psp->adev->dev, 2589 "DTM: Failed to initialize DTM\n"); 2590 2591 ret = psp_rap_initialize(psp); 2592 if (ret) 2593 dev_err(psp->adev->dev, 2594 "RAP: Failed to initialize RAP\n"); 2595 2596 ret = psp_securedisplay_initialize(psp); 2597 if (ret) 2598 dev_err(psp->adev->dev, 2599 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2600 } 2601 2602 mutex_unlock(&adev->firmware.mutex); 2603 2604 return 0; 2605 2606 failed: 2607 DRM_ERROR("PSP resume failed\n"); 2608 mutex_unlock(&adev->firmware.mutex); 2609 return ret; 2610 } 2611 2612 int psp_gpu_reset(struct amdgpu_device *adev) 2613 { 2614 int ret; 2615 2616 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2617 return 0; 2618 2619 mutex_lock(&adev->psp.mutex); 2620 ret = psp_mode1_reset(&adev->psp); 2621 mutex_unlock(&adev->psp.mutex); 2622 2623 return ret; 2624 } 2625 2626 int psp_rlc_autoload_start(struct psp_context *psp) 2627 { 2628 int ret; 2629 struct psp_gfx_cmd_resp *cmd; 2630 2631 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2632 if (!cmd) 2633 return -ENOMEM; 2634 2635 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2636 2637 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2638 psp->fence_buf_mc_addr); 2639 kfree(cmd); 2640 return ret; 2641 } 2642 2643 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2644 uint64_t cmd_gpu_addr, int cmd_size) 2645 { 2646 struct amdgpu_firmware_info ucode = {0}; 2647 2648 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2649 AMDGPU_UCODE_ID_VCN0_RAM; 2650 ucode.mc_addr = cmd_gpu_addr; 2651 ucode.ucode_size = cmd_size; 2652 2653 return psp_execute_np_fw_load(&adev->psp, &ucode); 2654 } 2655 2656 int psp_ring_cmd_submit(struct psp_context *psp, 2657 uint64_t cmd_buf_mc_addr, 2658 uint64_t fence_mc_addr, 2659 int index) 2660 { 2661 unsigned int psp_write_ptr_reg = 0; 2662 struct psp_gfx_rb_frame *write_frame; 2663 struct psp_ring *ring = &psp->km_ring; 2664 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2665 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2666 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2667 struct amdgpu_device *adev = psp->adev; 2668 uint32_t ring_size_dw = ring->ring_size / 4; 2669 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2670 2671 /* KM (GPCOM) prepare write pointer */ 2672 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2673 2674 /* Update KM RB frame pointer to new frame */ 2675 /* write_frame ptr increments by size of rb_frame in bytes */ 2676 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2677 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2678 write_frame = ring_buffer_start; 2679 else 2680 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2681 /* Check invalid write_frame ptr address */ 2682 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2683 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2684 ring_buffer_start, ring_buffer_end, write_frame); 2685 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2686 return -EINVAL; 2687 } 2688 2689 /* Initialize KM RB frame */ 2690 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2691 2692 /* Update KM RB frame */ 2693 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2694 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2695 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2696 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2697 write_frame->fence_value = index; 2698 amdgpu_asic_flush_hdp(adev, NULL); 2699 2700 /* Update the write Pointer in DWORDs */ 2701 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2702 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2703 return 0; 2704 } 2705 2706 int psp_init_asd_microcode(struct psp_context *psp, 2707 const char *chip_name) 2708 { 2709 struct amdgpu_device *adev = psp->adev; 2710 char fw_name[PSP_FW_NAME_LEN]; 2711 const struct psp_firmware_header_v1_0 *asd_hdr; 2712 int err = 0; 2713 2714 if (!chip_name) { 2715 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2716 return -EINVAL; 2717 } 2718 2719 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2720 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2721 if (err) 2722 goto out; 2723 2724 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2725 if (err) 2726 goto out; 2727 2728 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2729 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2730 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 2731 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2732 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2733 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2734 return 0; 2735 out: 2736 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2737 release_firmware(adev->psp.asd_fw); 2738 adev->psp.asd_fw = NULL; 2739 return err; 2740 } 2741 2742 int psp_init_toc_microcode(struct psp_context *psp, 2743 const char *chip_name) 2744 { 2745 struct amdgpu_device *adev = psp->adev; 2746 char fw_name[30]; 2747 const struct psp_firmware_header_v1_0 *toc_hdr; 2748 int err = 0; 2749 2750 if (!chip_name) { 2751 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2752 return -EINVAL; 2753 } 2754 2755 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2756 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2757 if (err) 2758 goto out; 2759 2760 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2761 if (err) 2762 goto out; 2763 2764 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2765 adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2766 adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version); 2767 adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2768 adev->psp.toc_start_addr = (uint8_t *)toc_hdr + 2769 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2770 return 0; 2771 out: 2772 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2773 release_firmware(adev->psp.toc_fw); 2774 adev->psp.toc_fw = NULL; 2775 return err; 2776 } 2777 2778 int psp_init_sos_microcode(struct psp_context *psp, 2779 const char *chip_name) 2780 { 2781 struct amdgpu_device *adev = psp->adev; 2782 char fw_name[PSP_FW_NAME_LEN]; 2783 const struct psp_firmware_header_v1_0 *sos_hdr; 2784 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 2785 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 2786 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2787 int err = 0; 2788 2789 if (!chip_name) { 2790 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 2791 return -EINVAL; 2792 } 2793 2794 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 2795 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 2796 if (err) 2797 goto out; 2798 2799 err = amdgpu_ucode_validate(adev->psp.sos_fw); 2800 if (err) 2801 goto out; 2802 2803 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2804 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 2805 2806 switch (sos_hdr->header.header_version_major) { 2807 case 1: 2808 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 2809 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 2810 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 2811 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 2812 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 2813 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2814 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2815 le32_to_cpu(sos_hdr->sos_offset_bytes); 2816 if (sos_hdr->header.header_version_minor == 1) { 2817 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 2818 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 2819 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2820 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 2821 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); 2822 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2823 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); 2824 } 2825 if (sos_hdr->header.header_version_minor == 2) { 2826 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 2827 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); 2828 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2829 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); 2830 } 2831 if (sos_hdr->header.header_version_minor == 3) { 2832 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 2833 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes); 2834 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2835 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes); 2836 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes); 2837 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2838 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes); 2839 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes); 2840 adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2841 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes); 2842 adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl_size_bytes); 2843 adev->psp.rl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2844 le32_to_cpu(sos_hdr_v1_3->rl_offset_bytes); 2845 } 2846 break; 2847 default: 2848 dev_err(adev->dev, 2849 "unsupported psp sos firmware\n"); 2850 err = -EINVAL; 2851 goto out; 2852 } 2853 2854 return 0; 2855 out: 2856 dev_err(adev->dev, 2857 "failed to init sos firmware\n"); 2858 release_firmware(adev->psp.sos_fw); 2859 adev->psp.sos_fw = NULL; 2860 2861 return err; 2862 } 2863 2864 static int parse_ta_bin_descriptor(struct psp_context *psp, 2865 const struct ta_fw_bin_desc *desc, 2866 const struct ta_firmware_header_v2_0 *ta_hdr) 2867 { 2868 uint8_t *ucode_start_addr = NULL; 2869 2870 if (!psp || !desc || !ta_hdr) 2871 return -EINVAL; 2872 2873 ucode_start_addr = (uint8_t *)ta_hdr + 2874 le32_to_cpu(desc->offset_bytes) + 2875 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 2876 2877 switch (desc->fw_type) { 2878 case TA_FW_TYPE_PSP_ASD: 2879 psp->asd_fw_version = le32_to_cpu(desc->fw_version); 2880 psp->asd_feature_version = le32_to_cpu(desc->fw_version); 2881 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 2882 psp->asd_start_addr = ucode_start_addr; 2883 break; 2884 case TA_FW_TYPE_PSP_XGMI: 2885 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 2886 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 2887 psp->ta_xgmi_start_addr = ucode_start_addr; 2888 break; 2889 case TA_FW_TYPE_PSP_RAS: 2890 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 2891 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 2892 psp->ta_ras_start_addr = ucode_start_addr; 2893 break; 2894 case TA_FW_TYPE_PSP_HDCP: 2895 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 2896 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 2897 psp->ta_hdcp_start_addr = ucode_start_addr; 2898 break; 2899 case TA_FW_TYPE_PSP_DTM: 2900 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 2901 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 2902 psp->ta_dtm_start_addr = ucode_start_addr; 2903 break; 2904 case TA_FW_TYPE_PSP_RAP: 2905 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version); 2906 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes); 2907 psp->ta_rap_start_addr = ucode_start_addr; 2908 break; 2909 case TA_FW_TYPE_PSP_SECUREDISPLAY: 2910 psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version); 2911 psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes); 2912 psp->ta_securedisplay_start_addr = ucode_start_addr; 2913 break; 2914 default: 2915 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 2916 break; 2917 } 2918 2919 return 0; 2920 } 2921 2922 int psp_init_ta_microcode(struct psp_context *psp, 2923 const char *chip_name) 2924 { 2925 struct amdgpu_device *adev = psp->adev; 2926 char fw_name[PSP_FW_NAME_LEN]; 2927 const struct ta_firmware_header_v2_0 *ta_hdr; 2928 int err = 0; 2929 int ta_index = 0; 2930 2931 if (!chip_name) { 2932 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 2933 return -EINVAL; 2934 } 2935 2936 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 2937 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 2938 if (err) 2939 goto out; 2940 2941 err = amdgpu_ucode_validate(adev->psp.ta_fw); 2942 if (err) 2943 goto out; 2944 2945 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 2946 2947 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 2948 dev_err(adev->dev, "unsupported TA header version\n"); 2949 err = -EINVAL; 2950 goto out; 2951 } 2952 2953 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) { 2954 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 2955 err = -EINVAL; 2956 goto out; 2957 } 2958 2959 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 2960 err = parse_ta_bin_descriptor(psp, 2961 &ta_hdr->ta_fw_bin[ta_index], 2962 ta_hdr); 2963 if (err) 2964 goto out; 2965 } 2966 2967 return 0; 2968 out: 2969 dev_err(adev->dev, "fail to initialize ta microcode\n"); 2970 release_firmware(adev->psp.ta_fw); 2971 adev->psp.ta_fw = NULL; 2972 return err; 2973 } 2974 2975 static int psp_set_clockgating_state(void *handle, 2976 enum amd_clockgating_state state) 2977 { 2978 return 0; 2979 } 2980 2981 static int psp_set_powergating_state(void *handle, 2982 enum amd_powergating_state state) 2983 { 2984 return 0; 2985 } 2986 2987 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 2988 struct device_attribute *attr, 2989 char *buf) 2990 { 2991 struct drm_device *ddev = dev_get_drvdata(dev); 2992 struct amdgpu_device *adev = drm_to_adev(ddev); 2993 uint32_t fw_ver; 2994 int ret; 2995 2996 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2997 DRM_INFO("PSP block is not ready yet."); 2998 return -EBUSY; 2999 } 3000 3001 mutex_lock(&adev->psp.mutex); 3002 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3003 mutex_unlock(&adev->psp.mutex); 3004 3005 if (ret) { 3006 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3007 return ret; 3008 } 3009 3010 return sysfs_emit(buf, "%x\n", fw_ver); 3011 } 3012 3013 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3014 struct device_attribute *attr, 3015 const char *buf, 3016 size_t count) 3017 { 3018 struct drm_device *ddev = dev_get_drvdata(dev); 3019 struct amdgpu_device *adev = drm_to_adev(ddev); 3020 void *cpu_addr; 3021 dma_addr_t dma_addr; 3022 int ret; 3023 char fw_name[100]; 3024 const struct firmware *usbc_pd_fw; 3025 3026 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3027 DRM_INFO("PSP block is not ready yet."); 3028 return -EBUSY; 3029 } 3030 3031 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3032 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3033 if (ret) 3034 goto fail; 3035 3036 /* We need contiguous physical mem to place the FW for psp to access */ 3037 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL); 3038 3039 ret = dma_mapping_error(adev->dev, dma_addr); 3040 if (ret) 3041 goto rel_buf; 3042 3043 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3044 3045 /* 3046 * x86 specific workaround. 3047 * Without it the buffer is invisible in PSP. 3048 * 3049 * TODO Remove once PSP starts snooping CPU cache 3050 */ 3051 #ifdef CONFIG_X86 3052 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1))); 3053 #endif 3054 3055 mutex_lock(&adev->psp.mutex); 3056 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr); 3057 mutex_unlock(&adev->psp.mutex); 3058 3059 rel_buf: 3060 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr); 3061 release_firmware(usbc_pd_fw); 3062 3063 fail: 3064 if (ret) { 3065 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3066 return ret; 3067 } 3068 3069 return count; 3070 } 3071 3072 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3073 psp_usbc_pd_fw_sysfs_read, 3074 psp_usbc_pd_fw_sysfs_write); 3075 3076 3077 3078 const struct amd_ip_funcs psp_ip_funcs = { 3079 .name = "psp", 3080 .early_init = psp_early_init, 3081 .late_init = NULL, 3082 .sw_init = psp_sw_init, 3083 .sw_fini = psp_sw_fini, 3084 .hw_init = psp_hw_init, 3085 .hw_fini = psp_hw_fini, 3086 .suspend = psp_suspend, 3087 .resume = psp_resume, 3088 .is_idle = NULL, 3089 .check_soft_reset = NULL, 3090 .wait_for_idle = NULL, 3091 .soft_reset = NULL, 3092 .set_clockgating_state = psp_set_clockgating_state, 3093 .set_powergating_state = psp_set_powergating_state, 3094 }; 3095 3096 static int psp_sysfs_init(struct amdgpu_device *adev) 3097 { 3098 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3099 3100 if (ret) 3101 DRM_ERROR("Failed to create USBC PD FW control file!"); 3102 3103 return ret; 3104 } 3105 3106 static void psp_sysfs_fini(struct amdgpu_device *adev) 3107 { 3108 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3109 } 3110 3111 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3112 { 3113 .type = AMD_IP_BLOCK_TYPE_PSP, 3114 .major = 3, 3115 .minor = 1, 3116 .rev = 0, 3117 .funcs = &psp_ip_funcs, 3118 }; 3119 3120 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3121 { 3122 .type = AMD_IP_BLOCK_TYPE_PSP, 3123 .major = 10, 3124 .minor = 0, 3125 .rev = 0, 3126 .funcs = &psp_ip_funcs, 3127 }; 3128 3129 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3130 { 3131 .type = AMD_IP_BLOCK_TYPE_PSP, 3132 .major = 11, 3133 .minor = 0, 3134 .rev = 0, 3135 .funcs = &psp_ip_funcs, 3136 }; 3137 3138 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3139 { 3140 .type = AMD_IP_BLOCK_TYPE_PSP, 3141 .major = 12, 3142 .minor = 0, 3143 .rev = 0, 3144 .funcs = &psp_ip_funcs, 3145 }; 3146 3147 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3148 .type = AMD_IP_BLOCK_TYPE_PSP, 3149 .major = 13, 3150 .minor = 0, 3151 .rev = 0, 3152 .funcs = &psp_ip_funcs, 3153 }; 3154