1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 42 #include "amdgpu_ras.h" 43 #include "amdgpu_securedisplay.h" 44 #include "amdgpu_atomfirmware.h" 45 46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 47 48 static int psp_sysfs_init(struct amdgpu_device *adev); 49 static void psp_sysfs_fini(struct amdgpu_device *adev); 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 static int psp_ring_init(struct psp_context *psp, 56 enum psp_ring_type ring_type) 57 { 58 int ret = 0; 59 struct psp_ring *ring; 60 struct amdgpu_device *adev = psp->adev; 61 62 ring = &psp->km_ring; 63 64 ring->ring_type = ring_type; 65 66 /* allocate 4k Page of Local Frame Buffer memory for ring */ 67 ring->ring_size = 0x1000; 68 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 69 AMDGPU_GEM_DOMAIN_VRAM | 70 AMDGPU_GEM_DOMAIN_GTT, 71 &adev->firmware.rbuf, 72 &ring->ring_mem_mc_addr, 73 (void **)&ring->ring_mem); 74 if (ret) { 75 ring->ring_size = 0; 76 return ret; 77 } 78 79 return 0; 80 } 81 82 /* 83 * Due to DF Cstate management centralized to PMFW, the firmware 84 * loading sequence will be updated as below: 85 * - Load KDB 86 * - Load SYS_DRV 87 * - Load tOS 88 * - Load PMFW 89 * - Setup TMR 90 * - Load other non-psp fw 91 * - Load ASD 92 * - Load XGMI/RAS/HDCP/DTM TA if any 93 * 94 * This new sequence is required for 95 * - Arcturus and onwards 96 */ 97 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 98 { 99 struct amdgpu_device *adev = psp->adev; 100 101 if (amdgpu_sriov_vf(adev)) { 102 psp->pmfw_centralized_cstate_management = false; 103 return; 104 } 105 106 switch (adev->ip_versions[MP0_HWIP][0]) { 107 case IP_VERSION(11, 0, 0): 108 case IP_VERSION(11, 0, 4): 109 case IP_VERSION(11, 0, 5): 110 case IP_VERSION(11, 0, 7): 111 case IP_VERSION(11, 0, 9): 112 case IP_VERSION(11, 0, 11): 113 case IP_VERSION(11, 0, 12): 114 case IP_VERSION(11, 0, 13): 115 case IP_VERSION(13, 0, 0): 116 case IP_VERSION(13, 0, 2): 117 case IP_VERSION(13, 0, 7): 118 psp->pmfw_centralized_cstate_management = true; 119 break; 120 default: 121 psp->pmfw_centralized_cstate_management = false; 122 break; 123 } 124 } 125 126 static int psp_init_sriov_microcode(struct psp_context *psp) 127 { 128 struct amdgpu_device *adev = psp->adev; 129 char ucode_prefix[30]; 130 int ret = 0; 131 132 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 133 134 switch (adev->ip_versions[MP0_HWIP][0]) { 135 case IP_VERSION(9, 0, 0): 136 case IP_VERSION(11, 0, 7): 137 case IP_VERSION(11, 0, 9): 138 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 139 ret = psp_init_cap_microcode(psp, ucode_prefix); 140 break; 141 case IP_VERSION(13, 0, 2): 142 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 143 ret = psp_init_cap_microcode(psp, ucode_prefix); 144 ret &= psp_init_ta_microcode(psp, ucode_prefix); 145 break; 146 case IP_VERSION(13, 0, 0): 147 adev->virt.autoload_ucode_id = 0; 148 break; 149 case IP_VERSION(13, 0, 6): 150 ret = psp_init_cap_microcode(psp, ucode_prefix); 151 break; 152 case IP_VERSION(13, 0, 10): 153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 154 ret = psp_init_cap_microcode(psp, ucode_prefix); 155 break; 156 default: 157 return -EINVAL; 158 } 159 return ret; 160 } 161 162 static int psp_early_init(void *handle) 163 { 164 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 165 struct psp_context *psp = &adev->psp; 166 167 switch (adev->ip_versions[MP0_HWIP][0]) { 168 case IP_VERSION(9, 0, 0): 169 psp_v3_1_set_psp_funcs(psp); 170 psp->autoload_supported = false; 171 break; 172 case IP_VERSION(10, 0, 0): 173 case IP_VERSION(10, 0, 1): 174 psp_v10_0_set_psp_funcs(psp); 175 psp->autoload_supported = false; 176 break; 177 case IP_VERSION(11, 0, 2): 178 case IP_VERSION(11, 0, 4): 179 psp_v11_0_set_psp_funcs(psp); 180 psp->autoload_supported = false; 181 break; 182 case IP_VERSION(11, 0, 0): 183 case IP_VERSION(11, 0, 5): 184 case IP_VERSION(11, 0, 9): 185 case IP_VERSION(11, 0, 7): 186 case IP_VERSION(11, 0, 11): 187 case IP_VERSION(11, 5, 0): 188 case IP_VERSION(11, 0, 12): 189 case IP_VERSION(11, 0, 13): 190 psp_v11_0_set_psp_funcs(psp); 191 psp->autoload_supported = true; 192 break; 193 case IP_VERSION(11, 0, 3): 194 case IP_VERSION(12, 0, 1): 195 psp_v12_0_set_psp_funcs(psp); 196 break; 197 case IP_VERSION(13, 0, 2): 198 case IP_VERSION(13, 0, 6): 199 psp_v13_0_set_psp_funcs(psp); 200 break; 201 case IP_VERSION(13, 0, 1): 202 case IP_VERSION(13, 0, 3): 203 case IP_VERSION(13, 0, 5): 204 case IP_VERSION(13, 0, 8): 205 case IP_VERSION(13, 0, 10): 206 case IP_VERSION(13, 0, 11): 207 psp_v13_0_set_psp_funcs(psp); 208 psp->autoload_supported = true; 209 break; 210 case IP_VERSION(11, 0, 8): 211 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 212 psp_v11_0_8_set_psp_funcs(psp); 213 psp->autoload_supported = false; 214 } 215 break; 216 case IP_VERSION(13, 0, 0): 217 case IP_VERSION(13, 0, 7): 218 psp_v13_0_set_psp_funcs(psp); 219 psp->autoload_supported = true; 220 break; 221 case IP_VERSION(13, 0, 4): 222 psp_v13_0_4_set_psp_funcs(psp); 223 psp->autoload_supported = true; 224 break; 225 default: 226 return -EINVAL; 227 } 228 229 psp->adev = adev; 230 231 psp_check_pmfw_centralized_cstate_management(psp); 232 233 if (amdgpu_sriov_vf(adev)) 234 return psp_init_sriov_microcode(psp); 235 else 236 return psp_init_microcode(psp); 237 } 238 239 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 240 { 241 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 242 &mem_ctx->shared_buf); 243 mem_ctx->shared_bo = NULL; 244 } 245 246 static void psp_free_shared_bufs(struct psp_context *psp) 247 { 248 void *tmr_buf; 249 void **pptr; 250 251 /* free TMR memory buffer */ 252 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 253 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 254 psp->tmr_bo = NULL; 255 256 /* free xgmi shared memory */ 257 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 258 259 /* free ras shared memory */ 260 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 261 262 /* free hdcp shared memory */ 263 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 264 265 /* free dtm shared memory */ 266 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 267 268 /* free rap shared memory */ 269 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 270 271 /* free securedisplay shared memory */ 272 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 273 274 275 } 276 277 static void psp_memory_training_fini(struct psp_context *psp) 278 { 279 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 280 281 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 282 kfree(ctx->sys_cache); 283 ctx->sys_cache = NULL; 284 } 285 286 static int psp_memory_training_init(struct psp_context *psp) 287 { 288 int ret; 289 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 290 291 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 292 DRM_DEBUG("memory training is not supported!\n"); 293 return 0; 294 } 295 296 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 297 if (ctx->sys_cache == NULL) { 298 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 299 ret = -ENOMEM; 300 goto Err_out; 301 } 302 303 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 304 ctx->train_data_size, 305 ctx->p2c_train_data_offset, 306 ctx->c2p_train_data_offset); 307 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 308 return 0; 309 310 Err_out: 311 psp_memory_training_fini(psp); 312 return ret; 313 } 314 315 /* 316 * Helper funciton to query psp runtime database entry 317 * 318 * @adev: amdgpu_device pointer 319 * @entry_type: the type of psp runtime database entry 320 * @db_entry: runtime database entry pointer 321 * 322 * Return false if runtime database doesn't exit or entry is invalid 323 * or true if the specific database entry is found, and copy to @db_entry 324 */ 325 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 326 enum psp_runtime_entry_type entry_type, 327 void *db_entry) 328 { 329 uint64_t db_header_pos, db_dir_pos; 330 struct psp_runtime_data_header db_header = {0}; 331 struct psp_runtime_data_directory db_dir = {0}; 332 bool ret = false; 333 int i; 334 335 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) 336 return false; 337 338 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 339 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 340 341 /* read runtime db header from vram */ 342 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 343 sizeof(struct psp_runtime_data_header), false); 344 345 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 346 /* runtime db doesn't exist, exit */ 347 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 348 return false; 349 } 350 351 /* read runtime database entry from vram */ 352 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 353 sizeof(struct psp_runtime_data_directory), false); 354 355 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 356 /* invalid db entry count, exit */ 357 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 358 return false; 359 } 360 361 /* look up for requested entry type */ 362 for (i = 0; i < db_dir.entry_count && !ret; i++) { 363 if (db_dir.entry_list[i].entry_type == entry_type) { 364 switch (entry_type) { 365 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 366 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 367 /* invalid db entry size */ 368 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 369 return false; 370 } 371 /* read runtime database entry */ 372 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 373 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 374 ret = true; 375 break; 376 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 377 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 378 /* invalid db entry size */ 379 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 380 return false; 381 } 382 /* read runtime database entry */ 383 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 384 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 385 ret = true; 386 break; 387 default: 388 ret = false; 389 break; 390 } 391 } 392 } 393 394 return ret; 395 } 396 397 static int psp_sw_init(void *handle) 398 { 399 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 400 struct psp_context *psp = &adev->psp; 401 int ret; 402 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 403 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 404 struct psp_runtime_scpm_entry scpm_entry; 405 406 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 407 if (!psp->cmd) { 408 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 409 ret = -ENOMEM; 410 } 411 412 adev->psp.xgmi_context.supports_extended_data = 413 !adev->gmc.xgmi.connected_to_cpu && 414 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 415 416 memset(&scpm_entry, 0, sizeof(scpm_entry)); 417 if ((psp_get_runtime_db_entry(adev, 418 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 419 &scpm_entry)) && 420 (scpm_entry.scpm_status != SCPM_DISABLE)) { 421 adev->scpm_enabled = true; 422 adev->scpm_status = scpm_entry.scpm_status; 423 } else { 424 adev->scpm_enabled = false; 425 adev->scpm_status = SCPM_DISABLE; 426 } 427 428 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 429 430 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 431 if (psp_get_runtime_db_entry(adev, 432 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 433 &boot_cfg_entry)) { 434 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 435 if ((psp->boot_cfg_bitmask) & 436 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 437 /* If psp runtime database exists, then 438 * only enable two stage memory training 439 * when TWO_STAGE_DRAM_TRAINING bit is set 440 * in runtime database */ 441 mem_training_ctx->enable_mem_training = true; 442 } 443 444 } else { 445 /* If psp runtime database doesn't exist or 446 * is invalid, force enable two stage memory 447 * training */ 448 mem_training_ctx->enable_mem_training = true; 449 } 450 451 if (mem_training_ctx->enable_mem_training) { 452 ret = psp_memory_training_init(psp); 453 if (ret) { 454 DRM_ERROR("Failed to initialize memory training!\n"); 455 return ret; 456 } 457 458 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 459 if (ret) { 460 DRM_ERROR("Failed to process memory training!\n"); 461 return ret; 462 } 463 } 464 465 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 466 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 467 ret = psp_sysfs_init(adev); 468 if (ret) 469 return ret; 470 } 471 472 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 473 amdgpu_sriov_vf(adev) ? 474 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 475 &psp->fw_pri_bo, 476 &psp->fw_pri_mc_addr, 477 &psp->fw_pri_buf); 478 if (ret) 479 return ret; 480 481 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 482 AMDGPU_GEM_DOMAIN_VRAM | 483 AMDGPU_GEM_DOMAIN_GTT, 484 &psp->fence_buf_bo, 485 &psp->fence_buf_mc_addr, 486 &psp->fence_buf); 487 if (ret) 488 goto failed1; 489 490 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 491 AMDGPU_GEM_DOMAIN_VRAM | 492 AMDGPU_GEM_DOMAIN_GTT, 493 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 494 (void **)&psp->cmd_buf_mem); 495 if (ret) 496 goto failed2; 497 498 return 0; 499 500 failed2: 501 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 502 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 503 failed1: 504 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 505 &psp->fence_buf_mc_addr, &psp->fence_buf); 506 return ret; 507 } 508 509 static int psp_sw_fini(void *handle) 510 { 511 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 512 struct psp_context *psp = &adev->psp; 513 struct psp_gfx_cmd_resp *cmd = psp->cmd; 514 515 psp_memory_training_fini(psp); 516 517 amdgpu_ucode_release(&psp->sos_fw); 518 amdgpu_ucode_release(&psp->asd_fw); 519 amdgpu_ucode_release(&psp->ta_fw); 520 amdgpu_ucode_release(&psp->cap_fw); 521 amdgpu_ucode_release(&psp->toc_fw); 522 523 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 524 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 525 psp_sysfs_fini(adev); 526 527 kfree(cmd); 528 cmd = NULL; 529 530 psp_free_shared_bufs(psp); 531 532 if (psp->km_ring.ring_mem) 533 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 534 &psp->km_ring.ring_mem_mc_addr, 535 (void **)&psp->km_ring.ring_mem); 536 537 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 538 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 539 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 540 &psp->fence_buf_mc_addr, &psp->fence_buf); 541 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 542 (void **)&psp->cmd_buf_mem); 543 544 return 0; 545 } 546 547 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 548 uint32_t reg_val, uint32_t mask, bool check_changed) 549 { 550 uint32_t val; 551 int i; 552 struct amdgpu_device *adev = psp->adev; 553 554 if (psp->adev->no_hw_access) 555 return 0; 556 557 for (i = 0; i < adev->usec_timeout; i++) { 558 val = RREG32(reg_index); 559 if (check_changed) { 560 if (val != reg_val) 561 return 0; 562 } else { 563 if ((val & mask) == reg_val) 564 return 0; 565 } 566 udelay(1); 567 } 568 569 return -ETIME; 570 } 571 572 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 573 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 574 { 575 uint32_t val; 576 int i; 577 struct amdgpu_device *adev = psp->adev; 578 579 if (psp->adev->no_hw_access) 580 return 0; 581 582 for (i = 0; i < msec_timeout; i++) { 583 val = RREG32(reg_index); 584 if ((val & mask) == reg_val) 585 return 0; 586 msleep(1); 587 } 588 589 return -ETIME; 590 } 591 592 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 593 { 594 switch (cmd_id) { 595 case GFX_CMD_ID_LOAD_TA: 596 return "LOAD_TA"; 597 case GFX_CMD_ID_UNLOAD_TA: 598 return "UNLOAD_TA"; 599 case GFX_CMD_ID_INVOKE_CMD: 600 return "INVOKE_CMD"; 601 case GFX_CMD_ID_LOAD_ASD: 602 return "LOAD_ASD"; 603 case GFX_CMD_ID_SETUP_TMR: 604 return "SETUP_TMR"; 605 case GFX_CMD_ID_LOAD_IP_FW: 606 return "LOAD_IP_FW"; 607 case GFX_CMD_ID_DESTROY_TMR: 608 return "DESTROY_TMR"; 609 case GFX_CMD_ID_SAVE_RESTORE: 610 return "SAVE_RESTORE_IP_FW"; 611 case GFX_CMD_ID_SETUP_VMR: 612 return "SETUP_VMR"; 613 case GFX_CMD_ID_DESTROY_VMR: 614 return "DESTROY_VMR"; 615 case GFX_CMD_ID_PROG_REG: 616 return "PROG_REG"; 617 case GFX_CMD_ID_GET_FW_ATTESTATION: 618 return "GET_FW_ATTESTATION"; 619 case GFX_CMD_ID_LOAD_TOC: 620 return "ID_LOAD_TOC"; 621 case GFX_CMD_ID_AUTOLOAD_RLC: 622 return "AUTOLOAD_RLC"; 623 case GFX_CMD_ID_BOOT_CFG: 624 return "BOOT_CFG"; 625 default: 626 return "UNKNOWN CMD"; 627 } 628 } 629 630 static int 631 psp_cmd_submit_buf(struct psp_context *psp, 632 struct amdgpu_firmware_info *ucode, 633 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 634 { 635 int ret; 636 int index; 637 int timeout = 20000; 638 bool ras_intr = false; 639 bool skip_unsupport = false; 640 641 if (psp->adev->no_hw_access) 642 return 0; 643 644 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 645 646 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 647 648 index = atomic_inc_return(&psp->fence_value); 649 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 650 if (ret) { 651 atomic_dec(&psp->fence_value); 652 goto exit; 653 } 654 655 amdgpu_device_invalidate_hdp(psp->adev, NULL); 656 while (*((unsigned int *)psp->fence_buf) != index) { 657 if (--timeout == 0) 658 break; 659 /* 660 * Shouldn't wait for timeout when err_event_athub occurs, 661 * because gpu reset thread triggered and lock resource should 662 * be released for psp resume sequence. 663 */ 664 ras_intr = amdgpu_ras_intr_triggered(); 665 if (ras_intr) 666 break; 667 usleep_range(10, 100); 668 amdgpu_device_invalidate_hdp(psp->adev, NULL); 669 } 670 671 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 672 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 673 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 674 675 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 676 677 /* In some cases, psp response status is not 0 even there is no 678 * problem while the command is submitted. Some version of PSP FW 679 * doesn't write 0 to that field. 680 * So here we would like to only print a warning instead of an error 681 * during psp initialization to avoid breaking hw_init and it doesn't 682 * return -EINVAL. 683 */ 684 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 685 if (ucode) 686 DRM_WARN("failed to load ucode %s(0x%X) ", 687 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 688 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 689 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 690 psp->cmd_buf_mem->resp.status); 691 /* If any firmware (including CAP) load fails under SRIOV, it should 692 * return failure to stop the VF from initializing. 693 * Also return failure in case of timeout 694 */ 695 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 696 ret = -EINVAL; 697 goto exit; 698 } 699 } 700 701 if (ucode) { 702 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 703 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 704 } 705 706 exit: 707 return ret; 708 } 709 710 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 711 { 712 struct psp_gfx_cmd_resp *cmd = psp->cmd; 713 714 mutex_lock(&psp->mutex); 715 716 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 717 718 return cmd; 719 } 720 721 static void release_psp_cmd_buf(struct psp_context *psp) 722 { 723 mutex_unlock(&psp->mutex); 724 } 725 726 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 727 struct psp_gfx_cmd_resp *cmd, 728 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 729 { 730 struct amdgpu_device *adev = psp->adev; 731 uint32_t size = 0; 732 uint64_t tmr_pa = 0; 733 734 if (tmr_bo) { 735 size = amdgpu_bo_size(tmr_bo); 736 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 737 } 738 739 if (amdgpu_sriov_vf(psp->adev)) 740 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 741 else 742 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 743 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 744 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 745 cmd->cmd.cmd_setup_tmr.buf_size = size; 746 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 747 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 748 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 749 } 750 751 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 752 uint64_t pri_buf_mc, uint32_t size) 753 { 754 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 755 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 756 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 757 cmd->cmd.cmd_load_toc.toc_size = size; 758 } 759 760 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 761 static int psp_load_toc(struct psp_context *psp, 762 uint32_t *tmr_size) 763 { 764 int ret; 765 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 766 767 /* Copy toc to psp firmware private buffer */ 768 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 769 770 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 771 772 ret = psp_cmd_submit_buf(psp, NULL, cmd, 773 psp->fence_buf_mc_addr); 774 if (!ret) 775 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 776 777 release_psp_cmd_buf(psp); 778 779 return ret; 780 } 781 782 static bool psp_boottime_tmr(struct psp_context *psp) 783 { 784 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 785 case IP_VERSION(13, 0, 6): 786 return true; 787 default: 788 return false; 789 } 790 } 791 792 /* Set up Trusted Memory Region */ 793 static int psp_tmr_init(struct psp_context *psp) 794 { 795 int ret = 0; 796 int tmr_size; 797 void *tmr_buf; 798 void **pptr; 799 800 /* 801 * According to HW engineer, they prefer the TMR address be "naturally 802 * aligned" , e.g. the start address be an integer divide of TMR size. 803 * 804 * Note: this memory need be reserved till the driver 805 * uninitializes. 806 */ 807 tmr_size = PSP_TMR_SIZE(psp->adev); 808 809 /* For ASICs support RLC autoload, psp will parse the toc 810 * and calculate the total size of TMR needed */ 811 if (!amdgpu_sriov_vf(psp->adev) && 812 psp->toc.start_addr && 813 psp->toc.size_bytes && 814 psp->fw_pri_buf) { 815 ret = psp_load_toc(psp, &tmr_size); 816 if (ret) { 817 DRM_ERROR("Failed to load toc\n"); 818 return ret; 819 } 820 } 821 822 if (!psp->tmr_bo) { 823 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 824 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 825 PSP_TMR_ALIGNMENT, 826 AMDGPU_HAS_VRAM(psp->adev) ? 827 AMDGPU_GEM_DOMAIN_VRAM : 828 AMDGPU_GEM_DOMAIN_GTT, 829 &psp->tmr_bo, &psp->tmr_mc_addr, 830 pptr); 831 } 832 833 return ret; 834 } 835 836 static bool psp_skip_tmr(struct psp_context *psp) 837 { 838 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 839 case IP_VERSION(11, 0, 9): 840 case IP_VERSION(11, 0, 7): 841 case IP_VERSION(13, 0, 2): 842 case IP_VERSION(13, 0, 6): 843 case IP_VERSION(13, 0, 10): 844 return true; 845 default: 846 return false; 847 } 848 } 849 850 static int psp_tmr_load(struct psp_context *psp) 851 { 852 int ret; 853 struct psp_gfx_cmd_resp *cmd; 854 855 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 856 * Already set up by host driver. 857 */ 858 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 859 return 0; 860 861 cmd = acquire_psp_cmd_buf(psp); 862 863 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 864 if (psp->tmr_bo) 865 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 866 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 867 868 ret = psp_cmd_submit_buf(psp, NULL, cmd, 869 psp->fence_buf_mc_addr); 870 871 release_psp_cmd_buf(psp); 872 873 return ret; 874 } 875 876 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 877 struct psp_gfx_cmd_resp *cmd) 878 { 879 if (amdgpu_sriov_vf(psp->adev)) 880 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 881 else 882 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 883 } 884 885 static int psp_tmr_unload(struct psp_context *psp) 886 { 887 int ret; 888 struct psp_gfx_cmd_resp *cmd; 889 890 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV, 891 * as TMR is not loaded at all 892 */ 893 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 894 return 0; 895 896 cmd = acquire_psp_cmd_buf(psp); 897 898 psp_prep_tmr_unload_cmd_buf(psp, cmd); 899 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 900 901 ret = psp_cmd_submit_buf(psp, NULL, cmd, 902 psp->fence_buf_mc_addr); 903 904 release_psp_cmd_buf(psp); 905 906 return ret; 907 } 908 909 static int psp_tmr_terminate(struct psp_context *psp) 910 { 911 return psp_tmr_unload(psp); 912 } 913 914 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 915 uint64_t *output_ptr) 916 { 917 int ret; 918 struct psp_gfx_cmd_resp *cmd; 919 920 if (!output_ptr) 921 return -EINVAL; 922 923 if (amdgpu_sriov_vf(psp->adev)) 924 return 0; 925 926 cmd = acquire_psp_cmd_buf(psp); 927 928 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 929 930 ret = psp_cmd_submit_buf(psp, NULL, cmd, 931 psp->fence_buf_mc_addr); 932 933 if (!ret) { 934 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 935 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 936 } 937 938 release_psp_cmd_buf(psp); 939 940 return ret; 941 } 942 943 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 944 { 945 struct psp_context *psp = &adev->psp; 946 struct psp_gfx_cmd_resp *cmd; 947 int ret; 948 949 if (amdgpu_sriov_vf(adev)) 950 return 0; 951 952 cmd = acquire_psp_cmd_buf(psp); 953 954 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 955 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 956 957 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 958 if (!ret) { 959 *boot_cfg = 960 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 961 } 962 963 release_psp_cmd_buf(psp); 964 965 return ret; 966 } 967 968 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 969 { 970 int ret; 971 struct psp_context *psp = &adev->psp; 972 struct psp_gfx_cmd_resp *cmd; 973 974 if (amdgpu_sriov_vf(adev)) 975 return 0; 976 977 cmd = acquire_psp_cmd_buf(psp); 978 979 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 980 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 981 cmd->cmd.boot_cfg.boot_config = boot_cfg; 982 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 983 984 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 985 986 release_psp_cmd_buf(psp); 987 988 return ret; 989 } 990 991 static int psp_rl_load(struct amdgpu_device *adev) 992 { 993 int ret; 994 struct psp_context *psp = &adev->psp; 995 struct psp_gfx_cmd_resp *cmd; 996 997 if (!is_psp_fw_valid(psp->rl)) 998 return 0; 999 1000 cmd = acquire_psp_cmd_buf(psp); 1001 1002 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1003 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 1004 1005 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1006 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1007 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1008 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1009 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1010 1011 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1012 1013 release_psp_cmd_buf(psp); 1014 1015 return ret; 1016 } 1017 1018 int psp_spatial_partition(struct psp_context *psp, int mode) 1019 { 1020 struct psp_gfx_cmd_resp *cmd; 1021 int ret; 1022 1023 if (amdgpu_sriov_vf(psp->adev)) 1024 return 0; 1025 1026 cmd = acquire_psp_cmd_buf(psp); 1027 1028 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1029 cmd->cmd.cmd_spatial_part.mode = mode; 1030 1031 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1032 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1033 1034 release_psp_cmd_buf(psp); 1035 1036 return ret; 1037 } 1038 1039 static int psp_asd_initialize(struct psp_context *psp) 1040 { 1041 int ret; 1042 1043 /* If PSP version doesn't match ASD version, asd loading will be failed. 1044 * add workaround to bypass it for sriov now. 1045 * TODO: add version check to make it common 1046 */ 1047 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1048 return 0; 1049 1050 psp->asd_context.mem_context.shared_mc_addr = 0; 1051 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1052 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1053 1054 ret = psp_ta_load(psp, &psp->asd_context); 1055 if (!ret) 1056 psp->asd_context.initialized = true; 1057 1058 return ret; 1059 } 1060 1061 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1062 uint32_t session_id) 1063 { 1064 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1065 cmd->cmd.cmd_unload_ta.session_id = session_id; 1066 } 1067 1068 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1069 { 1070 int ret; 1071 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1072 1073 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1074 1075 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1076 1077 context->resp_status = cmd->resp.status; 1078 1079 release_psp_cmd_buf(psp); 1080 1081 return ret; 1082 } 1083 1084 static int psp_asd_terminate(struct psp_context *psp) 1085 { 1086 int ret; 1087 1088 if (amdgpu_sriov_vf(psp->adev)) 1089 return 0; 1090 1091 if (!psp->asd_context.initialized) 1092 return 0; 1093 1094 ret = psp_ta_unload(psp, &psp->asd_context); 1095 if (!ret) 1096 psp->asd_context.initialized = false; 1097 1098 return ret; 1099 } 1100 1101 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1102 uint32_t id, uint32_t value) 1103 { 1104 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1105 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1106 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1107 } 1108 1109 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1110 uint32_t value) 1111 { 1112 struct psp_gfx_cmd_resp *cmd; 1113 int ret = 0; 1114 1115 if (reg >= PSP_REG_LAST) 1116 return -EINVAL; 1117 1118 cmd = acquire_psp_cmd_buf(psp); 1119 1120 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1121 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1122 if (ret) 1123 DRM_ERROR("PSP failed to program reg id %d", reg); 1124 1125 release_psp_cmd_buf(psp); 1126 1127 return ret; 1128 } 1129 1130 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1131 uint64_t ta_bin_mc, 1132 struct ta_context *context) 1133 { 1134 cmd->cmd_id = context->ta_load_type; 1135 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1136 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1137 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1138 1139 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1140 lower_32_bits(context->mem_context.shared_mc_addr); 1141 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1142 upper_32_bits(context->mem_context.shared_mc_addr); 1143 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1144 } 1145 1146 int psp_ta_init_shared_buf(struct psp_context *psp, 1147 struct ta_mem_context *mem_ctx) 1148 { 1149 /* 1150 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1151 * physical) for ta to host memory 1152 */ 1153 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1154 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1155 AMDGPU_GEM_DOMAIN_GTT, 1156 &mem_ctx->shared_bo, 1157 &mem_ctx->shared_mc_addr, 1158 &mem_ctx->shared_buf); 1159 } 1160 1161 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1162 uint32_t ta_cmd_id, 1163 uint32_t session_id) 1164 { 1165 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1166 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1167 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1168 } 1169 1170 int psp_ta_invoke(struct psp_context *psp, 1171 uint32_t ta_cmd_id, 1172 struct ta_context *context) 1173 { 1174 int ret; 1175 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1176 1177 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1178 1179 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1180 psp->fence_buf_mc_addr); 1181 1182 context->resp_status = cmd->resp.status; 1183 1184 release_psp_cmd_buf(psp); 1185 1186 return ret; 1187 } 1188 1189 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1190 { 1191 int ret; 1192 struct psp_gfx_cmd_resp *cmd; 1193 1194 cmd = acquire_psp_cmd_buf(psp); 1195 1196 psp_copy_fw(psp, context->bin_desc.start_addr, 1197 context->bin_desc.size_bytes); 1198 1199 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1200 1201 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1202 psp->fence_buf_mc_addr); 1203 1204 context->resp_status = cmd->resp.status; 1205 1206 if (!ret) 1207 context->session_id = cmd->resp.session_id; 1208 1209 release_psp_cmd_buf(psp); 1210 1211 return ret; 1212 } 1213 1214 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1215 { 1216 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1217 } 1218 1219 int psp_xgmi_terminate(struct psp_context *psp) 1220 { 1221 int ret; 1222 struct amdgpu_device *adev = psp->adev; 1223 1224 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1225 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1226 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1227 adev->gmc.xgmi.connected_to_cpu)) 1228 return 0; 1229 1230 if (!psp->xgmi_context.context.initialized) 1231 return 0; 1232 1233 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1234 1235 psp->xgmi_context.context.initialized = false; 1236 1237 return ret; 1238 } 1239 1240 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1241 { 1242 struct ta_xgmi_shared_memory *xgmi_cmd; 1243 int ret; 1244 1245 if (!psp->ta_fw || 1246 !psp->xgmi_context.context.bin_desc.size_bytes || 1247 !psp->xgmi_context.context.bin_desc.start_addr) 1248 return -ENOENT; 1249 1250 if (!load_ta) 1251 goto invoke; 1252 1253 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1254 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1255 1256 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1257 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1258 if (ret) 1259 return ret; 1260 } 1261 1262 /* Load XGMI TA */ 1263 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1264 if (!ret) 1265 psp->xgmi_context.context.initialized = true; 1266 else 1267 return ret; 1268 1269 invoke: 1270 /* Initialize XGMI session */ 1271 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1272 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1273 xgmi_cmd->flag_extend_link_record = set_extended_data; 1274 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1275 1276 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1277 1278 return ret; 1279 } 1280 1281 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1282 { 1283 struct ta_xgmi_shared_memory *xgmi_cmd; 1284 int ret; 1285 1286 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1287 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1288 1289 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1290 1291 /* Invoke xgmi ta to get hive id */ 1292 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1293 if (ret) 1294 return ret; 1295 1296 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1297 1298 return 0; 1299 } 1300 1301 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1302 { 1303 struct ta_xgmi_shared_memory *xgmi_cmd; 1304 int ret; 1305 1306 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1307 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1308 1309 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1310 1311 /* Invoke xgmi ta to get the node id */ 1312 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1313 if (ret) 1314 return ret; 1315 1316 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1317 1318 return 0; 1319 } 1320 1321 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1322 { 1323 return (psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1324 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1325 psp->adev->ip_versions[MP0_HWIP][0] >= IP_VERSION(13, 0, 6); 1326 } 1327 1328 /* 1329 * Chips that support extended topology information require the driver to 1330 * reflect topology information in the opposite direction. This is 1331 * because the TA has already exceeded its link record limit and if the 1332 * TA holds bi-directional information, the driver would have to do 1333 * multiple fetches instead of just two. 1334 */ 1335 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1336 struct psp_xgmi_node_info node_info) 1337 { 1338 struct amdgpu_device *mirror_adev; 1339 struct amdgpu_hive_info *hive; 1340 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1341 uint64_t dst_node_id = node_info.node_id; 1342 uint8_t dst_num_hops = node_info.num_hops; 1343 uint8_t dst_num_links = node_info.num_links; 1344 1345 hive = amdgpu_get_xgmi_hive(psp->adev); 1346 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1347 struct psp_xgmi_topology_info *mirror_top_info; 1348 int j; 1349 1350 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1351 continue; 1352 1353 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1354 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1355 if (mirror_top_info->nodes[j].node_id != src_node_id) 1356 continue; 1357 1358 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1359 /* 1360 * prevent 0 num_links value re-reflection since reflection 1361 * criteria is based on num_hops (direct or indirect). 1362 * 1363 */ 1364 if (dst_num_links) 1365 mirror_top_info->nodes[j].num_links = dst_num_links; 1366 1367 break; 1368 } 1369 1370 break; 1371 } 1372 1373 amdgpu_put_xgmi_hive(hive); 1374 } 1375 1376 int psp_xgmi_get_topology_info(struct psp_context *psp, 1377 int number_devices, 1378 struct psp_xgmi_topology_info *topology, 1379 bool get_extended_data) 1380 { 1381 struct ta_xgmi_shared_memory *xgmi_cmd; 1382 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1383 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1384 int i; 1385 int ret; 1386 1387 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1388 return -EINVAL; 1389 1390 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1391 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1392 xgmi_cmd->flag_extend_link_record = get_extended_data; 1393 1394 /* Fill in the shared memory with topology information as input */ 1395 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1396 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1397 topology_info_input->num_nodes = number_devices; 1398 1399 for (i = 0; i < topology_info_input->num_nodes; i++) { 1400 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1401 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1402 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1403 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1404 } 1405 1406 /* Invoke xgmi ta to get the topology information */ 1407 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1408 if (ret) 1409 return ret; 1410 1411 /* Read the output topology information from the shared memory */ 1412 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1413 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1414 for (i = 0; i < topology->num_nodes; i++) { 1415 /* extended data will either be 0 or equal to non-extended data */ 1416 if (topology_info_output->nodes[i].num_hops) 1417 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1418 1419 /* non-extended data gets everything here so no need to update */ 1420 if (!get_extended_data) { 1421 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1422 topology->nodes[i].is_sharing_enabled = 1423 topology_info_output->nodes[i].is_sharing_enabled; 1424 topology->nodes[i].sdma_engine = 1425 topology_info_output->nodes[i].sdma_engine; 1426 } 1427 1428 } 1429 1430 /* Invoke xgmi ta again to get the link information */ 1431 if (psp_xgmi_peer_link_info_supported(psp)) { 1432 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1433 bool requires_reflection = 1434 (psp->xgmi_context.supports_extended_data && get_extended_data) || 1435 psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6); 1436 1437 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1438 1439 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1440 1441 if (ret) 1442 return ret; 1443 1444 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1445 for (i = 0; i < topology->num_nodes; i++) { 1446 /* accumulate num_links on extended data */ 1447 topology->nodes[i].num_links = get_extended_data ? 1448 topology->nodes[i].num_links + 1449 link_info_output->nodes[i].num_links : 1450 ((requires_reflection && topology->nodes[i].num_links) ? topology->nodes[i].num_links : 1451 link_info_output->nodes[i].num_links); 1452 1453 /* reflect the topology information for bi-directionality */ 1454 if (requires_reflection && topology->nodes[i].num_hops) 1455 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1456 } 1457 } 1458 1459 return 0; 1460 } 1461 1462 int psp_xgmi_set_topology_info(struct psp_context *psp, 1463 int number_devices, 1464 struct psp_xgmi_topology_info *topology) 1465 { 1466 struct ta_xgmi_shared_memory *xgmi_cmd; 1467 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1468 int i; 1469 1470 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1471 return -EINVAL; 1472 1473 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1474 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1475 1476 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1477 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1478 topology_info_input->num_nodes = number_devices; 1479 1480 for (i = 0; i < topology_info_input->num_nodes; i++) { 1481 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1482 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1483 topology_info_input->nodes[i].is_sharing_enabled = 1; 1484 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1485 } 1486 1487 /* Invoke xgmi ta to set topology information */ 1488 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1489 } 1490 1491 // ras begin 1492 static void psp_ras_ta_check_status(struct psp_context *psp) 1493 { 1494 struct ta_ras_shared_memory *ras_cmd = 1495 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1496 1497 switch (ras_cmd->ras_status) { 1498 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1499 dev_warn(psp->adev->dev, 1500 "RAS WARNING: cmd failed due to unsupported ip\n"); 1501 break; 1502 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1503 dev_warn(psp->adev->dev, 1504 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1505 break; 1506 case TA_RAS_STATUS__SUCCESS: 1507 break; 1508 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1509 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1510 dev_warn(psp->adev->dev, 1511 "RAS WARNING: Inject error to critical region is not allowed\n"); 1512 break; 1513 default: 1514 dev_warn(psp->adev->dev, 1515 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1516 break; 1517 } 1518 } 1519 1520 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1521 { 1522 struct ta_ras_shared_memory *ras_cmd; 1523 int ret; 1524 1525 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1526 1527 /* 1528 * TODO: bypass the loading in sriov for now 1529 */ 1530 if (amdgpu_sriov_vf(psp->adev)) 1531 return 0; 1532 1533 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1534 1535 if (amdgpu_ras_intr_triggered()) 1536 return ret; 1537 1538 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 1539 DRM_WARN("RAS: Unsupported Interface"); 1540 return -EINVAL; 1541 } 1542 1543 if (!ret) { 1544 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1545 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1546 1547 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1548 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1549 dev_warn(psp->adev->dev, 1550 "RAS internal register access blocked\n"); 1551 1552 psp_ras_ta_check_status(psp); 1553 } 1554 1555 return ret; 1556 } 1557 1558 int psp_ras_enable_features(struct psp_context *psp, 1559 union ta_ras_cmd_input *info, bool enable) 1560 { 1561 struct ta_ras_shared_memory *ras_cmd; 1562 int ret; 1563 1564 if (!psp->ras_context.context.initialized) 1565 return -EINVAL; 1566 1567 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1568 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1569 1570 if (enable) 1571 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1572 else 1573 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1574 1575 ras_cmd->ras_in_message = *info; 1576 1577 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1578 if (ret) 1579 return -EINVAL; 1580 1581 return 0; 1582 } 1583 1584 int psp_ras_terminate(struct psp_context *psp) 1585 { 1586 int ret; 1587 1588 /* 1589 * TODO: bypass the terminate in sriov for now 1590 */ 1591 if (amdgpu_sriov_vf(psp->adev)) 1592 return 0; 1593 1594 if (!psp->ras_context.context.initialized) 1595 return 0; 1596 1597 ret = psp_ta_unload(psp, &psp->ras_context.context); 1598 1599 psp->ras_context.context.initialized = false; 1600 1601 return ret; 1602 } 1603 1604 int psp_ras_initialize(struct psp_context *psp) 1605 { 1606 int ret; 1607 uint32_t boot_cfg = 0xFF; 1608 struct amdgpu_device *adev = psp->adev; 1609 struct ta_ras_shared_memory *ras_cmd; 1610 1611 /* 1612 * TODO: bypass the initialize in sriov for now 1613 */ 1614 if (amdgpu_sriov_vf(adev)) 1615 return 0; 1616 1617 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1618 !adev->psp.ras_context.context.bin_desc.start_addr) { 1619 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1620 return 0; 1621 } 1622 1623 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1624 /* query GECC enablement status from boot config 1625 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1626 */ 1627 ret = psp_boot_config_get(adev, &boot_cfg); 1628 if (ret) 1629 dev_warn(adev->dev, "PSP get boot config failed\n"); 1630 1631 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1632 if (!boot_cfg) { 1633 dev_info(adev->dev, "GECC is disabled\n"); 1634 } else { 1635 /* disable GECC in next boot cycle if ras is 1636 * disabled by module parameter amdgpu_ras_enable 1637 * and/or amdgpu_ras_mask, or boot_config_get call 1638 * is failed 1639 */ 1640 ret = psp_boot_config_set(adev, 0); 1641 if (ret) 1642 dev_warn(adev->dev, "PSP set boot config failed\n"); 1643 else 1644 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1645 } 1646 } else { 1647 if (boot_cfg == 1) { 1648 dev_info(adev->dev, "GECC is enabled\n"); 1649 } else { 1650 /* enable GECC in next boot cycle if it is disabled 1651 * in boot config, or force enable GECC if failed to 1652 * get boot configuration 1653 */ 1654 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1655 if (ret) 1656 dev_warn(adev->dev, "PSP set boot config failed\n"); 1657 else 1658 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1659 } 1660 } 1661 } 1662 1663 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1664 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1665 1666 if (!psp->ras_context.context.mem_context.shared_buf) { 1667 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1668 if (ret) 1669 return ret; 1670 } 1671 1672 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1673 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1674 1675 if (amdgpu_ras_is_poison_mode_supported(adev)) 1676 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1677 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1678 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1679 ras_cmd->ras_in_message.init_flags.xcc_mask = 1680 adev->gfx.xcc_mask; 1681 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 1682 1683 ret = psp_ta_load(psp, &psp->ras_context.context); 1684 1685 if (!ret && !ras_cmd->ras_status) 1686 psp->ras_context.context.initialized = true; 1687 else { 1688 if (ras_cmd->ras_status) 1689 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1690 1691 /* fail to load RAS TA */ 1692 psp->ras_context.context.initialized = false; 1693 } 1694 1695 return ret; 1696 } 1697 1698 int psp_ras_trigger_error(struct psp_context *psp, 1699 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 1700 { 1701 struct ta_ras_shared_memory *ras_cmd; 1702 struct amdgpu_device *adev = psp->adev; 1703 int ret; 1704 uint32_t dev_mask; 1705 1706 if (!psp->ras_context.context.initialized) 1707 return -EINVAL; 1708 1709 switch (info->block_id) { 1710 case TA_RAS_BLOCK__GFX: 1711 dev_mask = GET_MASK(GC, instance_mask); 1712 break; 1713 case TA_RAS_BLOCK__SDMA: 1714 dev_mask = GET_MASK(SDMA0, instance_mask); 1715 break; 1716 case TA_RAS_BLOCK__VCN: 1717 case TA_RAS_BLOCK__JPEG: 1718 dev_mask = GET_MASK(VCN, instance_mask); 1719 break; 1720 default: 1721 dev_mask = instance_mask; 1722 break; 1723 } 1724 1725 /* reuse sub_block_index for backward compatibility */ 1726 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 1727 dev_mask &= AMDGPU_RAS_INST_MASK; 1728 info->sub_block_index |= dev_mask; 1729 1730 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1731 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1732 1733 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1734 ras_cmd->ras_in_message.trigger_error = *info; 1735 1736 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1737 if (ret) 1738 return -EINVAL; 1739 1740 /* If err_event_athub occurs error inject was successful, however 1741 return status from TA is no long reliable */ 1742 if (amdgpu_ras_intr_triggered()) 1743 return 0; 1744 1745 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1746 return -EACCES; 1747 else if (ras_cmd->ras_status) 1748 return -EINVAL; 1749 1750 return 0; 1751 } 1752 // ras end 1753 1754 // HDCP start 1755 static int psp_hdcp_initialize(struct psp_context *psp) 1756 { 1757 int ret; 1758 1759 /* 1760 * TODO: bypass the initialize in sriov for now 1761 */ 1762 if (amdgpu_sriov_vf(psp->adev)) 1763 return 0; 1764 1765 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1766 !psp->hdcp_context.context.bin_desc.start_addr) { 1767 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1768 return 0; 1769 } 1770 1771 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1772 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1773 1774 if (!psp->hdcp_context.context.mem_context.shared_buf) { 1775 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1776 if (ret) 1777 return ret; 1778 } 1779 1780 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1781 if (!ret) { 1782 psp->hdcp_context.context.initialized = true; 1783 mutex_init(&psp->hdcp_context.mutex); 1784 } 1785 1786 return ret; 1787 } 1788 1789 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1790 { 1791 /* 1792 * TODO: bypass the loading in sriov for now 1793 */ 1794 if (amdgpu_sriov_vf(psp->adev)) 1795 return 0; 1796 1797 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1798 } 1799 1800 static int psp_hdcp_terminate(struct psp_context *psp) 1801 { 1802 int ret; 1803 1804 /* 1805 * TODO: bypass the terminate in sriov for now 1806 */ 1807 if (amdgpu_sriov_vf(psp->adev)) 1808 return 0; 1809 1810 if (!psp->hdcp_context.context.initialized) 1811 return 0; 1812 1813 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1814 1815 psp->hdcp_context.context.initialized = false; 1816 1817 return ret; 1818 } 1819 // HDCP end 1820 1821 // DTM start 1822 static int psp_dtm_initialize(struct psp_context *psp) 1823 { 1824 int ret; 1825 1826 /* 1827 * TODO: bypass the initialize in sriov for now 1828 */ 1829 if (amdgpu_sriov_vf(psp->adev)) 1830 return 0; 1831 1832 if (!psp->dtm_context.context.bin_desc.size_bytes || 1833 !psp->dtm_context.context.bin_desc.start_addr) { 1834 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1835 return 0; 1836 } 1837 1838 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1839 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1840 1841 if (!psp->dtm_context.context.mem_context.shared_buf) { 1842 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1843 if (ret) 1844 return ret; 1845 } 1846 1847 ret = psp_ta_load(psp, &psp->dtm_context.context); 1848 if (!ret) { 1849 psp->dtm_context.context.initialized = true; 1850 mutex_init(&psp->dtm_context.mutex); 1851 } 1852 1853 return ret; 1854 } 1855 1856 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1857 { 1858 /* 1859 * TODO: bypass the loading in sriov for now 1860 */ 1861 if (amdgpu_sriov_vf(psp->adev)) 1862 return 0; 1863 1864 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1865 } 1866 1867 static int psp_dtm_terminate(struct psp_context *psp) 1868 { 1869 int ret; 1870 1871 /* 1872 * TODO: bypass the terminate in sriov for now 1873 */ 1874 if (amdgpu_sriov_vf(psp->adev)) 1875 return 0; 1876 1877 if (!psp->dtm_context.context.initialized) 1878 return 0; 1879 1880 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1881 1882 psp->dtm_context.context.initialized = false; 1883 1884 return ret; 1885 } 1886 // DTM end 1887 1888 // RAP start 1889 static int psp_rap_initialize(struct psp_context *psp) 1890 { 1891 int ret; 1892 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1893 1894 /* 1895 * TODO: bypass the initialize in sriov for now 1896 */ 1897 if (amdgpu_sriov_vf(psp->adev)) 1898 return 0; 1899 1900 if (!psp->rap_context.context.bin_desc.size_bytes || 1901 !psp->rap_context.context.bin_desc.start_addr) { 1902 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1903 return 0; 1904 } 1905 1906 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1907 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1908 1909 if (!psp->rap_context.context.mem_context.shared_buf) { 1910 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1911 if (ret) 1912 return ret; 1913 } 1914 1915 ret = psp_ta_load(psp, &psp->rap_context.context); 1916 if (!ret) { 1917 psp->rap_context.context.initialized = true; 1918 mutex_init(&psp->rap_context.mutex); 1919 } else 1920 return ret; 1921 1922 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1923 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1924 psp_rap_terminate(psp); 1925 /* free rap shared memory */ 1926 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1927 1928 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1929 ret, status); 1930 1931 return ret; 1932 } 1933 1934 return 0; 1935 } 1936 1937 static int psp_rap_terminate(struct psp_context *psp) 1938 { 1939 int ret; 1940 1941 if (!psp->rap_context.context.initialized) 1942 return 0; 1943 1944 ret = psp_ta_unload(psp, &psp->rap_context.context); 1945 1946 psp->rap_context.context.initialized = false; 1947 1948 return ret; 1949 } 1950 1951 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1952 { 1953 struct ta_rap_shared_memory *rap_cmd; 1954 int ret = 0; 1955 1956 if (!psp->rap_context.context.initialized) 1957 return 0; 1958 1959 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1960 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1961 return -EINVAL; 1962 1963 mutex_lock(&psp->rap_context.mutex); 1964 1965 rap_cmd = (struct ta_rap_shared_memory *) 1966 psp->rap_context.context.mem_context.shared_buf; 1967 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1968 1969 rap_cmd->cmd_id = ta_cmd_id; 1970 rap_cmd->validation_method_id = METHOD_A; 1971 1972 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1973 if (ret) 1974 goto out_unlock; 1975 1976 if (status) 1977 *status = rap_cmd->rap_status; 1978 1979 out_unlock: 1980 mutex_unlock(&psp->rap_context.mutex); 1981 1982 return ret; 1983 } 1984 // RAP end 1985 1986 /* securedisplay start */ 1987 static int psp_securedisplay_initialize(struct psp_context *psp) 1988 { 1989 int ret; 1990 struct ta_securedisplay_cmd *securedisplay_cmd; 1991 1992 /* 1993 * TODO: bypass the initialize in sriov for now 1994 */ 1995 if (amdgpu_sriov_vf(psp->adev)) 1996 return 0; 1997 1998 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1999 !psp->securedisplay_context.context.bin_desc.start_addr) { 2000 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 2001 return 0; 2002 } 2003 2004 psp->securedisplay_context.context.mem_context.shared_mem_size = 2005 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2006 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2007 2008 if (!psp->securedisplay_context.context.initialized) { 2009 ret = psp_ta_init_shared_buf(psp, 2010 &psp->securedisplay_context.context.mem_context); 2011 if (ret) 2012 return ret; 2013 } 2014 2015 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2016 if (!ret) { 2017 psp->securedisplay_context.context.initialized = true; 2018 mutex_init(&psp->securedisplay_context.mutex); 2019 } else 2020 return ret; 2021 2022 mutex_lock(&psp->securedisplay_context.mutex); 2023 2024 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2025 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2026 2027 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2028 2029 mutex_unlock(&psp->securedisplay_context.mutex); 2030 2031 if (ret) { 2032 psp_securedisplay_terminate(psp); 2033 /* free securedisplay shared memory */ 2034 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2035 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2036 return -EINVAL; 2037 } 2038 2039 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2040 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2041 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2042 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2043 } 2044 2045 return 0; 2046 } 2047 2048 static int psp_securedisplay_terminate(struct psp_context *psp) 2049 { 2050 int ret; 2051 2052 /* 2053 * TODO:bypass the terminate in sriov for now 2054 */ 2055 if (amdgpu_sriov_vf(psp->adev)) 2056 return 0; 2057 2058 if (!psp->securedisplay_context.context.initialized) 2059 return 0; 2060 2061 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2062 2063 psp->securedisplay_context.context.initialized = false; 2064 2065 return ret; 2066 } 2067 2068 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2069 { 2070 int ret; 2071 2072 if (!psp->securedisplay_context.context.initialized) 2073 return -EINVAL; 2074 2075 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2076 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2077 return -EINVAL; 2078 2079 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2080 2081 return ret; 2082 } 2083 /* SECUREDISPLAY end */ 2084 2085 static int psp_hw_start(struct psp_context *psp) 2086 { 2087 struct amdgpu_device *adev = psp->adev; 2088 int ret; 2089 2090 if (!amdgpu_sriov_vf(adev)) { 2091 if ((is_psp_fw_valid(psp->kdb)) && 2092 (psp->funcs->bootloader_load_kdb != NULL)) { 2093 ret = psp_bootloader_load_kdb(psp); 2094 if (ret) { 2095 DRM_ERROR("PSP load kdb failed!\n"); 2096 return ret; 2097 } 2098 } 2099 2100 if ((is_psp_fw_valid(psp->spl)) && 2101 (psp->funcs->bootloader_load_spl != NULL)) { 2102 ret = psp_bootloader_load_spl(psp); 2103 if (ret) { 2104 DRM_ERROR("PSP load spl failed!\n"); 2105 return ret; 2106 } 2107 } 2108 2109 if ((is_psp_fw_valid(psp->sys)) && 2110 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2111 ret = psp_bootloader_load_sysdrv(psp); 2112 if (ret) { 2113 DRM_ERROR("PSP load sys drv failed!\n"); 2114 return ret; 2115 } 2116 } 2117 2118 if ((is_psp_fw_valid(psp->soc_drv)) && 2119 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2120 ret = psp_bootloader_load_soc_drv(psp); 2121 if (ret) { 2122 DRM_ERROR("PSP load soc drv failed!\n"); 2123 return ret; 2124 } 2125 } 2126 2127 if ((is_psp_fw_valid(psp->intf_drv)) && 2128 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2129 ret = psp_bootloader_load_intf_drv(psp); 2130 if (ret) { 2131 DRM_ERROR("PSP load intf drv failed!\n"); 2132 return ret; 2133 } 2134 } 2135 2136 if ((is_psp_fw_valid(psp->dbg_drv)) && 2137 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2138 ret = psp_bootloader_load_dbg_drv(psp); 2139 if (ret) { 2140 DRM_ERROR("PSP load dbg drv failed!\n"); 2141 return ret; 2142 } 2143 } 2144 2145 if ((is_psp_fw_valid(psp->ras_drv)) && 2146 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2147 ret = psp_bootloader_load_ras_drv(psp); 2148 if (ret) { 2149 DRM_ERROR("PSP load ras_drv failed!\n"); 2150 return ret; 2151 } 2152 } 2153 2154 if ((is_psp_fw_valid(psp->sos)) && 2155 (psp->funcs->bootloader_load_sos != NULL)) { 2156 ret = psp_bootloader_load_sos(psp); 2157 if (ret) { 2158 DRM_ERROR("PSP load sos failed!\n"); 2159 return ret; 2160 } 2161 } 2162 } 2163 2164 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2165 if (ret) { 2166 DRM_ERROR("PSP create ring failed!\n"); 2167 return ret; 2168 } 2169 2170 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2171 goto skip_pin_bo; 2172 2173 if (!psp_boottime_tmr(psp)) { 2174 ret = psp_tmr_init(psp); 2175 if (ret) { 2176 DRM_ERROR("PSP tmr init failed!\n"); 2177 return ret; 2178 } 2179 } 2180 2181 skip_pin_bo: 2182 /* 2183 * For ASICs with DF Cstate management centralized 2184 * to PMFW, TMR setup should be performed after PMFW 2185 * loaded and before other non-psp firmware loaded. 2186 */ 2187 if (psp->pmfw_centralized_cstate_management) { 2188 ret = psp_load_smu_fw(psp); 2189 if (ret) 2190 return ret; 2191 } 2192 2193 ret = psp_tmr_load(psp); 2194 if (ret) { 2195 DRM_ERROR("PSP load tmr failed!\n"); 2196 return ret; 2197 } 2198 2199 return 0; 2200 } 2201 2202 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2203 enum psp_gfx_fw_type *type) 2204 { 2205 switch (ucode->ucode_id) { 2206 case AMDGPU_UCODE_ID_CAP: 2207 *type = GFX_FW_TYPE_CAP; 2208 break; 2209 case AMDGPU_UCODE_ID_SDMA0: 2210 *type = GFX_FW_TYPE_SDMA0; 2211 break; 2212 case AMDGPU_UCODE_ID_SDMA1: 2213 *type = GFX_FW_TYPE_SDMA1; 2214 break; 2215 case AMDGPU_UCODE_ID_SDMA2: 2216 *type = GFX_FW_TYPE_SDMA2; 2217 break; 2218 case AMDGPU_UCODE_ID_SDMA3: 2219 *type = GFX_FW_TYPE_SDMA3; 2220 break; 2221 case AMDGPU_UCODE_ID_SDMA4: 2222 *type = GFX_FW_TYPE_SDMA4; 2223 break; 2224 case AMDGPU_UCODE_ID_SDMA5: 2225 *type = GFX_FW_TYPE_SDMA5; 2226 break; 2227 case AMDGPU_UCODE_ID_SDMA6: 2228 *type = GFX_FW_TYPE_SDMA6; 2229 break; 2230 case AMDGPU_UCODE_ID_SDMA7: 2231 *type = GFX_FW_TYPE_SDMA7; 2232 break; 2233 case AMDGPU_UCODE_ID_CP_MES: 2234 *type = GFX_FW_TYPE_CP_MES; 2235 break; 2236 case AMDGPU_UCODE_ID_CP_MES_DATA: 2237 *type = GFX_FW_TYPE_MES_STACK; 2238 break; 2239 case AMDGPU_UCODE_ID_CP_MES1: 2240 *type = GFX_FW_TYPE_CP_MES_KIQ; 2241 break; 2242 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2243 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2244 break; 2245 case AMDGPU_UCODE_ID_CP_CE: 2246 *type = GFX_FW_TYPE_CP_CE; 2247 break; 2248 case AMDGPU_UCODE_ID_CP_PFP: 2249 *type = GFX_FW_TYPE_CP_PFP; 2250 break; 2251 case AMDGPU_UCODE_ID_CP_ME: 2252 *type = GFX_FW_TYPE_CP_ME; 2253 break; 2254 case AMDGPU_UCODE_ID_CP_MEC1: 2255 *type = GFX_FW_TYPE_CP_MEC; 2256 break; 2257 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2258 *type = GFX_FW_TYPE_CP_MEC_ME1; 2259 break; 2260 case AMDGPU_UCODE_ID_CP_MEC2: 2261 *type = GFX_FW_TYPE_CP_MEC; 2262 break; 2263 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2264 *type = GFX_FW_TYPE_CP_MEC_ME2; 2265 break; 2266 case AMDGPU_UCODE_ID_RLC_P: 2267 *type = GFX_FW_TYPE_RLC_P; 2268 break; 2269 case AMDGPU_UCODE_ID_RLC_V: 2270 *type = GFX_FW_TYPE_RLC_V; 2271 break; 2272 case AMDGPU_UCODE_ID_RLC_G: 2273 *type = GFX_FW_TYPE_RLC_G; 2274 break; 2275 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2276 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2277 break; 2278 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2279 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2280 break; 2281 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2282 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2283 break; 2284 case AMDGPU_UCODE_ID_RLC_IRAM: 2285 *type = GFX_FW_TYPE_RLC_IRAM; 2286 break; 2287 case AMDGPU_UCODE_ID_RLC_DRAM: 2288 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2289 break; 2290 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2291 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2292 break; 2293 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2294 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2295 break; 2296 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2297 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2298 break; 2299 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2300 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2301 break; 2302 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2303 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2304 break; 2305 case AMDGPU_UCODE_ID_SMC: 2306 *type = GFX_FW_TYPE_SMU; 2307 break; 2308 case AMDGPU_UCODE_ID_PPTABLE: 2309 *type = GFX_FW_TYPE_PPTABLE; 2310 break; 2311 case AMDGPU_UCODE_ID_UVD: 2312 *type = GFX_FW_TYPE_UVD; 2313 break; 2314 case AMDGPU_UCODE_ID_UVD1: 2315 *type = GFX_FW_TYPE_UVD1; 2316 break; 2317 case AMDGPU_UCODE_ID_VCE: 2318 *type = GFX_FW_TYPE_VCE; 2319 break; 2320 case AMDGPU_UCODE_ID_VCN: 2321 *type = GFX_FW_TYPE_VCN; 2322 break; 2323 case AMDGPU_UCODE_ID_VCN1: 2324 *type = GFX_FW_TYPE_VCN1; 2325 break; 2326 case AMDGPU_UCODE_ID_DMCU_ERAM: 2327 *type = GFX_FW_TYPE_DMCU_ERAM; 2328 break; 2329 case AMDGPU_UCODE_ID_DMCU_INTV: 2330 *type = GFX_FW_TYPE_DMCU_ISR; 2331 break; 2332 case AMDGPU_UCODE_ID_VCN0_RAM: 2333 *type = GFX_FW_TYPE_VCN0_RAM; 2334 break; 2335 case AMDGPU_UCODE_ID_VCN1_RAM: 2336 *type = GFX_FW_TYPE_VCN1_RAM; 2337 break; 2338 case AMDGPU_UCODE_ID_DMCUB: 2339 *type = GFX_FW_TYPE_DMUB; 2340 break; 2341 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2342 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2343 break; 2344 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2345 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2346 break; 2347 case AMDGPU_UCODE_ID_IMU_I: 2348 *type = GFX_FW_TYPE_IMU_I; 2349 break; 2350 case AMDGPU_UCODE_ID_IMU_D: 2351 *type = GFX_FW_TYPE_IMU_D; 2352 break; 2353 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2354 *type = GFX_FW_TYPE_RS64_PFP; 2355 break; 2356 case AMDGPU_UCODE_ID_CP_RS64_ME: 2357 *type = GFX_FW_TYPE_RS64_ME; 2358 break; 2359 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2360 *type = GFX_FW_TYPE_RS64_MEC; 2361 break; 2362 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2363 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2364 break; 2365 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2366 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2367 break; 2368 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2369 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2370 break; 2371 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2372 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2373 break; 2374 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2375 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2376 break; 2377 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2378 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2379 break; 2380 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2381 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2382 break; 2383 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2384 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2385 break; 2386 case AMDGPU_UCODE_ID_MAXIMUM: 2387 default: 2388 return -EINVAL; 2389 } 2390 2391 return 0; 2392 } 2393 2394 static void psp_print_fw_hdr(struct psp_context *psp, 2395 struct amdgpu_firmware_info *ucode) 2396 { 2397 struct amdgpu_device *adev = psp->adev; 2398 struct common_firmware_header *hdr; 2399 2400 switch (ucode->ucode_id) { 2401 case AMDGPU_UCODE_ID_SDMA0: 2402 case AMDGPU_UCODE_ID_SDMA1: 2403 case AMDGPU_UCODE_ID_SDMA2: 2404 case AMDGPU_UCODE_ID_SDMA3: 2405 case AMDGPU_UCODE_ID_SDMA4: 2406 case AMDGPU_UCODE_ID_SDMA5: 2407 case AMDGPU_UCODE_ID_SDMA6: 2408 case AMDGPU_UCODE_ID_SDMA7: 2409 hdr = (struct common_firmware_header *) 2410 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2411 amdgpu_ucode_print_sdma_hdr(hdr); 2412 break; 2413 case AMDGPU_UCODE_ID_CP_CE: 2414 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2415 amdgpu_ucode_print_gfx_hdr(hdr); 2416 break; 2417 case AMDGPU_UCODE_ID_CP_PFP: 2418 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2419 amdgpu_ucode_print_gfx_hdr(hdr); 2420 break; 2421 case AMDGPU_UCODE_ID_CP_ME: 2422 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2423 amdgpu_ucode_print_gfx_hdr(hdr); 2424 break; 2425 case AMDGPU_UCODE_ID_CP_MEC1: 2426 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2427 amdgpu_ucode_print_gfx_hdr(hdr); 2428 break; 2429 case AMDGPU_UCODE_ID_RLC_G: 2430 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2431 amdgpu_ucode_print_rlc_hdr(hdr); 2432 break; 2433 case AMDGPU_UCODE_ID_SMC: 2434 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2435 amdgpu_ucode_print_smc_hdr(hdr); 2436 break; 2437 default: 2438 break; 2439 } 2440 } 2441 2442 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2443 struct psp_gfx_cmd_resp *cmd) 2444 { 2445 int ret; 2446 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2447 2448 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2449 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2450 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2451 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2452 2453 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2454 if (ret) 2455 DRM_ERROR("Unknown firmware type\n"); 2456 2457 return ret; 2458 } 2459 2460 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2461 struct amdgpu_firmware_info *ucode) 2462 { 2463 int ret = 0; 2464 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2465 2466 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2467 if (!ret) { 2468 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2469 psp->fence_buf_mc_addr); 2470 } 2471 2472 release_psp_cmd_buf(psp); 2473 2474 return ret; 2475 } 2476 2477 static int psp_load_smu_fw(struct psp_context *psp) 2478 { 2479 int ret; 2480 struct amdgpu_device *adev = psp->adev; 2481 struct amdgpu_firmware_info *ucode = 2482 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2483 struct amdgpu_ras *ras = psp->ras_context.ras; 2484 2485 /* 2486 * Skip SMU FW reloading in case of using BACO for runpm only, 2487 * as SMU is always alive. 2488 */ 2489 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2490 return 0; 2491 2492 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2493 return 0; 2494 2495 if ((amdgpu_in_reset(adev) && 2496 ras && adev->ras_enabled && 2497 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2498 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2499 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2500 if (ret) 2501 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2502 } 2503 2504 ret = psp_execute_non_psp_fw_load(psp, ucode); 2505 2506 if (ret) 2507 DRM_ERROR("PSP load smu failed!\n"); 2508 2509 return ret; 2510 } 2511 2512 static bool fw_load_skip_check(struct psp_context *psp, 2513 struct amdgpu_firmware_info *ucode) 2514 { 2515 if (!ucode->fw || !ucode->ucode_size) 2516 return true; 2517 2518 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2519 (psp_smu_reload_quirk(psp) || 2520 psp->autoload_supported || 2521 psp->pmfw_centralized_cstate_management)) 2522 return true; 2523 2524 if (amdgpu_sriov_vf(psp->adev) && 2525 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2526 return true; 2527 2528 if (psp->autoload_supported && 2529 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2530 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2531 /* skip mec JT when autoload is enabled */ 2532 return true; 2533 2534 return false; 2535 } 2536 2537 int psp_load_fw_list(struct psp_context *psp, 2538 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2539 { 2540 int ret = 0, i; 2541 struct amdgpu_firmware_info *ucode; 2542 2543 for (i = 0; i < ucode_count; ++i) { 2544 ucode = ucode_list[i]; 2545 psp_print_fw_hdr(psp, ucode); 2546 ret = psp_execute_non_psp_fw_load(psp, ucode); 2547 if (ret) 2548 return ret; 2549 } 2550 return ret; 2551 } 2552 2553 static int psp_load_non_psp_fw(struct psp_context *psp) 2554 { 2555 int i, ret; 2556 struct amdgpu_firmware_info *ucode; 2557 struct amdgpu_device *adev = psp->adev; 2558 2559 if (psp->autoload_supported && 2560 !psp->pmfw_centralized_cstate_management) { 2561 ret = psp_load_smu_fw(psp); 2562 if (ret) 2563 return ret; 2564 } 2565 2566 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2567 ucode = &adev->firmware.ucode[i]; 2568 2569 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2570 !fw_load_skip_check(psp, ucode)) { 2571 ret = psp_load_smu_fw(psp); 2572 if (ret) 2573 return ret; 2574 continue; 2575 } 2576 2577 if (fw_load_skip_check(psp, ucode)) 2578 continue; 2579 2580 if (psp->autoload_supported && 2581 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2582 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2583 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2584 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2585 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2586 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2587 /* PSP only receive one SDMA fw for sienna_cichlid, 2588 * as all four sdma fw are same */ 2589 continue; 2590 2591 psp_print_fw_hdr(psp, ucode); 2592 2593 ret = psp_execute_non_psp_fw_load(psp, ucode); 2594 if (ret) 2595 return ret; 2596 2597 /* Start rlc autoload after psp recieved all the gfx firmware */ 2598 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2599 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2600 ret = psp_rlc_autoload_start(psp); 2601 if (ret) { 2602 DRM_ERROR("Failed to start rlc autoload\n"); 2603 return ret; 2604 } 2605 } 2606 } 2607 2608 return 0; 2609 } 2610 2611 static int psp_load_fw(struct amdgpu_device *adev) 2612 { 2613 int ret; 2614 struct psp_context *psp = &adev->psp; 2615 2616 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2617 /* should not destroy ring, only stop */ 2618 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2619 } else { 2620 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2621 2622 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2623 if (ret) { 2624 DRM_ERROR("PSP ring init failed!\n"); 2625 goto failed; 2626 } 2627 } 2628 2629 ret = psp_hw_start(psp); 2630 if (ret) 2631 goto failed; 2632 2633 ret = psp_load_non_psp_fw(psp); 2634 if (ret) 2635 goto failed1; 2636 2637 ret = psp_asd_initialize(psp); 2638 if (ret) { 2639 DRM_ERROR("PSP load asd failed!\n"); 2640 goto failed1; 2641 } 2642 2643 ret = psp_rl_load(adev); 2644 if (ret) { 2645 DRM_ERROR("PSP load RL failed!\n"); 2646 goto failed1; 2647 } 2648 2649 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2650 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2651 ret = psp_xgmi_initialize(psp, false, true); 2652 /* Warning the XGMI seesion initialize failure 2653 * Instead of stop driver initialization 2654 */ 2655 if (ret) 2656 dev_err(psp->adev->dev, 2657 "XGMI: Failed to initialize XGMI session\n"); 2658 } 2659 } 2660 2661 if (psp->ta_fw) { 2662 ret = psp_ras_initialize(psp); 2663 if (ret) 2664 dev_err(psp->adev->dev, 2665 "RAS: Failed to initialize RAS\n"); 2666 2667 ret = psp_hdcp_initialize(psp); 2668 if (ret) 2669 dev_err(psp->adev->dev, 2670 "HDCP: Failed to initialize HDCP\n"); 2671 2672 ret = psp_dtm_initialize(psp); 2673 if (ret) 2674 dev_err(psp->adev->dev, 2675 "DTM: Failed to initialize DTM\n"); 2676 2677 ret = psp_rap_initialize(psp); 2678 if (ret) 2679 dev_err(psp->adev->dev, 2680 "RAP: Failed to initialize RAP\n"); 2681 2682 ret = psp_securedisplay_initialize(psp); 2683 if (ret) 2684 dev_err(psp->adev->dev, 2685 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2686 } 2687 2688 return 0; 2689 2690 failed1: 2691 psp_free_shared_bufs(psp); 2692 failed: 2693 /* 2694 * all cleanup jobs (xgmi terminate, ras terminate, 2695 * ring destroy, cmd/fence/fw buffers destory, 2696 * psp->cmd destory) are delayed to psp_hw_fini 2697 */ 2698 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2699 return ret; 2700 } 2701 2702 static int psp_hw_init(void *handle) 2703 { 2704 int ret; 2705 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2706 2707 mutex_lock(&adev->firmware.mutex); 2708 /* 2709 * This sequence is just used on hw_init only once, no need on 2710 * resume. 2711 */ 2712 ret = amdgpu_ucode_init_bo(adev); 2713 if (ret) 2714 goto failed; 2715 2716 ret = psp_load_fw(adev); 2717 if (ret) { 2718 DRM_ERROR("PSP firmware loading failed\n"); 2719 goto failed; 2720 } 2721 2722 mutex_unlock(&adev->firmware.mutex); 2723 return 0; 2724 2725 failed: 2726 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2727 mutex_unlock(&adev->firmware.mutex); 2728 return -EINVAL; 2729 } 2730 2731 static int psp_hw_fini(void *handle) 2732 { 2733 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2734 struct psp_context *psp = &adev->psp; 2735 2736 if (psp->ta_fw) { 2737 psp_ras_terminate(psp); 2738 psp_securedisplay_terminate(psp); 2739 psp_rap_terminate(psp); 2740 psp_dtm_terminate(psp); 2741 psp_hdcp_terminate(psp); 2742 2743 if (adev->gmc.xgmi.num_physical_nodes > 1) 2744 psp_xgmi_terminate(psp); 2745 } 2746 2747 psp_asd_terminate(psp); 2748 psp_tmr_terminate(psp); 2749 2750 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2751 2752 return 0; 2753 } 2754 2755 static int psp_suspend(void *handle) 2756 { 2757 int ret = 0; 2758 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2759 struct psp_context *psp = &adev->psp; 2760 2761 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2762 psp->xgmi_context.context.initialized) { 2763 ret = psp_xgmi_terminate(psp); 2764 if (ret) { 2765 DRM_ERROR("Failed to terminate xgmi ta\n"); 2766 goto out; 2767 } 2768 } 2769 2770 if (psp->ta_fw) { 2771 ret = psp_ras_terminate(psp); 2772 if (ret) { 2773 DRM_ERROR("Failed to terminate ras ta\n"); 2774 goto out; 2775 } 2776 ret = psp_hdcp_terminate(psp); 2777 if (ret) { 2778 DRM_ERROR("Failed to terminate hdcp ta\n"); 2779 goto out; 2780 } 2781 ret = psp_dtm_terminate(psp); 2782 if (ret) { 2783 DRM_ERROR("Failed to terminate dtm ta\n"); 2784 goto out; 2785 } 2786 ret = psp_rap_terminate(psp); 2787 if (ret) { 2788 DRM_ERROR("Failed to terminate rap ta\n"); 2789 goto out; 2790 } 2791 ret = psp_securedisplay_terminate(psp); 2792 if (ret) { 2793 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2794 goto out; 2795 } 2796 } 2797 2798 ret = psp_asd_terminate(psp); 2799 if (ret) { 2800 DRM_ERROR("Failed to terminate asd\n"); 2801 goto out; 2802 } 2803 2804 ret = psp_tmr_terminate(psp); 2805 if (ret) { 2806 DRM_ERROR("Failed to terminate tmr\n"); 2807 goto out; 2808 } 2809 2810 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2811 if (ret) 2812 DRM_ERROR("PSP ring stop failed\n"); 2813 2814 out: 2815 return ret; 2816 } 2817 2818 static int psp_resume(void *handle) 2819 { 2820 int ret; 2821 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2822 struct psp_context *psp = &adev->psp; 2823 2824 DRM_INFO("PSP is resuming...\n"); 2825 2826 if (psp->mem_train_ctx.enable_mem_training) { 2827 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2828 if (ret) { 2829 DRM_ERROR("Failed to process memory training!\n"); 2830 return ret; 2831 } 2832 } 2833 2834 mutex_lock(&adev->firmware.mutex); 2835 2836 ret = psp_hw_start(psp); 2837 if (ret) 2838 goto failed; 2839 2840 ret = psp_load_non_psp_fw(psp); 2841 if (ret) 2842 goto failed; 2843 2844 ret = psp_asd_initialize(psp); 2845 if (ret) { 2846 DRM_ERROR("PSP load asd failed!\n"); 2847 goto failed; 2848 } 2849 2850 ret = psp_rl_load(adev); 2851 if (ret) { 2852 dev_err(adev->dev, "PSP load RL failed!\n"); 2853 goto failed; 2854 } 2855 2856 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2857 ret = psp_xgmi_initialize(psp, false, true); 2858 /* Warning the XGMI seesion initialize failure 2859 * Instead of stop driver initialization 2860 */ 2861 if (ret) 2862 dev_err(psp->adev->dev, 2863 "XGMI: Failed to initialize XGMI session\n"); 2864 } 2865 2866 if (psp->ta_fw) { 2867 ret = psp_ras_initialize(psp); 2868 if (ret) 2869 dev_err(psp->adev->dev, 2870 "RAS: Failed to initialize RAS\n"); 2871 2872 ret = psp_hdcp_initialize(psp); 2873 if (ret) 2874 dev_err(psp->adev->dev, 2875 "HDCP: Failed to initialize HDCP\n"); 2876 2877 ret = psp_dtm_initialize(psp); 2878 if (ret) 2879 dev_err(psp->adev->dev, 2880 "DTM: Failed to initialize DTM\n"); 2881 2882 ret = psp_rap_initialize(psp); 2883 if (ret) 2884 dev_err(psp->adev->dev, 2885 "RAP: Failed to initialize RAP\n"); 2886 2887 ret = psp_securedisplay_initialize(psp); 2888 if (ret) 2889 dev_err(psp->adev->dev, 2890 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2891 } 2892 2893 mutex_unlock(&adev->firmware.mutex); 2894 2895 return 0; 2896 2897 failed: 2898 DRM_ERROR("PSP resume failed\n"); 2899 mutex_unlock(&adev->firmware.mutex); 2900 return ret; 2901 } 2902 2903 int psp_gpu_reset(struct amdgpu_device *adev) 2904 { 2905 int ret; 2906 2907 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2908 return 0; 2909 2910 mutex_lock(&adev->psp.mutex); 2911 ret = psp_mode1_reset(&adev->psp); 2912 mutex_unlock(&adev->psp.mutex); 2913 2914 return ret; 2915 } 2916 2917 int psp_rlc_autoload_start(struct psp_context *psp) 2918 { 2919 int ret; 2920 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2921 2922 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2923 2924 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2925 psp->fence_buf_mc_addr); 2926 2927 release_psp_cmd_buf(psp); 2928 2929 return ret; 2930 } 2931 2932 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2933 uint64_t cmd_gpu_addr, int cmd_size) 2934 { 2935 struct amdgpu_firmware_info ucode = {0}; 2936 2937 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2938 AMDGPU_UCODE_ID_VCN0_RAM; 2939 ucode.mc_addr = cmd_gpu_addr; 2940 ucode.ucode_size = cmd_size; 2941 2942 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2943 } 2944 2945 int psp_ring_cmd_submit(struct psp_context *psp, 2946 uint64_t cmd_buf_mc_addr, 2947 uint64_t fence_mc_addr, 2948 int index) 2949 { 2950 unsigned int psp_write_ptr_reg = 0; 2951 struct psp_gfx_rb_frame *write_frame; 2952 struct psp_ring *ring = &psp->km_ring; 2953 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2954 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2955 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2956 struct amdgpu_device *adev = psp->adev; 2957 uint32_t ring_size_dw = ring->ring_size / 4; 2958 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2959 2960 /* KM (GPCOM) prepare write pointer */ 2961 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2962 2963 /* Update KM RB frame pointer to new frame */ 2964 /* write_frame ptr increments by size of rb_frame in bytes */ 2965 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2966 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2967 write_frame = ring_buffer_start; 2968 else 2969 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2970 /* Check invalid write_frame ptr address */ 2971 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2972 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2973 ring_buffer_start, ring_buffer_end, write_frame); 2974 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2975 return -EINVAL; 2976 } 2977 2978 /* Initialize KM RB frame */ 2979 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2980 2981 /* Update KM RB frame */ 2982 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2983 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2984 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2985 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2986 write_frame->fence_value = index; 2987 amdgpu_device_flush_hdp(adev, NULL); 2988 2989 /* Update the write Pointer in DWORDs */ 2990 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2991 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2992 return 0; 2993 } 2994 2995 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 2996 { 2997 struct amdgpu_device *adev = psp->adev; 2998 char fw_name[PSP_FW_NAME_LEN]; 2999 const struct psp_firmware_header_v1_0 *asd_hdr; 3000 int err = 0; 3001 3002 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 3003 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name); 3004 if (err) 3005 goto out; 3006 3007 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3008 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3009 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3010 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3011 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 3012 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3013 return 0; 3014 out: 3015 amdgpu_ucode_release(&adev->psp.asd_fw); 3016 return err; 3017 } 3018 3019 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3020 { 3021 struct amdgpu_device *adev = psp->adev; 3022 char fw_name[PSP_FW_NAME_LEN]; 3023 const struct psp_firmware_header_v1_0 *toc_hdr; 3024 int err = 0; 3025 3026 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 3027 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 3028 if (err) 3029 goto out; 3030 3031 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3032 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3033 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3034 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3035 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3036 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3037 return 0; 3038 out: 3039 amdgpu_ucode_release(&adev->psp.toc_fw); 3040 return err; 3041 } 3042 3043 static int parse_sos_bin_descriptor(struct psp_context *psp, 3044 const struct psp_fw_bin_desc *desc, 3045 const struct psp_firmware_header_v2_0 *sos_hdr) 3046 { 3047 uint8_t *ucode_start_addr = NULL; 3048 3049 if (!psp || !desc || !sos_hdr) 3050 return -EINVAL; 3051 3052 ucode_start_addr = (uint8_t *)sos_hdr + 3053 le32_to_cpu(desc->offset_bytes) + 3054 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3055 3056 switch (desc->fw_type) { 3057 case PSP_FW_TYPE_PSP_SOS: 3058 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3059 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3060 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3061 psp->sos.start_addr = ucode_start_addr; 3062 break; 3063 case PSP_FW_TYPE_PSP_SYS_DRV: 3064 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3065 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3066 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3067 psp->sys.start_addr = ucode_start_addr; 3068 break; 3069 case PSP_FW_TYPE_PSP_KDB: 3070 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3071 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3072 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3073 psp->kdb.start_addr = ucode_start_addr; 3074 break; 3075 case PSP_FW_TYPE_PSP_TOC: 3076 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3077 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3078 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3079 psp->toc.start_addr = ucode_start_addr; 3080 break; 3081 case PSP_FW_TYPE_PSP_SPL: 3082 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3083 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3084 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3085 psp->spl.start_addr = ucode_start_addr; 3086 break; 3087 case PSP_FW_TYPE_PSP_RL: 3088 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3089 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3090 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3091 psp->rl.start_addr = ucode_start_addr; 3092 break; 3093 case PSP_FW_TYPE_PSP_SOC_DRV: 3094 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3095 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3096 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3097 psp->soc_drv.start_addr = ucode_start_addr; 3098 break; 3099 case PSP_FW_TYPE_PSP_INTF_DRV: 3100 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3101 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3102 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3103 psp->intf_drv.start_addr = ucode_start_addr; 3104 break; 3105 case PSP_FW_TYPE_PSP_DBG_DRV: 3106 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3107 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3108 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3109 psp->dbg_drv.start_addr = ucode_start_addr; 3110 break; 3111 case PSP_FW_TYPE_PSP_RAS_DRV: 3112 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3113 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3114 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3115 psp->ras_drv.start_addr = ucode_start_addr; 3116 break; 3117 default: 3118 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3119 break; 3120 } 3121 3122 return 0; 3123 } 3124 3125 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3126 { 3127 const struct psp_firmware_header_v1_0 *sos_hdr; 3128 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3129 uint8_t *ucode_array_start_addr; 3130 3131 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3132 ucode_array_start_addr = (uint8_t *)sos_hdr + 3133 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3134 3135 if (adev->gmc.xgmi.connected_to_cpu || 3136 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3137 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3138 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3139 3140 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3141 adev->psp.sys.start_addr = ucode_array_start_addr; 3142 3143 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3144 adev->psp.sos.start_addr = ucode_array_start_addr + 3145 le32_to_cpu(sos_hdr->sos.offset_bytes); 3146 } else { 3147 /* Load alternate PSP SOS FW */ 3148 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3149 3150 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3151 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3152 3153 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3154 adev->psp.sys.start_addr = ucode_array_start_addr + 3155 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3156 3157 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3158 adev->psp.sos.start_addr = ucode_array_start_addr + 3159 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3160 } 3161 3162 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3163 dev_warn(adev->dev, "PSP SOS FW not available"); 3164 return -EINVAL; 3165 } 3166 3167 return 0; 3168 } 3169 3170 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3171 { 3172 struct amdgpu_device *adev = psp->adev; 3173 char fw_name[PSP_FW_NAME_LEN]; 3174 const struct psp_firmware_header_v1_0 *sos_hdr; 3175 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3176 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3177 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3178 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3179 int err = 0; 3180 uint8_t *ucode_array_start_addr; 3181 int fw_index = 0; 3182 3183 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3184 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name); 3185 if (err) 3186 goto out; 3187 3188 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3189 ucode_array_start_addr = (uint8_t *)sos_hdr + 3190 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3191 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3192 3193 switch (sos_hdr->header.header_version_major) { 3194 case 1: 3195 err = psp_init_sos_base_fw(adev); 3196 if (err) 3197 goto out; 3198 3199 if (sos_hdr->header.header_version_minor == 1) { 3200 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3201 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3202 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3203 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3204 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3205 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3206 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3207 } 3208 if (sos_hdr->header.header_version_minor == 2) { 3209 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3210 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3211 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3212 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3213 } 3214 if (sos_hdr->header.header_version_minor == 3) { 3215 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3216 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3217 adev->psp.toc.start_addr = ucode_array_start_addr + 3218 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3219 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3220 adev->psp.kdb.start_addr = ucode_array_start_addr + 3221 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3222 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3223 adev->psp.spl.start_addr = ucode_array_start_addr + 3224 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3225 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3226 adev->psp.rl.start_addr = ucode_array_start_addr + 3227 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3228 } 3229 break; 3230 case 2: 3231 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3232 3233 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3234 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3235 err = -EINVAL; 3236 goto out; 3237 } 3238 3239 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3240 err = parse_sos_bin_descriptor(psp, 3241 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3242 sos_hdr_v2_0); 3243 if (err) 3244 goto out; 3245 } 3246 break; 3247 default: 3248 dev_err(adev->dev, 3249 "unsupported psp sos firmware\n"); 3250 err = -EINVAL; 3251 goto out; 3252 } 3253 3254 return 0; 3255 out: 3256 amdgpu_ucode_release(&adev->psp.sos_fw); 3257 3258 return err; 3259 } 3260 3261 static int parse_ta_bin_descriptor(struct psp_context *psp, 3262 const struct psp_fw_bin_desc *desc, 3263 const struct ta_firmware_header_v2_0 *ta_hdr) 3264 { 3265 uint8_t *ucode_start_addr = NULL; 3266 3267 if (!psp || !desc || !ta_hdr) 3268 return -EINVAL; 3269 3270 ucode_start_addr = (uint8_t *)ta_hdr + 3271 le32_to_cpu(desc->offset_bytes) + 3272 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3273 3274 switch (desc->fw_type) { 3275 case TA_FW_TYPE_PSP_ASD: 3276 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3277 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3278 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3279 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3280 break; 3281 case TA_FW_TYPE_PSP_XGMI: 3282 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3283 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3284 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3285 break; 3286 case TA_FW_TYPE_PSP_RAS: 3287 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3288 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3289 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3290 break; 3291 case TA_FW_TYPE_PSP_HDCP: 3292 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3293 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3294 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3295 break; 3296 case TA_FW_TYPE_PSP_DTM: 3297 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3298 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3299 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3300 break; 3301 case TA_FW_TYPE_PSP_RAP: 3302 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3303 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3304 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3305 break; 3306 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3307 psp->securedisplay_context.context.bin_desc.fw_version = 3308 le32_to_cpu(desc->fw_version); 3309 psp->securedisplay_context.context.bin_desc.size_bytes = 3310 le32_to_cpu(desc->size_bytes); 3311 psp->securedisplay_context.context.bin_desc.start_addr = 3312 ucode_start_addr; 3313 break; 3314 default: 3315 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3316 break; 3317 } 3318 3319 return 0; 3320 } 3321 3322 static int parse_ta_v1_microcode(struct psp_context *psp) 3323 { 3324 const struct ta_firmware_header_v1_0 *ta_hdr; 3325 struct amdgpu_device *adev = psp->adev; 3326 3327 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3328 3329 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3330 return -EINVAL; 3331 3332 adev->psp.xgmi_context.context.bin_desc.fw_version = 3333 le32_to_cpu(ta_hdr->xgmi.fw_version); 3334 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3335 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3336 adev->psp.xgmi_context.context.bin_desc.start_addr = 3337 (uint8_t *)ta_hdr + 3338 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3339 3340 adev->psp.ras_context.context.bin_desc.fw_version = 3341 le32_to_cpu(ta_hdr->ras.fw_version); 3342 adev->psp.ras_context.context.bin_desc.size_bytes = 3343 le32_to_cpu(ta_hdr->ras.size_bytes); 3344 adev->psp.ras_context.context.bin_desc.start_addr = 3345 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3346 le32_to_cpu(ta_hdr->ras.offset_bytes); 3347 3348 adev->psp.hdcp_context.context.bin_desc.fw_version = 3349 le32_to_cpu(ta_hdr->hdcp.fw_version); 3350 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3351 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3352 adev->psp.hdcp_context.context.bin_desc.start_addr = 3353 (uint8_t *)ta_hdr + 3354 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3355 3356 adev->psp.dtm_context.context.bin_desc.fw_version = 3357 le32_to_cpu(ta_hdr->dtm.fw_version); 3358 adev->psp.dtm_context.context.bin_desc.size_bytes = 3359 le32_to_cpu(ta_hdr->dtm.size_bytes); 3360 adev->psp.dtm_context.context.bin_desc.start_addr = 3361 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3362 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3363 3364 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3365 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3366 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3367 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3368 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3369 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3370 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3371 3372 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3373 3374 return 0; 3375 } 3376 3377 static int parse_ta_v2_microcode(struct psp_context *psp) 3378 { 3379 const struct ta_firmware_header_v2_0 *ta_hdr; 3380 struct amdgpu_device *adev = psp->adev; 3381 int err = 0; 3382 int ta_index = 0; 3383 3384 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3385 3386 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3387 return -EINVAL; 3388 3389 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3390 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3391 return -EINVAL; 3392 } 3393 3394 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3395 err = parse_ta_bin_descriptor(psp, 3396 &ta_hdr->ta_fw_bin[ta_index], 3397 ta_hdr); 3398 if (err) 3399 return err; 3400 } 3401 3402 return 0; 3403 } 3404 3405 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3406 { 3407 const struct common_firmware_header *hdr; 3408 struct amdgpu_device *adev = psp->adev; 3409 char fw_name[PSP_FW_NAME_LEN]; 3410 int err; 3411 3412 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3413 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name); 3414 if (err) 3415 return err; 3416 3417 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3418 switch (le16_to_cpu(hdr->header_version_major)) { 3419 case 1: 3420 err = parse_ta_v1_microcode(psp); 3421 break; 3422 case 2: 3423 err = parse_ta_v2_microcode(psp); 3424 break; 3425 default: 3426 dev_err(adev->dev, "unsupported TA header version\n"); 3427 err = -EINVAL; 3428 } 3429 3430 if (err) 3431 amdgpu_ucode_release(&adev->psp.ta_fw); 3432 3433 return err; 3434 } 3435 3436 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 3437 { 3438 struct amdgpu_device *adev = psp->adev; 3439 char fw_name[PSP_FW_NAME_LEN]; 3440 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3441 struct amdgpu_firmware_info *info = NULL; 3442 int err = 0; 3443 3444 if (!amdgpu_sriov_vf(adev)) { 3445 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3446 return -EINVAL; 3447 } 3448 3449 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3450 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name); 3451 if (err) { 3452 if (err == -ENODEV) { 3453 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3454 err = 0; 3455 goto out; 3456 } 3457 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3458 } 3459 3460 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3461 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3462 info->fw = adev->psp.cap_fw; 3463 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3464 adev->psp.cap_fw->data; 3465 adev->firmware.fw_size += ALIGN( 3466 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3467 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3468 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3469 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3470 3471 return 0; 3472 3473 out: 3474 amdgpu_ucode_release(&adev->psp.cap_fw); 3475 return err; 3476 } 3477 3478 static int psp_set_clockgating_state(void *handle, 3479 enum amd_clockgating_state state) 3480 { 3481 return 0; 3482 } 3483 3484 static int psp_set_powergating_state(void *handle, 3485 enum amd_powergating_state state) 3486 { 3487 return 0; 3488 } 3489 3490 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3491 struct device_attribute *attr, 3492 char *buf) 3493 { 3494 struct drm_device *ddev = dev_get_drvdata(dev); 3495 struct amdgpu_device *adev = drm_to_adev(ddev); 3496 uint32_t fw_ver; 3497 int ret; 3498 3499 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3500 DRM_INFO("PSP block is not ready yet."); 3501 return -EBUSY; 3502 } 3503 3504 mutex_lock(&adev->psp.mutex); 3505 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3506 mutex_unlock(&adev->psp.mutex); 3507 3508 if (ret) { 3509 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3510 return ret; 3511 } 3512 3513 return sysfs_emit(buf, "%x\n", fw_ver); 3514 } 3515 3516 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3517 struct device_attribute *attr, 3518 const char *buf, 3519 size_t count) 3520 { 3521 struct drm_device *ddev = dev_get_drvdata(dev); 3522 struct amdgpu_device *adev = drm_to_adev(ddev); 3523 int ret, idx; 3524 char fw_name[100]; 3525 const struct firmware *usbc_pd_fw; 3526 struct amdgpu_bo *fw_buf_bo = NULL; 3527 uint64_t fw_pri_mc_addr; 3528 void *fw_pri_cpu_addr; 3529 3530 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3531 DRM_INFO("PSP block is not ready yet."); 3532 return -EBUSY; 3533 } 3534 3535 if (!drm_dev_enter(ddev, &idx)) 3536 return -ENODEV; 3537 3538 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3539 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3540 if (ret) 3541 goto fail; 3542 3543 /* LFB address which is aligned to 1MB boundary per PSP request */ 3544 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3545 AMDGPU_GEM_DOMAIN_VRAM | 3546 AMDGPU_GEM_DOMAIN_GTT, 3547 &fw_buf_bo, &fw_pri_mc_addr, 3548 &fw_pri_cpu_addr); 3549 if (ret) 3550 goto rel_buf; 3551 3552 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3553 3554 mutex_lock(&adev->psp.mutex); 3555 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3556 mutex_unlock(&adev->psp.mutex); 3557 3558 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3559 3560 rel_buf: 3561 release_firmware(usbc_pd_fw); 3562 fail: 3563 if (ret) { 3564 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3565 count = ret; 3566 } 3567 3568 drm_dev_exit(idx); 3569 return count; 3570 } 3571 3572 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3573 { 3574 int idx; 3575 3576 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3577 return; 3578 3579 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3580 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3581 3582 drm_dev_exit(idx); 3583 } 3584 3585 static DEVICE_ATTR(usbc_pd_fw, 0644, 3586 psp_usbc_pd_fw_sysfs_read, 3587 psp_usbc_pd_fw_sysfs_write); 3588 3589 int is_psp_fw_valid(struct psp_bin_desc bin) 3590 { 3591 return bin.size_bytes; 3592 } 3593 3594 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3595 struct bin_attribute *bin_attr, 3596 char *buffer, loff_t pos, size_t count) 3597 { 3598 struct device *dev = kobj_to_dev(kobj); 3599 struct drm_device *ddev = dev_get_drvdata(dev); 3600 struct amdgpu_device *adev = drm_to_adev(ddev); 3601 3602 adev->psp.vbflash_done = false; 3603 3604 /* Safeguard against memory drain */ 3605 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3606 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3607 kvfree(adev->psp.vbflash_tmp_buf); 3608 adev->psp.vbflash_tmp_buf = NULL; 3609 adev->psp.vbflash_image_size = 0; 3610 return -ENOMEM; 3611 } 3612 3613 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3614 if (!adev->psp.vbflash_tmp_buf) { 3615 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3616 if (!adev->psp.vbflash_tmp_buf) 3617 return -ENOMEM; 3618 } 3619 3620 mutex_lock(&adev->psp.mutex); 3621 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3622 adev->psp.vbflash_image_size += count; 3623 mutex_unlock(&adev->psp.mutex); 3624 3625 dev_info(adev->dev, "VBIOS flash write PSP done"); 3626 3627 return count; 3628 } 3629 3630 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3631 struct bin_attribute *bin_attr, char *buffer, 3632 loff_t pos, size_t count) 3633 { 3634 struct device *dev = kobj_to_dev(kobj); 3635 struct drm_device *ddev = dev_get_drvdata(dev); 3636 struct amdgpu_device *adev = drm_to_adev(ddev); 3637 struct amdgpu_bo *fw_buf_bo = NULL; 3638 uint64_t fw_pri_mc_addr; 3639 void *fw_pri_cpu_addr; 3640 int ret; 3641 3642 if (adev->psp.vbflash_image_size == 0) 3643 return -EINVAL; 3644 3645 dev_info(adev->dev, "VBIOS flash to PSP started"); 3646 3647 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3648 AMDGPU_GPU_PAGE_SIZE, 3649 AMDGPU_GEM_DOMAIN_VRAM, 3650 &fw_buf_bo, 3651 &fw_pri_mc_addr, 3652 &fw_pri_cpu_addr); 3653 if (ret) 3654 goto rel_buf; 3655 3656 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3657 3658 mutex_lock(&adev->psp.mutex); 3659 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3660 mutex_unlock(&adev->psp.mutex); 3661 3662 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3663 3664 rel_buf: 3665 kvfree(adev->psp.vbflash_tmp_buf); 3666 adev->psp.vbflash_tmp_buf = NULL; 3667 adev->psp.vbflash_image_size = 0; 3668 3669 if (ret) { 3670 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret); 3671 return ret; 3672 } 3673 3674 dev_info(adev->dev, "VBIOS flash to PSP done"); 3675 return 0; 3676 } 3677 3678 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3679 struct device_attribute *attr, 3680 char *buf) 3681 { 3682 struct drm_device *ddev = dev_get_drvdata(dev); 3683 struct amdgpu_device *adev = drm_to_adev(ddev); 3684 uint32_t vbflash_status; 3685 3686 vbflash_status = psp_vbflash_status(&adev->psp); 3687 if (!adev->psp.vbflash_done) 3688 vbflash_status = 0; 3689 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3690 vbflash_status = 1; 3691 3692 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3693 } 3694 3695 static const struct bin_attribute psp_vbflash_bin_attr = { 3696 .attr = {.name = "psp_vbflash", .mode = 0660}, 3697 .size = 0, 3698 .write = amdgpu_psp_vbflash_write, 3699 .read = amdgpu_psp_vbflash_read, 3700 }; 3701 3702 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 3703 3704 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev) 3705 { 3706 int ret = 0; 3707 struct psp_context *psp = &adev->psp; 3708 3709 if (amdgpu_sriov_vf(adev)) 3710 return -EINVAL; 3711 3712 switch (adev->ip_versions[MP0_HWIP][0]) { 3713 case IP_VERSION(13, 0, 0): 3714 case IP_VERSION(13, 0, 7): 3715 case IP_VERSION(13, 0, 10): 3716 if (!psp->adev) { 3717 psp->adev = adev; 3718 psp_v13_0_set_psp_funcs(psp); 3719 } 3720 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3721 if (ret) 3722 dev_err(adev->dev, "Failed to create device file psp_vbflash"); 3723 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status); 3724 if (ret) 3725 dev_err(adev->dev, "Failed to create device file psp_vbflash_status"); 3726 return ret; 3727 default: 3728 return 0; 3729 } 3730 } 3731 3732 const struct amd_ip_funcs psp_ip_funcs = { 3733 .name = "psp", 3734 .early_init = psp_early_init, 3735 .late_init = NULL, 3736 .sw_init = psp_sw_init, 3737 .sw_fini = psp_sw_fini, 3738 .hw_init = psp_hw_init, 3739 .hw_fini = psp_hw_fini, 3740 .suspend = psp_suspend, 3741 .resume = psp_resume, 3742 .is_idle = NULL, 3743 .check_soft_reset = NULL, 3744 .wait_for_idle = NULL, 3745 .soft_reset = NULL, 3746 .set_clockgating_state = psp_set_clockgating_state, 3747 .set_powergating_state = psp_set_powergating_state, 3748 }; 3749 3750 static int psp_sysfs_init(struct amdgpu_device *adev) 3751 { 3752 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3753 3754 if (ret) 3755 DRM_ERROR("Failed to create USBC PD FW control file!"); 3756 3757 return ret; 3758 } 3759 3760 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev) 3761 { 3762 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3763 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status); 3764 } 3765 3766 static void psp_sysfs_fini(struct amdgpu_device *adev) 3767 { 3768 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3769 } 3770 3771 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 3772 .type = AMD_IP_BLOCK_TYPE_PSP, 3773 .major = 3, 3774 .minor = 1, 3775 .rev = 0, 3776 .funcs = &psp_ip_funcs, 3777 }; 3778 3779 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 3780 .type = AMD_IP_BLOCK_TYPE_PSP, 3781 .major = 10, 3782 .minor = 0, 3783 .rev = 0, 3784 .funcs = &psp_ip_funcs, 3785 }; 3786 3787 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 3788 .type = AMD_IP_BLOCK_TYPE_PSP, 3789 .major = 11, 3790 .minor = 0, 3791 .rev = 0, 3792 .funcs = &psp_ip_funcs, 3793 }; 3794 3795 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3796 .type = AMD_IP_BLOCK_TYPE_PSP, 3797 .major = 11, 3798 .minor = 0, 3799 .rev = 8, 3800 .funcs = &psp_ip_funcs, 3801 }; 3802 3803 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 3804 .type = AMD_IP_BLOCK_TYPE_PSP, 3805 .major = 12, 3806 .minor = 0, 3807 .rev = 0, 3808 .funcs = &psp_ip_funcs, 3809 }; 3810 3811 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3812 .type = AMD_IP_BLOCK_TYPE_PSP, 3813 .major = 13, 3814 .minor = 0, 3815 .rev = 0, 3816 .funcs = &psp_ip_funcs, 3817 }; 3818 3819 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3820 .type = AMD_IP_BLOCK_TYPE_PSP, 3821 .major = 13, 3822 .minor = 0, 3823 .rev = 4, 3824 .funcs = &psp_ip_funcs, 3825 }; 3826