1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/dma-mapping.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v3_1.h" 34 #include "psp_v10_0.h" 35 #include "psp_v11_0.h" 36 #include "psp_v12_0.h" 37 38 #include "amdgpu_ras.h" 39 40 static int psp_sysfs_init(struct amdgpu_device *adev); 41 static void psp_sysfs_fini(struct amdgpu_device *adev); 42 43 static int psp_load_smu_fw(struct psp_context *psp); 44 45 /* 46 * Due to DF Cstate management centralized to PMFW, the firmware 47 * loading sequence will be updated as below: 48 * - Load KDB 49 * - Load SYS_DRV 50 * - Load tOS 51 * - Load PMFW 52 * - Setup TMR 53 * - Load other non-psp fw 54 * - Load ASD 55 * - Load XGMI/RAS/HDCP/DTM TA if any 56 * 57 * This new sequence is required for 58 * - Arcturus 59 * - Navi12 and onwards 60 */ 61 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 62 { 63 struct amdgpu_device *adev = psp->adev; 64 65 psp->pmfw_centralized_cstate_management = false; 66 67 if (amdgpu_sriov_vf(adev)) 68 return; 69 70 if (adev->flags & AMD_IS_APU) 71 return; 72 73 if ((adev->asic_type == CHIP_ARCTURUS) || 74 (adev->asic_type >= CHIP_NAVI12)) 75 psp->pmfw_centralized_cstate_management = true; 76 } 77 78 static int psp_early_init(void *handle) 79 { 80 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 81 struct psp_context *psp = &adev->psp; 82 83 switch (adev->asic_type) { 84 case CHIP_VEGA10: 85 case CHIP_VEGA12: 86 psp_v3_1_set_psp_funcs(psp); 87 psp->autoload_supported = false; 88 break; 89 case CHIP_RAVEN: 90 psp_v10_0_set_psp_funcs(psp); 91 psp->autoload_supported = false; 92 break; 93 case CHIP_VEGA20: 94 case CHIP_ARCTURUS: 95 psp_v11_0_set_psp_funcs(psp); 96 psp->autoload_supported = false; 97 break; 98 case CHIP_NAVI10: 99 case CHIP_NAVI14: 100 case CHIP_NAVI12: 101 case CHIP_SIENNA_CICHLID: 102 case CHIP_NAVY_FLOUNDER: 103 psp_v11_0_set_psp_funcs(psp); 104 psp->autoload_supported = true; 105 break; 106 case CHIP_RENOIR: 107 psp_v12_0_set_psp_funcs(psp); 108 break; 109 default: 110 return -EINVAL; 111 } 112 113 psp->adev = adev; 114 115 psp_check_pmfw_centralized_cstate_management(psp); 116 117 return 0; 118 } 119 120 static void psp_memory_training_fini(struct psp_context *psp) 121 { 122 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 123 124 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 125 kfree(ctx->sys_cache); 126 ctx->sys_cache = NULL; 127 } 128 129 static int psp_memory_training_init(struct psp_context *psp) 130 { 131 int ret; 132 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 133 134 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 135 DRM_DEBUG("memory training is not supported!\n"); 136 return 0; 137 } 138 139 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 140 if (ctx->sys_cache == NULL) { 141 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 142 ret = -ENOMEM; 143 goto Err_out; 144 } 145 146 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 147 ctx->train_data_size, 148 ctx->p2c_train_data_offset, 149 ctx->c2p_train_data_offset); 150 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 151 return 0; 152 153 Err_out: 154 psp_memory_training_fini(psp); 155 return ret; 156 } 157 158 static int psp_sw_init(void *handle) 159 { 160 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 161 struct psp_context *psp = &adev->psp; 162 int ret; 163 164 if (!amdgpu_sriov_vf(adev)) { 165 ret = psp_init_microcode(psp); 166 if (ret) { 167 DRM_ERROR("Failed to load psp firmware!\n"); 168 return ret; 169 } 170 } 171 172 ret = psp_memory_training_init(psp); 173 if (ret) { 174 DRM_ERROR("Failed to initialize memory training!\n"); 175 return ret; 176 } 177 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 178 if (ret) { 179 DRM_ERROR("Failed to process memory training!\n"); 180 return ret; 181 } 182 183 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 184 ret= psp_sysfs_init(adev); 185 if (ret) { 186 return ret; 187 } 188 } 189 190 return 0; 191 } 192 193 static int psp_sw_fini(void *handle) 194 { 195 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 196 197 psp_memory_training_fini(&adev->psp); 198 if (adev->psp.sos_fw) { 199 release_firmware(adev->psp.sos_fw); 200 adev->psp.sos_fw = NULL; 201 } 202 if (adev->psp.asd_fw) { 203 release_firmware(adev->psp.asd_fw); 204 adev->psp.asd_fw = NULL; 205 } 206 if (adev->psp.ta_fw) { 207 release_firmware(adev->psp.ta_fw); 208 adev->psp.ta_fw = NULL; 209 } 210 211 if (adev->asic_type == CHIP_NAVI10 || 212 adev->asic_type == CHIP_SIENNA_CICHLID) 213 psp_sysfs_fini(adev); 214 215 return 0; 216 } 217 218 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 219 uint32_t reg_val, uint32_t mask, bool check_changed) 220 { 221 uint32_t val; 222 int i; 223 struct amdgpu_device *adev = psp->adev; 224 225 if (psp->adev->in_pci_err_recovery) 226 return 0; 227 228 for (i = 0; i < adev->usec_timeout; i++) { 229 val = RREG32(reg_index); 230 if (check_changed) { 231 if (val != reg_val) 232 return 0; 233 } else { 234 if ((val & mask) == reg_val) 235 return 0; 236 } 237 udelay(1); 238 } 239 240 return -ETIME; 241 } 242 243 static int 244 psp_cmd_submit_buf(struct psp_context *psp, 245 struct amdgpu_firmware_info *ucode, 246 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 247 { 248 int ret; 249 int index; 250 int timeout = 2000; 251 bool ras_intr = false; 252 bool skip_unsupport = false; 253 254 if (psp->adev->in_pci_err_recovery) 255 return 0; 256 257 mutex_lock(&psp->mutex); 258 259 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 260 261 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 262 263 index = atomic_inc_return(&psp->fence_value); 264 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 265 if (ret) { 266 atomic_dec(&psp->fence_value); 267 mutex_unlock(&psp->mutex); 268 return ret; 269 } 270 271 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 272 while (*((unsigned int *)psp->fence_buf) != index) { 273 if (--timeout == 0) 274 break; 275 /* 276 * Shouldn't wait for timeout when err_event_athub occurs, 277 * because gpu reset thread triggered and lock resource should 278 * be released for psp resume sequence. 279 */ 280 ras_intr = amdgpu_ras_intr_triggered(); 281 if (ras_intr) 282 break; 283 msleep(1); 284 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 285 } 286 287 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 288 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 289 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 290 291 /* In some cases, psp response status is not 0 even there is no 292 * problem while the command is submitted. Some version of PSP FW 293 * doesn't write 0 to that field. 294 * So here we would like to only print a warning instead of an error 295 * during psp initialization to avoid breaking hw_init and it doesn't 296 * return -EINVAL. 297 */ 298 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 299 if (ucode) 300 DRM_WARN("failed to load ucode id (%d) ", 301 ucode->ucode_id); 302 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n", 303 psp->cmd_buf_mem->cmd_id, 304 psp->cmd_buf_mem->resp.status); 305 if (!timeout) { 306 mutex_unlock(&psp->mutex); 307 return -EINVAL; 308 } 309 } 310 311 /* get xGMI session id from response buffer */ 312 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id; 313 314 if (ucode) { 315 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 316 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 317 } 318 mutex_unlock(&psp->mutex); 319 320 return ret; 321 } 322 323 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 324 struct psp_gfx_cmd_resp *cmd, 325 uint64_t tmr_mc, uint32_t size) 326 { 327 if (amdgpu_sriov_vf(psp->adev)) 328 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 329 else 330 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 331 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 332 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 333 cmd->cmd.cmd_setup_tmr.buf_size = size; 334 } 335 336 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 337 uint64_t pri_buf_mc, uint32_t size) 338 { 339 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 340 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 341 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 342 cmd->cmd.cmd_load_toc.toc_size = size; 343 } 344 345 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 346 static int psp_load_toc(struct psp_context *psp, 347 uint32_t *tmr_size) 348 { 349 int ret; 350 struct psp_gfx_cmd_resp *cmd; 351 352 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 353 if (!cmd) 354 return -ENOMEM; 355 /* Copy toc to psp firmware private buffer */ 356 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 357 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size); 358 359 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 360 361 ret = psp_cmd_submit_buf(psp, NULL, cmd, 362 psp->fence_buf_mc_addr); 363 if (!ret) 364 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 365 kfree(cmd); 366 return ret; 367 } 368 369 /* Set up Trusted Memory Region */ 370 static int psp_tmr_init(struct psp_context *psp) 371 { 372 int ret; 373 int tmr_size; 374 void *tmr_buf; 375 void **pptr; 376 377 /* 378 * According to HW engineer, they prefer the TMR address be "naturally 379 * aligned" , e.g. the start address be an integer divide of TMR size. 380 * 381 * Note: this memory need be reserved till the driver 382 * uninitializes. 383 */ 384 tmr_size = PSP_TMR_SIZE; 385 386 /* For ASICs support RLC autoload, psp will parse the toc 387 * and calculate the total size of TMR needed */ 388 if (!amdgpu_sriov_vf(psp->adev) && 389 psp->toc_start_addr && 390 psp->toc_bin_size && 391 psp->fw_pri_buf) { 392 ret = psp_load_toc(psp, &tmr_size); 393 if (ret) { 394 DRM_ERROR("Failed to load toc\n"); 395 return ret; 396 } 397 } 398 399 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 400 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE, 401 AMDGPU_GEM_DOMAIN_VRAM, 402 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 403 404 return ret; 405 } 406 407 static int psp_clear_vf_fw(struct psp_context *psp) 408 { 409 int ret; 410 struct psp_gfx_cmd_resp *cmd; 411 412 if (!amdgpu_sriov_vf(psp->adev) || psp->adev->asic_type != CHIP_NAVI12) 413 return 0; 414 415 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 416 if (!cmd) 417 return -ENOMEM; 418 419 cmd->cmd_id = GFX_CMD_ID_CLEAR_VF_FW; 420 421 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 422 kfree(cmd); 423 424 return ret; 425 } 426 427 static bool psp_skip_tmr(struct psp_context *psp) 428 { 429 switch (psp->adev->asic_type) { 430 case CHIP_NAVI12: 431 case CHIP_SIENNA_CICHLID: 432 return true; 433 default: 434 return false; 435 } 436 } 437 438 static int psp_tmr_load(struct psp_context *psp) 439 { 440 int ret; 441 struct psp_gfx_cmd_resp *cmd; 442 443 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 444 * Already set up by host driver. 445 */ 446 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 447 return 0; 448 449 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 450 if (!cmd) 451 return -ENOMEM; 452 453 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, 454 amdgpu_bo_size(psp->tmr_bo)); 455 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 456 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 457 458 ret = psp_cmd_submit_buf(psp, NULL, cmd, 459 psp->fence_buf_mc_addr); 460 461 kfree(cmd); 462 463 return ret; 464 } 465 466 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 467 struct psp_gfx_cmd_resp *cmd) 468 { 469 if (amdgpu_sriov_vf(psp->adev)) 470 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 471 else 472 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 473 } 474 475 static int psp_tmr_unload(struct psp_context *psp) 476 { 477 int ret; 478 struct psp_gfx_cmd_resp *cmd; 479 480 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 481 if (!cmd) 482 return -ENOMEM; 483 484 psp_prep_tmr_unload_cmd_buf(psp, cmd); 485 DRM_INFO("free PSP TMR buffer\n"); 486 487 ret = psp_cmd_submit_buf(psp, NULL, cmd, 488 psp->fence_buf_mc_addr); 489 490 kfree(cmd); 491 492 return ret; 493 } 494 495 static int psp_tmr_terminate(struct psp_context *psp) 496 { 497 int ret; 498 void *tmr_buf; 499 void **pptr; 500 501 ret = psp_tmr_unload(psp); 502 if (ret) 503 return ret; 504 505 /* free TMR memory buffer */ 506 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 507 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 508 509 return 0; 510 } 511 512 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 513 uint64_t asd_mc, uint32_t size) 514 { 515 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 516 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 517 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 518 cmd->cmd.cmd_load_ta.app_len = size; 519 520 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 521 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 522 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 523 } 524 525 static int psp_asd_load(struct psp_context *psp) 526 { 527 int ret; 528 struct psp_gfx_cmd_resp *cmd; 529 530 /* If PSP version doesn't match ASD version, asd loading will be failed. 531 * add workaround to bypass it for sriov now. 532 * TODO: add version check to make it common 533 */ 534 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_fw) 535 return 0; 536 537 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 538 if (!cmd) 539 return -ENOMEM; 540 541 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 542 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 543 544 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 545 psp->asd_ucode_size); 546 547 ret = psp_cmd_submit_buf(psp, NULL, cmd, 548 psp->fence_buf_mc_addr); 549 if (!ret) { 550 psp->asd_context.asd_initialized = true; 551 psp->asd_context.session_id = cmd->resp.session_id; 552 } 553 554 kfree(cmd); 555 556 return ret; 557 } 558 559 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 560 uint32_t session_id) 561 { 562 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 563 cmd->cmd.cmd_unload_ta.session_id = session_id; 564 } 565 566 static int psp_asd_unload(struct psp_context *psp) 567 { 568 int ret; 569 struct psp_gfx_cmd_resp *cmd; 570 571 if (amdgpu_sriov_vf(psp->adev)) 572 return 0; 573 574 if (!psp->asd_context.asd_initialized) 575 return 0; 576 577 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 578 if (!cmd) 579 return -ENOMEM; 580 581 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 582 583 ret = psp_cmd_submit_buf(psp, NULL, cmd, 584 psp->fence_buf_mc_addr); 585 if (!ret) 586 psp->asd_context.asd_initialized = false; 587 588 kfree(cmd); 589 590 return ret; 591 } 592 593 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 594 uint32_t id, uint32_t value) 595 { 596 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 597 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 598 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 599 } 600 601 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 602 uint32_t value) 603 { 604 struct psp_gfx_cmd_resp *cmd = NULL; 605 int ret = 0; 606 607 if (reg >= PSP_REG_LAST) 608 return -EINVAL; 609 610 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 611 if (!cmd) 612 return -ENOMEM; 613 614 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 615 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 616 617 kfree(cmd); 618 return ret; 619 } 620 621 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 622 uint64_t ta_bin_mc, 623 uint32_t ta_bin_size, 624 uint64_t ta_shared_mc, 625 uint32_t ta_shared_size) 626 { 627 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 628 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 629 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 630 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 631 632 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 633 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 634 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 635 } 636 637 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 638 { 639 int ret; 640 641 /* 642 * Allocate 16k memory aligned to 4k from Frame Buffer (local 643 * physical) for xgmi ta <-> Driver 644 */ 645 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 646 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 647 &psp->xgmi_context.xgmi_shared_bo, 648 &psp->xgmi_context.xgmi_shared_mc_addr, 649 &psp->xgmi_context.xgmi_shared_buf); 650 651 return ret; 652 } 653 654 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 655 uint32_t ta_cmd_id, 656 uint32_t session_id) 657 { 658 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 659 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 660 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 661 } 662 663 static int psp_ta_invoke(struct psp_context *psp, 664 uint32_t ta_cmd_id, 665 uint32_t session_id) 666 { 667 int ret; 668 struct psp_gfx_cmd_resp *cmd; 669 670 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 671 if (!cmd) 672 return -ENOMEM; 673 674 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 675 676 ret = psp_cmd_submit_buf(psp, NULL, cmd, 677 psp->fence_buf_mc_addr); 678 679 kfree(cmd); 680 681 return ret; 682 } 683 684 static int psp_xgmi_load(struct psp_context *psp) 685 { 686 int ret; 687 struct psp_gfx_cmd_resp *cmd; 688 689 /* 690 * TODO: bypass the loading in sriov for now 691 */ 692 693 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 694 if (!cmd) 695 return -ENOMEM; 696 697 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 698 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 699 700 psp_prep_ta_load_cmd_buf(cmd, 701 psp->fw_pri_mc_addr, 702 psp->ta_xgmi_ucode_size, 703 psp->xgmi_context.xgmi_shared_mc_addr, 704 PSP_XGMI_SHARED_MEM_SIZE); 705 706 ret = psp_cmd_submit_buf(psp, NULL, cmd, 707 psp->fence_buf_mc_addr); 708 709 if (!ret) { 710 psp->xgmi_context.initialized = 1; 711 psp->xgmi_context.session_id = cmd->resp.session_id; 712 } 713 714 kfree(cmd); 715 716 return ret; 717 } 718 719 static int psp_xgmi_unload(struct psp_context *psp) 720 { 721 int ret; 722 struct psp_gfx_cmd_resp *cmd; 723 struct amdgpu_device *adev = psp->adev; 724 725 /* XGMI TA unload currently is not supported on Arcturus */ 726 if (adev->asic_type == CHIP_ARCTURUS) 727 return 0; 728 729 /* 730 * TODO: bypass the unloading in sriov for now 731 */ 732 733 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 734 if (!cmd) 735 return -ENOMEM; 736 737 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 738 739 ret = psp_cmd_submit_buf(psp, NULL, cmd, 740 psp->fence_buf_mc_addr); 741 742 kfree(cmd); 743 744 return ret; 745 } 746 747 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 748 { 749 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 750 } 751 752 int psp_xgmi_terminate(struct psp_context *psp) 753 { 754 int ret; 755 756 if (!psp->xgmi_context.initialized) 757 return 0; 758 759 ret = psp_xgmi_unload(psp); 760 if (ret) 761 return ret; 762 763 psp->xgmi_context.initialized = 0; 764 765 /* free xgmi shared memory */ 766 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 767 &psp->xgmi_context.xgmi_shared_mc_addr, 768 &psp->xgmi_context.xgmi_shared_buf); 769 770 return 0; 771 } 772 773 int psp_xgmi_initialize(struct psp_context *psp) 774 { 775 struct ta_xgmi_shared_memory *xgmi_cmd; 776 int ret; 777 778 if (!psp->adev->psp.ta_fw || 779 !psp->adev->psp.ta_xgmi_ucode_size || 780 !psp->adev->psp.ta_xgmi_start_addr) 781 return -ENOENT; 782 783 if (!psp->xgmi_context.initialized) { 784 ret = psp_xgmi_init_shared_buf(psp); 785 if (ret) 786 return ret; 787 } 788 789 /* Load XGMI TA */ 790 ret = psp_xgmi_load(psp); 791 if (ret) 792 return ret; 793 794 /* Initialize XGMI session */ 795 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 796 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 797 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 798 799 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 800 801 return ret; 802 } 803 804 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 805 { 806 struct ta_xgmi_shared_memory *xgmi_cmd; 807 int ret; 808 809 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 810 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 811 812 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 813 814 /* Invoke xgmi ta to get hive id */ 815 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 816 if (ret) 817 return ret; 818 819 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 820 821 return 0; 822 } 823 824 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 825 { 826 struct ta_xgmi_shared_memory *xgmi_cmd; 827 int ret; 828 829 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 830 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 831 832 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 833 834 /* Invoke xgmi ta to get the node id */ 835 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 836 if (ret) 837 return ret; 838 839 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 840 841 return 0; 842 } 843 844 int psp_xgmi_get_topology_info(struct psp_context *psp, 845 int number_devices, 846 struct psp_xgmi_topology_info *topology) 847 { 848 struct ta_xgmi_shared_memory *xgmi_cmd; 849 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 850 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 851 int i; 852 int ret; 853 854 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 855 return -EINVAL; 856 857 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 858 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 859 860 /* Fill in the shared memory with topology information as input */ 861 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 862 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 863 topology_info_input->num_nodes = number_devices; 864 865 for (i = 0; i < topology_info_input->num_nodes; i++) { 866 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 867 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 868 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 869 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 870 } 871 872 /* Invoke xgmi ta to get the topology information */ 873 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 874 if (ret) 875 return ret; 876 877 /* Read the output topology information from the shared memory */ 878 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 879 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 880 for (i = 0; i < topology->num_nodes; i++) { 881 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 882 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 883 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 884 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 885 } 886 887 return 0; 888 } 889 890 int psp_xgmi_set_topology_info(struct psp_context *psp, 891 int number_devices, 892 struct psp_xgmi_topology_info *topology) 893 { 894 struct ta_xgmi_shared_memory *xgmi_cmd; 895 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 896 int i; 897 898 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 899 return -EINVAL; 900 901 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 902 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 903 904 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 905 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 906 topology_info_input->num_nodes = number_devices; 907 908 for (i = 0; i < topology_info_input->num_nodes; i++) { 909 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 910 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 911 topology_info_input->nodes[i].is_sharing_enabled = 1; 912 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 913 } 914 915 /* Invoke xgmi ta to set topology information */ 916 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 917 } 918 919 // ras begin 920 static int psp_ras_init_shared_buf(struct psp_context *psp) 921 { 922 int ret; 923 924 /* 925 * Allocate 16k memory aligned to 4k from Frame Buffer (local 926 * physical) for ras ta <-> Driver 927 */ 928 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 929 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 930 &psp->ras.ras_shared_bo, 931 &psp->ras.ras_shared_mc_addr, 932 &psp->ras.ras_shared_buf); 933 934 return ret; 935 } 936 937 static int psp_ras_load(struct psp_context *psp) 938 { 939 int ret; 940 struct psp_gfx_cmd_resp *cmd; 941 struct ta_ras_shared_memory *ras_cmd; 942 943 /* 944 * TODO: bypass the loading in sriov for now 945 */ 946 if (amdgpu_sriov_vf(psp->adev)) 947 return 0; 948 949 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 950 if (!cmd) 951 return -ENOMEM; 952 953 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 954 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 955 956 psp_prep_ta_load_cmd_buf(cmd, 957 psp->fw_pri_mc_addr, 958 psp->ta_ras_ucode_size, 959 psp->ras.ras_shared_mc_addr, 960 PSP_RAS_SHARED_MEM_SIZE); 961 962 ret = psp_cmd_submit_buf(psp, NULL, cmd, 963 psp->fence_buf_mc_addr); 964 965 ras_cmd = (struct ta_ras_shared_memory*)psp->ras.ras_shared_buf; 966 967 if (!ret) { 968 psp->ras.session_id = cmd->resp.session_id; 969 970 if (!ras_cmd->ras_status) 971 psp->ras.ras_initialized = true; 972 else 973 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 974 } 975 976 if (ret || ras_cmd->ras_status) 977 amdgpu_ras_fini(psp->adev); 978 979 kfree(cmd); 980 981 return ret; 982 } 983 984 static int psp_ras_unload(struct psp_context *psp) 985 { 986 int ret; 987 struct psp_gfx_cmd_resp *cmd; 988 989 /* 990 * TODO: bypass the unloading in sriov for now 991 */ 992 if (amdgpu_sriov_vf(psp->adev)) 993 return 0; 994 995 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 996 if (!cmd) 997 return -ENOMEM; 998 999 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 1000 1001 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1002 psp->fence_buf_mc_addr); 1003 1004 kfree(cmd); 1005 1006 return ret; 1007 } 1008 1009 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1010 { 1011 struct ta_ras_shared_memory *ras_cmd; 1012 int ret; 1013 1014 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1015 1016 /* 1017 * TODO: bypass the loading in sriov for now 1018 */ 1019 if (amdgpu_sriov_vf(psp->adev)) 1020 return 0; 1021 1022 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 1023 1024 if (amdgpu_ras_intr_triggered()) 1025 return ret; 1026 1027 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1028 { 1029 DRM_WARN("RAS: Unsupported Interface"); 1030 return -EINVAL; 1031 } 1032 1033 if (!ret) { 1034 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1035 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1036 1037 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1038 } 1039 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1040 dev_warn(psp->adev->dev, 1041 "RAS internal register access blocked\n"); 1042 } 1043 1044 return ret; 1045 } 1046 1047 int psp_ras_enable_features(struct psp_context *psp, 1048 union ta_ras_cmd_input *info, bool enable) 1049 { 1050 struct ta_ras_shared_memory *ras_cmd; 1051 int ret; 1052 1053 if (!psp->ras.ras_initialized) 1054 return -EINVAL; 1055 1056 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1057 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1058 1059 if (enable) 1060 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1061 else 1062 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1063 1064 ras_cmd->ras_in_message = *info; 1065 1066 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1067 if (ret) 1068 return -EINVAL; 1069 1070 return ras_cmd->ras_status; 1071 } 1072 1073 static int psp_ras_terminate(struct psp_context *psp) 1074 { 1075 int ret; 1076 1077 /* 1078 * TODO: bypass the terminate in sriov for now 1079 */ 1080 if (amdgpu_sriov_vf(psp->adev)) 1081 return 0; 1082 1083 if (!psp->ras.ras_initialized) 1084 return 0; 1085 1086 ret = psp_ras_unload(psp); 1087 if (ret) 1088 return ret; 1089 1090 psp->ras.ras_initialized = false; 1091 1092 /* free ras shared memory */ 1093 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1094 &psp->ras.ras_shared_mc_addr, 1095 &psp->ras.ras_shared_buf); 1096 1097 return 0; 1098 } 1099 1100 static int psp_ras_initialize(struct psp_context *psp) 1101 { 1102 int ret; 1103 1104 /* 1105 * TODO: bypass the initialize in sriov for now 1106 */ 1107 if (amdgpu_sriov_vf(psp->adev)) 1108 return 0; 1109 1110 if (!psp->adev->psp.ta_ras_ucode_size || 1111 !psp->adev->psp.ta_ras_start_addr) { 1112 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n"); 1113 return 0; 1114 } 1115 1116 if (!psp->ras.ras_initialized) { 1117 ret = psp_ras_init_shared_buf(psp); 1118 if (ret) 1119 return ret; 1120 } 1121 1122 ret = psp_ras_load(psp); 1123 if (ret) 1124 return ret; 1125 1126 return 0; 1127 } 1128 1129 int psp_ras_trigger_error(struct psp_context *psp, 1130 struct ta_ras_trigger_error_input *info) 1131 { 1132 struct ta_ras_shared_memory *ras_cmd; 1133 int ret; 1134 1135 if (!psp->ras.ras_initialized) 1136 return -EINVAL; 1137 1138 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1139 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1140 1141 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1142 ras_cmd->ras_in_message.trigger_error = *info; 1143 1144 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1145 if (ret) 1146 return -EINVAL; 1147 1148 /* If err_event_athub occurs error inject was successful, however 1149 return status from TA is no long reliable */ 1150 if (amdgpu_ras_intr_triggered()) 1151 return 0; 1152 1153 return ras_cmd->ras_status; 1154 } 1155 // ras end 1156 1157 // HDCP start 1158 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1159 { 1160 int ret; 1161 1162 /* 1163 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1164 * physical) for hdcp ta <-> Driver 1165 */ 1166 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1167 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1168 &psp->hdcp_context.hdcp_shared_bo, 1169 &psp->hdcp_context.hdcp_shared_mc_addr, 1170 &psp->hdcp_context.hdcp_shared_buf); 1171 1172 return ret; 1173 } 1174 1175 static int psp_hdcp_load(struct psp_context *psp) 1176 { 1177 int ret; 1178 struct psp_gfx_cmd_resp *cmd; 1179 1180 /* 1181 * TODO: bypass the loading in sriov for now 1182 */ 1183 if (amdgpu_sriov_vf(psp->adev)) 1184 return 0; 1185 1186 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1187 if (!cmd) 1188 return -ENOMEM; 1189 1190 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1191 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr, 1192 psp->ta_hdcp_ucode_size); 1193 1194 psp_prep_ta_load_cmd_buf(cmd, 1195 psp->fw_pri_mc_addr, 1196 psp->ta_hdcp_ucode_size, 1197 psp->hdcp_context.hdcp_shared_mc_addr, 1198 PSP_HDCP_SHARED_MEM_SIZE); 1199 1200 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1201 1202 if (!ret) { 1203 psp->hdcp_context.hdcp_initialized = true; 1204 psp->hdcp_context.session_id = cmd->resp.session_id; 1205 mutex_init(&psp->hdcp_context.mutex); 1206 } 1207 1208 kfree(cmd); 1209 1210 return ret; 1211 } 1212 static int psp_hdcp_initialize(struct psp_context *psp) 1213 { 1214 int ret; 1215 1216 /* 1217 * TODO: bypass the initialize in sriov for now 1218 */ 1219 if (amdgpu_sriov_vf(psp->adev)) 1220 return 0; 1221 1222 if (!psp->adev->psp.ta_hdcp_ucode_size || 1223 !psp->adev->psp.ta_hdcp_start_addr) { 1224 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1225 return 0; 1226 } 1227 1228 if (!psp->hdcp_context.hdcp_initialized) { 1229 ret = psp_hdcp_init_shared_buf(psp); 1230 if (ret) 1231 return ret; 1232 } 1233 1234 ret = psp_hdcp_load(psp); 1235 if (ret) 1236 return ret; 1237 1238 return 0; 1239 } 1240 1241 static int psp_hdcp_unload(struct psp_context *psp) 1242 { 1243 int ret; 1244 struct psp_gfx_cmd_resp *cmd; 1245 1246 /* 1247 * TODO: bypass the unloading in sriov for now 1248 */ 1249 if (amdgpu_sriov_vf(psp->adev)) 1250 return 0; 1251 1252 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1253 if (!cmd) 1254 return -ENOMEM; 1255 1256 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1257 1258 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1259 1260 kfree(cmd); 1261 1262 return ret; 1263 } 1264 1265 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1266 { 1267 /* 1268 * TODO: bypass the loading in sriov for now 1269 */ 1270 if (amdgpu_sriov_vf(psp->adev)) 1271 return 0; 1272 1273 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1274 } 1275 1276 static int psp_hdcp_terminate(struct psp_context *psp) 1277 { 1278 int ret; 1279 1280 /* 1281 * TODO: bypass the terminate in sriov for now 1282 */ 1283 if (amdgpu_sriov_vf(psp->adev)) 1284 return 0; 1285 1286 if (!psp->hdcp_context.hdcp_initialized) 1287 return 0; 1288 1289 ret = psp_hdcp_unload(psp); 1290 if (ret) 1291 return ret; 1292 1293 psp->hdcp_context.hdcp_initialized = false; 1294 1295 /* free hdcp shared memory */ 1296 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1297 &psp->hdcp_context.hdcp_shared_mc_addr, 1298 &psp->hdcp_context.hdcp_shared_buf); 1299 1300 return 0; 1301 } 1302 // HDCP end 1303 1304 // DTM start 1305 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1306 { 1307 int ret; 1308 1309 /* 1310 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1311 * physical) for dtm ta <-> Driver 1312 */ 1313 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1314 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1315 &psp->dtm_context.dtm_shared_bo, 1316 &psp->dtm_context.dtm_shared_mc_addr, 1317 &psp->dtm_context.dtm_shared_buf); 1318 1319 return ret; 1320 } 1321 1322 static int psp_dtm_load(struct psp_context *psp) 1323 { 1324 int ret; 1325 struct psp_gfx_cmd_resp *cmd; 1326 1327 /* 1328 * TODO: bypass the loading in sriov for now 1329 */ 1330 if (amdgpu_sriov_vf(psp->adev)) 1331 return 0; 1332 1333 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1334 if (!cmd) 1335 return -ENOMEM; 1336 1337 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1338 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1339 1340 psp_prep_ta_load_cmd_buf(cmd, 1341 psp->fw_pri_mc_addr, 1342 psp->ta_dtm_ucode_size, 1343 psp->dtm_context.dtm_shared_mc_addr, 1344 PSP_DTM_SHARED_MEM_SIZE); 1345 1346 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1347 1348 if (!ret) { 1349 psp->dtm_context.dtm_initialized = true; 1350 psp->dtm_context.session_id = cmd->resp.session_id; 1351 mutex_init(&psp->dtm_context.mutex); 1352 } 1353 1354 kfree(cmd); 1355 1356 return ret; 1357 } 1358 1359 static int psp_dtm_initialize(struct psp_context *psp) 1360 { 1361 int ret; 1362 1363 /* 1364 * TODO: bypass the initialize in sriov for now 1365 */ 1366 if (amdgpu_sriov_vf(psp->adev)) 1367 return 0; 1368 1369 if (!psp->adev->psp.ta_dtm_ucode_size || 1370 !psp->adev->psp.ta_dtm_start_addr) { 1371 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1372 return 0; 1373 } 1374 1375 if (!psp->dtm_context.dtm_initialized) { 1376 ret = psp_dtm_init_shared_buf(psp); 1377 if (ret) 1378 return ret; 1379 } 1380 1381 ret = psp_dtm_load(psp); 1382 if (ret) 1383 return ret; 1384 1385 return 0; 1386 } 1387 1388 static int psp_dtm_unload(struct psp_context *psp) 1389 { 1390 int ret; 1391 struct psp_gfx_cmd_resp *cmd; 1392 1393 /* 1394 * TODO: bypass the unloading in sriov for now 1395 */ 1396 if (amdgpu_sriov_vf(psp->adev)) 1397 return 0; 1398 1399 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1400 if (!cmd) 1401 return -ENOMEM; 1402 1403 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1404 1405 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1406 1407 kfree(cmd); 1408 1409 return ret; 1410 } 1411 1412 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1413 { 1414 /* 1415 * TODO: bypass the loading in sriov for now 1416 */ 1417 if (amdgpu_sriov_vf(psp->adev)) 1418 return 0; 1419 1420 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1421 } 1422 1423 static int psp_dtm_terminate(struct psp_context *psp) 1424 { 1425 int ret; 1426 1427 /* 1428 * TODO: bypass the terminate in sriov for now 1429 */ 1430 if (amdgpu_sriov_vf(psp->adev)) 1431 return 0; 1432 1433 if (!psp->dtm_context.dtm_initialized) 1434 return 0; 1435 1436 ret = psp_dtm_unload(psp); 1437 if (ret) 1438 return ret; 1439 1440 psp->dtm_context.dtm_initialized = false; 1441 1442 /* free hdcp shared memory */ 1443 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1444 &psp->dtm_context.dtm_shared_mc_addr, 1445 &psp->dtm_context.dtm_shared_buf); 1446 1447 return 0; 1448 } 1449 // DTM end 1450 1451 // RAP start 1452 static int psp_rap_init_shared_buf(struct psp_context *psp) 1453 { 1454 int ret; 1455 1456 /* 1457 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1458 * physical) for rap ta <-> Driver 1459 */ 1460 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE, 1461 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1462 &psp->rap_context.rap_shared_bo, 1463 &psp->rap_context.rap_shared_mc_addr, 1464 &psp->rap_context.rap_shared_buf); 1465 1466 return ret; 1467 } 1468 1469 static int psp_rap_load(struct psp_context *psp) 1470 { 1471 int ret; 1472 struct psp_gfx_cmd_resp *cmd; 1473 1474 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1475 if (!cmd) 1476 return -ENOMEM; 1477 1478 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1479 memcpy(psp->fw_pri_buf, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); 1480 1481 psp_prep_ta_load_cmd_buf(cmd, 1482 psp->fw_pri_mc_addr, 1483 psp->ta_rap_ucode_size, 1484 psp->rap_context.rap_shared_mc_addr, 1485 PSP_RAP_SHARED_MEM_SIZE); 1486 1487 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1488 1489 if (!ret) { 1490 psp->rap_context.rap_initialized = true; 1491 psp->rap_context.session_id = cmd->resp.session_id; 1492 mutex_init(&psp->rap_context.mutex); 1493 } 1494 1495 kfree(cmd); 1496 1497 return ret; 1498 } 1499 1500 static int psp_rap_unload(struct psp_context *psp) 1501 { 1502 int ret; 1503 struct psp_gfx_cmd_resp *cmd; 1504 1505 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1506 if (!cmd) 1507 return -ENOMEM; 1508 1509 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id); 1510 1511 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1512 1513 kfree(cmd); 1514 1515 return ret; 1516 } 1517 1518 static int psp_rap_initialize(struct psp_context *psp) 1519 { 1520 int ret; 1521 1522 /* 1523 * TODO: bypass the initialize in sriov for now 1524 */ 1525 if (amdgpu_sriov_vf(psp->adev)) 1526 return 0; 1527 1528 if (!psp->adev->psp.ta_rap_ucode_size || 1529 !psp->adev->psp.ta_rap_start_addr) { 1530 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1531 return 0; 1532 } 1533 1534 if (!psp->rap_context.rap_initialized) { 1535 ret = psp_rap_init_shared_buf(psp); 1536 if (ret) 1537 return ret; 1538 } 1539 1540 ret = psp_rap_load(psp); 1541 if (ret) 1542 return ret; 1543 1544 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE); 1545 if (ret != TA_RAP_STATUS__SUCCESS) { 1546 psp_rap_unload(psp); 1547 1548 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1549 &psp->rap_context.rap_shared_mc_addr, 1550 &psp->rap_context.rap_shared_buf); 1551 1552 psp->rap_context.rap_initialized = false; 1553 1554 dev_warn(psp->adev->dev, "RAP TA initialize fail.\n"); 1555 return -EINVAL; 1556 } 1557 1558 return 0; 1559 } 1560 1561 static int psp_rap_terminate(struct psp_context *psp) 1562 { 1563 int ret; 1564 1565 if (!psp->rap_context.rap_initialized) 1566 return 0; 1567 1568 ret = psp_rap_unload(psp); 1569 1570 psp->rap_context.rap_initialized = false; 1571 1572 /* free rap shared memory */ 1573 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1574 &psp->rap_context.rap_shared_mc_addr, 1575 &psp->rap_context.rap_shared_buf); 1576 1577 return ret; 1578 } 1579 1580 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1581 { 1582 struct ta_rap_shared_memory *rap_cmd; 1583 int ret; 1584 1585 if (!psp->rap_context.rap_initialized) 1586 return -EINVAL; 1587 1588 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1589 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1590 return -EINVAL; 1591 1592 mutex_lock(&psp->rap_context.mutex); 1593 1594 rap_cmd = (struct ta_rap_shared_memory *) 1595 psp->rap_context.rap_shared_buf; 1596 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1597 1598 rap_cmd->cmd_id = ta_cmd_id; 1599 rap_cmd->validation_method_id = METHOD_A; 1600 1601 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id); 1602 if (ret) { 1603 mutex_unlock(&psp->rap_context.mutex); 1604 return ret; 1605 } 1606 1607 mutex_unlock(&psp->rap_context.mutex); 1608 1609 return rap_cmd->rap_status; 1610 } 1611 // RAP end 1612 1613 static int psp_hw_start(struct psp_context *psp) 1614 { 1615 struct amdgpu_device *adev = psp->adev; 1616 int ret; 1617 1618 if (!amdgpu_sriov_vf(adev)) { 1619 if (psp->kdb_bin_size && 1620 (psp->funcs->bootloader_load_kdb != NULL)) { 1621 ret = psp_bootloader_load_kdb(psp); 1622 if (ret) { 1623 DRM_ERROR("PSP load kdb failed!\n"); 1624 return ret; 1625 } 1626 } 1627 1628 if (psp->spl_bin_size) { 1629 ret = psp_bootloader_load_spl(psp); 1630 if (ret) { 1631 DRM_ERROR("PSP load spl failed!\n"); 1632 return ret; 1633 } 1634 } 1635 1636 ret = psp_bootloader_load_sysdrv(psp); 1637 if (ret) { 1638 DRM_ERROR("PSP load sysdrv failed!\n"); 1639 return ret; 1640 } 1641 1642 ret = psp_bootloader_load_sos(psp); 1643 if (ret) { 1644 DRM_ERROR("PSP load sos failed!\n"); 1645 return ret; 1646 } 1647 } 1648 1649 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1650 if (ret) { 1651 DRM_ERROR("PSP create ring failed!\n"); 1652 return ret; 1653 } 1654 1655 ret = psp_clear_vf_fw(psp); 1656 if (ret) { 1657 DRM_ERROR("PSP clear vf fw!\n"); 1658 return ret; 1659 } 1660 1661 ret = psp_tmr_init(psp); 1662 if (ret) { 1663 DRM_ERROR("PSP tmr init failed!\n"); 1664 return ret; 1665 } 1666 1667 /* 1668 * For ASICs with DF Cstate management centralized 1669 * to PMFW, TMR setup should be performed after PMFW 1670 * loaded and before other non-psp firmware loaded. 1671 */ 1672 if (psp->pmfw_centralized_cstate_management) { 1673 ret = psp_load_smu_fw(psp); 1674 if (ret) 1675 return ret; 1676 } 1677 1678 ret = psp_tmr_load(psp); 1679 if (ret) { 1680 DRM_ERROR("PSP load tmr failed!\n"); 1681 return ret; 1682 } 1683 1684 return 0; 1685 } 1686 1687 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 1688 enum psp_gfx_fw_type *type) 1689 { 1690 switch (ucode->ucode_id) { 1691 case AMDGPU_UCODE_ID_SDMA0: 1692 *type = GFX_FW_TYPE_SDMA0; 1693 break; 1694 case AMDGPU_UCODE_ID_SDMA1: 1695 *type = GFX_FW_TYPE_SDMA1; 1696 break; 1697 case AMDGPU_UCODE_ID_SDMA2: 1698 *type = GFX_FW_TYPE_SDMA2; 1699 break; 1700 case AMDGPU_UCODE_ID_SDMA3: 1701 *type = GFX_FW_TYPE_SDMA3; 1702 break; 1703 case AMDGPU_UCODE_ID_SDMA4: 1704 *type = GFX_FW_TYPE_SDMA4; 1705 break; 1706 case AMDGPU_UCODE_ID_SDMA5: 1707 *type = GFX_FW_TYPE_SDMA5; 1708 break; 1709 case AMDGPU_UCODE_ID_SDMA6: 1710 *type = GFX_FW_TYPE_SDMA6; 1711 break; 1712 case AMDGPU_UCODE_ID_SDMA7: 1713 *type = GFX_FW_TYPE_SDMA7; 1714 break; 1715 case AMDGPU_UCODE_ID_CP_MES: 1716 *type = GFX_FW_TYPE_CP_MES; 1717 break; 1718 case AMDGPU_UCODE_ID_CP_MES_DATA: 1719 *type = GFX_FW_TYPE_MES_STACK; 1720 break; 1721 case AMDGPU_UCODE_ID_CP_CE: 1722 *type = GFX_FW_TYPE_CP_CE; 1723 break; 1724 case AMDGPU_UCODE_ID_CP_PFP: 1725 *type = GFX_FW_TYPE_CP_PFP; 1726 break; 1727 case AMDGPU_UCODE_ID_CP_ME: 1728 *type = GFX_FW_TYPE_CP_ME; 1729 break; 1730 case AMDGPU_UCODE_ID_CP_MEC1: 1731 *type = GFX_FW_TYPE_CP_MEC; 1732 break; 1733 case AMDGPU_UCODE_ID_CP_MEC1_JT: 1734 *type = GFX_FW_TYPE_CP_MEC_ME1; 1735 break; 1736 case AMDGPU_UCODE_ID_CP_MEC2: 1737 *type = GFX_FW_TYPE_CP_MEC; 1738 break; 1739 case AMDGPU_UCODE_ID_CP_MEC2_JT: 1740 *type = GFX_FW_TYPE_CP_MEC_ME2; 1741 break; 1742 case AMDGPU_UCODE_ID_RLC_G: 1743 *type = GFX_FW_TYPE_RLC_G; 1744 break; 1745 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 1746 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 1747 break; 1748 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 1749 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 1750 break; 1751 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 1752 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 1753 break; 1754 case AMDGPU_UCODE_ID_RLC_IRAM: 1755 *type = GFX_FW_TYPE_RLC_IRAM; 1756 break; 1757 case AMDGPU_UCODE_ID_RLC_DRAM: 1758 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 1759 break; 1760 case AMDGPU_UCODE_ID_SMC: 1761 *type = GFX_FW_TYPE_SMU; 1762 break; 1763 case AMDGPU_UCODE_ID_UVD: 1764 *type = GFX_FW_TYPE_UVD; 1765 break; 1766 case AMDGPU_UCODE_ID_UVD1: 1767 *type = GFX_FW_TYPE_UVD1; 1768 break; 1769 case AMDGPU_UCODE_ID_VCE: 1770 *type = GFX_FW_TYPE_VCE; 1771 break; 1772 case AMDGPU_UCODE_ID_VCN: 1773 *type = GFX_FW_TYPE_VCN; 1774 break; 1775 case AMDGPU_UCODE_ID_VCN1: 1776 *type = GFX_FW_TYPE_VCN1; 1777 break; 1778 case AMDGPU_UCODE_ID_DMCU_ERAM: 1779 *type = GFX_FW_TYPE_DMCU_ERAM; 1780 break; 1781 case AMDGPU_UCODE_ID_DMCU_INTV: 1782 *type = GFX_FW_TYPE_DMCU_ISR; 1783 break; 1784 case AMDGPU_UCODE_ID_VCN0_RAM: 1785 *type = GFX_FW_TYPE_VCN0_RAM; 1786 break; 1787 case AMDGPU_UCODE_ID_VCN1_RAM: 1788 *type = GFX_FW_TYPE_VCN1_RAM; 1789 break; 1790 case AMDGPU_UCODE_ID_DMCUB: 1791 *type = GFX_FW_TYPE_DMUB; 1792 break; 1793 case AMDGPU_UCODE_ID_MAXIMUM: 1794 default: 1795 return -EINVAL; 1796 } 1797 1798 return 0; 1799 } 1800 1801 static void psp_print_fw_hdr(struct psp_context *psp, 1802 struct amdgpu_firmware_info *ucode) 1803 { 1804 struct amdgpu_device *adev = psp->adev; 1805 struct common_firmware_header *hdr; 1806 1807 switch (ucode->ucode_id) { 1808 case AMDGPU_UCODE_ID_SDMA0: 1809 case AMDGPU_UCODE_ID_SDMA1: 1810 case AMDGPU_UCODE_ID_SDMA2: 1811 case AMDGPU_UCODE_ID_SDMA3: 1812 case AMDGPU_UCODE_ID_SDMA4: 1813 case AMDGPU_UCODE_ID_SDMA5: 1814 case AMDGPU_UCODE_ID_SDMA6: 1815 case AMDGPU_UCODE_ID_SDMA7: 1816 hdr = (struct common_firmware_header *) 1817 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 1818 amdgpu_ucode_print_sdma_hdr(hdr); 1819 break; 1820 case AMDGPU_UCODE_ID_CP_CE: 1821 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 1822 amdgpu_ucode_print_gfx_hdr(hdr); 1823 break; 1824 case AMDGPU_UCODE_ID_CP_PFP: 1825 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 1826 amdgpu_ucode_print_gfx_hdr(hdr); 1827 break; 1828 case AMDGPU_UCODE_ID_CP_ME: 1829 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 1830 amdgpu_ucode_print_gfx_hdr(hdr); 1831 break; 1832 case AMDGPU_UCODE_ID_CP_MEC1: 1833 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 1834 amdgpu_ucode_print_gfx_hdr(hdr); 1835 break; 1836 case AMDGPU_UCODE_ID_RLC_G: 1837 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 1838 amdgpu_ucode_print_rlc_hdr(hdr); 1839 break; 1840 case AMDGPU_UCODE_ID_SMC: 1841 hdr = (struct common_firmware_header *)adev->pm.fw->data; 1842 amdgpu_ucode_print_smc_hdr(hdr); 1843 break; 1844 default: 1845 break; 1846 } 1847 } 1848 1849 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 1850 struct psp_gfx_cmd_resp *cmd) 1851 { 1852 int ret; 1853 uint64_t fw_mem_mc_addr = ucode->mc_addr; 1854 1855 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 1856 1857 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1858 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 1859 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 1860 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 1861 1862 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 1863 if (ret) 1864 DRM_ERROR("Unknown firmware type\n"); 1865 1866 return ret; 1867 } 1868 1869 static int psp_execute_np_fw_load(struct psp_context *psp, 1870 struct amdgpu_firmware_info *ucode) 1871 { 1872 int ret = 0; 1873 1874 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 1875 if (ret) 1876 return ret; 1877 1878 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 1879 psp->fence_buf_mc_addr); 1880 1881 return ret; 1882 } 1883 1884 static int psp_load_smu_fw(struct psp_context *psp) 1885 { 1886 int ret; 1887 struct amdgpu_device* adev = psp->adev; 1888 struct amdgpu_firmware_info *ucode = 1889 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 1890 struct amdgpu_ras *ras = psp->ras.ras; 1891 1892 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 1893 return 0; 1894 1895 1896 if (amdgpu_in_reset(adev) && ras && ras->supported) { 1897 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 1898 if (ret) { 1899 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 1900 } 1901 } 1902 1903 ret = psp_execute_np_fw_load(psp, ucode); 1904 1905 if (ret) 1906 DRM_ERROR("PSP load smu failed!\n"); 1907 1908 return ret; 1909 } 1910 1911 static bool fw_load_skip_check(struct psp_context *psp, 1912 struct amdgpu_firmware_info *ucode) 1913 { 1914 if (!ucode->fw) 1915 return true; 1916 1917 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 1918 (psp_smu_reload_quirk(psp) || 1919 psp->autoload_supported || 1920 psp->pmfw_centralized_cstate_management)) 1921 return true; 1922 1923 if (amdgpu_sriov_vf(psp->adev) && 1924 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 1925 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 1926 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 1927 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 1928 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 1929 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 1930 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 1931 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 1932 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 1933 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 1934 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 1935 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 1936 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 1937 /*skip ucode loading in SRIOV VF */ 1938 return true; 1939 1940 if (psp->autoload_supported && 1941 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 1942 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 1943 /* skip mec JT when autoload is enabled */ 1944 return true; 1945 1946 return false; 1947 } 1948 1949 static int psp_np_fw_load(struct psp_context *psp) 1950 { 1951 int i, ret; 1952 struct amdgpu_firmware_info *ucode; 1953 struct amdgpu_device* adev = psp->adev; 1954 1955 if (psp->autoload_supported && 1956 !psp->pmfw_centralized_cstate_management) { 1957 ret = psp_load_smu_fw(psp); 1958 if (ret) 1959 return ret; 1960 } 1961 1962 for (i = 0; i < adev->firmware.max_ucodes; i++) { 1963 ucode = &adev->firmware.ucode[i]; 1964 1965 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 1966 !fw_load_skip_check(psp, ucode)) { 1967 ret = psp_load_smu_fw(psp); 1968 if (ret) 1969 return ret; 1970 continue; 1971 } 1972 1973 if (fw_load_skip_check(psp, ucode)) 1974 continue; 1975 1976 if (psp->autoload_supported && 1977 (adev->asic_type == CHIP_SIENNA_CICHLID || 1978 adev->asic_type == CHIP_NAVY_FLOUNDER) && 1979 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 1980 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 1981 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 1982 /* PSP only receive one SDMA fw for sienna_cichlid, 1983 * as all four sdma fw are same */ 1984 continue; 1985 1986 psp_print_fw_hdr(psp, ucode); 1987 1988 ret = psp_execute_np_fw_load(psp, ucode); 1989 if (ret) 1990 return ret; 1991 1992 /* Start rlc autoload after psp recieved all the gfx firmware */ 1993 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 1994 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 1995 ret = psp_rlc_autoload_start(psp); 1996 if (ret) { 1997 DRM_ERROR("Failed to start rlc autoload\n"); 1998 return ret; 1999 } 2000 } 2001 } 2002 2003 return 0; 2004 } 2005 2006 static int psp_load_fw(struct amdgpu_device *adev) 2007 { 2008 int ret; 2009 struct psp_context *psp = &adev->psp; 2010 2011 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2012 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2013 goto skip_memalloc; 2014 } 2015 2016 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2017 if (!psp->cmd) 2018 return -ENOMEM; 2019 2020 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2021 AMDGPU_GEM_DOMAIN_GTT, 2022 &psp->fw_pri_bo, 2023 &psp->fw_pri_mc_addr, 2024 &psp->fw_pri_buf); 2025 if (ret) 2026 goto failed; 2027 2028 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2029 AMDGPU_GEM_DOMAIN_VRAM, 2030 &psp->fence_buf_bo, 2031 &psp->fence_buf_mc_addr, 2032 &psp->fence_buf); 2033 if (ret) 2034 goto failed; 2035 2036 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2037 AMDGPU_GEM_DOMAIN_VRAM, 2038 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2039 (void **)&psp->cmd_buf_mem); 2040 if (ret) 2041 goto failed; 2042 2043 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2044 2045 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2046 if (ret) { 2047 DRM_ERROR("PSP ring init failed!\n"); 2048 goto failed; 2049 } 2050 2051 skip_memalloc: 2052 ret = psp_hw_start(psp); 2053 if (ret) 2054 goto failed; 2055 2056 ret = psp_np_fw_load(psp); 2057 if (ret) 2058 goto failed; 2059 2060 ret = psp_asd_load(psp); 2061 if (ret) { 2062 DRM_ERROR("PSP load asd failed!\n"); 2063 return ret; 2064 } 2065 2066 if (psp->adev->psp.ta_fw) { 2067 ret = psp_ras_initialize(psp); 2068 if (ret) 2069 dev_err(psp->adev->dev, 2070 "RAS: Failed to initialize RAS\n"); 2071 2072 ret = psp_hdcp_initialize(psp); 2073 if (ret) 2074 dev_err(psp->adev->dev, 2075 "HDCP: Failed to initialize HDCP\n"); 2076 2077 ret = psp_dtm_initialize(psp); 2078 if (ret) 2079 dev_err(psp->adev->dev, 2080 "DTM: Failed to initialize DTM\n"); 2081 2082 ret = psp_rap_initialize(psp); 2083 if (ret) 2084 dev_err(psp->adev->dev, 2085 "RAP: Failed to initialize RAP\n"); 2086 } 2087 2088 return 0; 2089 2090 failed: 2091 /* 2092 * all cleanup jobs (xgmi terminate, ras terminate, 2093 * ring destroy, cmd/fence/fw buffers destory, 2094 * psp->cmd destory) are delayed to psp_hw_fini 2095 */ 2096 return ret; 2097 } 2098 2099 static int psp_hw_init(void *handle) 2100 { 2101 int ret; 2102 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2103 2104 mutex_lock(&adev->firmware.mutex); 2105 /* 2106 * This sequence is just used on hw_init only once, no need on 2107 * resume. 2108 */ 2109 ret = amdgpu_ucode_init_bo(adev); 2110 if (ret) 2111 goto failed; 2112 2113 ret = psp_load_fw(adev); 2114 if (ret) { 2115 DRM_ERROR("PSP firmware loading failed\n"); 2116 goto failed; 2117 } 2118 2119 mutex_unlock(&adev->firmware.mutex); 2120 return 0; 2121 2122 failed: 2123 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2124 mutex_unlock(&adev->firmware.mutex); 2125 return -EINVAL; 2126 } 2127 2128 static int psp_hw_fini(void *handle) 2129 { 2130 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2131 struct psp_context *psp = &adev->psp; 2132 int ret; 2133 2134 if (psp->adev->psp.ta_fw) { 2135 psp_ras_terminate(psp); 2136 psp_rap_terminate(psp); 2137 psp_dtm_terminate(psp); 2138 psp_hdcp_terminate(psp); 2139 } 2140 2141 psp_asd_unload(psp); 2142 ret = psp_clear_vf_fw(psp); 2143 if (ret) { 2144 DRM_ERROR("PSP clear vf fw!\n"); 2145 return ret; 2146 } 2147 2148 psp_tmr_terminate(psp); 2149 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2150 2151 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2152 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2153 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2154 &psp->fence_buf_mc_addr, &psp->fence_buf); 2155 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2156 (void **)&psp->cmd_buf_mem); 2157 2158 kfree(psp->cmd); 2159 psp->cmd = NULL; 2160 2161 return 0; 2162 } 2163 2164 static int psp_suspend(void *handle) 2165 { 2166 int ret; 2167 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2168 struct psp_context *psp = &adev->psp; 2169 2170 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2171 psp->xgmi_context.initialized == 1) { 2172 ret = psp_xgmi_terminate(psp); 2173 if (ret) { 2174 DRM_ERROR("Failed to terminate xgmi ta\n"); 2175 return ret; 2176 } 2177 } 2178 2179 if (psp->adev->psp.ta_fw) { 2180 ret = psp_ras_terminate(psp); 2181 if (ret) { 2182 DRM_ERROR("Failed to terminate ras ta\n"); 2183 return ret; 2184 } 2185 ret = psp_hdcp_terminate(psp); 2186 if (ret) { 2187 DRM_ERROR("Failed to terminate hdcp ta\n"); 2188 return ret; 2189 } 2190 ret = psp_dtm_terminate(psp); 2191 if (ret) { 2192 DRM_ERROR("Failed to terminate dtm ta\n"); 2193 return ret; 2194 } 2195 ret = psp_rap_terminate(psp); 2196 if (ret) { 2197 DRM_ERROR("Failed to terminate rap ta\n"); 2198 return ret; 2199 } 2200 } 2201 2202 ret = psp_asd_unload(psp); 2203 if (ret) { 2204 DRM_ERROR("Failed to unload asd\n"); 2205 return ret; 2206 } 2207 2208 ret = psp_tmr_terminate(psp); 2209 if (ret) { 2210 DRM_ERROR("Failed to terminate tmr\n"); 2211 return ret; 2212 } 2213 2214 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2215 if (ret) { 2216 DRM_ERROR("PSP ring stop failed\n"); 2217 return ret; 2218 } 2219 2220 return 0; 2221 } 2222 2223 static int psp_resume(void *handle) 2224 { 2225 int ret; 2226 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2227 struct psp_context *psp = &adev->psp; 2228 2229 DRM_INFO("PSP is resuming...\n"); 2230 2231 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2232 if (ret) { 2233 DRM_ERROR("Failed to process memory training!\n"); 2234 return ret; 2235 } 2236 2237 mutex_lock(&adev->firmware.mutex); 2238 2239 ret = psp_hw_start(psp); 2240 if (ret) 2241 goto failed; 2242 2243 ret = psp_np_fw_load(psp); 2244 if (ret) 2245 goto failed; 2246 2247 ret = psp_asd_load(psp); 2248 if (ret) { 2249 DRM_ERROR("PSP load asd failed!\n"); 2250 goto failed; 2251 } 2252 2253 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2254 ret = psp_xgmi_initialize(psp); 2255 /* Warning the XGMI seesion initialize failure 2256 * Instead of stop driver initialization 2257 */ 2258 if (ret) 2259 dev_err(psp->adev->dev, 2260 "XGMI: Failed to initialize XGMI session\n"); 2261 } 2262 2263 if (psp->adev->psp.ta_fw) { 2264 ret = psp_ras_initialize(psp); 2265 if (ret) 2266 dev_err(psp->adev->dev, 2267 "RAS: Failed to initialize RAS\n"); 2268 2269 ret = psp_hdcp_initialize(psp); 2270 if (ret) 2271 dev_err(psp->adev->dev, 2272 "HDCP: Failed to initialize HDCP\n"); 2273 2274 ret = psp_dtm_initialize(psp); 2275 if (ret) 2276 dev_err(psp->adev->dev, 2277 "DTM: Failed to initialize DTM\n"); 2278 2279 ret = psp_rap_initialize(psp); 2280 if (ret) 2281 dev_err(psp->adev->dev, 2282 "RAP: Failed to initialize RAP\n"); 2283 } 2284 2285 mutex_unlock(&adev->firmware.mutex); 2286 2287 return 0; 2288 2289 failed: 2290 DRM_ERROR("PSP resume failed\n"); 2291 mutex_unlock(&adev->firmware.mutex); 2292 return ret; 2293 } 2294 2295 int psp_gpu_reset(struct amdgpu_device *adev) 2296 { 2297 int ret; 2298 2299 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2300 return 0; 2301 2302 mutex_lock(&adev->psp.mutex); 2303 ret = psp_mode1_reset(&adev->psp); 2304 mutex_unlock(&adev->psp.mutex); 2305 2306 return ret; 2307 } 2308 2309 int psp_rlc_autoload_start(struct psp_context *psp) 2310 { 2311 int ret; 2312 struct psp_gfx_cmd_resp *cmd; 2313 2314 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2315 if (!cmd) 2316 return -ENOMEM; 2317 2318 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2319 2320 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2321 psp->fence_buf_mc_addr); 2322 kfree(cmd); 2323 return ret; 2324 } 2325 2326 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2327 uint64_t cmd_gpu_addr, int cmd_size) 2328 { 2329 struct amdgpu_firmware_info ucode = {0}; 2330 2331 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2332 AMDGPU_UCODE_ID_VCN0_RAM; 2333 ucode.mc_addr = cmd_gpu_addr; 2334 ucode.ucode_size = cmd_size; 2335 2336 return psp_execute_np_fw_load(&adev->psp, &ucode); 2337 } 2338 2339 int psp_ring_cmd_submit(struct psp_context *psp, 2340 uint64_t cmd_buf_mc_addr, 2341 uint64_t fence_mc_addr, 2342 int index) 2343 { 2344 unsigned int psp_write_ptr_reg = 0; 2345 struct psp_gfx_rb_frame *write_frame; 2346 struct psp_ring *ring = &psp->km_ring; 2347 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2348 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2349 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2350 struct amdgpu_device *adev = psp->adev; 2351 uint32_t ring_size_dw = ring->ring_size / 4; 2352 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2353 2354 /* KM (GPCOM) prepare write pointer */ 2355 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2356 2357 /* Update KM RB frame pointer to new frame */ 2358 /* write_frame ptr increments by size of rb_frame in bytes */ 2359 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2360 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2361 write_frame = ring_buffer_start; 2362 else 2363 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2364 /* Check invalid write_frame ptr address */ 2365 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2366 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2367 ring_buffer_start, ring_buffer_end, write_frame); 2368 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2369 return -EINVAL; 2370 } 2371 2372 /* Initialize KM RB frame */ 2373 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2374 2375 /* Update KM RB frame */ 2376 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2377 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2378 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2379 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2380 write_frame->fence_value = index; 2381 amdgpu_asic_flush_hdp(adev, NULL); 2382 2383 /* Update the write Pointer in DWORDs */ 2384 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2385 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2386 return 0; 2387 } 2388 2389 int psp_init_asd_microcode(struct psp_context *psp, 2390 const char *chip_name) 2391 { 2392 struct amdgpu_device *adev = psp->adev; 2393 char fw_name[30]; 2394 const struct psp_firmware_header_v1_0 *asd_hdr; 2395 int err = 0; 2396 2397 if (!chip_name) { 2398 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2399 return -EINVAL; 2400 } 2401 2402 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2403 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2404 if (err) 2405 goto out; 2406 2407 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2408 if (err) 2409 goto out; 2410 2411 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2412 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2413 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 2414 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2415 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2416 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2417 return 0; 2418 out: 2419 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2420 release_firmware(adev->psp.asd_fw); 2421 adev->psp.asd_fw = NULL; 2422 return err; 2423 } 2424 2425 int psp_init_sos_microcode(struct psp_context *psp, 2426 const char *chip_name) 2427 { 2428 struct amdgpu_device *adev = psp->adev; 2429 char fw_name[30]; 2430 const struct psp_firmware_header_v1_0 *sos_hdr; 2431 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 2432 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 2433 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2434 int err = 0; 2435 2436 if (!chip_name) { 2437 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 2438 return -EINVAL; 2439 } 2440 2441 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 2442 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 2443 if (err) 2444 goto out; 2445 2446 err = amdgpu_ucode_validate(adev->psp.sos_fw); 2447 if (err) 2448 goto out; 2449 2450 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2451 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 2452 2453 switch (sos_hdr->header.header_version_major) { 2454 case 1: 2455 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 2456 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 2457 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 2458 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 2459 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 2460 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2461 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2462 le32_to_cpu(sos_hdr->sos_offset_bytes); 2463 if (sos_hdr->header.header_version_minor == 1) { 2464 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 2465 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 2466 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2467 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 2468 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); 2469 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2470 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); 2471 } 2472 if (sos_hdr->header.header_version_minor == 2) { 2473 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 2474 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); 2475 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2476 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); 2477 } 2478 if (sos_hdr->header.header_version_minor == 3) { 2479 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 2480 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes); 2481 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2482 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes); 2483 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes); 2484 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2485 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes); 2486 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes); 2487 adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2488 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes); 2489 } 2490 break; 2491 default: 2492 dev_err(adev->dev, 2493 "unsupported psp sos firmware\n"); 2494 err = -EINVAL; 2495 goto out; 2496 } 2497 2498 return 0; 2499 out: 2500 dev_err(adev->dev, 2501 "failed to init sos firmware\n"); 2502 release_firmware(adev->psp.sos_fw); 2503 adev->psp.sos_fw = NULL; 2504 2505 return err; 2506 } 2507 2508 int parse_ta_bin_descriptor(struct psp_context *psp, 2509 const struct ta_fw_bin_desc *desc, 2510 const struct ta_firmware_header_v2_0 *ta_hdr) 2511 { 2512 uint8_t *ucode_start_addr = NULL; 2513 2514 if (!psp || !desc || !ta_hdr) 2515 return -EINVAL; 2516 2517 ucode_start_addr = (uint8_t *)ta_hdr + 2518 le32_to_cpu(desc->offset_bytes) + 2519 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 2520 2521 switch (desc->fw_type) { 2522 case TA_FW_TYPE_PSP_ASD: 2523 psp->asd_fw_version = le32_to_cpu(desc->fw_version); 2524 psp->asd_feature_version = le32_to_cpu(desc->fw_version); 2525 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 2526 psp->asd_start_addr = ucode_start_addr; 2527 break; 2528 case TA_FW_TYPE_PSP_XGMI: 2529 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 2530 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 2531 psp->ta_xgmi_start_addr = ucode_start_addr; 2532 break; 2533 case TA_FW_TYPE_PSP_RAS: 2534 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 2535 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 2536 psp->ta_ras_start_addr = ucode_start_addr; 2537 break; 2538 case TA_FW_TYPE_PSP_HDCP: 2539 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 2540 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 2541 psp->ta_hdcp_start_addr = ucode_start_addr; 2542 break; 2543 case TA_FW_TYPE_PSP_DTM: 2544 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 2545 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 2546 psp->ta_dtm_start_addr = ucode_start_addr; 2547 break; 2548 case TA_FW_TYPE_PSP_RAP: 2549 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version); 2550 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes); 2551 psp->ta_rap_start_addr = ucode_start_addr; 2552 break; 2553 default: 2554 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 2555 break; 2556 } 2557 2558 return 0; 2559 } 2560 2561 int psp_init_ta_microcode(struct psp_context *psp, 2562 const char *chip_name) 2563 { 2564 struct amdgpu_device *adev = psp->adev; 2565 char fw_name[30]; 2566 const struct ta_firmware_header_v2_0 *ta_hdr; 2567 int err = 0; 2568 int ta_index = 0; 2569 2570 if (!chip_name) { 2571 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 2572 return -EINVAL; 2573 } 2574 2575 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 2576 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 2577 if (err) 2578 goto out; 2579 2580 err = amdgpu_ucode_validate(adev->psp.ta_fw); 2581 if (err) 2582 goto out; 2583 2584 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 2585 2586 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 2587 dev_err(adev->dev, "unsupported TA header version\n"); 2588 err = -EINVAL; 2589 goto out; 2590 } 2591 2592 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) { 2593 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 2594 err = -EINVAL; 2595 goto out; 2596 } 2597 2598 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 2599 err = parse_ta_bin_descriptor(psp, 2600 &ta_hdr->ta_fw_bin[ta_index], 2601 ta_hdr); 2602 if (err) 2603 goto out; 2604 } 2605 2606 return 0; 2607 out: 2608 dev_err(adev->dev, "fail to initialize ta microcode\n"); 2609 release_firmware(adev->psp.ta_fw); 2610 adev->psp.ta_fw = NULL; 2611 return err; 2612 } 2613 2614 static int psp_set_clockgating_state(void *handle, 2615 enum amd_clockgating_state state) 2616 { 2617 return 0; 2618 } 2619 2620 static int psp_set_powergating_state(void *handle, 2621 enum amd_powergating_state state) 2622 { 2623 return 0; 2624 } 2625 2626 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 2627 struct device_attribute *attr, 2628 char *buf) 2629 { 2630 struct drm_device *ddev = dev_get_drvdata(dev); 2631 struct amdgpu_device *adev = drm_to_adev(ddev); 2632 uint32_t fw_ver; 2633 int ret; 2634 2635 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2636 DRM_INFO("PSP block is not ready yet."); 2637 return -EBUSY; 2638 } 2639 2640 mutex_lock(&adev->psp.mutex); 2641 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 2642 mutex_unlock(&adev->psp.mutex); 2643 2644 if (ret) { 2645 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 2646 return ret; 2647 } 2648 2649 return snprintf(buf, PAGE_SIZE, "%x\n", fw_ver); 2650 } 2651 2652 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 2653 struct device_attribute *attr, 2654 const char *buf, 2655 size_t count) 2656 { 2657 struct drm_device *ddev = dev_get_drvdata(dev); 2658 struct amdgpu_device *adev = drm_to_adev(ddev); 2659 void *cpu_addr; 2660 dma_addr_t dma_addr; 2661 int ret; 2662 char fw_name[100]; 2663 const struct firmware *usbc_pd_fw; 2664 2665 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2666 DRM_INFO("PSP block is not ready yet."); 2667 return -EBUSY; 2668 } 2669 2670 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 2671 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 2672 if (ret) 2673 goto fail; 2674 2675 /* We need contiguous physical mem to place the FW for psp to access */ 2676 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL); 2677 2678 ret = dma_mapping_error(adev->dev, dma_addr); 2679 if (ret) 2680 goto rel_buf; 2681 2682 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 2683 2684 /* 2685 * x86 specific workaround. 2686 * Without it the buffer is invisible in PSP. 2687 * 2688 * TODO Remove once PSP starts snooping CPU cache 2689 */ 2690 #ifdef CONFIG_X86 2691 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1))); 2692 #endif 2693 2694 mutex_lock(&adev->psp.mutex); 2695 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr); 2696 mutex_unlock(&adev->psp.mutex); 2697 2698 rel_buf: 2699 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr); 2700 release_firmware(usbc_pd_fw); 2701 2702 fail: 2703 if (ret) { 2704 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 2705 return ret; 2706 } 2707 2708 return count; 2709 } 2710 2711 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 2712 psp_usbc_pd_fw_sysfs_read, 2713 psp_usbc_pd_fw_sysfs_write); 2714 2715 2716 2717 const struct amd_ip_funcs psp_ip_funcs = { 2718 .name = "psp", 2719 .early_init = psp_early_init, 2720 .late_init = NULL, 2721 .sw_init = psp_sw_init, 2722 .sw_fini = psp_sw_fini, 2723 .hw_init = psp_hw_init, 2724 .hw_fini = psp_hw_fini, 2725 .suspend = psp_suspend, 2726 .resume = psp_resume, 2727 .is_idle = NULL, 2728 .check_soft_reset = NULL, 2729 .wait_for_idle = NULL, 2730 .soft_reset = NULL, 2731 .set_clockgating_state = psp_set_clockgating_state, 2732 .set_powergating_state = psp_set_powergating_state, 2733 }; 2734 2735 static int psp_sysfs_init(struct amdgpu_device *adev) 2736 { 2737 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 2738 2739 if (ret) 2740 DRM_ERROR("Failed to create USBC PD FW control file!"); 2741 2742 return ret; 2743 } 2744 2745 static void psp_sysfs_fini(struct amdgpu_device *adev) 2746 { 2747 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 2748 } 2749 2750 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 2751 { 2752 .type = AMD_IP_BLOCK_TYPE_PSP, 2753 .major = 3, 2754 .minor = 1, 2755 .rev = 0, 2756 .funcs = &psp_ip_funcs, 2757 }; 2758 2759 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 2760 { 2761 .type = AMD_IP_BLOCK_TYPE_PSP, 2762 .major = 10, 2763 .minor = 0, 2764 .rev = 0, 2765 .funcs = &psp_ip_funcs, 2766 }; 2767 2768 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 2769 { 2770 .type = AMD_IP_BLOCK_TYPE_PSP, 2771 .major = 11, 2772 .minor = 0, 2773 .rev = 0, 2774 .funcs = &psp_ip_funcs, 2775 }; 2776 2777 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 2778 { 2779 .type = AMD_IP_BLOCK_TYPE_PSP, 2780 .major = 12, 2781 .minor = 0, 2782 .rev = 0, 2783 .funcs = &psp_ip_funcs, 2784 }; 2785