1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/dma-mapping.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v3_1.h" 34 #include "psp_v10_0.h" 35 #include "psp_v11_0.h" 36 #include "psp_v12_0.h" 37 38 #include "amdgpu_ras.h" 39 40 static int psp_sysfs_init(struct amdgpu_device *adev); 41 static void psp_sysfs_fini(struct amdgpu_device *adev); 42 43 static int psp_load_smu_fw(struct psp_context *psp); 44 45 /* 46 * Due to DF Cstate management centralized to PMFW, the firmware 47 * loading sequence will be updated as below: 48 * - Load KDB 49 * - Load SYS_DRV 50 * - Load tOS 51 * - Load PMFW 52 * - Setup TMR 53 * - Load other non-psp fw 54 * - Load ASD 55 * - Load XGMI/RAS/HDCP/DTM TA if any 56 * 57 * This new sequence is required for 58 * - Arcturus 59 * - Navi12 and onwards 60 */ 61 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 62 { 63 struct amdgpu_device *adev = psp->adev; 64 65 psp->pmfw_centralized_cstate_management = false; 66 67 if (amdgpu_sriov_vf(adev)) 68 return; 69 70 if (adev->flags & AMD_IS_APU) 71 return; 72 73 if ((adev->asic_type == CHIP_ARCTURUS) || 74 (adev->asic_type >= CHIP_NAVI12)) 75 psp->pmfw_centralized_cstate_management = true; 76 } 77 78 static int psp_early_init(void *handle) 79 { 80 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 81 struct psp_context *psp = &adev->psp; 82 83 switch (adev->asic_type) { 84 case CHIP_VEGA10: 85 case CHIP_VEGA12: 86 psp_v3_1_set_psp_funcs(psp); 87 psp->autoload_supported = false; 88 break; 89 case CHIP_RAVEN: 90 psp_v10_0_set_psp_funcs(psp); 91 psp->autoload_supported = false; 92 break; 93 case CHIP_VEGA20: 94 case CHIP_ARCTURUS: 95 psp_v11_0_set_psp_funcs(psp); 96 psp->autoload_supported = false; 97 break; 98 case CHIP_NAVI10: 99 case CHIP_NAVI14: 100 case CHIP_NAVI12: 101 psp_v11_0_set_psp_funcs(psp); 102 psp->autoload_supported = true; 103 break; 104 case CHIP_RENOIR: 105 psp_v12_0_set_psp_funcs(psp); 106 break; 107 default: 108 return -EINVAL; 109 } 110 111 psp->adev = adev; 112 113 psp_check_pmfw_centralized_cstate_management(psp); 114 115 return 0; 116 } 117 118 static void psp_memory_training_fini(struct psp_context *psp) 119 { 120 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 121 122 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 123 kfree(ctx->sys_cache); 124 ctx->sys_cache = NULL; 125 } 126 127 static int psp_memory_training_init(struct psp_context *psp) 128 { 129 int ret; 130 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 131 132 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 133 DRM_DEBUG("memory training is not supported!\n"); 134 return 0; 135 } 136 137 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 138 if (ctx->sys_cache == NULL) { 139 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 140 ret = -ENOMEM; 141 goto Err_out; 142 } 143 144 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 145 ctx->train_data_size, 146 ctx->p2c_train_data_offset, 147 ctx->c2p_train_data_offset); 148 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 149 return 0; 150 151 Err_out: 152 psp_memory_training_fini(psp); 153 return ret; 154 } 155 156 static int psp_sw_init(void *handle) 157 { 158 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 159 struct psp_context *psp = &adev->psp; 160 int ret; 161 162 ret = psp_init_microcode(psp); 163 if (ret) { 164 DRM_ERROR("Failed to load psp firmware!\n"); 165 return ret; 166 } 167 168 ret = psp_memory_training_init(psp); 169 if (ret) { 170 DRM_ERROR("Failed to initialize memory training!\n"); 171 return ret; 172 } 173 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 174 if (ret) { 175 DRM_ERROR("Failed to process memory training!\n"); 176 return ret; 177 } 178 179 if (adev->asic_type == CHIP_NAVI10) { 180 ret= psp_sysfs_init(adev); 181 if (ret) { 182 return ret; 183 } 184 } 185 186 return 0; 187 } 188 189 static int psp_sw_fini(void *handle) 190 { 191 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 192 193 psp_memory_training_fini(&adev->psp); 194 release_firmware(adev->psp.sos_fw); 195 adev->psp.sos_fw = NULL; 196 release_firmware(adev->psp.asd_fw); 197 adev->psp.asd_fw = NULL; 198 if (adev->psp.ta_fw) { 199 release_firmware(adev->psp.ta_fw); 200 adev->psp.ta_fw = NULL; 201 } 202 203 if (adev->asic_type == CHIP_NAVI10) 204 psp_sysfs_fini(adev); 205 206 return 0; 207 } 208 209 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 210 uint32_t reg_val, uint32_t mask, bool check_changed) 211 { 212 uint32_t val; 213 int i; 214 struct amdgpu_device *adev = psp->adev; 215 216 for (i = 0; i < adev->usec_timeout; i++) { 217 val = RREG32(reg_index); 218 if (check_changed) { 219 if (val != reg_val) 220 return 0; 221 } else { 222 if ((val & mask) == reg_val) 223 return 0; 224 } 225 udelay(1); 226 } 227 228 return -ETIME; 229 } 230 231 static int 232 psp_cmd_submit_buf(struct psp_context *psp, 233 struct amdgpu_firmware_info *ucode, 234 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 235 { 236 int ret; 237 int index; 238 int timeout = 2000; 239 bool ras_intr = false; 240 bool skip_unsupport = false; 241 242 mutex_lock(&psp->mutex); 243 244 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 245 246 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 247 248 index = atomic_inc_return(&psp->fence_value); 249 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 250 if (ret) { 251 atomic_dec(&psp->fence_value); 252 mutex_unlock(&psp->mutex); 253 return ret; 254 } 255 256 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 257 while (*((unsigned int *)psp->fence_buf) != index) { 258 if (--timeout == 0) 259 break; 260 /* 261 * Shouldn't wait for timeout when err_event_athub occurs, 262 * because gpu reset thread triggered and lock resource should 263 * be released for psp resume sequence. 264 */ 265 ras_intr = amdgpu_ras_intr_triggered(); 266 if (ras_intr) 267 break; 268 msleep(1); 269 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 270 } 271 272 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command in SRIOV */ 273 skip_unsupport = (psp->cmd_buf_mem->resp.status == 0xffff000a) && amdgpu_sriov_vf(psp->adev); 274 275 /* In some cases, psp response status is not 0 even there is no 276 * problem while the command is submitted. Some version of PSP FW 277 * doesn't write 0 to that field. 278 * So here we would like to only print a warning instead of an error 279 * during psp initialization to avoid breaking hw_init and it doesn't 280 * return -EINVAL. 281 */ 282 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 283 if (ucode) 284 DRM_WARN("failed to load ucode id (%d) ", 285 ucode->ucode_id); 286 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n", 287 psp->cmd_buf_mem->cmd_id, 288 psp->cmd_buf_mem->resp.status); 289 if (!timeout) { 290 mutex_unlock(&psp->mutex); 291 return -EINVAL; 292 } 293 } 294 295 /* get xGMI session id from response buffer */ 296 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id; 297 298 if (ucode) { 299 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 300 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 301 } 302 mutex_unlock(&psp->mutex); 303 304 return ret; 305 } 306 307 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 308 struct psp_gfx_cmd_resp *cmd, 309 uint64_t tmr_mc, uint32_t size) 310 { 311 if (amdgpu_sriov_vf(psp->adev)) 312 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 313 else 314 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 315 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 316 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 317 cmd->cmd.cmd_setup_tmr.buf_size = size; 318 } 319 320 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 321 uint64_t pri_buf_mc, uint32_t size) 322 { 323 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 324 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 325 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 326 cmd->cmd.cmd_load_toc.toc_size = size; 327 } 328 329 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 330 static int psp_load_toc(struct psp_context *psp, 331 uint32_t *tmr_size) 332 { 333 int ret; 334 struct psp_gfx_cmd_resp *cmd; 335 336 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 337 if (!cmd) 338 return -ENOMEM; 339 /* Copy toc to psp firmware private buffer */ 340 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 341 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size); 342 343 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 344 345 ret = psp_cmd_submit_buf(psp, NULL, cmd, 346 psp->fence_buf_mc_addr); 347 if (!ret) 348 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 349 kfree(cmd); 350 return ret; 351 } 352 353 /* Set up Trusted Memory Region */ 354 static int psp_tmr_init(struct psp_context *psp) 355 { 356 int ret; 357 int tmr_size; 358 void *tmr_buf; 359 void **pptr; 360 361 /* 362 * According to HW engineer, they prefer the TMR address be "naturally 363 * aligned" , e.g. the start address be an integer divide of TMR size. 364 * 365 * Note: this memory need be reserved till the driver 366 * uninitializes. 367 */ 368 tmr_size = PSP_TMR_SIZE; 369 370 /* For ASICs support RLC autoload, psp will parse the toc 371 * and calculate the total size of TMR needed */ 372 if (!amdgpu_sriov_vf(psp->adev) && 373 psp->toc_start_addr && 374 psp->toc_bin_size && 375 psp->fw_pri_buf) { 376 ret = psp_load_toc(psp, &tmr_size); 377 if (ret) { 378 DRM_ERROR("Failed to load toc\n"); 379 return ret; 380 } 381 } 382 383 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 384 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE, 385 AMDGPU_GEM_DOMAIN_VRAM, 386 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 387 388 return ret; 389 } 390 391 static int psp_tmr_load(struct psp_context *psp) 392 { 393 int ret; 394 struct psp_gfx_cmd_resp *cmd; 395 396 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 397 if (!cmd) 398 return -ENOMEM; 399 400 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, 401 amdgpu_bo_size(psp->tmr_bo)); 402 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 403 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 404 405 ret = psp_cmd_submit_buf(psp, NULL, cmd, 406 psp->fence_buf_mc_addr); 407 408 kfree(cmd); 409 410 return ret; 411 } 412 413 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 414 uint64_t asd_mc, uint32_t size) 415 { 416 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 417 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 418 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 419 cmd->cmd.cmd_load_ta.app_len = size; 420 421 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 422 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 423 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 424 } 425 426 static int psp_asd_load(struct psp_context *psp) 427 { 428 int ret; 429 struct psp_gfx_cmd_resp *cmd; 430 431 /* If PSP version doesn't match ASD version, asd loading will be failed. 432 * add workaround to bypass it for sriov now. 433 * TODO: add version check to make it common 434 */ 435 if (amdgpu_sriov_vf(psp->adev)) 436 return 0; 437 438 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 439 if (!cmd) 440 return -ENOMEM; 441 442 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 443 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 444 445 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 446 psp->asd_ucode_size); 447 448 ret = psp_cmd_submit_buf(psp, NULL, cmd, 449 psp->fence_buf_mc_addr); 450 if (!ret) { 451 psp->asd_context.asd_initialized = true; 452 psp->asd_context.session_id = cmd->resp.session_id; 453 } 454 455 kfree(cmd); 456 457 return ret; 458 } 459 460 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 461 uint32_t session_id) 462 { 463 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 464 cmd->cmd.cmd_unload_ta.session_id = session_id; 465 } 466 467 static int psp_asd_unload(struct psp_context *psp) 468 { 469 int ret; 470 struct psp_gfx_cmd_resp *cmd; 471 472 if (amdgpu_sriov_vf(psp->adev)) 473 return 0; 474 475 if (!psp->asd_context.asd_initialized) 476 return 0; 477 478 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 479 if (!cmd) 480 return -ENOMEM; 481 482 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 483 484 ret = psp_cmd_submit_buf(psp, NULL, cmd, 485 psp->fence_buf_mc_addr); 486 if (!ret) 487 psp->asd_context.asd_initialized = false; 488 489 kfree(cmd); 490 491 return ret; 492 } 493 494 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 495 uint32_t id, uint32_t value) 496 { 497 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 498 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 499 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 500 } 501 502 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 503 uint32_t value) 504 { 505 struct psp_gfx_cmd_resp *cmd = NULL; 506 int ret = 0; 507 508 if (reg >= PSP_REG_LAST) 509 return -EINVAL; 510 511 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 512 if (!cmd) 513 return -ENOMEM; 514 515 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 516 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 517 518 kfree(cmd); 519 return ret; 520 } 521 522 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 523 uint64_t ta_bin_mc, 524 uint32_t ta_bin_size, 525 uint64_t ta_shared_mc, 526 uint32_t ta_shared_size) 527 { 528 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 529 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 530 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 531 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 532 533 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 534 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 535 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 536 } 537 538 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 539 { 540 int ret; 541 542 /* 543 * Allocate 16k memory aligned to 4k from Frame Buffer (local 544 * physical) for xgmi ta <-> Driver 545 */ 546 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 547 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 548 &psp->xgmi_context.xgmi_shared_bo, 549 &psp->xgmi_context.xgmi_shared_mc_addr, 550 &psp->xgmi_context.xgmi_shared_buf); 551 552 return ret; 553 } 554 555 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 556 uint32_t ta_cmd_id, 557 uint32_t session_id) 558 { 559 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 560 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 561 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 562 } 563 564 int psp_ta_invoke(struct psp_context *psp, 565 uint32_t ta_cmd_id, 566 uint32_t session_id) 567 { 568 int ret; 569 struct psp_gfx_cmd_resp *cmd; 570 571 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 572 if (!cmd) 573 return -ENOMEM; 574 575 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 576 577 ret = psp_cmd_submit_buf(psp, NULL, cmd, 578 psp->fence_buf_mc_addr); 579 580 kfree(cmd); 581 582 return ret; 583 } 584 585 static int psp_xgmi_load(struct psp_context *psp) 586 { 587 int ret; 588 struct psp_gfx_cmd_resp *cmd; 589 590 /* 591 * TODO: bypass the loading in sriov for now 592 */ 593 594 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 595 if (!cmd) 596 return -ENOMEM; 597 598 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 599 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 600 601 psp_prep_ta_load_cmd_buf(cmd, 602 psp->fw_pri_mc_addr, 603 psp->ta_xgmi_ucode_size, 604 psp->xgmi_context.xgmi_shared_mc_addr, 605 PSP_XGMI_SHARED_MEM_SIZE); 606 607 ret = psp_cmd_submit_buf(psp, NULL, cmd, 608 psp->fence_buf_mc_addr); 609 610 if (!ret) { 611 psp->xgmi_context.initialized = 1; 612 psp->xgmi_context.session_id = cmd->resp.session_id; 613 } 614 615 kfree(cmd); 616 617 return ret; 618 } 619 620 static int psp_xgmi_unload(struct psp_context *psp) 621 { 622 int ret; 623 struct psp_gfx_cmd_resp *cmd; 624 struct amdgpu_device *adev = psp->adev; 625 626 /* XGMI TA unload currently is not supported on Arcturus */ 627 if (adev->asic_type == CHIP_ARCTURUS) 628 return 0; 629 630 /* 631 * TODO: bypass the unloading in sriov for now 632 */ 633 634 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 635 if (!cmd) 636 return -ENOMEM; 637 638 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 639 640 ret = psp_cmd_submit_buf(psp, NULL, cmd, 641 psp->fence_buf_mc_addr); 642 643 kfree(cmd); 644 645 return ret; 646 } 647 648 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 649 { 650 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 651 } 652 653 int psp_xgmi_terminate(struct psp_context *psp) 654 { 655 int ret; 656 657 if (!psp->xgmi_context.initialized) 658 return 0; 659 660 ret = psp_xgmi_unload(psp); 661 if (ret) 662 return ret; 663 664 psp->xgmi_context.initialized = 0; 665 666 /* free xgmi shared memory */ 667 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 668 &psp->xgmi_context.xgmi_shared_mc_addr, 669 &psp->xgmi_context.xgmi_shared_buf); 670 671 return 0; 672 } 673 674 int psp_xgmi_initialize(struct psp_context *psp) 675 { 676 struct ta_xgmi_shared_memory *xgmi_cmd; 677 int ret; 678 679 if (!psp->adev->psp.ta_fw || 680 !psp->adev->psp.ta_xgmi_ucode_size || 681 !psp->adev->psp.ta_xgmi_start_addr) 682 return -ENOENT; 683 684 if (!psp->xgmi_context.initialized) { 685 ret = psp_xgmi_init_shared_buf(psp); 686 if (ret) 687 return ret; 688 } 689 690 /* Load XGMI TA */ 691 ret = psp_xgmi_load(psp); 692 if (ret) 693 return ret; 694 695 /* Initialize XGMI session */ 696 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 697 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 698 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 699 700 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 701 702 return ret; 703 } 704 705 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 706 { 707 struct ta_xgmi_shared_memory *xgmi_cmd; 708 int ret; 709 710 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 711 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 712 713 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 714 715 /* Invoke xgmi ta to get hive id */ 716 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 717 if (ret) 718 return ret; 719 720 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 721 722 return 0; 723 } 724 725 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 726 { 727 struct ta_xgmi_shared_memory *xgmi_cmd; 728 int ret; 729 730 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 731 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 732 733 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 734 735 /* Invoke xgmi ta to get the node id */ 736 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 737 if (ret) 738 return ret; 739 740 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 741 742 return 0; 743 } 744 745 int psp_xgmi_get_topology_info(struct psp_context *psp, 746 int number_devices, 747 struct psp_xgmi_topology_info *topology) 748 { 749 struct ta_xgmi_shared_memory *xgmi_cmd; 750 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 751 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 752 int i; 753 int ret; 754 755 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 756 return -EINVAL; 757 758 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 759 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 760 761 /* Fill in the shared memory with topology information as input */ 762 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 763 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 764 topology_info_input->num_nodes = number_devices; 765 766 for (i = 0; i < topology_info_input->num_nodes; i++) { 767 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 768 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 769 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 770 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 771 } 772 773 /* Invoke xgmi ta to get the topology information */ 774 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 775 if (ret) 776 return ret; 777 778 /* Read the output topology information from the shared memory */ 779 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 780 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 781 for (i = 0; i < topology->num_nodes; i++) { 782 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 783 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 784 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 785 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 786 } 787 788 return 0; 789 } 790 791 int psp_xgmi_set_topology_info(struct psp_context *psp, 792 int number_devices, 793 struct psp_xgmi_topology_info *topology) 794 { 795 struct ta_xgmi_shared_memory *xgmi_cmd; 796 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 797 int i; 798 799 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 800 return -EINVAL; 801 802 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 803 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 804 805 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 806 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 807 topology_info_input->num_nodes = number_devices; 808 809 for (i = 0; i < topology_info_input->num_nodes; i++) { 810 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 811 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 812 topology_info_input->nodes[i].is_sharing_enabled = 1; 813 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 814 } 815 816 /* Invoke xgmi ta to set topology information */ 817 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 818 } 819 820 // ras begin 821 static int psp_ras_init_shared_buf(struct psp_context *psp) 822 { 823 int ret; 824 825 /* 826 * Allocate 16k memory aligned to 4k from Frame Buffer (local 827 * physical) for ras ta <-> Driver 828 */ 829 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 830 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 831 &psp->ras.ras_shared_bo, 832 &psp->ras.ras_shared_mc_addr, 833 &psp->ras.ras_shared_buf); 834 835 return ret; 836 } 837 838 static int psp_ras_load(struct psp_context *psp) 839 { 840 int ret; 841 struct psp_gfx_cmd_resp *cmd; 842 843 /* 844 * TODO: bypass the loading in sriov for now 845 */ 846 if (amdgpu_sriov_vf(psp->adev)) 847 return 0; 848 849 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 850 if (!cmd) 851 return -ENOMEM; 852 853 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 854 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 855 856 psp_prep_ta_load_cmd_buf(cmd, 857 psp->fw_pri_mc_addr, 858 psp->ta_ras_ucode_size, 859 psp->ras.ras_shared_mc_addr, 860 PSP_RAS_SHARED_MEM_SIZE); 861 862 ret = psp_cmd_submit_buf(psp, NULL, cmd, 863 psp->fence_buf_mc_addr); 864 865 if (!ret) { 866 psp->ras.ras_initialized = true; 867 psp->ras.session_id = cmd->resp.session_id; 868 } 869 870 kfree(cmd); 871 872 return ret; 873 } 874 875 static int psp_ras_unload(struct psp_context *psp) 876 { 877 int ret; 878 struct psp_gfx_cmd_resp *cmd; 879 880 /* 881 * TODO: bypass the unloading in sriov for now 882 */ 883 if (amdgpu_sriov_vf(psp->adev)) 884 return 0; 885 886 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 887 if (!cmd) 888 return -ENOMEM; 889 890 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 891 892 ret = psp_cmd_submit_buf(psp, NULL, cmd, 893 psp->fence_buf_mc_addr); 894 895 kfree(cmd); 896 897 return ret; 898 } 899 900 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 901 { 902 struct ta_ras_shared_memory *ras_cmd; 903 int ret; 904 905 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 906 907 /* 908 * TODO: bypass the loading in sriov for now 909 */ 910 if (amdgpu_sriov_vf(psp->adev)) 911 return 0; 912 913 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 914 915 if (amdgpu_ras_intr_triggered()) 916 return ret; 917 918 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 919 { 920 DRM_WARN("RAS: Unsupported Interface"); 921 return -EINVAL; 922 } 923 924 if (!ret) { 925 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 926 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 927 928 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 929 } 930 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 931 dev_warn(psp->adev->dev, 932 "RAS internal register access blocked\n"); 933 } 934 935 return ret; 936 } 937 938 int psp_ras_enable_features(struct psp_context *psp, 939 union ta_ras_cmd_input *info, bool enable) 940 { 941 struct ta_ras_shared_memory *ras_cmd; 942 int ret; 943 944 if (!psp->ras.ras_initialized) 945 return -EINVAL; 946 947 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 948 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 949 950 if (enable) 951 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 952 else 953 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 954 955 ras_cmd->ras_in_message = *info; 956 957 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 958 if (ret) 959 return -EINVAL; 960 961 return ras_cmd->ras_status; 962 } 963 964 static int psp_ras_terminate(struct psp_context *psp) 965 { 966 int ret; 967 968 /* 969 * TODO: bypass the terminate in sriov for now 970 */ 971 if (amdgpu_sriov_vf(psp->adev)) 972 return 0; 973 974 if (!psp->ras.ras_initialized) 975 return 0; 976 977 ret = psp_ras_unload(psp); 978 if (ret) 979 return ret; 980 981 psp->ras.ras_initialized = false; 982 983 /* free ras shared memory */ 984 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 985 &psp->ras.ras_shared_mc_addr, 986 &psp->ras.ras_shared_buf); 987 988 return 0; 989 } 990 991 static int psp_ras_initialize(struct psp_context *psp) 992 { 993 int ret; 994 995 /* 996 * TODO: bypass the initialize in sriov for now 997 */ 998 if (amdgpu_sriov_vf(psp->adev)) 999 return 0; 1000 1001 if (!psp->adev->psp.ta_ras_ucode_size || 1002 !psp->adev->psp.ta_ras_start_addr) { 1003 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n"); 1004 return 0; 1005 } 1006 1007 if (!psp->ras.ras_initialized) { 1008 ret = psp_ras_init_shared_buf(psp); 1009 if (ret) 1010 return ret; 1011 } 1012 1013 ret = psp_ras_load(psp); 1014 if (ret) 1015 return ret; 1016 1017 return 0; 1018 } 1019 1020 int psp_ras_trigger_error(struct psp_context *psp, 1021 struct ta_ras_trigger_error_input *info) 1022 { 1023 struct ta_ras_shared_memory *ras_cmd; 1024 int ret; 1025 1026 if (!psp->ras.ras_initialized) 1027 return -EINVAL; 1028 1029 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1030 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1031 1032 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1033 ras_cmd->ras_in_message.trigger_error = *info; 1034 1035 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1036 if (ret) 1037 return -EINVAL; 1038 1039 /* If err_event_athub occurs error inject was successful, however 1040 return status from TA is no long reliable */ 1041 if (amdgpu_ras_intr_triggered()) 1042 return 0; 1043 1044 return ras_cmd->ras_status; 1045 } 1046 // ras end 1047 1048 // HDCP start 1049 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1050 { 1051 int ret; 1052 1053 /* 1054 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1055 * physical) for hdcp ta <-> Driver 1056 */ 1057 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1058 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1059 &psp->hdcp_context.hdcp_shared_bo, 1060 &psp->hdcp_context.hdcp_shared_mc_addr, 1061 &psp->hdcp_context.hdcp_shared_buf); 1062 1063 return ret; 1064 } 1065 1066 static int psp_hdcp_load(struct psp_context *psp) 1067 { 1068 int ret; 1069 struct psp_gfx_cmd_resp *cmd; 1070 1071 /* 1072 * TODO: bypass the loading in sriov for now 1073 */ 1074 if (amdgpu_sriov_vf(psp->adev)) 1075 return 0; 1076 1077 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1078 if (!cmd) 1079 return -ENOMEM; 1080 1081 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1082 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr, 1083 psp->ta_hdcp_ucode_size); 1084 1085 psp_prep_ta_load_cmd_buf(cmd, 1086 psp->fw_pri_mc_addr, 1087 psp->ta_hdcp_ucode_size, 1088 psp->hdcp_context.hdcp_shared_mc_addr, 1089 PSP_HDCP_SHARED_MEM_SIZE); 1090 1091 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1092 1093 if (!ret) { 1094 psp->hdcp_context.hdcp_initialized = true; 1095 psp->hdcp_context.session_id = cmd->resp.session_id; 1096 mutex_init(&psp->hdcp_context.mutex); 1097 } 1098 1099 kfree(cmd); 1100 1101 return ret; 1102 } 1103 static int psp_hdcp_initialize(struct psp_context *psp) 1104 { 1105 int ret; 1106 1107 /* 1108 * TODO: bypass the initialize in sriov for now 1109 */ 1110 if (amdgpu_sriov_vf(psp->adev)) 1111 return 0; 1112 1113 if (!psp->adev->psp.ta_hdcp_ucode_size || 1114 !psp->adev->psp.ta_hdcp_start_addr) { 1115 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1116 return 0; 1117 } 1118 1119 if (!psp->hdcp_context.hdcp_initialized) { 1120 ret = psp_hdcp_init_shared_buf(psp); 1121 if (ret) 1122 return ret; 1123 } 1124 1125 ret = psp_hdcp_load(psp); 1126 if (ret) 1127 return ret; 1128 1129 return 0; 1130 } 1131 1132 static int psp_hdcp_unload(struct psp_context *psp) 1133 { 1134 int ret; 1135 struct psp_gfx_cmd_resp *cmd; 1136 1137 /* 1138 * TODO: bypass the unloading in sriov for now 1139 */ 1140 if (amdgpu_sriov_vf(psp->adev)) 1141 return 0; 1142 1143 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1144 if (!cmd) 1145 return -ENOMEM; 1146 1147 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1148 1149 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1150 1151 kfree(cmd); 1152 1153 return ret; 1154 } 1155 1156 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1157 { 1158 /* 1159 * TODO: bypass the loading in sriov for now 1160 */ 1161 if (amdgpu_sriov_vf(psp->adev)) 1162 return 0; 1163 1164 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1165 } 1166 1167 static int psp_hdcp_terminate(struct psp_context *psp) 1168 { 1169 int ret; 1170 1171 /* 1172 * TODO: bypass the terminate in sriov for now 1173 */ 1174 if (amdgpu_sriov_vf(psp->adev)) 1175 return 0; 1176 1177 if (!psp->hdcp_context.hdcp_initialized) 1178 return 0; 1179 1180 ret = psp_hdcp_unload(psp); 1181 if (ret) 1182 return ret; 1183 1184 psp->hdcp_context.hdcp_initialized = false; 1185 1186 /* free hdcp shared memory */ 1187 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1188 &psp->hdcp_context.hdcp_shared_mc_addr, 1189 &psp->hdcp_context.hdcp_shared_buf); 1190 1191 return 0; 1192 } 1193 // HDCP end 1194 1195 // DTM start 1196 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1197 { 1198 int ret; 1199 1200 /* 1201 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1202 * physical) for dtm ta <-> Driver 1203 */ 1204 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1205 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1206 &psp->dtm_context.dtm_shared_bo, 1207 &psp->dtm_context.dtm_shared_mc_addr, 1208 &psp->dtm_context.dtm_shared_buf); 1209 1210 return ret; 1211 } 1212 1213 static int psp_dtm_load(struct psp_context *psp) 1214 { 1215 int ret; 1216 struct psp_gfx_cmd_resp *cmd; 1217 1218 /* 1219 * TODO: bypass the loading in sriov for now 1220 */ 1221 if (amdgpu_sriov_vf(psp->adev)) 1222 return 0; 1223 1224 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1225 if (!cmd) 1226 return -ENOMEM; 1227 1228 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1229 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1230 1231 psp_prep_ta_load_cmd_buf(cmd, 1232 psp->fw_pri_mc_addr, 1233 psp->ta_dtm_ucode_size, 1234 psp->dtm_context.dtm_shared_mc_addr, 1235 PSP_DTM_SHARED_MEM_SIZE); 1236 1237 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1238 1239 if (!ret) { 1240 psp->dtm_context.dtm_initialized = true; 1241 psp->dtm_context.session_id = cmd->resp.session_id; 1242 mutex_init(&psp->dtm_context.mutex); 1243 } 1244 1245 kfree(cmd); 1246 1247 return ret; 1248 } 1249 1250 static int psp_dtm_initialize(struct psp_context *psp) 1251 { 1252 int ret; 1253 1254 /* 1255 * TODO: bypass the initialize in sriov for now 1256 */ 1257 if (amdgpu_sriov_vf(psp->adev)) 1258 return 0; 1259 1260 if (!psp->adev->psp.ta_dtm_ucode_size || 1261 !psp->adev->psp.ta_dtm_start_addr) { 1262 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1263 return 0; 1264 } 1265 1266 if (!psp->dtm_context.dtm_initialized) { 1267 ret = psp_dtm_init_shared_buf(psp); 1268 if (ret) 1269 return ret; 1270 } 1271 1272 ret = psp_dtm_load(psp); 1273 if (ret) 1274 return ret; 1275 1276 return 0; 1277 } 1278 1279 static int psp_dtm_unload(struct psp_context *psp) 1280 { 1281 int ret; 1282 struct psp_gfx_cmd_resp *cmd; 1283 1284 /* 1285 * TODO: bypass the unloading in sriov for now 1286 */ 1287 if (amdgpu_sriov_vf(psp->adev)) 1288 return 0; 1289 1290 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1291 if (!cmd) 1292 return -ENOMEM; 1293 1294 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1295 1296 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1297 1298 kfree(cmd); 1299 1300 return ret; 1301 } 1302 1303 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1304 { 1305 /* 1306 * TODO: bypass the loading in sriov for now 1307 */ 1308 if (amdgpu_sriov_vf(psp->adev)) 1309 return 0; 1310 1311 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1312 } 1313 1314 static int psp_dtm_terminate(struct psp_context *psp) 1315 { 1316 int ret; 1317 1318 /* 1319 * TODO: bypass the terminate in sriov for now 1320 */ 1321 if (amdgpu_sriov_vf(psp->adev)) 1322 return 0; 1323 1324 if (!psp->dtm_context.dtm_initialized) 1325 return 0; 1326 1327 ret = psp_dtm_unload(psp); 1328 if (ret) 1329 return ret; 1330 1331 psp->dtm_context.dtm_initialized = false; 1332 1333 /* free hdcp shared memory */ 1334 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1335 &psp->dtm_context.dtm_shared_mc_addr, 1336 &psp->dtm_context.dtm_shared_buf); 1337 1338 return 0; 1339 } 1340 // DTM end 1341 1342 static int psp_hw_start(struct psp_context *psp) 1343 { 1344 struct amdgpu_device *adev = psp->adev; 1345 int ret; 1346 1347 if (!amdgpu_sriov_vf(adev)) { 1348 if (psp->kdb_bin_size && 1349 (psp->funcs->bootloader_load_kdb != NULL)) { 1350 ret = psp_bootloader_load_kdb(psp); 1351 if (ret) { 1352 DRM_ERROR("PSP load kdb failed!\n"); 1353 return ret; 1354 } 1355 } 1356 1357 ret = psp_bootloader_load_sysdrv(psp); 1358 if (ret) { 1359 DRM_ERROR("PSP load sysdrv failed!\n"); 1360 return ret; 1361 } 1362 1363 ret = psp_bootloader_load_sos(psp); 1364 if (ret) { 1365 DRM_ERROR("PSP load sos failed!\n"); 1366 return ret; 1367 } 1368 } 1369 1370 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1371 if (ret) { 1372 DRM_ERROR("PSP create ring failed!\n"); 1373 return ret; 1374 } 1375 1376 ret = psp_tmr_init(psp); 1377 if (ret) { 1378 DRM_ERROR("PSP tmr init failed!\n"); 1379 return ret; 1380 } 1381 1382 /* 1383 * For ASICs with DF Cstate management centralized 1384 * to PMFW, TMR setup should be performed after PMFW 1385 * loaded and before other non-psp firmware loaded. 1386 */ 1387 if (psp->pmfw_centralized_cstate_management) { 1388 ret = psp_load_smu_fw(psp); 1389 if (ret) 1390 return ret; 1391 } 1392 1393 ret = psp_tmr_load(psp); 1394 if (ret) { 1395 DRM_ERROR("PSP load tmr failed!\n"); 1396 return ret; 1397 } 1398 1399 return 0; 1400 } 1401 1402 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 1403 enum psp_gfx_fw_type *type) 1404 { 1405 switch (ucode->ucode_id) { 1406 case AMDGPU_UCODE_ID_SDMA0: 1407 *type = GFX_FW_TYPE_SDMA0; 1408 break; 1409 case AMDGPU_UCODE_ID_SDMA1: 1410 *type = GFX_FW_TYPE_SDMA1; 1411 break; 1412 case AMDGPU_UCODE_ID_SDMA2: 1413 *type = GFX_FW_TYPE_SDMA2; 1414 break; 1415 case AMDGPU_UCODE_ID_SDMA3: 1416 *type = GFX_FW_TYPE_SDMA3; 1417 break; 1418 case AMDGPU_UCODE_ID_SDMA4: 1419 *type = GFX_FW_TYPE_SDMA4; 1420 break; 1421 case AMDGPU_UCODE_ID_SDMA5: 1422 *type = GFX_FW_TYPE_SDMA5; 1423 break; 1424 case AMDGPU_UCODE_ID_SDMA6: 1425 *type = GFX_FW_TYPE_SDMA6; 1426 break; 1427 case AMDGPU_UCODE_ID_SDMA7: 1428 *type = GFX_FW_TYPE_SDMA7; 1429 break; 1430 case AMDGPU_UCODE_ID_CP_CE: 1431 *type = GFX_FW_TYPE_CP_CE; 1432 break; 1433 case AMDGPU_UCODE_ID_CP_PFP: 1434 *type = GFX_FW_TYPE_CP_PFP; 1435 break; 1436 case AMDGPU_UCODE_ID_CP_ME: 1437 *type = GFX_FW_TYPE_CP_ME; 1438 break; 1439 case AMDGPU_UCODE_ID_CP_MEC1: 1440 *type = GFX_FW_TYPE_CP_MEC; 1441 break; 1442 case AMDGPU_UCODE_ID_CP_MEC1_JT: 1443 *type = GFX_FW_TYPE_CP_MEC_ME1; 1444 break; 1445 case AMDGPU_UCODE_ID_CP_MEC2: 1446 *type = GFX_FW_TYPE_CP_MEC; 1447 break; 1448 case AMDGPU_UCODE_ID_CP_MEC2_JT: 1449 *type = GFX_FW_TYPE_CP_MEC_ME2; 1450 break; 1451 case AMDGPU_UCODE_ID_RLC_G: 1452 *type = GFX_FW_TYPE_RLC_G; 1453 break; 1454 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 1455 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 1456 break; 1457 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 1458 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 1459 break; 1460 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 1461 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 1462 break; 1463 case AMDGPU_UCODE_ID_SMC: 1464 *type = GFX_FW_TYPE_SMU; 1465 break; 1466 case AMDGPU_UCODE_ID_UVD: 1467 *type = GFX_FW_TYPE_UVD; 1468 break; 1469 case AMDGPU_UCODE_ID_UVD1: 1470 *type = GFX_FW_TYPE_UVD1; 1471 break; 1472 case AMDGPU_UCODE_ID_VCE: 1473 *type = GFX_FW_TYPE_VCE; 1474 break; 1475 case AMDGPU_UCODE_ID_VCN: 1476 *type = GFX_FW_TYPE_VCN; 1477 break; 1478 case AMDGPU_UCODE_ID_VCN1: 1479 *type = GFX_FW_TYPE_VCN1; 1480 break; 1481 case AMDGPU_UCODE_ID_DMCU_ERAM: 1482 *type = GFX_FW_TYPE_DMCU_ERAM; 1483 break; 1484 case AMDGPU_UCODE_ID_DMCU_INTV: 1485 *type = GFX_FW_TYPE_DMCU_ISR; 1486 break; 1487 case AMDGPU_UCODE_ID_VCN0_RAM: 1488 *type = GFX_FW_TYPE_VCN0_RAM; 1489 break; 1490 case AMDGPU_UCODE_ID_VCN1_RAM: 1491 *type = GFX_FW_TYPE_VCN1_RAM; 1492 break; 1493 case AMDGPU_UCODE_ID_DMCUB: 1494 *type = GFX_FW_TYPE_DMUB; 1495 break; 1496 case AMDGPU_UCODE_ID_MAXIMUM: 1497 default: 1498 return -EINVAL; 1499 } 1500 1501 return 0; 1502 } 1503 1504 static void psp_print_fw_hdr(struct psp_context *psp, 1505 struct amdgpu_firmware_info *ucode) 1506 { 1507 struct amdgpu_device *adev = psp->adev; 1508 struct common_firmware_header *hdr; 1509 1510 switch (ucode->ucode_id) { 1511 case AMDGPU_UCODE_ID_SDMA0: 1512 case AMDGPU_UCODE_ID_SDMA1: 1513 case AMDGPU_UCODE_ID_SDMA2: 1514 case AMDGPU_UCODE_ID_SDMA3: 1515 case AMDGPU_UCODE_ID_SDMA4: 1516 case AMDGPU_UCODE_ID_SDMA5: 1517 case AMDGPU_UCODE_ID_SDMA6: 1518 case AMDGPU_UCODE_ID_SDMA7: 1519 hdr = (struct common_firmware_header *) 1520 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 1521 amdgpu_ucode_print_sdma_hdr(hdr); 1522 break; 1523 case AMDGPU_UCODE_ID_CP_CE: 1524 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 1525 amdgpu_ucode_print_gfx_hdr(hdr); 1526 break; 1527 case AMDGPU_UCODE_ID_CP_PFP: 1528 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 1529 amdgpu_ucode_print_gfx_hdr(hdr); 1530 break; 1531 case AMDGPU_UCODE_ID_CP_ME: 1532 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 1533 amdgpu_ucode_print_gfx_hdr(hdr); 1534 break; 1535 case AMDGPU_UCODE_ID_CP_MEC1: 1536 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 1537 amdgpu_ucode_print_gfx_hdr(hdr); 1538 break; 1539 case AMDGPU_UCODE_ID_RLC_G: 1540 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 1541 amdgpu_ucode_print_rlc_hdr(hdr); 1542 break; 1543 case AMDGPU_UCODE_ID_SMC: 1544 hdr = (struct common_firmware_header *)adev->pm.fw->data; 1545 amdgpu_ucode_print_smc_hdr(hdr); 1546 break; 1547 default: 1548 break; 1549 } 1550 } 1551 1552 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 1553 struct psp_gfx_cmd_resp *cmd) 1554 { 1555 int ret; 1556 uint64_t fw_mem_mc_addr = ucode->mc_addr; 1557 1558 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 1559 1560 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1561 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 1562 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 1563 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 1564 1565 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 1566 if (ret) 1567 DRM_ERROR("Unknown firmware type\n"); 1568 1569 return ret; 1570 } 1571 1572 static int psp_execute_np_fw_load(struct psp_context *psp, 1573 struct amdgpu_firmware_info *ucode) 1574 { 1575 int ret = 0; 1576 1577 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 1578 if (ret) 1579 return ret; 1580 1581 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 1582 psp->fence_buf_mc_addr); 1583 1584 return ret; 1585 } 1586 1587 static int psp_load_smu_fw(struct psp_context *psp) 1588 { 1589 int ret; 1590 struct amdgpu_device* adev = psp->adev; 1591 struct amdgpu_firmware_info *ucode = 1592 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 1593 struct amdgpu_ras *ras = psp->ras.ras; 1594 1595 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 1596 return 0; 1597 1598 1599 if (adev->in_gpu_reset && ras && ras->supported) { 1600 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 1601 if (ret) { 1602 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 1603 } 1604 } 1605 1606 ret = psp_execute_np_fw_load(psp, ucode); 1607 1608 if (ret) 1609 DRM_ERROR("PSP load smu failed!\n"); 1610 1611 return ret; 1612 } 1613 1614 static bool fw_load_skip_check(struct psp_context *psp, 1615 struct amdgpu_firmware_info *ucode) 1616 { 1617 if (!ucode->fw) 1618 return true; 1619 1620 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 1621 (psp_smu_reload_quirk(psp) || 1622 psp->autoload_supported || 1623 psp->pmfw_centralized_cstate_management)) 1624 return true; 1625 1626 if (amdgpu_sriov_vf(psp->adev) && 1627 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 1628 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 1629 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 1630 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 1631 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 1632 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 1633 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 1634 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 1635 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 1636 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 1637 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 1638 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 1639 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 1640 /*skip ucode loading in SRIOV VF */ 1641 return true; 1642 1643 if (psp->autoload_supported && 1644 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 1645 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 1646 /* skip mec JT when autoload is enabled */ 1647 return true; 1648 1649 return false; 1650 } 1651 1652 static int psp_np_fw_load(struct psp_context *psp) 1653 { 1654 int i, ret; 1655 struct amdgpu_firmware_info *ucode; 1656 struct amdgpu_device* adev = psp->adev; 1657 1658 if (psp->autoload_supported && 1659 !psp->pmfw_centralized_cstate_management) { 1660 ret = psp_load_smu_fw(psp); 1661 if (ret) 1662 return ret; 1663 } 1664 1665 for (i = 0; i < adev->firmware.max_ucodes; i++) { 1666 ucode = &adev->firmware.ucode[i]; 1667 1668 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 1669 !fw_load_skip_check(psp, ucode)) { 1670 ret = psp_load_smu_fw(psp); 1671 if (ret) 1672 return ret; 1673 continue; 1674 } 1675 1676 if (fw_load_skip_check(psp, ucode)) 1677 continue; 1678 1679 psp_print_fw_hdr(psp, ucode); 1680 1681 ret = psp_execute_np_fw_load(psp, ucode); 1682 if (ret) 1683 return ret; 1684 1685 /* Start rlc autoload after psp recieved all the gfx firmware */ 1686 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 1687 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 1688 ret = psp_rlc_autoload_start(psp); 1689 if (ret) { 1690 DRM_ERROR("Failed to start rlc autoload\n"); 1691 return ret; 1692 } 1693 } 1694 } 1695 1696 return 0; 1697 } 1698 1699 static int psp_load_fw(struct amdgpu_device *adev) 1700 { 1701 int ret; 1702 struct psp_context *psp = &adev->psp; 1703 1704 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) { 1705 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 1706 goto skip_memalloc; 1707 } 1708 1709 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1710 if (!psp->cmd) 1711 return -ENOMEM; 1712 1713 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 1714 AMDGPU_GEM_DOMAIN_GTT, 1715 &psp->fw_pri_bo, 1716 &psp->fw_pri_mc_addr, 1717 &psp->fw_pri_buf); 1718 if (ret) 1719 goto failed; 1720 1721 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 1722 AMDGPU_GEM_DOMAIN_VRAM, 1723 &psp->fence_buf_bo, 1724 &psp->fence_buf_mc_addr, 1725 &psp->fence_buf); 1726 if (ret) 1727 goto failed; 1728 1729 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 1730 AMDGPU_GEM_DOMAIN_VRAM, 1731 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 1732 (void **)&psp->cmd_buf_mem); 1733 if (ret) 1734 goto failed; 1735 1736 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 1737 1738 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 1739 if (ret) { 1740 DRM_ERROR("PSP ring init failed!\n"); 1741 goto failed; 1742 } 1743 1744 skip_memalloc: 1745 ret = psp_hw_start(psp); 1746 if (ret) 1747 goto failed; 1748 1749 ret = psp_np_fw_load(psp); 1750 if (ret) 1751 goto failed; 1752 1753 ret = psp_asd_load(psp); 1754 if (ret) { 1755 DRM_ERROR("PSP load asd failed!\n"); 1756 return ret; 1757 } 1758 1759 if (psp->adev->psp.ta_fw) { 1760 ret = psp_ras_initialize(psp); 1761 if (ret) 1762 dev_err(psp->adev->dev, 1763 "RAS: Failed to initialize RAS\n"); 1764 1765 ret = psp_hdcp_initialize(psp); 1766 if (ret) 1767 dev_err(psp->adev->dev, 1768 "HDCP: Failed to initialize HDCP\n"); 1769 1770 ret = psp_dtm_initialize(psp); 1771 if (ret) 1772 dev_err(psp->adev->dev, 1773 "DTM: Failed to initialize DTM\n"); 1774 } 1775 1776 return 0; 1777 1778 failed: 1779 /* 1780 * all cleanup jobs (xgmi terminate, ras terminate, 1781 * ring destroy, cmd/fence/fw buffers destory, 1782 * psp->cmd destory) are delayed to psp_hw_fini 1783 */ 1784 return ret; 1785 } 1786 1787 static int psp_hw_init(void *handle) 1788 { 1789 int ret; 1790 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1791 1792 mutex_lock(&adev->firmware.mutex); 1793 /* 1794 * This sequence is just used on hw_init only once, no need on 1795 * resume. 1796 */ 1797 ret = amdgpu_ucode_init_bo(adev); 1798 if (ret) 1799 goto failed; 1800 1801 ret = psp_load_fw(adev); 1802 if (ret) { 1803 DRM_ERROR("PSP firmware loading failed\n"); 1804 goto failed; 1805 } 1806 1807 mutex_unlock(&adev->firmware.mutex); 1808 return 0; 1809 1810 failed: 1811 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 1812 mutex_unlock(&adev->firmware.mutex); 1813 return -EINVAL; 1814 } 1815 1816 static int psp_hw_fini(void *handle) 1817 { 1818 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1819 struct psp_context *psp = &adev->psp; 1820 void *tmr_buf; 1821 void **pptr; 1822 1823 if (psp->adev->psp.ta_fw) { 1824 psp_ras_terminate(psp); 1825 psp_dtm_terminate(psp); 1826 psp_hdcp_terminate(psp); 1827 } 1828 1829 psp_asd_unload(psp); 1830 1831 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 1832 1833 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 1834 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 1835 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 1836 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 1837 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 1838 &psp->fence_buf_mc_addr, &psp->fence_buf); 1839 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 1840 (void **)&psp->cmd_buf_mem); 1841 1842 kfree(psp->cmd); 1843 psp->cmd = NULL; 1844 1845 return 0; 1846 } 1847 1848 static int psp_suspend(void *handle) 1849 { 1850 int ret; 1851 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1852 struct psp_context *psp = &adev->psp; 1853 1854 if (adev->gmc.xgmi.num_physical_nodes > 1 && 1855 psp->xgmi_context.initialized == 1) { 1856 ret = psp_xgmi_terminate(psp); 1857 if (ret) { 1858 DRM_ERROR("Failed to terminate xgmi ta\n"); 1859 return ret; 1860 } 1861 } 1862 1863 if (psp->adev->psp.ta_fw) { 1864 ret = psp_ras_terminate(psp); 1865 if (ret) { 1866 DRM_ERROR("Failed to terminate ras ta\n"); 1867 return ret; 1868 } 1869 ret = psp_hdcp_terminate(psp); 1870 if (ret) { 1871 DRM_ERROR("Failed to terminate hdcp ta\n"); 1872 return ret; 1873 } 1874 ret = psp_dtm_terminate(psp); 1875 if (ret) { 1876 DRM_ERROR("Failed to terminate dtm ta\n"); 1877 return ret; 1878 } 1879 } 1880 1881 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 1882 if (ret) { 1883 DRM_ERROR("PSP ring stop failed\n"); 1884 return ret; 1885 } 1886 1887 return 0; 1888 } 1889 1890 static int psp_resume(void *handle) 1891 { 1892 int ret; 1893 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1894 struct psp_context *psp = &adev->psp; 1895 1896 DRM_INFO("PSP is resuming...\n"); 1897 1898 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 1899 if (ret) { 1900 DRM_ERROR("Failed to process memory training!\n"); 1901 return ret; 1902 } 1903 1904 mutex_lock(&adev->firmware.mutex); 1905 1906 ret = psp_hw_start(psp); 1907 if (ret) 1908 goto failed; 1909 1910 ret = psp_np_fw_load(psp); 1911 if (ret) 1912 goto failed; 1913 1914 ret = psp_asd_load(psp); 1915 if (ret) { 1916 DRM_ERROR("PSP load asd failed!\n"); 1917 goto failed; 1918 } 1919 1920 if (adev->gmc.xgmi.num_physical_nodes > 1) { 1921 ret = psp_xgmi_initialize(psp); 1922 /* Warning the XGMI seesion initialize failure 1923 * Instead of stop driver initialization 1924 */ 1925 if (ret) 1926 dev_err(psp->adev->dev, 1927 "XGMI: Failed to initialize XGMI session\n"); 1928 } 1929 1930 if (psp->adev->psp.ta_fw) { 1931 ret = psp_ras_initialize(psp); 1932 if (ret) 1933 dev_err(psp->adev->dev, 1934 "RAS: Failed to initialize RAS\n"); 1935 1936 ret = psp_hdcp_initialize(psp); 1937 if (ret) 1938 dev_err(psp->adev->dev, 1939 "HDCP: Failed to initialize HDCP\n"); 1940 1941 ret = psp_dtm_initialize(psp); 1942 if (ret) 1943 dev_err(psp->adev->dev, 1944 "DTM: Failed to initialize DTM\n"); 1945 } 1946 1947 mutex_unlock(&adev->firmware.mutex); 1948 1949 return 0; 1950 1951 failed: 1952 DRM_ERROR("PSP resume failed\n"); 1953 mutex_unlock(&adev->firmware.mutex); 1954 return ret; 1955 } 1956 1957 int psp_gpu_reset(struct amdgpu_device *adev) 1958 { 1959 int ret; 1960 1961 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 1962 return 0; 1963 1964 mutex_lock(&adev->psp.mutex); 1965 ret = psp_mode1_reset(&adev->psp); 1966 mutex_unlock(&adev->psp.mutex); 1967 1968 return ret; 1969 } 1970 1971 int psp_rlc_autoload_start(struct psp_context *psp) 1972 { 1973 int ret; 1974 struct psp_gfx_cmd_resp *cmd; 1975 1976 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1977 if (!cmd) 1978 return -ENOMEM; 1979 1980 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 1981 1982 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1983 psp->fence_buf_mc_addr); 1984 kfree(cmd); 1985 return ret; 1986 } 1987 1988 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 1989 uint64_t cmd_gpu_addr, int cmd_size) 1990 { 1991 struct amdgpu_firmware_info ucode = {0}; 1992 1993 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 1994 AMDGPU_UCODE_ID_VCN0_RAM; 1995 ucode.mc_addr = cmd_gpu_addr; 1996 ucode.ucode_size = cmd_size; 1997 1998 return psp_execute_np_fw_load(&adev->psp, &ucode); 1999 } 2000 2001 int psp_ring_cmd_submit(struct psp_context *psp, 2002 uint64_t cmd_buf_mc_addr, 2003 uint64_t fence_mc_addr, 2004 int index) 2005 { 2006 unsigned int psp_write_ptr_reg = 0; 2007 struct psp_gfx_rb_frame *write_frame; 2008 struct psp_ring *ring = &psp->km_ring; 2009 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2010 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2011 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2012 struct amdgpu_device *adev = psp->adev; 2013 uint32_t ring_size_dw = ring->ring_size / 4; 2014 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2015 2016 /* KM (GPCOM) prepare write pointer */ 2017 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2018 2019 /* Update KM RB frame pointer to new frame */ 2020 /* write_frame ptr increments by size of rb_frame in bytes */ 2021 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2022 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2023 write_frame = ring_buffer_start; 2024 else 2025 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2026 /* Check invalid write_frame ptr address */ 2027 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2028 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2029 ring_buffer_start, ring_buffer_end, write_frame); 2030 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2031 return -EINVAL; 2032 } 2033 2034 /* Initialize KM RB frame */ 2035 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2036 2037 /* Update KM RB frame */ 2038 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2039 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2040 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2041 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2042 write_frame->fence_value = index; 2043 amdgpu_asic_flush_hdp(adev, NULL); 2044 2045 /* Update the write Pointer in DWORDs */ 2046 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2047 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2048 return 0; 2049 } 2050 2051 int psp_init_asd_microcode(struct psp_context *psp, 2052 const char *chip_name) 2053 { 2054 struct amdgpu_device *adev = psp->adev; 2055 char fw_name[30]; 2056 const struct psp_firmware_header_v1_0 *asd_hdr; 2057 int err = 0; 2058 2059 if (!chip_name) { 2060 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2061 return -EINVAL; 2062 } 2063 2064 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2065 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2066 if (err) 2067 goto out; 2068 2069 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2070 if (err) 2071 goto out; 2072 2073 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2074 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2075 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 2076 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2077 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2078 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2079 return 0; 2080 out: 2081 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2082 release_firmware(adev->psp.asd_fw); 2083 adev->psp.asd_fw = NULL; 2084 return err; 2085 } 2086 2087 int psp_init_sos_microcode(struct psp_context *psp, 2088 const char *chip_name) 2089 { 2090 struct amdgpu_device *adev = psp->adev; 2091 char fw_name[30]; 2092 const struct psp_firmware_header_v1_0 *sos_hdr; 2093 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 2094 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 2095 int err = 0; 2096 2097 if (!chip_name) { 2098 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 2099 return -EINVAL; 2100 } 2101 2102 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 2103 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 2104 if (err) 2105 goto out; 2106 2107 err = amdgpu_ucode_validate(adev->psp.sos_fw); 2108 if (err) 2109 goto out; 2110 2111 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2112 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 2113 2114 switch (sos_hdr->header.header_version_major) { 2115 case 1: 2116 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 2117 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 2118 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 2119 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 2120 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 2121 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2122 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2123 le32_to_cpu(sos_hdr->sos_offset_bytes); 2124 if (sos_hdr->header.header_version_minor == 1) { 2125 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 2126 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 2127 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2128 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 2129 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); 2130 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2131 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); 2132 } 2133 if (sos_hdr->header.header_version_minor == 2) { 2134 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 2135 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); 2136 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2137 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); 2138 } 2139 break; 2140 default: 2141 dev_err(adev->dev, 2142 "unsupported psp sos firmware\n"); 2143 err = -EINVAL; 2144 goto out; 2145 } 2146 2147 return 0; 2148 out: 2149 dev_err(adev->dev, 2150 "failed to init sos firmware\n"); 2151 release_firmware(adev->psp.sos_fw); 2152 adev->psp.sos_fw = NULL; 2153 2154 return err; 2155 } 2156 2157 static int psp_set_clockgating_state(void *handle, 2158 enum amd_clockgating_state state) 2159 { 2160 return 0; 2161 } 2162 2163 static int psp_set_powergating_state(void *handle, 2164 enum amd_powergating_state state) 2165 { 2166 return 0; 2167 } 2168 2169 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 2170 struct device_attribute *attr, 2171 char *buf) 2172 { 2173 struct drm_device *ddev = dev_get_drvdata(dev); 2174 struct amdgpu_device *adev = ddev->dev_private; 2175 uint32_t fw_ver; 2176 int ret; 2177 2178 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2179 DRM_INFO("PSP block is not ready yet."); 2180 return -EBUSY; 2181 } 2182 2183 mutex_lock(&adev->psp.mutex); 2184 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 2185 mutex_unlock(&adev->psp.mutex); 2186 2187 if (ret) { 2188 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 2189 return ret; 2190 } 2191 2192 return snprintf(buf, PAGE_SIZE, "%x\n", fw_ver); 2193 } 2194 2195 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 2196 struct device_attribute *attr, 2197 const char *buf, 2198 size_t count) 2199 { 2200 struct drm_device *ddev = dev_get_drvdata(dev); 2201 struct amdgpu_device *adev = ddev->dev_private; 2202 void *cpu_addr; 2203 dma_addr_t dma_addr; 2204 int ret; 2205 char fw_name[100]; 2206 const struct firmware *usbc_pd_fw; 2207 2208 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2209 DRM_INFO("PSP block is not ready yet."); 2210 return -EBUSY; 2211 } 2212 2213 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 2214 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 2215 if (ret) 2216 goto fail; 2217 2218 /* We need contiguous physical mem to place the FW for psp to access */ 2219 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL); 2220 2221 ret = dma_mapping_error(adev->dev, dma_addr); 2222 if (ret) 2223 goto rel_buf; 2224 2225 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 2226 2227 /* 2228 * x86 specific workaround. 2229 * Without it the buffer is invisible in PSP. 2230 * 2231 * TODO Remove once PSP starts snooping CPU cache 2232 */ 2233 #ifdef CONFIG_X86 2234 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1))); 2235 #endif 2236 2237 mutex_lock(&adev->psp.mutex); 2238 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr); 2239 mutex_unlock(&adev->psp.mutex); 2240 2241 rel_buf: 2242 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr); 2243 release_firmware(usbc_pd_fw); 2244 2245 fail: 2246 if (ret) { 2247 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 2248 return ret; 2249 } 2250 2251 return count; 2252 } 2253 2254 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 2255 psp_usbc_pd_fw_sysfs_read, 2256 psp_usbc_pd_fw_sysfs_write); 2257 2258 2259 2260 const struct amd_ip_funcs psp_ip_funcs = { 2261 .name = "psp", 2262 .early_init = psp_early_init, 2263 .late_init = NULL, 2264 .sw_init = psp_sw_init, 2265 .sw_fini = psp_sw_fini, 2266 .hw_init = psp_hw_init, 2267 .hw_fini = psp_hw_fini, 2268 .suspend = psp_suspend, 2269 .resume = psp_resume, 2270 .is_idle = NULL, 2271 .check_soft_reset = NULL, 2272 .wait_for_idle = NULL, 2273 .soft_reset = NULL, 2274 .set_clockgating_state = psp_set_clockgating_state, 2275 .set_powergating_state = psp_set_powergating_state, 2276 }; 2277 2278 static int psp_sysfs_init(struct amdgpu_device *adev) 2279 { 2280 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 2281 2282 if (ret) 2283 DRM_ERROR("Failed to create USBC PD FW control file!"); 2284 2285 return ret; 2286 } 2287 2288 static void psp_sysfs_fini(struct amdgpu_device *adev) 2289 { 2290 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 2291 } 2292 2293 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 2294 { 2295 .type = AMD_IP_BLOCK_TYPE_PSP, 2296 .major = 3, 2297 .minor = 1, 2298 .rev = 0, 2299 .funcs = &psp_ip_funcs, 2300 }; 2301 2302 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 2303 { 2304 .type = AMD_IP_BLOCK_TYPE_PSP, 2305 .major = 10, 2306 .minor = 0, 2307 .rev = 0, 2308 .funcs = &psp_ip_funcs, 2309 }; 2310 2311 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 2312 { 2313 .type = AMD_IP_BLOCK_TYPE_PSP, 2314 .major = 11, 2315 .minor = 0, 2316 .rev = 0, 2317 .funcs = &psp_ip_funcs, 2318 }; 2319 2320 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 2321 { 2322 .type = AMD_IP_BLOCK_TYPE_PSP, 2323 .major = 12, 2324 .minor = 0, 2325 .rev = 0, 2326 .funcs = &psp_ip_funcs, 2327 }; 2328