1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_OBJECT_H__ 29 #define __AMDGPU_OBJECT_H__ 30 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu.h" 33 #include "amdgpu_res_cursor.h" 34 35 #ifdef CONFIG_MMU_NOTIFIER 36 #include <linux/mmu_notifier.h> 37 #endif 38 39 #define AMDGPU_BO_INVALID_OFFSET LONG_MAX 40 #define AMDGPU_BO_MAX_PLACEMENTS 3 41 42 /* BO flag to indicate a KFD userptr BO */ 43 #define AMDGPU_AMDKFD_CREATE_USERPTR_BO (1ULL << 63) 44 #define AMDGPU_AMDKFD_CREATE_SVM_BO (1ULL << 62) 45 46 #define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo) 47 #define to_amdgpu_bo_vm(abo) container_of((abo), struct amdgpu_bo_vm, bo) 48 49 struct amdgpu_bo_param { 50 unsigned long size; 51 int byte_align; 52 u32 bo_ptr_size; 53 u32 domain; 54 u32 preferred_domain; 55 u64 flags; 56 enum ttm_bo_type type; 57 bool no_wait_gpu; 58 struct dma_resv *resv; 59 }; 60 61 /* bo virtual addresses in a vm */ 62 struct amdgpu_bo_va_mapping { 63 struct amdgpu_bo_va *bo_va; 64 struct list_head list; 65 struct rb_node rb; 66 uint64_t start; 67 uint64_t last; 68 uint64_t __subtree_last; 69 uint64_t offset; 70 uint64_t flags; 71 }; 72 73 /* User space allocated BO in a VM */ 74 struct amdgpu_bo_va { 75 struct amdgpu_vm_bo_base base; 76 77 /* protected by bo being reserved */ 78 unsigned ref_count; 79 80 /* all other members protected by the VM PD being reserved */ 81 struct dma_fence *last_pt_update; 82 83 /* mappings for this bo_va */ 84 struct list_head invalids; 85 struct list_head valids; 86 87 /* If the mappings are cleared or filled */ 88 bool cleared; 89 90 bool is_xgmi; 91 }; 92 93 struct amdgpu_bo { 94 /* Protected by tbo.reserved */ 95 u32 preferred_domains; 96 u32 allowed_domains; 97 struct ttm_place placements[AMDGPU_BO_MAX_PLACEMENTS]; 98 struct ttm_placement placement; 99 struct ttm_buffer_object tbo; 100 struct ttm_bo_kmap_obj kmap; 101 u64 flags; 102 unsigned prime_shared_count; 103 /* per VM structure for page tables and with virtual addresses */ 104 struct amdgpu_vm_bo_base *vm_bo; 105 /* Constant after initialization */ 106 struct amdgpu_bo *parent; 107 108 #ifdef CONFIG_MMU_NOTIFIER 109 struct mmu_interval_notifier notifier; 110 #endif 111 112 struct list_head shadow_list; 113 114 struct kgd_mem *kfd_bo; 115 }; 116 117 struct amdgpu_bo_user { 118 struct amdgpu_bo bo; 119 u64 tiling_flags; 120 u64 metadata_flags; 121 void *metadata; 122 u32 metadata_size; 123 124 }; 125 126 struct amdgpu_bo_vm { 127 struct amdgpu_bo bo; 128 struct amdgpu_bo *shadow; 129 struct amdgpu_vm_pt entries[]; 130 }; 131 132 static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo) 133 { 134 return container_of(tbo, struct amdgpu_bo, tbo); 135 } 136 137 /** 138 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type 139 * @mem_type: ttm memory type 140 * 141 * Returns corresponding domain of the ttm mem_type 142 */ 143 static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) 144 { 145 switch (mem_type) { 146 case TTM_PL_VRAM: 147 return AMDGPU_GEM_DOMAIN_VRAM; 148 case TTM_PL_TT: 149 return AMDGPU_GEM_DOMAIN_GTT; 150 case TTM_PL_SYSTEM: 151 return AMDGPU_GEM_DOMAIN_CPU; 152 case AMDGPU_PL_GDS: 153 return AMDGPU_GEM_DOMAIN_GDS; 154 case AMDGPU_PL_GWS: 155 return AMDGPU_GEM_DOMAIN_GWS; 156 case AMDGPU_PL_OA: 157 return AMDGPU_GEM_DOMAIN_OA; 158 default: 159 break; 160 } 161 return 0; 162 } 163 164 /** 165 * amdgpu_bo_reserve - reserve bo 166 * @bo: bo structure 167 * @no_intr: don't return -ERESTARTSYS on pending signal 168 * 169 * Returns: 170 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by 171 * a signal. Release all buffer reservations and return to user-space. 172 */ 173 static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr) 174 { 175 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 176 int r; 177 178 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL); 179 if (unlikely(r != 0)) { 180 if (r != -ERESTARTSYS) 181 dev_err(adev->dev, "%p reserve failed\n", bo); 182 return r; 183 } 184 return 0; 185 } 186 187 static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo) 188 { 189 ttm_bo_unreserve(&bo->tbo); 190 } 191 192 static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo) 193 { 194 return bo->tbo.base.size; 195 } 196 197 static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo) 198 { 199 return bo->tbo.base.size / AMDGPU_GPU_PAGE_SIZE; 200 } 201 202 static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo) 203 { 204 return (bo->tbo.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; 205 } 206 207 /** 208 * amdgpu_bo_mmap_offset - return mmap offset of bo 209 * @bo: amdgpu object for which we query the offset 210 * 211 * Returns mmap offset of the object. 212 */ 213 static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo) 214 { 215 return drm_vma_node_offset_addr(&bo->tbo.base.vma_node); 216 } 217 218 /** 219 * amdgpu_bo_in_cpu_visible_vram - check if BO is (partly) in visible VRAM 220 */ 221 static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo) 222 { 223 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 224 struct amdgpu_res_cursor cursor; 225 226 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) 227 return false; 228 229 amdgpu_res_first(&bo->tbo.mem, 0, amdgpu_bo_size(bo), &cursor); 230 while (cursor.remaining) { 231 if (cursor.start < adev->gmc.visible_vram_size) 232 return true; 233 234 amdgpu_res_next(&cursor, cursor.size); 235 } 236 237 return false; 238 } 239 240 /** 241 * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced 242 */ 243 static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo) 244 { 245 return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC; 246 } 247 248 /** 249 * amdgpu_bo_encrypted - test if the BO is encrypted 250 * @bo: pointer to a buffer object 251 * 252 * Return true if the buffer object is encrypted, false otherwise. 253 */ 254 static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo) 255 { 256 return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED; 257 } 258 259 /** 260 * amdgpu_bo_shadowed - check if the BO is shadowed 261 * 262 * @bo: BO to be tested. 263 * 264 * Returns: 265 * NULL if not shadowed or else return a BO pointer. 266 */ 267 static inline struct amdgpu_bo *amdgpu_bo_shadowed(struct amdgpu_bo *bo) 268 { 269 if (bo->tbo.type == ttm_bo_type_kernel) 270 return to_amdgpu_bo_vm(bo)->shadow; 271 272 return NULL; 273 } 274 275 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 276 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 277 278 int amdgpu_bo_create(struct amdgpu_device *adev, 279 struct amdgpu_bo_param *bp, 280 struct amdgpu_bo **bo_ptr); 281 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 282 unsigned long size, int align, 283 u32 domain, struct amdgpu_bo **bo_ptr, 284 u64 *gpu_addr, void **cpu_addr); 285 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 286 unsigned long size, int align, 287 u32 domain, struct amdgpu_bo **bo_ptr, 288 u64 *gpu_addr, void **cpu_addr); 289 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 290 uint64_t offset, uint64_t size, uint32_t domain, 291 struct amdgpu_bo **bo_ptr, void **cpu_addr); 292 int amdgpu_bo_create_user(struct amdgpu_device *adev, 293 struct amdgpu_bo_param *bp, 294 struct amdgpu_bo_user **ubo_ptr); 295 int amdgpu_bo_create_vm(struct amdgpu_device *adev, 296 struct amdgpu_bo_param *bp, 297 struct amdgpu_bo_vm **ubo_ptr); 298 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 299 void **cpu_addr); 300 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr); 301 void *amdgpu_bo_kptr(struct amdgpu_bo *bo); 302 void amdgpu_bo_kunmap(struct amdgpu_bo *bo); 303 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo); 304 void amdgpu_bo_unref(struct amdgpu_bo **bo); 305 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain); 306 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 307 u64 min_offset, u64 max_offset); 308 void amdgpu_bo_unpin(struct amdgpu_bo *bo); 309 int amdgpu_bo_evict_vram(struct amdgpu_device *adev); 310 int amdgpu_bo_init(struct amdgpu_device *adev); 311 void amdgpu_bo_fini(struct amdgpu_device *adev); 312 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags); 313 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags); 314 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 315 uint32_t metadata_size, uint64_t flags); 316 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 317 size_t buffer_size, uint32_t *metadata_size, 318 uint64_t *flags); 319 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 320 bool evict, 321 struct ttm_resource *new_mem); 322 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo); 323 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo); 324 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 325 bool shared); 326 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 327 enum amdgpu_sync_mode sync_mode, void *owner, 328 bool intr); 329 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr); 330 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo); 331 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo); 332 int amdgpu_bo_validate(struct amdgpu_bo *bo); 333 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, uint64_t *vram_mem, 334 uint64_t *gtt_mem, uint64_t *cpu_mem); 335 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo *bo); 336 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, 337 struct dma_fence **fence); 338 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, 339 uint32_t domain); 340 341 /* 342 * sub allocation 343 */ 344 345 static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo) 346 { 347 return sa_bo->manager->gpu_addr + sa_bo->soffset; 348 } 349 350 static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo) 351 { 352 return sa_bo->manager->cpu_ptr + sa_bo->soffset; 353 } 354 355 int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev, 356 struct amdgpu_sa_manager *sa_manager, 357 unsigned size, u32 align, u32 domain); 358 void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev, 359 struct amdgpu_sa_manager *sa_manager); 360 int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev, 361 struct amdgpu_sa_manager *sa_manager); 362 int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, 363 struct amdgpu_sa_bo **sa_bo, 364 unsigned size, unsigned align); 365 void amdgpu_sa_bo_free(struct amdgpu_device *adev, 366 struct amdgpu_sa_bo **sa_bo, 367 struct dma_fence *fence); 368 #if defined(CONFIG_DEBUG_FS) 369 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager, 370 struct seq_file *m); 371 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m); 372 #endif 373 void amdgpu_debugfs_sa_init(struct amdgpu_device *adev); 374 375 bool amdgpu_bo_support_uswc(u64 bo_flags); 376 377 378 #endif 379