1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_OBJECT_H__ 29 #define __AMDGPU_OBJECT_H__ 30 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu.h" 33 #include "amdgpu_res_cursor.h" 34 35 #ifdef CONFIG_MMU_NOTIFIER 36 #include <linux/mmu_notifier.h> 37 #endif 38 39 #define AMDGPU_BO_INVALID_OFFSET LONG_MAX 40 #define AMDGPU_BO_MAX_PLACEMENTS 3 41 42 /* BO flag to indicate a KFD userptr BO */ 43 #define AMDGPU_AMDKFD_CREATE_USERPTR_BO (1ULL << 63) 44 #define AMDGPU_AMDKFD_CREATE_SVM_BO (1ULL << 62) 45 46 #define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo) 47 #define to_amdgpu_bo_vm(abo) container_of((abo), struct amdgpu_bo_vm, bo) 48 49 struct amdgpu_bo_param { 50 unsigned long size; 51 int byte_align; 52 u32 bo_ptr_size; 53 u32 domain; 54 u32 preferred_domain; 55 u64 flags; 56 enum ttm_bo_type type; 57 bool no_wait_gpu; 58 struct dma_resv *resv; 59 void (*destroy)(struct ttm_buffer_object *bo); 60 }; 61 62 /* bo virtual addresses in a vm */ 63 struct amdgpu_bo_va_mapping { 64 struct amdgpu_bo_va *bo_va; 65 struct list_head list; 66 struct rb_node rb; 67 uint64_t start; 68 uint64_t last; 69 uint64_t __subtree_last; 70 uint64_t offset; 71 uint64_t flags; 72 }; 73 74 /* User space allocated BO in a VM */ 75 struct amdgpu_bo_va { 76 struct amdgpu_vm_bo_base base; 77 78 /* protected by bo being reserved */ 79 unsigned ref_count; 80 81 /* all other members protected by the VM PD being reserved */ 82 struct dma_fence *last_pt_update; 83 84 /* mappings for this bo_va */ 85 struct list_head invalids; 86 struct list_head valids; 87 88 /* If the mappings are cleared or filled */ 89 bool cleared; 90 91 bool is_xgmi; 92 }; 93 94 struct amdgpu_bo { 95 /* Protected by tbo.reserved */ 96 u32 preferred_domains; 97 u32 allowed_domains; 98 struct ttm_place placements[AMDGPU_BO_MAX_PLACEMENTS]; 99 struct ttm_placement placement; 100 struct ttm_buffer_object tbo; 101 struct ttm_bo_kmap_obj kmap; 102 u64 flags; 103 unsigned prime_shared_count; 104 /* per VM structure for page tables and with virtual addresses */ 105 struct amdgpu_vm_bo_base *vm_bo; 106 /* Constant after initialization */ 107 struct amdgpu_bo *parent; 108 109 #ifdef CONFIG_MMU_NOTIFIER 110 struct mmu_interval_notifier notifier; 111 #endif 112 struct kgd_mem *kfd_bo; 113 }; 114 115 struct amdgpu_bo_user { 116 struct amdgpu_bo bo; 117 u64 tiling_flags; 118 u64 metadata_flags; 119 void *metadata; 120 u32 metadata_size; 121 122 }; 123 124 struct amdgpu_bo_vm { 125 struct amdgpu_bo bo; 126 struct amdgpu_bo *shadow; 127 struct list_head shadow_list; 128 struct amdgpu_vm_bo_base entries[]; 129 }; 130 131 static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo) 132 { 133 return container_of(tbo, struct amdgpu_bo, tbo); 134 } 135 136 /** 137 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type 138 * @mem_type: ttm memory type 139 * 140 * Returns corresponding domain of the ttm mem_type 141 */ 142 static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) 143 { 144 switch (mem_type) { 145 case TTM_PL_VRAM: 146 return AMDGPU_GEM_DOMAIN_VRAM; 147 case TTM_PL_TT: 148 return AMDGPU_GEM_DOMAIN_GTT; 149 case TTM_PL_SYSTEM: 150 return AMDGPU_GEM_DOMAIN_CPU; 151 case AMDGPU_PL_GDS: 152 return AMDGPU_GEM_DOMAIN_GDS; 153 case AMDGPU_PL_GWS: 154 return AMDGPU_GEM_DOMAIN_GWS; 155 case AMDGPU_PL_OA: 156 return AMDGPU_GEM_DOMAIN_OA; 157 default: 158 break; 159 } 160 return 0; 161 } 162 163 /** 164 * amdgpu_bo_reserve - reserve bo 165 * @bo: bo structure 166 * @no_intr: don't return -ERESTARTSYS on pending signal 167 * 168 * Returns: 169 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by 170 * a signal. Release all buffer reservations and return to user-space. 171 */ 172 static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr) 173 { 174 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 175 int r; 176 177 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL); 178 if (unlikely(r != 0)) { 179 if (r != -ERESTARTSYS) 180 dev_err(adev->dev, "%p reserve failed\n", bo); 181 return r; 182 } 183 return 0; 184 } 185 186 static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo) 187 { 188 ttm_bo_unreserve(&bo->tbo); 189 } 190 191 static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo) 192 { 193 return bo->tbo.base.size; 194 } 195 196 static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo) 197 { 198 return bo->tbo.base.size / AMDGPU_GPU_PAGE_SIZE; 199 } 200 201 static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo) 202 { 203 return (bo->tbo.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; 204 } 205 206 /** 207 * amdgpu_bo_mmap_offset - return mmap offset of bo 208 * @bo: amdgpu object for which we query the offset 209 * 210 * Returns mmap offset of the object. 211 */ 212 static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo) 213 { 214 return drm_vma_node_offset_addr(&bo->tbo.base.vma_node); 215 } 216 217 /** 218 * amdgpu_bo_in_cpu_visible_vram - check if BO is (partly) in visible VRAM 219 */ 220 static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo) 221 { 222 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 223 struct amdgpu_res_cursor cursor; 224 225 if (bo->tbo.resource->mem_type != TTM_PL_VRAM) 226 return false; 227 228 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor); 229 while (cursor.remaining) { 230 if (cursor.start < adev->gmc.visible_vram_size) 231 return true; 232 233 amdgpu_res_next(&cursor, cursor.size); 234 } 235 236 return false; 237 } 238 239 /** 240 * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced 241 */ 242 static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo) 243 { 244 return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC; 245 } 246 247 /** 248 * amdgpu_bo_encrypted - test if the BO is encrypted 249 * @bo: pointer to a buffer object 250 * 251 * Return true if the buffer object is encrypted, false otherwise. 252 */ 253 static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo) 254 { 255 return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED; 256 } 257 258 /** 259 * amdgpu_bo_shadowed - check if the BO is shadowed 260 * 261 * @bo: BO to be tested. 262 * 263 * Returns: 264 * NULL if not shadowed or else return a BO pointer. 265 */ 266 static inline struct amdgpu_bo *amdgpu_bo_shadowed(struct amdgpu_bo *bo) 267 { 268 if (bo->tbo.type == ttm_bo_type_kernel) 269 return to_amdgpu_bo_vm(bo)->shadow; 270 271 return NULL; 272 } 273 274 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 275 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 276 277 int amdgpu_bo_create(struct amdgpu_device *adev, 278 struct amdgpu_bo_param *bp, 279 struct amdgpu_bo **bo_ptr); 280 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 281 unsigned long size, int align, 282 u32 domain, struct amdgpu_bo **bo_ptr, 283 u64 *gpu_addr, void **cpu_addr); 284 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 285 unsigned long size, int align, 286 u32 domain, struct amdgpu_bo **bo_ptr, 287 u64 *gpu_addr, void **cpu_addr); 288 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 289 uint64_t offset, uint64_t size, uint32_t domain, 290 struct amdgpu_bo **bo_ptr, void **cpu_addr); 291 int amdgpu_bo_create_user(struct amdgpu_device *adev, 292 struct amdgpu_bo_param *bp, 293 struct amdgpu_bo_user **ubo_ptr); 294 int amdgpu_bo_create_vm(struct amdgpu_device *adev, 295 struct amdgpu_bo_param *bp, 296 struct amdgpu_bo_vm **ubo_ptr); 297 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 298 void **cpu_addr); 299 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr); 300 void *amdgpu_bo_kptr(struct amdgpu_bo *bo); 301 void amdgpu_bo_kunmap(struct amdgpu_bo *bo); 302 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo); 303 void amdgpu_bo_unref(struct amdgpu_bo **bo); 304 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain); 305 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 306 u64 min_offset, u64 max_offset); 307 void amdgpu_bo_unpin(struct amdgpu_bo *bo); 308 int amdgpu_bo_evict_vram(struct amdgpu_device *adev); 309 int amdgpu_bo_init(struct amdgpu_device *adev); 310 void amdgpu_bo_fini(struct amdgpu_device *adev); 311 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags); 312 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags); 313 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 314 uint32_t metadata_size, uint64_t flags); 315 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 316 size_t buffer_size, uint32_t *metadata_size, 317 uint64_t *flags); 318 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 319 bool evict, 320 struct ttm_resource *new_mem); 321 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo); 322 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo); 323 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 324 bool shared); 325 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 326 enum amdgpu_sync_mode sync_mode, void *owner, 327 bool intr); 328 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr); 329 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo); 330 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo); 331 int amdgpu_bo_validate(struct amdgpu_bo *bo); 332 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, uint64_t *vram_mem, 333 uint64_t *gtt_mem, uint64_t *cpu_mem); 334 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo); 335 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, 336 struct dma_fence **fence); 337 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, 338 uint32_t domain); 339 340 /* 341 * sub allocation 342 */ 343 344 static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo) 345 { 346 return sa_bo->manager->gpu_addr + sa_bo->soffset; 347 } 348 349 static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo) 350 { 351 return sa_bo->manager->cpu_ptr + sa_bo->soffset; 352 } 353 354 int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev, 355 struct amdgpu_sa_manager *sa_manager, 356 unsigned size, u32 align, u32 domain); 357 void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev, 358 struct amdgpu_sa_manager *sa_manager); 359 int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev, 360 struct amdgpu_sa_manager *sa_manager); 361 int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, 362 struct amdgpu_sa_bo **sa_bo, 363 unsigned size, unsigned align); 364 void amdgpu_sa_bo_free(struct amdgpu_device *adev, 365 struct amdgpu_sa_bo **sa_bo, 366 struct dma_fence *fence); 367 #if defined(CONFIG_DEBUG_FS) 368 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager, 369 struct seq_file *m); 370 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m); 371 #endif 372 void amdgpu_debugfs_sa_init(struct amdgpu_device *adev); 373 374 bool amdgpu_bo_support_uswc(u64 bo_flags); 375 376 377 #endif 378