1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_OBJECT_H__ 29 #define __AMDGPU_OBJECT_H__ 30 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu.h" 33 34 #define AMDGPU_BO_INVALID_OFFSET LONG_MAX 35 #define AMDGPU_BO_MAX_PLACEMENTS 3 36 37 struct amdgpu_bo_param { 38 unsigned long size; 39 int byte_align; 40 u32 domain; 41 u32 preferred_domain; 42 u64 flags; 43 enum ttm_bo_type type; 44 struct reservation_object *resv; 45 }; 46 47 /* bo virtual addresses in a vm */ 48 struct amdgpu_bo_va_mapping { 49 struct amdgpu_bo_va *bo_va; 50 struct list_head list; 51 struct rb_node rb; 52 uint64_t start; 53 uint64_t last; 54 uint64_t __subtree_last; 55 uint64_t offset; 56 uint64_t flags; 57 }; 58 59 /* User space allocated BO in a VM */ 60 struct amdgpu_bo_va { 61 struct amdgpu_vm_bo_base base; 62 63 /* protected by bo being reserved */ 64 unsigned ref_count; 65 66 /* all other members protected by the VM PD being reserved */ 67 struct dma_fence *last_pt_update; 68 69 /* mappings for this bo_va */ 70 struct list_head invalids; 71 struct list_head valids; 72 73 /* If the mappings are cleared or filled */ 74 bool cleared; 75 76 bool is_xgmi; 77 }; 78 79 struct amdgpu_bo { 80 /* Protected by tbo.reserved */ 81 u32 preferred_domains; 82 u32 allowed_domains; 83 struct ttm_place placements[AMDGPU_BO_MAX_PLACEMENTS]; 84 struct ttm_placement placement; 85 struct ttm_buffer_object tbo; 86 struct ttm_bo_kmap_obj kmap; 87 u64 flags; 88 unsigned pin_count; 89 u64 tiling_flags; 90 u64 metadata_flags; 91 void *metadata; 92 u32 metadata_size; 93 unsigned prime_shared_count; 94 /* per VM structure for page tables and with virtual addresses */ 95 struct amdgpu_vm_bo_base *vm_bo; 96 /* Constant after initialization */ 97 struct drm_gem_object gem_base; 98 struct amdgpu_bo *parent; 99 struct amdgpu_bo *shadow; 100 101 struct ttm_bo_kmap_obj dma_buf_vmap; 102 struct amdgpu_mn *mn; 103 104 union { 105 struct list_head mn_list; 106 struct list_head shadow_list; 107 }; 108 109 struct kgd_mem *kfd_bo; 110 }; 111 112 static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo) 113 { 114 return container_of(tbo, struct amdgpu_bo, tbo); 115 } 116 117 /** 118 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type 119 * @mem_type: ttm memory type 120 * 121 * Returns corresponding domain of the ttm mem_type 122 */ 123 static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) 124 { 125 switch (mem_type) { 126 case TTM_PL_VRAM: 127 return AMDGPU_GEM_DOMAIN_VRAM; 128 case TTM_PL_TT: 129 return AMDGPU_GEM_DOMAIN_GTT; 130 case TTM_PL_SYSTEM: 131 return AMDGPU_GEM_DOMAIN_CPU; 132 case AMDGPU_PL_GDS: 133 return AMDGPU_GEM_DOMAIN_GDS; 134 case AMDGPU_PL_GWS: 135 return AMDGPU_GEM_DOMAIN_GWS; 136 case AMDGPU_PL_OA: 137 return AMDGPU_GEM_DOMAIN_OA; 138 default: 139 break; 140 } 141 return 0; 142 } 143 144 /** 145 * amdgpu_bo_reserve - reserve bo 146 * @bo: bo structure 147 * @no_intr: don't return -ERESTARTSYS on pending signal 148 * 149 * Returns: 150 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by 151 * a signal. Release all buffer reservations and return to user-space. 152 */ 153 static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr) 154 { 155 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 156 int r; 157 158 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL); 159 if (unlikely(r != 0)) { 160 if (r != -ERESTARTSYS) 161 dev_err(adev->dev, "%p reserve failed\n", bo); 162 return r; 163 } 164 return 0; 165 } 166 167 static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo) 168 { 169 ttm_bo_unreserve(&bo->tbo); 170 } 171 172 static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo) 173 { 174 return bo->tbo.num_pages << PAGE_SHIFT; 175 } 176 177 static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo) 178 { 179 return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; 180 } 181 182 static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo) 183 { 184 return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; 185 } 186 187 /** 188 * amdgpu_bo_mmap_offset - return mmap offset of bo 189 * @bo: amdgpu object for which we query the offset 190 * 191 * Returns mmap offset of the object. 192 */ 193 static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo) 194 { 195 return drm_vma_node_offset_addr(&bo->tbo.vma_node); 196 } 197 198 /** 199 * amdgpu_bo_in_cpu_visible_vram - check if BO is (partly) in visible VRAM 200 */ 201 static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo) 202 { 203 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 204 unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 205 struct drm_mm_node *node = bo->tbo.mem.mm_node; 206 unsigned long pages_left; 207 208 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) 209 return false; 210 211 for (pages_left = bo->tbo.mem.num_pages; pages_left; 212 pages_left -= node->size, node++) 213 if (node->start < fpfn) 214 return true; 215 216 return false; 217 } 218 219 /** 220 * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced 221 */ 222 static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo) 223 { 224 return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC; 225 } 226 227 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 228 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 229 230 int amdgpu_bo_create(struct amdgpu_device *adev, 231 struct amdgpu_bo_param *bp, 232 struct amdgpu_bo **bo_ptr); 233 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 234 unsigned long size, int align, 235 u32 domain, struct amdgpu_bo **bo_ptr, 236 u64 *gpu_addr, void **cpu_addr); 237 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 238 unsigned long size, int align, 239 u32 domain, struct amdgpu_bo **bo_ptr, 240 u64 *gpu_addr, void **cpu_addr); 241 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 242 void **cpu_addr); 243 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr); 244 void *amdgpu_bo_kptr(struct amdgpu_bo *bo); 245 void amdgpu_bo_kunmap(struct amdgpu_bo *bo); 246 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo); 247 void amdgpu_bo_unref(struct amdgpu_bo **bo); 248 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain); 249 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 250 u64 min_offset, u64 max_offset); 251 int amdgpu_bo_unpin(struct amdgpu_bo *bo); 252 int amdgpu_bo_evict_vram(struct amdgpu_device *adev); 253 int amdgpu_bo_init(struct amdgpu_device *adev); 254 int amdgpu_bo_late_init(struct amdgpu_device *adev); 255 void amdgpu_bo_fini(struct amdgpu_device *adev); 256 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 257 struct vm_area_struct *vma); 258 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags); 259 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags); 260 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 261 uint32_t metadata_size, uint64_t flags); 262 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 263 size_t buffer_size, uint32_t *metadata_size, 264 uint64_t *flags); 265 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 266 bool evict, 267 struct ttm_mem_reg *new_mem); 268 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo); 269 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 270 bool shared); 271 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr); 272 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo); 273 int amdgpu_bo_validate(struct amdgpu_bo *bo); 274 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, 275 struct dma_fence **fence); 276 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, 277 uint32_t domain); 278 279 /* 280 * sub allocation 281 */ 282 283 static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo) 284 { 285 return sa_bo->manager->gpu_addr + sa_bo->soffset; 286 } 287 288 static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo) 289 { 290 return sa_bo->manager->cpu_ptr + sa_bo->soffset; 291 } 292 293 int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev, 294 struct amdgpu_sa_manager *sa_manager, 295 unsigned size, u32 align, u32 domain); 296 void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev, 297 struct amdgpu_sa_manager *sa_manager); 298 int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev, 299 struct amdgpu_sa_manager *sa_manager); 300 int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, 301 struct amdgpu_sa_bo **sa_bo, 302 unsigned size, unsigned align); 303 void amdgpu_sa_bo_free(struct amdgpu_device *adev, 304 struct amdgpu_sa_bo **sa_bo, 305 struct dma_fence *fence); 306 #if defined(CONFIG_DEBUG_FS) 307 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager, 308 struct seq_file *m); 309 #endif 310 311 312 #endif 313